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EMBEDDED IntelDX2 PROCESSOR
- 208-Lead Shrink Quad Flat Pack (SQFP)
EMBEDDED IntelDX2 PROCESSOR
s Integrated Floating-Point Unit s Speed-Multiplying Technology s 32-Bit RISC Technology Core s 8-Kbyte Write-Through Cache s Four Internal Write Buffers s Burst Bus Cycles s Dynamic Bus Sizing for 8- and 16-bit s SL Technology s Data Bus Parity Generation and Checking s Boundary Scan (JTAG) s 3.3-Volt Processor, 50 MHz, 25 MHz CLK
- 208-Lead Shrink Quad Flat Pack (SQFP)
s 5-Volt Processor, 66 MHz, 33 MHz CLK
Data Bus Devices
- 168-Pin Pin Grid Array (PGA) s Binary Compatible with Large Software Base
64-Bit Interunit Transfer Bus
32-Bit Data Bus 32-Bit Data Bus Linear Address 32 PCD PWT Core Clock
Clock Multiplier
Barrel Shifter Register File ALU
Base / Index Bus 32
Segmentation Unit Descriptor Registers Limit and Attribute PLA
Bus Interface
Paging Unit
Cache Unit
Address Drivers Write Buffers 4 x 32 Data Bus Transceivers Bus Control
A31-A2 BE3#- BE0#
Physical Address Translation Lookaside Buffer
8 Kbyte Cache
D31-D0
Displacement Bus
Prefetcher Request Sequencer 32-Byte Code Queue 2x16 Bytes Burst Bus Control Bus Size Control Cache Control
MicroInstruction
ADS# W / R# D / C# M / IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# FERR# IGNNE# STPCLK#
BRDY# BLAST#
Floating Point Unit
Control & Protection Test Unit
Code Stream Instruction Decode Decoded Instruction Path
BS16# BS8#
Floating Point Register File
KEN# FLUSH# AHOLD EADS#
Control ROM
Parity Generation and Control Boundary Scan Control
DP3-DP0 PCHK#
TCK TMS TDI TD0
A3223-01
Contents
EMBEDDED IntelDX2 PROCESSOR
Contents
Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28.
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 3.3 V Processor ..................................... 39 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 3.3 V Processor ..................................... 39 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 5 V Processor ................... 40 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 5 V Processor ................... 40 208-Lead SQFP Package Dimensions .......................................... 41 Principal Dimensions and Data for 168-Pin Pin Grid Array Package .................... 42
The Embedded IntelDX2 Processor Family ...................................... 2 Pinout Differences for 208-Lead SQFP Package ................................... 5 Pin Assignment for 208-Lead SQFP Package ...................................... 6 Pin Cross Reference for 208-Lead SQFP Package .................................. 8 Pinout Differences for 168-Pin PGA Package ..................................... 11 Pin Assignment for 168-Pin PGA Package ....................................... 12 Pin Cross Reference for 168-Pin PGA Package ................................... 14 Embedded IntelDX2 Processor Pin Descriptions ................................. 16 Output Pins ............................................................... 23 Input / Output Pins ........................................................... 23 Test Pins ................................................................. 23 Input Pins ................................................................. 24 CPUID Instruction Description ................................................. 25 Boundary Scan Component Identification Code (3.3 Volt Processor) ................... 26 Boundary Scan Component Identification Code (5 Volt Processor) .................... 27 Absolute Maximum Ratings ................................................... 28 Operating Supply Voltages ................................................... 28 3.3 V DC Specifications ...................................................... 29 3.3 V ICC Values ........................................................... 30 5 V DC Specifications ....................................................... 31 5 V ICC Values ............................................................. 32 AC Characteristics .......................................................... 33 AC Specifications for the Test Access Port ....................................... 34 168-Pin Ceramic PGA Package Dimensions ...................................... 42 Ceramic PGA Package Dimension Symbols ...................................... 43 Thermal Resistance, JA (°C / W) ............................................... 44 Thermal Resistance, JC (°C / W) ............................................... 44 Maximum Tambient, TA max (°C) ................................................ 44
Embedded IntelDX2 Processor
INTRODUCTION
· Instruction Pipelining - Overlapped instruction fetching, decoding, address translation and execution. · On-Chip Floating-Point Unit - Intel486 processors support the 32-, 64-, and 80-bit formats specified in IEEE standard 754. The unit is binary compatible with the 8087, Intel287TM, Intel387 coprocessors, and Intel OverDrive® processor. · On-Chip Cache with Cache Consistency Support - An 8-Kbyte, write-through, internal cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. · External Cache Control - Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency. · On-Chip Memory Management Unit - Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both memory segmentation and paging are supported. · Burst Cycles - Burst transfers allow a new double-word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. · Write Buffers - The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. · Bus Backoff - When another bus master needs control of the bus during a processor initiated bus cycle, the embedded IntelDX2 processor floats its bus signals, then restarts the cycle when the bus becomes available again. · Instruction Restart - Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications. · Dynamic Bus Sizing - External controllers can dynamically alter the effective width of the data bus. Bus widths of 8, 16, or 32 bits can be used.
Features
The embedded IntelDX2 processor offers these features: · 32-bit RISC-Technology Core - The embedded IntelDX2 processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. · Single Cycle Execution - Many instructions execute in a single clock cycle.
Other brands and names are the property of their respective owners.
Embedded IntelDX2 Processor
Family Members
Table 1 shows the embedded IntelDX2 processors and briefly describes their characteristics.
Table 1. The Embedded IntelDX2 Processor Family Product SB80486DX2SC50 A80486DX2SA66 Supply Voltage
Maximum Processor Frequency 50 MHz 66 MHz
Maximum External Bus Frequency 25 MHz 33 MHz
Package 208-Lead SQFP 168-Pin PGA
Embedded IntelDX2 Processor
HOW TO USE THIS DOCUMENT
PIN DESCRIPTIONS Pin Assignments
The following figures and tables show the pin assignments of each package type for the embedded IntelDX2 processor. Tables are provided showing the pin differences between the embedded IntelDX2 processor and other embedded Intel486 processor products. 208-Lead SQFP - Quad Flat Pack · Figure 2, Package Diagram for 208-Lead SQFP Embedded IntelDX2 Processor (pg. 4) · Table 2, Pinout Differences for 208-Lead SQFP Package (pg. 5) · Table 3, Pin Assignment for 208-Lead SQFP Package (pg. 6) · Table 4, Pin Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - Pin Grid Array · Figure 3, Package Diagram for 168-Pin PGA Embedded IntelDX2 Processor (pg. 10) · Table 5, Pinout Differences for 168-Pin PGA Package (pg. 11) · Table 6, Pin Assignment for 168-Pin PGA Package (pg. 12) · Table 7, Pin Cross Reference for 168-Pin PGA Package (pg. 14)
Embedded IntelDX2 Processor
VSS VCC VCC PCHK# BRDY# BOFF# BS16# BS8# VCC VSS INC RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W / R# VSS VCC BREQ BE0# BE1# BE2# BE3# VCC VSS M / IO# VCC D / C# PWT PCD VCC VSS VCC VCC EADS# A20M# RESET FLUSH# INTR NMI VSS
VSS LOCK# PLOCK# VCC BLAST# ADS# A2 VSS VCC VSS VCC A3 A4 A5 RESERVED# A6 A7 VCC A8 VSS VCC A9 A10 VCC VSS VCC A11 VSS A12 VCC A13 A14 VCC VSS A15 A16 VCC A17 VSS VCC TDI TMS A18 A19 A20 VCC VCC A21 A22 A23 A24 VSS
208-Lead SQFP Embedded IntelDX2 Processor
Top View
VSS VCC A25 A26 A27 A28 VCC A29 A30 A31 VSS DP0 D0 D1 D2 D3 D4 VCC VSS VCC VCC VSS VCC VCC VSS VCC D5 D6 VCC NC D7 DP1 D8 D9 VSS VCC VSS D10 D11 D12 D13 VSS VCC D14 D15 VCC VSS DP2 D16 VSS VCC VSS
VSS VCC VSS VCC VSS SRESET SMIACT# VCC VSS VCC INC INC SMI# FERR# NC TDO VCC INC INC IGNNE# STPCLK# D31 D30 VSS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24 VSS VCC DP3 D23 D22 D21 VSS VCC NC VSS VCC D20 D19 D18 VCC D17 VSS
A3227-01
Figure 2. Package Diagram for 208-Lead SQFP Embedded IntelDX2 Processor
Embedded IntelDX2 Processor
Table 2. Pinout Differences for 208-Lead SQFP Package Pin #
Embedded Intel486 SX Processor
VCC1 INC
Embedded IntelDX2 Processor
VCC INC INC INC FERR# INC INC IGNNE#
Embedded Write-Back Enhanced IntelDX4 Processor
VCC5 CLKMUL HITM# WB / WT# FERR# CACHE# INV IGNNE#
INC INC INC INC INC INC
NOTES: 1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to the VCC plane. 2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processor. However, new signals are defined for the location of the INC pins in the embedded IntelDX4 processor. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used.
Embedded IntelDX2 Processor
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2) Pin#
Description
VSS VCC VCC1 PCHK# BRDY# BOFF# BS16# BS8# VCC VSS INC2 RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W / R# VSS VCC BREQ BE0# BE1# BE2# BE3# VCC
Description
VSS VCC VSS VCC VSS SRESET SMIACT# VCC VSS VCC INC2 INC2 SMI# FERR# NC3 TDO VCC INC2 INC
Description
VSS VCC VSS D16 DP2 VSS VCC D15 D14 VCC VSS D13 D12 D11 D10 VSS VCC VSS D9 D8 DP1 D7 NC3 VCC D6 D5 VCC VSS VCC VCC VSS VCC VCC VSS VCC
Description
VSS A24 A23 A22 A21 VCC VCC A20 A19 A18 TMS TDI VCC VSS A17 VCC A16 A15 VSS VCC A14 A13 VCC A12 VSS A11 VCC VSS VCC A10 A9 VCC VSS A8 VCC
IGNNE# STPCLK# D31 D30 VSS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24
Embedded IntelDX2 Processor
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2) Pin#
Description
VSS M / IO# VCC D / C# PWT PCD VCC VSS VCC VCC EADS# A20M# RESET FLUSH# INTR NMI VSS
Description
VSS VCC DP3 D23 D22 D21 VSS VCC NC 3 VSS VCC D20 D19 D18 VCC D17 VSS
Description
D4 D3 D2 D1 D0 DP0 VSS A31 A30 A29 VCC A28 A27 A26 A25 VCC VSS
Description
A7 A6 RESERVED# A5 A4 A3 VCC VSS VCC VSS A2 ADS# BLAST# VCC PLOCK# LOCK# VSS
NOTES: 1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to the VCC plane. 2. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processors. However, signals are defined for the location of the INC pins in the IntelDX4 processor. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used. 3. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.
Embedded IntelDX2 Processor
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2) Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 161 160 159 158 154 153 152 151 149 148 147 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin # 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 99 93 92 91 87 85 84 83 79 78 75 74 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK D / C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HLDA HOLD IGNNE# INTR KEN# LOCK# M / IO# NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# Pin # 47 203 17 31 32 33 34 204 6 5 30 7 8 24 39 145 125 109 90 46 66 49 26 16 72 50 13 207 37 51 41 4 206 40 12 194 48 65 59 134 136 199 201 NC 67 96 127 INC 11 63 64 70 71 VCC 2 3 9 14 19 20 22 23 25 29 35 38 42 44 45 54 56 60 62 69 77 80 82 86 89 95 98 102 106 111 114 121 128 131 133 VSS 1 10 15 21 28 36 43 52 53 55 57 61 76 81 88 94 97 104 105 107 110 115 120 122 132 135 138 146 156 157 170 175 181 184 189
Embedded IntelDX2 Processor
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2) Address Pin # Data Pin # Control SRESET STPCLK# TCK TDI TDO TMS W / R# Pin # 58 73 18 168 68 167 27 NC INC V CC 137 139 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 VSS 208
Embedded IntelDX2 Processor
VCC VSS
168-Pin PGA Embedded IntelDX2 Processor
SRESET
Pin Side View
VCC RESERVED#
SMIACT#
FERR#
IGNNE#
FLUSH# A20M# HOLD KEN# STPCLK# BRDY#
LOCK#
RESET
VCC PLOCK# BLAST# A4
AHOLD EADS# BS16# BOFF#
PCHK#
A3226-01
Figure 3. Package Diagram for 168-Pin PGA Embedded IntelDX2 Processor
Embedded IntelDX2 Processor
Table 5. Pinout Differences for 168-Pin PGA Package Pin # A10 A12 B12 B13 J1 R17 S4 Embedded IntelDX2 Processor INC INC INC INC VCC INC NC Embedded Write-Back Enhanced IntelDX4 Processor INV HITM# CACHE# WB / WT# V CC5 CLKMUL VOLDET
Embedded IntelDX2 Processor
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2) Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 Description D20 D22 TCK D23 DP3 D24
Pin # D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G16 G17 H1 H2 H3 H15 H16 H17 J1 J2 J3 J15 J16 J17 K1 K2
Description BOFF#
VSS VCC
Pin # P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11
Description A29 A30 HLDA
VCC VSS
D10 HOLD
VCC VSS
DP1 D8 D15 KEN# RDY# BE3#
VSS VCC
A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2 BREQ PLOCK# PCHK# A28 A25
VCC VSS
INC1 INC
TDI IGNNE# INTR AHOLD D19 D21
VSS VSS VSS
D12 STPCLK#
VCC VSS VSS
D3 DP2 BRDY#
VCC VSS VCC
D5 D16 BE2# BE1# PCD
VSS VCC
INC1 INC1 TMS NMI TDO
VCC VCC VCC VCC
Embedded IntelDX2 Processor
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2) Pin # B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 Description EADS# D11 D18 CLK
VCC VCC
Pin # K3 K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1
Description D14 BE0#
VCC VSS VSS
Pin # R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Description A11 A8
A3 BLAST# INC1 A27 A26 A23 NC2 A14
D6 D7 PWT
VCC VSS VSS VCC
D27 D26 D28 D30 SRESET RESERVED# SMIACT# NC2 FERR# FLUSH# RESET BS16# D9 D13 D17 A20M# BS8#
VCC VSS
VSS VSS VSS VSS VSS
D2 D1 DP0 LOCK# M / IO# W / R# D0
A6 A4 ADS#
NOTES: 1. INC. Internal No Connect. These pins are not connected to any internal pad in the embedded IntelDX2 processors. However, signals are defined for the location of the INC pins in the IntelDX4 processor. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used. 2. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.
Embedded IntelDX2 Processor
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2) Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # Q14 R15 S16 Q12 S15 Q13 R13 Q11 S13 R12 S7 Q10 S5 R7 Q9 Q3 R5 Q4 Q8 Q5 Q7 S3 Q6 R2 S2 S1 R1 P2 P3 Q1 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin # P1 N2 N1 H2 M3 J2 L2 L3 F2 D1 E3 C1 G3 D2 K3 F3 J3 D3 C2 B1 A1 B2 A2 A4 A6 B6 C7 C6 C8 A8 C9 B8 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK D / C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HLDA HOLD IGNNE# INTR KEN# LOCK# M / IO# NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# Pin # D15 S17 A17 K15 J16 J15 F17 R16 D17 H15 Q15 C17 D16 C3 M15 N3 F1 H3 A5 B17 C14 C15 P15 E15 A15 A16 F15 N15 N16 B15 J17 Q17 Q16 L15 F16 C11 C16 B10 C12 NC C13 S4 INC A10 A12 A13 B12 B13 R17 Vcc B7 B9 B11 C4 C5 E2 E16 G2 G16 H16 J1 K2 K16 L16 M2 M16 P16 R3 R6 R8 R9 R10 R11 R14 Vss A7 A9 A11 B3 B4 B5 E1 E17 G1 G17 H1 H17 K1 K17 L1 L17 M1 M17 P17 Q2 R4 S6 S8 S9 S10 S11 S12 S14
Embedded IntelDX2 Processor
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 2 of 2) Address Pin # Data Pin # Control SRESET STPCLK# TCK TDI TDO TMS W / R# Pin # C10 G15 A3 A14 B16 B14 N17 NC INC Vcc Vss
Embedded IntelDX2 Processor
Pin Quick Reference
ADDRESS BUS A31-A4 A3-A2 I / O O
BE3# BE2# BE1# BE0#
DATA BUS D31-D0 I / O
DATA PARITY DP3-DP0 I / O
Embedded IntelDX2 Processor
Table 8. Embedded IntelDX2 Processor Pin Descriptions (Sheet 2 of 7) Symbol M / IO# D / C# W / R# Type O O O Name and Function Memory / Input-Output, Data / Control and Write / Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. M / IO# 0 0 0 0 1 1 1 1 D / C# 0 0 1 1 0 0 1 1 W / R# 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge HALT / Special Cycle (see details below) I / O Read I / O Write Code Read Reserved Memory Read Memory Write BE3# - BE0# 1110 1011 1011 A4-A2 000 000 100
BUS CYCLE DEFINITION
HALT / Special Cycle Cycle Name Shutdown HALT Stop Grant bus cycle LOCK# O
Bus Lock indicates that the current bus cycle is locked. The embedded IntelDX2 processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the embedded IntelDX2 processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits). For Intel486 processors with on-chip Floating-Point Unit, floating-point long reads and writes (64 bits) also require more than one bus cycle to complete. The embedded IntelDX2 processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. Normally PLOCK# and BLAST# are inverse of each other. However, during the first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip Floating-Point Unit) both PLOCK# and BLAST# are asserted. PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold.
PLOCK#
BUS CONTROL ADS# O Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold.
Embedded IntelDX2 Processor
INTERRUPTS RESET I
Embedded IntelDX2 Processor
SMIACT#
STPCLK#
BUS ARBITRATION BREQ O
Embedded IntelDX2 Processor
CACHE INVALIDATION AHOLD I
EADS#
CACHE CONTROL KEN# I
FLUSH#
PAGE CACHEABILITY PWT PCD O O
Embedded IntelDX2 Processor
BUS SIZE CONTROL
ADDRESS MASK A20M# I
TEST ACCESS PORT TCK I
Embedded IntelDX2 Processor
Table 8. Embedded IntelDX2 Processor Pin Descriptions (Sheet 7 of 7) Symbol FERR# Type O Name and Function The Floating Point Error pin is driven active when a floating point error occurs. FERR# is similar to the ERROR# pin on the Intel387 Math CoProcessor. FERR# is included for compatibility with systems using DOS type floating point error reporting. FERR# will not go active if FP errors are masked in FPU register. FERR# is active LOW, and is not floated during bus hold. When the Ignore Numeric Error pin is asserted the processor will ignore a numeric error and continue executing non-control floating point instructions, but FERR# will still be activated by the processor. When IGNNE# is de-asserted the processor will freeze on a non-control floating point instruction, if a previous floating point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is set. IGNNE# is active LOW and is provided with a small internal pull-up resistor. IGNNE# is asynchronous but setup and hold times t20 and t21 must be met to ensure recognition on any specific clock. Reserved is reserved for future use. This pin MUST be connected to an external pull-up resistor circuit. The recommended resistor value is 10 kOhms. The pull-up resistor must be connected only to the RESERVED# pin. Do not share this resistor with other pins requiring pull-ups.
NUMERIC ERROR REPORTING
IGNNE#
RESERVED PINS RESERVED# I
Embedded IntelDX2 Processor
Table 9. Output Pins Output Signal Name BREQ HLDA BE3#-BE0# PWT, PCD W / R#, M / IO#, D / C# LOCK# PLOCK# ADS# BLAST# PCHK# FERR# A3-A2 SMIACT# Active Level HIGH HIGH LOW HIGH HIGH / LOW LOW LOW LOW LOW LOW LOW HIGH LOW · · · · · · · · · Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States Previous State As per HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State Previous State Previous State
NOTES: The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Table 10. Input / Output Pins Output Signal Name D31-D0 DP3-DP0 A31-A4 Active Level HIGH HIGH HIGH · Floated During Address Hold Floated During Bus Hold · · · During Stop Grant and Stop Clock States Floated Floated Previous State
NOTES: The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Table 11. Test Pins Name TCK TDI TDO TMS Input or Output Input Input Output Input Sampled / Driven On N / A Rising Edge of TCK Failing Edge of TCK Rising Edge of TCK
Embedded IntelDX2 Processor
Table 12. Input Pins Name
CLK RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR NMI IGNNE# RESERVED# SMI# STPCLK# TCK TDI TMS LOW LOW HIGH HIGH HIGH Asynchronous Asynchronous Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down
Active Level
Synchronous / Asynchronous
Internal Pull-Up / Pull-Down
NOTES: 1. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is unused.
Embedded IntelDX2 Processor
ARCHITECTURAL AND FUNCTIONAL OVERVIEW
can change the value of this flag, the CPUID instruction is available. The actual state of the ID Flag bit is irrelevant and provides no significance to the hardware. This bit is cleared (reset to zero) upon device reset (RESET or SRESET) for compatibility with Intel486 processor designs that do not support the CPUID instruction. CPUID-instruction details are provided here for the embedded IntelDX2 processor. Refer to Intel Application Note AP-485 Intel Processor Identification with the CPUID Instruction (Order No. 241618) for a description that covers all aspects of the CPUID instruction and how it pertains to other Intel processors. 4.1.1 Operation of the CPUID Instruction
CPUID Instruction
The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX.
Table 13. CPUID Instruction Description OP CODE 0F A2 Instruction CPUID Processor Core Clocks 9 14 9 Parameter passed in EAX
(Input Value)
Description Vendor (Intel) ID String Processor Identification Undefined (Do Not Use)
Vendor ID String (ASCII Characters)
EBX EDX ECX
u (75) I (49) l (6C)
n (6E) e (65) e (65)
e (65) n (6E) t (74)
G (47) i (69) n (6E)
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel."
Embedded IntelDX2 Processor
Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon instruction execution are:
31--------------14 Processor Signature EAX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 0011 Model 3--0 XXXX Stepping
(Intel releases information about stepping numbers as needed) 31-------------------------------------------------0 Intel Reserved (Do Not Use) EBX ECX Intel Reserved Intel Reserved 31--------------------------------------2 Feature Flags EDX 0---------------------------------------0 1 1 VME 0 0 FPU
Identification After Reset
31--------------14 Processor Signature EDX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 0011 Model 3--0 XXXX Stepping
Processor Identification - Upon reset, the EDX register contains the processor signature:
(Intel releases information about stepping numbers as needed)
Boundary Scan (JTAG)
Device Identification
Tables 14 and 15 show the 32-bit code for the embedded IntelDX2 processor. This code is loaded into the Device Identification Register. Table 14. Boundary Scan Component Identification Code (3.3 Volt Processor)
Intel Architecture Type
Embedded IntelDX2 Processor
Table 15. Boundary Scan Component Identification Code (5 Volt Processor)
(Intel releases information about version numbers as needed)
Boundary Scan Register Bits and Bit Order
The following is the bit order of the embedded IntelDX2 processor boundary scan register: TDO A2, A3, A4, A5, RESERVED#, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, D0, D1, D2, D3, D4, D5, D6, D7, DP1, D8, D9, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, IGNNE#, FERR#, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D / C#, M / IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W / R#, HLDA, CLK, RESERVED#, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL TDI
The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N / C) signals of the embedded IntelDX2 processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the direction of bidirectional or threestate output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional. · WRCTL controls D31-D0 and DP3-DP0 · ABUSCTL controls A31-A2 · BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W / R#, BE0#, BE1#, BE2#, BE3#, M / IO#, D / C#, PWT, and PCD · MISCCTL controls PCHK#, HLDA, and BREQ
Embedded IntelDX2 Processor
ELECTRICAL SPECIFICATIONS Maximum Ratings
DC Specifications
Table 16 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the embedded IntelDX2 processor contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications. Table 16. Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature DC Voltage on Any Pin with Respect to Ground Supply Voltage VCC with Respect to VSS -65 °C to +110 °C -65 °C to +150 °C -0.5 V to VCC + 0.5 V -0.5 V to +6.5 V
Embedded IntelDX2 Processor
VIL VIH VIHC VOL
Parameter
-0.3 2.0 VCC -0.6
+0.8 VCC +0.3 VCC +0.3 0.4 0.2
Notes
Note 1
ILI IIH IIL I LO CIN COUT CCLK
Input Leakage Current Input Leakage Current SRESET Input Leakage Current Output Leakage Current Input Capacitance I / O or Output Capacitance CLK Capacitance
Embedded IntelDX2 Processor
AC Specifications
Note 2
t8 t8a t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t18a t19
Embedded IntelDX2 Processor
Note 3
t22 t23
NOTES: 1. TCK period CLK period. 2. Rise / Fall times are measured between 0.8V and 2.0V. Rise / Fall times can be relaxed by 1 ns per 10-ns increase in TCK period. 3. Parameters t30 - t37 are measured from TCK.
Embedded IntelDX2 Processor
Tx CLK
EADS#
BS8#, BS16#, KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET, IGNNE# A31-A4 (READ)
Figure 5. Input Setup and Hold Timing
Embedded IntelDX2 Processor
T2 CLK
RDY#, BRDY#
D31-D0, DP3-DP0
Figure 6. Input Setup and Hold Timing
T2 CLK
RDY#, BRDY#
D31-D0, DP3-DP0
VALID
MIN MAX
PCHK#
VALID
Figure 7. PCHK# Valid Delay Timing
Embedded IntelDX2 Processor
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID n
VALID n+1
D31-D0, DP3-DP0
VALID n
VALID n+1
BLAST#, PLOCK#
VALID n
VALID n+1
Figure 8. Output Valid Delay Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, FERR#
VALID
D31-D0, DP3-DP0
VALID
BLAST#, PLOCK#
VALID
Figure 9. Maximum Float Delay Timing
Embedded IntelDX2 Processor
0.8 V t28 t26 t29
Figure 10. TCK Waveform
TCK t30 TMS, TDI t32 TDO t34 OUTPUT t36 INPUT VALID VALID t37 VALID t 35 VALID VALID t33 t31
Figure 11. Test Signal Timing Diagram
Embedded IntelDX2 Processor
Capacitive Derating Curves
The following graphs are the capacitive derating curves for the embedded IntelDX2 processor. nom+7 nom+6 nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 125 150
nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 Capacitive Load (pF) 125 150
Embedded IntelDX2 Processor
nom+5 nom+4
Delay (ns)
nom+3 nom+2 nom+1 nom nom-1 nom-2
A3234-01
Figure 14. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition, 5 V Processor
nom+7 nom+6 nom+5 nom+4
Delay (ns)
nom+3 nom+2 nom+1 nom nom-1 nom-2
25 Note:
75 100 Capacitive Load (pF)
A3235-01
Figure 15. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition, 5 V Processor
Embedded IntelDX2 Processor
MECHANICAL DATA
This section describes the packaging dimensions and thermal specifications for the embedded IntelDX2 processor.
Package Dimensions
25.50 (ref)
208 157 .40 Min 0.13 + 0.12-0.08 156 0° Min 7° Max
Top View
0.13 Min 0.25 Max
NOTE: Length measurements same as width measurements 1.76 Max Tolerance Window for Lead Skew from Theoretical True Position 0.10 Max
Units: mm
A3262-01
Figure 16. 208-Lead SQFP Package Dimensions
Embedded IntelDX2 Processor
Figure 17. Principal Dimensions and Data for 168-Pin Pin Grid Array Package
Table 24. 168-Pin Ceramic PGA Package Dimensions Symbol A A1 A2 A3 B D D1 e1 L N S1 1.52 Millimeters Min 3.56 0.64 2.8 1.14 0.43 44.07 40.51 2.29 2.54 168 2.54 0.060 Max 4.57 1.14 3.5 1.40 0.51 44.83 40.77 2.79 3.30 SOLID LID SOLID LID Notes Min 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 168 0.100 Inches Max 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID LID SOLID LID Notes
Embedded IntelDX2 Processor
Table 25. Ceramic PGA Package Dimension Symbols Letter or Symbol A A1 A2 A3 B D D1 e1 L S1 Description of Dimensions Distance from seating plane to highest point of body Distance between seating plane and base plane (lid) Distance from base plane to highest point of body Distance from seating plane to bottom of body Diameter of terminal lead pin Largest overall package dimension of length A body length dimension, outer lead center to outer lead center Linear spacing between true lead position centerlines Distance from seating plane to end of lead Other body dimension, outer lead center to edge of body
NOTES: 1. Controlling dimension: millimeter. 2. Dimension "e1" ("e") is non-cumulative. 3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415-0.0430 inch. 4. Dimensions "B", "B1" and "C" are nominal. 5. Details of Pin 1 identifier are optional.
Embedded IntelDX2 Processor
Package Thermal Specifications
Where TJ, TA, TC equals Junction, Ambient and Case Temperature respectively. JC, JA equals Junction-to-Case and Junction-to-Ambient thermal Resistance, respectively. P is defined as Maximum Power Consumption. Values for JA and JC are given in the following tables for each product at its maximum operating frequencies. Maximum TA is shown for each product operating at various processor frequencies (twice the CLK frequencies).
Table 26. Thermal Resistance, JA (°C / W) JA vs. Airflow - ft / min. (m / sec) 0 (0) 208-Lead SQFP (3.3V) - Without Heat Sink 168-Pin PGA (5V) - Without Heat Sink 168-Pin PGA (5V) - With Heat Sink
0.350" high omnidirectional heat sink.
Table 27. Thermal Resistance, JC (°C / W) JC vs. Airflow - ft / min. (m / sec) 0 (0) 0 208-Lead SQFP (3.3V) 168-Pin PGA (5V) 3.5 1.5 200 (1.01) 200 6.0 - 400 (2.03) 400 6.0 - 600 (3.04) 600 6.0 -
Table 28. Maximum Tambient, TA max (°C) Airflow - ft / min. (m / sec) Freq. (MHz) IntelDX2 Processor 208-Lead SQFP (3.3V) Without Heat Sink 168-Pin PGA (5V) Without Heat Sink 168-Pin PGA (5V) With Heat Sink 40 50 50 66 50 66 57 51 15 -4 33 19 70 67 26 11 56 48 73 70 35 22 65 59 75 73 46 36 69 65 0 (0) 200 (1.01) 400 (2.03) 600 (3.04)
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