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EMBEDDED WRITE-BACK ENHANCED IntelDX4 PROCESSOR

- 208-Lead Shrink Quad Flat Pack (SQFP)

EMBEDDED WRITE-BACK ENHANCED IntelDX4 PROCESSOR
s Up to 100 MHz Operation s Integrated Floating-Point Unit s Speed-Multiplying Technology s 32-Bit RISC Technology Core s 16-Kbyte Write-Back Cache s 3.3 V Core Operation with 5 V Tolerant s SL Technology s Data Bus Parity Generation and Checking s Boundary Scan (JTAG) s 3.3-Volt Processor, 75 MHz, 25 MHz CLK
- 208-Lead Shrink Quad Flat Pack (SQFP)
s 3.3-Volt Processor, 100 MHz, 33 MHz CLK
I / O Buffers
s Burst Bus Cycles s Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices
- 208-Lead Shrink Quad Flat Pack (SQFP) - 168-Pin Pin Grid Array (PGA) s Binary Compatible with Large Software Base
64-Bit Interunit Transfer Bus
32-Bit Data Bus 32-Bit Data Bus Linear Address 32 PCD PWT
CLKMUL Core Clock Clock Multiplier CLK
Barrel Shifter Register File ALU
Base / Index Bus
Segmentation Unit Descriptor Registers Limit and Attribute PLA
Bus Interface Cache Unit
A31-A2 BE3#- BE0#
Paging Unit
Address Drivers Write Buffers 4 x 32 Data Bus Transceivers Bus Control
ADS# W / R# D / C# M / IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# FERR# IGNNE# STPCLK# D31-D0
Physical Address
Translation Lookaside Buffer
16 Kbyte Cache
Displacement Bus
Request Sequencer Prefetcher Burst Bus Control 32-Byte Code Queue 2 x 16 Bytes Bus Size Control Cache Control Parity Generation and Control Boundary Scan Control
MicroInstruction
BRDY# BLAST#
BS16# BS8#
Floating Point Unit
Control & Protection Test Unit
Code Stream Instruction Decode
KEN# FLUSH# AHOLD EADS# CACHE# HITM# INV WB / WT#
Floating Point Register File
Control ROM
Decoded Instruction Path
PCHK# DP3-DP0
TCK TMS TDI TDO
A3232-01
Contents
EMBEDDED WRITE-BACK ENHANCED IntelDX4 PROCESSOR
Contents
Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26.
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition ................................................... 40 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition ................................................... 40 Typical Loading Delay versus Load Capacitance in Mixed Voltage System .............. 41 208-Lead SQFP Package Dimensions .......................................... 42 Principal Dimensions and Data for 168-Pin Grid Array Package ....................... 43
The Embedded Write-Back Enhanced IntelDX4 Processor Family .................... 2 Pinout Differences for 208-Lead SQFP Package ................................... 5 Pin Assignment for 208-Lead SQFP Package ...................................... 6 Pin Cross Reference for 208-Lead SQFP Package .................................. 8 Pinout Differences for 168-Pin PGA Package ..................................... 11 Pin Assignment for 168-Pin PGA Package ....................................... 12 Pin Cross Reference for 168-Pin PGA Package ................................... 14 Embedded Write-Back Enhanced IntelDX4 Processor Pin Descriptions ............... 16 Output Pins ............................................................... 24 Input / Output Pins ........................................................... 24 Test Pins ................................................................. 25 Input Pins ................................................................. 25 CPUID Instruction Description ................................................. 26 Boundary Scan Component Identification Code (Write-Through / Standard Bus Mode) ...... 28 Boundary Scan Component Identification Code (Write-Back / Enhanced Bus Mode) ........ 29 Absolute Maximum Ratings ................................................... 30 Operating Supply Voltages ................................................... 30 DC Specifications ........................................................... 31 ICC Values ................................................................ 32 AC Characteristics .......................................................... 33 AC Specifications for the Test Access Port ....................................... 35 168-Pin Ceramic PGA Package Dimensions ...................................... 43 Ceramic PGA Package Dimension Symbols ...................................... 44 Thermal Resistance, JA (°C / W) ............................................... 45 Thermal Resistance, JC (°C / W) ............................................... 45 Maximum Tambient, TA max (°C) ................................................ 45
Embedded Write-Back Enhanced IntelDX4 Processor
INTRODUCTION
Features
The Embedded Write-Back Enhanced IntelDX4 processor offers these features: · 32-bit RISC-Technology Core - The Embedded Write-Back Enhanced IntelDX4 processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. · Single Cycle Execution - Many instructions execute in a single clock cycle. · Instruction Pipelining - Overlapped instruction fetching, decoding, address translation and execution. · On-Chip Floating-Point Unit - Intel486 processors support the 32-, 64-, and 80-bit formats specified in IEEE standard 754. The unit is binary compatible with the 8087, Intel287TM, Intel387 coprocessors, and Intel OverDrive® processor. · On-Chip Cache with Cache Consistency Support - A 16-Kbyte internal cache is used for both data and instructions. It is configurable to be write-back or write-through on a line-by-line basis. The internal cache implements a modified MESI protocol, which is applicable to uniprocessor systems. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. · External Cache Control - Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency. · On-Chip Memory Management Unit - Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both memory segmentation and paging are supported. · Burst Cycles - Burst transfers allow a new double-word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. Data written from the processor to memory can also be burst transfers. · Write Buffers - The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. 1
Embedded Write-Back Enhanced IntelDX4 Processor
Family Members
Table 1 shows the Embedded Write-Back Enhanced IntelDX4 processors and briefly describes their characteristics.
Table 1. The Embedded Write-Back Enhanced IntelDX4 Processor Family Product FC80486DX4WB75 FC80486DX4WB100 A80486DX4WB100 Supply Voltage
Maximum Processor Frequency 75 MHz 100 MHz 100 MHz
Maximum External Bus Frequency 25 MHz 33 MHz 33 MHz
Package 208-Lead SQFP 208-Lead SQFP 168-Pin PGA
Embedded Write-Back Enhanced IntelDX4 Processor
HOW TO USE THIS DOCUMENT
PIN DESCRIPTIONS Pin Assignments
The following figures and tables show the pin assignments of each package type for the Embedded Write-Back Enhanced IntelDX4 processor. Tables are provided showing the pin differences between the Embedded Write-Back Enhanced IntelDX4 processor and other embedded Intel486 processor products. 208-Lead SQFP - Quad Flat Pack · Figure 2, Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4 Processor (pg. 4) · Table 2, Pinout Differences for 208-Lead SQFP Package (pg. 5) · Table 3, Pin Assignment for 208-Lead SQFP Package (pg. 6) · Table 4, Pin Cross Reference for 208-Lead SQFP Package (pg. 8) 168-Pin PGA - Pin Grid Array · Figure 3, Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4 Processor (pg. 10) · Table 5, Pinout Differences for 168-Pin PGA Package (pg. 11) · Table 6, Pin Assignment for 168-Pin PGA Package (pg. 12) · Table 7, Pin Cross Reference for 168-Pin PGA Package (pg. 14)
Embedded Write-Back Enhanced IntelDX4 Processor
VSS VCC VCC5 PCHK# BRDY# BOFF# BS16# BS8# VCC VSS CLKMUL RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W / R# VSS VCC BREQ BE0# BE1# BE2# BE3# VCC VSS M / IO# VCC D / C# PWT PCD VCC VSS VCC VCC EADS# A20M# RESET FLUSH# INTR NMI VSS
VSS LOCK# PLOCK# VCC BLAST# ADS# A2 VSS VCC VSS VCC A3 A4 A5 RESERVED# A6 A7 VCC A8 VSS VCC A9 A10 VCC VSS VCC A11 VSS A12 VCC A13 A14 VCC VSS A15 A16 VCC A17 VSS VCC TDI TMS A18 A19 A20 VCC VCC A21 A22 A23 A24 VSS
208-Lead SQFP Embedded Write-Back Enhanced IntelDX4 Processor
Top View
VSS VCC A25 A26 A27 A28 VCC A29 A30 A31 VSS DP0 D0 D1 D2 D3 D4 VCC VSS VCC VCC VSS VCC VCC VSS VCC D5 D6 VCC NC D7 DP1 D8 D9 VSS VCC VSS D10 D11 D12 D13 VSS VCC D14 D15 VCC VSS DP2 D16 VSS VCC VSS
VSS VCC VSS VCC VSS SRESET SMIACT# VCC VSS VCC HITM# WB / WT# SMI# FERR# NC TDO VCC CACHE# INV IGNNE# STPCLK# D31 D30 VSS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24 VSS VCC DP3 D23 D22 D21 VSS VCC NC VSS VCC D20 D19 D18 VCC D17 VSS
A3230-01
Figure 2. Package Diagram for 208-Lead SQFP Embedded Write-Back Enhanced IntelDX4 Processor
Embedded Write-Back Enhanced IntelDX4 Processor
Table 2. Pinout Differences for 208-Lead SQFP Package Pin #
Embedded Intel486 SX Processor
VCC1 INC2 INC INC INC INC INC INC
Embedded IntelDX2 Processor
VCC INC INC INC FERR# INC INC IGNNE#
Embedded Write-Back Enhanced IntelDX4 Processor
VCC5 CLKMUL HITM# WB / WT# FERR# CACHE# INV IGNNE#
NOTES: 1. This pin location is for the VCC5 pin on the embedded IntelDX4 processor. For compatibility with 3.3V processors that have 5V-tolerant input buffers (i.e., embedded IntelDX4 processors), this pin should be connected to a VCC trace, not to the VCC plane. 2. INC. Internal No Connect. These pins are not connected to any internal pad. However, signals are defined for the location of the INC pins in the embedded IntelDX4 processor. One system design can accommodate any one of these processors provided the purpose of each INC pin is understood before it is used.
Embedded Write-Back Enhanced IntelDX4 Processor
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 1 of 2) Pin#
Description
VSS VCC VCC5 PCHK# BRDY# BOFF# BS16# BS8# VCC VSS CLKMUL RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK VCC HLDA W / R# VSS VCC BREQ BE0# BE1# BE2# BE3# VCC
Description
VSS VCC VSS VCC VSS SRESET SMIACT# VCC VSS VCC HITM# WB / WT# SMI# FERR# NC1 TDO VCC CACHE# INV IGNNE# STPCLK# D31 D30 VSS VCC D29 D28 VCC VSS VCC D27 D26 D25 VCC D24
Description
VSS VCC VSS D16 DP2 VSS VCC D15 D14 VCC VSS D13 D12 D11 D10 VSS VCC VSS D9 D8 DP1 D7 NC1 VCC D6 D5 VCC VSS VCC VCC VSS VCC VCC VSS VCC
Description
VSS A24 A23 A22 A21 VCC VCC A20 A19 A18 TMS TDI VCC VSS A17 VCC A16 A15 VSS VCC A14 A13 VCC A12 VSS A11 VCC VSS VCC A10 A9 VCC VSS A8 VCC
Embedded Write-Back Enhanced IntelDX4 Processor
Table 3. Pin Assignment for 208-Lead SQFP Package (Sheet 2 of 2) Pin#
Description
VSS M / IO# VCC D / C# PWT PCD VCC VSS VCC VCC EADS# A20M# RESET FLUSH# INTR NMI VSS
Description
VSS VCC DP3 D23 D22 D21 VSS VCC
Description
D4 D3 D2 D1 D0 DP0 VSS A31 A30 A29 VCC A28 A27 A26 A25 VCC VSS
Description
A7 A6 RESERVED# A5 A4 A3 VCC VSS VCC VSS A2 ADS# BLAST# VCC PLOCK# LOCK# VSS
VSS VCC D20 D19 D18 VCC D17 VSS
NOTE: 1. NC. Do Not Connect. These pins should always remain unconnected. Connection of NC pins to VCC, or VSS or to any other signal can result in component malfunction or incompatibility with future steppings of the Intel486 processors.
Embedded Write-Back Enhanced IntelDX4 Processor
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 1 of 2) Address A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # 202 197 196 195 193 192 190 187 186 182 180 178 177 174 173 171 166 165 164 161 160 159 158 154 153 152 151 149 148 147 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin # 144 143 142 141 140 130 129 126 124 123 119 118 117 116 113 112 108 103 101 100 99 93 92 91 87 85 84 83 79 78 75 74 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CACHE# CLK CLKMUL D / C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR INV KEN# LOCK# M / IO# Pin # 47 203 17 31 32 33 34 204 6 5 30 7 8 70 24 11 39 145 125 109 90 46 66 49 63 26 16 72 50 71 13 207 37 NC 67 96 127 VCC5 3 VCC 2 9 14 19 20 22 23 25 29 35 38 42 44 45 54 56 60 62 69 77 80 82 86 89 95 98 102 106 111 114 121 128 131 VSS 1 10 15 21 28 36 43 52 53 55 57 61 76 81 88 94 97 104 105 107 110 115 120 122 132 135 138 146 156 157 170 175 181
Embedded Write-Back Enhanced IntelDX4 Processor
Table 4. Pin Cross Reference for 208-Lead SQFP Package (Sheet 2 of 2) Address Pin # Data Pin # Control NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# TCK TDI TDO TMS WB / WT# W / R# Pin # 51 41 4 206 40 12 194 48 65 59 58 73 18 168 68 167 64 27 NC V CC5 VCC 133 134 136 137 139 150 155 162 163 169 172 176 179 183 185 188 191 198 200 205 V SS 184 189 199 201 208
Embedded Write-Back Enhanced IntelDX4 Processor
J VCC5
VSS VOLDET
168-Pin PGA Embedded Write-Back Enhanced IntelDX4 Processor
SRESET
Pin Side View
VSS VCC RESERVED#
A9 VCC VSS
HITM# CACHE# SMIACT#
FERR#
IGNNE#
FLUSH# A20M# HOLD KEN# STPCLK# BRDY#
LOCK#
RESET
VCC PLOCK# BLAST# A4
AHOLD EADS# BS16# BOFF#
PCHK# CLKMUL ADS#
A3231-01
Figure 3. Package Diagram for 168-Pin PGA Embedded Write-Back Enhanced IntelDX4 Processor
Embedded Write-Back Enhanced IntelDX4 Processor
Table 5. Pinout Differences for 168-Pin PGA Package Pin # A10 A12 B12 B13 J1 R17 S4 Embedded IntelDX2 Processor INC INC INC INC V CC INC NC Embedded Write-Back Enhanced IntelDX4 Processor INV HITM# CACHE# WB / WT# V CC5 CLKMUL VOLDET
Embedded Write-Back Enhanced IntelDX4 Processor
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 1 of 2) Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 Description D20 D22 TCK D23 DP3 D24
Pin # D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G16 G17 H1 H2 H3 H15 H16 H17 J1 J2 J3 J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2
Description BOFF#
VSS VCC
Pin # P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17
Description A29 A30 HLDA
VCC VSS
D10 HOLD
VCC VSS
DP1 D8 D15 KEN# RDY# BE3#
VSS VCC
A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2 BREQ PLOCK# PCHK# A28 A25
VCC VSS
HITM# INC TDI IGNNE# INTR AHOLD D19 D21
VSS VSS VSS
D12 STPCLK#
VCC VSS VSS
D3 DP2 BRDY#
VCC VSS VCC5
D5 D16 BE2# BE1# PCD
VSS VCC
CACHE# WB / WT# TMS NMI TDO EADS# D11 D18 CLK
VCC VCC
VCC VCC VCC VCC
D14 BE0#
VCC VSS VSS
A11 A8
A3 BLAST# CLKMUL
Embedded Write-Back Enhanced IntelDX4 Processor
Table 6. Pin Assignment for 168-Pin PGA Package (Sheet 2 of 2) Pin # C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 Description D27 D26 D28 D30 SRESET RESERVED# SMIACT# NC FERR# FLUSH# RESET BS16# D9 D13 D17 A20M# BS8# Pin # L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1 Description D7 PWT
VCC VSS VSS VCC
Pin # S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17
Description A27 A26 A23 VOLDET A14
VCC VSS
VSS VSS VSS VSS VSS
D2 D1 DP0 LOCK# M / IO# W / R# D0
A6 A4 ADS#
Embedded Write-Back Enhanced IntelDX4 Processor
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 1 of 2) Addres s A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pin # Q14 R15 S16 Q12 S15 Q13 R13 Q11 S13 R12 S7 Q10 S5 R7 Q9 Q3 R5 Q4 Q8 Q5 Q7 S3 Q6 R2 S2 S1 R1 P2 P3 Q1 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Pin # P1 N2 N1 H2 M3 J2 L2 L3 F2 D1 E3 C1 G3 D2 K3 F3 J3 D3 C2 B1 A1 B2 A2 A4 A6 B6 C7 C6 C8 A8 C9 B8 Control A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK CLKMUL CACHE# D / C# DP0 DP1 DP2 DP3 EADS# FERR# FLUSH# HITM# HLDA HOLD IGNNE# INTR INV KEN# LOCK# M / IO# 14 Pin # D15 S17 A17 K15 J16 J15 F17 R16 D17 H15 Q15 C17 D16 C3 R17 B12 M15 N3 F1 H3 A5 B17 C14 C15 A12 P15 E15 A15 A16 A10 F15 N15 N16 NC C13 INC A13 Vcc5 J1 Vcc B7 B9 B11 C4 C5 E2 E16 G2 G16 H16 K2 K16 L16 M2 M16 P16 R3 R6 R8 R9 R10 R11 R14 Vss A7 A9 A11 B3 B4 B5 E1 E17 G1 G17 H1 H17 K1 K17 L1 L17 M1 M17 P17 Q2 R4 S6 S8 S9 S10 S11 S12 S14
Embedded Write-Back Enhanced IntelDX4 Processor
Table 7. Pin Cross Reference for 168-Pin PGA Package (Sheet 2 of 2) Addres s Pin # Data Pin # Control NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# TCK TDI TDO TMS VOLDET WB / WT# W / R# Pin # B15 J17 Q17 Q16 L15 F16 C11 C16 B10 C12 C10 G15 A3 A14 B16 B14 S4 B13 N17 NC INC Vcc5 Vcc Vss
Embedded Write-Back Enhanced IntelDX4 Processor
Pin Quick Reference
ADDRESS BUS A31-A4 A3-A2 I / O O
BE3# BE2# BE1# BE0#
DATA PARITY DP3-DP0 I / O
Embedded Write-Back Enhanced IntelDX4 Processor
Table 8. Embedded Write-Back Enhanced IntelDX4 Processor Pin Descriptions (Sheet 2 of 8) Symbol M / IO# D / C# W / R# Type O O O Name and Function Memory / Input-Output, Data / Control and Write / Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. M / IO# 0 0 0 0 1 1 1 1 D / C# 0 0 1 1 0 0 1 1 Cycle Name Shutdown HALT Stop Grant bus cycle LOCK# O W / R# 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge HALT / Special Cycle (see details below) I / O Read I / O Write Code Read Reserved Memory Read Memory Write HALT / Special Cycle BE3# - BE0# 1110 1011 1011 A4-A2 000 000 100
BUS CYCLE DEFINITION
Bus Lock indicates that the current bus cycle is locked. The Embedded WriteBack Enhanced IntelDX4 processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the Embedded Write-Back Enhanced IntelDX4 processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits). For Intel486 processors with on-chip FloatingPoint Unit, floating-point long reads and writes (64 bits) also require more than one bus cycle to complete. The Embedded Write-Back Enhanced IntelDX4 processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. Normally PLOCK# and BLAST# are inverse of each other. However, during the first bus cycle of a 64-bit floating-point write (for Intel486 processors with on-chip Floating-Point Unit) both PLOCK# and BLAST# are asserted. PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold.
PLOCK#
BUS CONTROL ADS# O Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold.
Embedded Write-Back Enhanced IntelDX4 Processor
INTERRUPTS RESET I
Embedded Write-Back Enhanced IntelDX4 Processor
SMIACT#
STPCLK#
BUS ARBITRATION BREQ O
Embedded Write-Back Enhanced IntelDX4 Processor
CACHE INVALIDATION AHOLD I
EADS#
CACHE CONTROL KEN# I
FLUSH#
PAGE CACHEABILITY PWT PCD O O
Embedded Write-Back Enhanced IntelDX4 Processor
BUS SIZE CONTROL
ADDRESS MASK A20M# I
TEST ACCESS PORT TCK I
NUMERIC ERROR REPORTING FERR# O
Embedded Write-Back Enhanced IntelDX4 Processor
WRITE-BACK ENHANCED MODE CACHE# O
FLUSH#
HITM#
PLOCK#
SRESET
Embedded Write-Back Enhanced IntelDX4 Processor
CLKMUL, VCC5, AND VOLDET CLKMUL I
VOLDET
RESERVED PINS RESERVED# I
Embedded Write-Back Enhanced IntelDX4 Processor
Table 9. Output Pins Output Signal Name
BREQ HLDA BE3#-BE0# PWT, PCD W / R#, M / IO#, D / C# LOCK# PLOCK# ADS# BLAST# PCHK# FERR# A3-A2 SMIACT# CACHE# HITM# VOLDET
Active Level
HIGH HIGH LOW HIGH HIGH / LOW LOW LOW LOW LOW LOW LOW HIGH LOW LOW LOW LOW
Floated During Address Hold
Floated During Bus Hold
During Stop Grant and Stop Clock States
Previous State1 As per HOLD
Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State
Previous State Previous State HIGH2 HIGH2 LOW
NOTES: 1. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating. 2. For the case of snoop cycles (via EADS#) during Stop Grant state, CACHE# and HITM# can go active depending on the snoop hit in the internal cache.
Table 10. Input / Output Pins Output Signal Name D31-D0 DP3-DP0 A31-A4 Active Level HIGH HIGH HIGH · Floated During Address Hold Floated During Bus Hold · · · During Stop Grant and Stop Clock States Floated Floated Previous State
NOTE: The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Embedded Write-Back Enhanced IntelDX4 Processor
Table 11. Test Pins Name TCK TDI TDO TMS Input or Output Input Input Output Input Sampled / Driven On N / A Rising Edge of TCK Failing Edge of TCK Rising Edge of TCK
Table 12. Input Pins (Sheet 1 of 2) Name CLK RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR NMI IGNNE# RESERVED# SMI# STPCLK# INV HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW LOW HIGH Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Synchronous Pull-Up Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Active Level Synchronous / Asynchronous Internal Pull-Up / Pull-Down
NOTE: 1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K pullup resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external 10-K pull-up resistor is recommended.
Embedded Write-Back Enhanced IntelDX4 Processor
Table 12. Input Pins (Sheet 2 of 2) Name WB / WT# CLKMUL TCK TDI TMS Active Level HIGH / LOW HIGH HIGH HIGH HIGH Synchronous / Asynchronous Synchronous Internal Pull-Up / Pull-Down Pull-Down Pull-Up1 Pull-Up Pull-Up Pull-Up
NOTE: 1. Even though STPCLK# and CLKMUL have internal pull-up resistors, they cannot be left floating. An external 10-K pullup resistor is needed if the STPCLK# pin is unused. CLKMUL must be driven to a valid logic level. If tied HIGH, an external 10-K pull-up resistor is recommended.
ARCHITECTURAL AND FUNCTIONAL OVERVIEW
CPUID Instruction
The Embedded Write-Back Enhanced IntelDX4 processor supports the CPUID instruction (see Table 13). Because not all Intel processors support the CPUID instruction, a simple test can determine if the instruction is supported. The test involves the
The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX.
Table 13. CPUID Instruction Description OP CODE 0F A2 Instruction CPUID Processor Core Clocks 9 14 9 Parameter passed in EAX
(Input Value)
Description Vendor (Intel) ID String Processor Identification Undefined (Do Not Use)
Embedded Write-Back Enhanced IntelDX4 Processor
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel." The state of the WB / WT# input pin is sampled by the processor on the falling edge of the RESET signal. If WB / WT# is LOW, the processor is configured to operate in Write-Through / Standard Bus mode. If HIGH, it is configured to operate in Write-Back / Enhanced Bus mode. The value of the "Model" field of the processor signature register depends on the bus mode for which the processor is configured. Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon instruction execution are:
31--------------14 Processor Signature for Write-Through / Standard Bus mode Processor Signature for WriteBack / Enhanced Bus mode EAX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 1000 Model 3--0 XXXX Stepping
(Do Not Use) Intel Reserved
00 Processor Type
0100 Family
1001 Model
XXXX Stepping
(Intel releases information about stepping numbers as needed) 31-------------------------------------------------0 Intel Reserved (Do Not Use) EBX ECX Intel Reserved Intel Reserved 31--------------------------------------2 Feature Flags EDX 0---------------------------------------0 1 1 VME 0 0 FPU
Embedded Write-Back Enhanced IntelDX4 Processor
Identification After Reset
31--------------14 13, 12 00 Processor Type 11--8 0100 Family 7--4 1000 Model 3--0 XXXX Stepping
Processor Identification - Upon reset, the EDX register contains the processor signature:
Processor Signature for Write-Through / Standard Bus mode Processor Signature for WriteBack / Enhanced Bus mode EDX (Do Not Use) Intel Reserved
(Do Not Use) Intel Reserved
00 Processor Type
0100 Family
1001 Model
XXXX Stepping
(Intel releases information about stepping numbers as needed)
Boundary Scan (JTAG)
Device Identification
Tables 14 and 15 show the 32-bit code for the Embedded Write-Back Enhanced IntelDX4 processor. This code is loaded into the Device Identification Register.
Table 14. Boundary Scan Component Identification Code (Write-Through / Standard Bus Mode)
Intel Architecture Type
31--28 XXXX
Embedded Write-Back Enhanced IntelDX4 Processor
Table 15. Boundary Scan Component Identification Code (Write-Back / Enhanced Bus Mode)
31--28 XXXX
(Intel releases information about version numbers as needed)
Boundary Scan Register Bits and Bit Order TDO A2, A3, A4, A5, RESERVED#, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, D0, D1, D2, D3, D4, D5, D6, D7, DP1, D8, D9, D10, D11, D12, D13, D14, D15, DP2, D16, D17, D18, D19, D20, D21, D22, D23, DP3, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, IGNNE#, INV, CACHE#, FERR#, SMI#, WB / WT#, HITM#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D / C#, M / IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W / R#, HLDA, CLK, AHOLD, HOLD, KEN#, RDY#, CLKMUL, BS8#, BS16#, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL TDI
The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N / C) signals of the Embedded Write-Back Enhanced IntelDX4 processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the direction of bidirectional or three-state output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional. · WRCTL controls D31-D0 and DP3-DP0 · ABUSCTL controls A31-A2 · BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W / R#, BE0#, BE1#, BE2#, BE3#, M / IO#, D / C#, PWT, PCD, and CACHE# · MISCCTL controls PCHK#, HLDA, BREQ, and HITM# The following is the bit order of the Embedded WriteBack Enhanced IntelDX4 processor boundary scan register:
Embedded Write-Back Enhanced IntelDX4 Processor
ELECTRICAL SPECIFICATIONS Maximum Ratings
DC Specifications
Table 16 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the Embedded Write-Back Enhanced IntelDX4 processorcontains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications. Table 16. Absolute Maximum Ratings
Case Temperature under Bias Storage Temperature DC Voltage on Any Pin with Respect to Ground Supply Voltage VCC with Respect to VSS Reference Voltage VCC5 with Respect to VSS Transient Voltage on any Input -65 °C to +110 °C -65 °C to +150 °C -0.5 V to VCC5 + 0.5 V -0.5 V to +4.6 V -0.5 V to +6.5 V The lesser of: VCC5 + 1.6 V or 6.5 V 55 mA
Current Sink on VCC5
Embedded Write-Back Enhanced IntelDX4 Processor
VIL VIH VIHC VOL
Parameter
-0.3 2.0 VCC5 -0.6
+0.8 VCC5 +0.3 VCC5 +0.3 0.45 0.45 0.40 0.20
Notes
Note 2
VOH ICC5 ILI IIH IIL ILO CIN COUT CCLK
Embedded Write-Back Enhanced IntelDX4 Processor
AC Specifications
Note 3
t8 t8a t9 t10 t11 t12 t13 t14 t15 t16 t17
Embedded Write-Back Enhanced IntelDX4 Processor
Note 4
t22 t23
Embedded Write-Back Enhanced IntelDX4 Processor
Tx CLK
INV, EADS#
BS8#, BS16#, KEN#, WB / WT#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET, IGNNE# A31-A4 (READ)
Figure 5. Input Setup and Hold Timing
Embedded Write-Back Enhanced IntelDX4 Processor
T2 CLK
RDY#, BRDY#
D31-D0, DP3-DP0
Figure 6. Input Setup and Hold Timing
T2 CLK
RDY#, BRDY#
D31-D0 DP3-DP0
VALID
MIN MAX
PCHK#
VALID
Figure 7. PCHK# Valid Delay Timing
Embedded Write-Back Enhanced IntelDX4 Processor
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, FERR#, CACHE#, HITM#
VALID n
VALID n+1
D31-D0, DP3-DP0
VALID n
VALID n+1
SMIACT#, BLAST#, PLOCK#
VALID n
VALID n+1
Figure 8. Output Valid Delay Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, CACHE#
VALID
D31-D0, DP3-DP0
VALID
BLAST#, PLOCK#
VALID
Figure 9. Maximum Float Delay Timing
Embedded Write-Back Enhanced IntelDX4 Processor
0.8 V t28 t26 t29
Figure 10. TCK Waveform
TCK t 30 TMS TDI t32 TDO t34 OUTPUT t36 INPUT VALID VALID t37 VALID t35 VALID t31
VALID t 33
Figure 11. Test Signal Timing Diagram
Embedded Write-Back Enhanced IntelDX4 Processor
Capacitive Derating Curves
These graphs are the capacitive derating curves for the Embedded Write-Back Enhanced IntelDX4 processor.
nom+7 nom+6 nom+5
Delay (ns)
nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2
25 Note:
75 100 Capacitive Load (pF)
A3238-01
Figure 12. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition
nom+5 nom+4
Delay (ns)
nom+3 nom+2 nom+1 nom nom-1 nom-2
A3237-01
Figure 13. Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition
Embedded Write-Back Enhanced IntelDX4 Processor
In a mixed voltage system (processors at 3 volts, peripherals at 5 volts), the bus is driven to 5 volts by the peripheral logic. Therefore, the processor must discharge the capacitance on the bus from 5 volts to 0 volts, which takes more time than the 3 volts to 0 volts transition. Inaccurate capacitive derating impacts timing margins and may result in system failures under certain load conditions.
When designing for higher loads in mixed voltage systems, timing margins should be evaluated based on the derating curves shown in Figure 14. For more accurate delay prediction, use I / O buffer models.
Figure 14. Typical Loading Delay versus Load Capacitance in Mixed Voltage System
Embedded Write-Back Enhanced IntelDX4 Processor
MECHANICAL DATA
This section describes the packaging dimensions and thermal specifications for the Embedded Write-Back Enhanced IntelDX4 processor.
Package Dimensions
25.50 (ref)
.40 Min 0.13 + 0.12-0.08 156 0° Min 7° Max
Top View
Metal Heat Spreader
0.13 Min 0.25 Max
NOTE: Length measurements same as width measurements 1.76 Max Tolerance Window for Lead Skew from Theoretical True Position 0.10 Max
Units: mm
A3260-01
Figure 15. 208-Lead SQFP Package Dimensions
Embedded Write-Back Enhanced IntelDX4 Processor
Figure 16. Principal Dimensions and Data for 168-Pin Grid Array Package
Table 22. 168-Pin Ceramic PGA Package Dimensions Symbol A A1 A2 A3 B D D1 e1 L N S1 1.52 Millimeters Min 3.56 0.64 2.8 1.14 0.43 44.07 40.51 2.29 2.54 168 2.54 0.060 Max 4.57 1.14 3.5 1.40 0.51 44.83 40.77 2.79 3.30 SOLID LID SOLID LID Notes Min 0.140 0.025 0.110 0.045 0.017 1.735 1.595 0.090 0.100 168 0.100 Inches Max 0.180 0.045 0.140 0.055 0.020 1.765 1.605 0.110 0.130 SOLID LID SOLID LID Notes
Embedded Write-Back Enhanced IntelDX4 Processor
Table 23. Ceramic PGA Package Dimension Symbols Letter or Symbol A A1 A2 A3 B D D1 e1 L S1 Description of Dimensions Distance from seating plane to highest point of body Distance between seating plane and base plane (lid) Distance from base plane to highest point of body Distance from seating plane to bottom of body Diameter of terminal lead pin Largest overall package dimension of length A body length dimension, outer lead center to outer lead center Linear spacing between true lead position centerlines Distance from seating plane to end of lead Other body dimension, outer lead center to edge of body
NOTES: 1. Controlling dimension: millimeter. 2. Dimension "e1" ("e") is non-cumulative. 3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415-0.0430 inch. 4. Dimensions "B", "B1" and "C" are nominal. 5. Details of Pin 1 identifier are optional.
Package Thermal Specifications
Embedded Write-Back Enhanced IntelDX4 Processor
Table 24. Thermal Resistance, JA (°C / W) JA vs. Airflow - ft / min. (m / sec) Package 168-Pin PGA 168-Pin PGA 208-Lead SQFP 208-Lead SQFP Heat Sink No Yes No Yes 0 (0) 17.5 13.5 12.5 10.5 200 (1.01) 15.0 8.5 10.0 6.5 400 (2.03) 13.0 6.5 9.0 5.0 600 (3.04) 11.5 5.5 8.5 4.0 800 (4.06) 10.0 4.5 1000 (5.07) 9.5 4.25
Table 25. Thermal Resistance, JC (°C / W) Package 168-Pin PGA 168-Pin PGA 208-Lead SQFP 208-Lead SQFP Heat Sink No Yes No Yes JC 2.0 2.0 1.2 0.8
Table 26. Maximum Tambient, TA max (°C) Airflow - ft / min. (m / sec) Package 168-Pin PGA 168-Pin PGA 208-Lead SQFP 208-Lead SQFP 208-Lead SQFP 208-Lead SQFP Heat Sink No Yes No Yes No Yes Freq. (MHz) 100 100 100 100 75 75 0 (0) 18.5 35.5 36.5 43.5 200 (1.01) 29.0 57.0 46.0 60.5 400 (2.03) 37.5 65.5 50.0 67.0 600 (3.04) 44.0 70.0 52.5 71.0