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EMBEDDED ULTRA-LOW POWER Intel486 GX PROCESSOR

s Ultra-Low Power Member of the Intel486 s 16-Bit External Data Bus

EMBEDDED ULTRA-LOW POWER Intel486 GX PROCESSOR
s Ultra-Low Power Member of the Intel486 s 16-Bit External Data Bus
Processor Family s - 32-Bit RISC Technology Core s - 8-Kbyte Write-Through Cache s - Four Internal Write Buffers - Burst Bus Cycles s - Data Bus Parity Generation and s Checking - Intel System Management Mode (SMM) - Boundary Scan (JTAG)
176-Lead Thin Quad Flat Pack (TQFP) Separate Voltage Supply for Core Circuitry Fast Core-Clock Restart Auto Clock Freeze Ideal for Embedded Battery-Operated and Hand-Held Applications
64-Bit Interunit Transfer Bus
32-Bit Data Bus 32-Bit Data Bus Linear Address
PCD PWT
Core Clock
Clock Control
CLK Input
Barrel Shifter Register File ALU
Base / Index Bus 32
Segmentation Unit Descriptor Registers Limit and Attribute PLA
Bus Interface
Paging Unit
Cache Unit
20 Physical Address 8 Kbyte Cache
Address Drivers Write Buffers 4 x 32 Data Bus 32 Transceivers
A31-A2 BE3#- BE0#
Translation Lookaside Buffer
D15-D0
128 Displacement Bus 32 MicroInstruction 32-Byte Code Queue 2x16 Bytes Prefetcher
Bus Control
Request Sequencer Burst Bus Control
ADS# W / R# D / C# M / IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# STPCLK#
Control & Protection Test Unit
Code Stream Instruction Decode Decoded Instruction Path 24
BRDY# BLAST#
Control ROM
Parity Generation and Control Cache Control Boundary Scan Control
DP1-DP0, PCHK#
KEN# FLUSH# AHOLD EADS#
TCK TMS TDI TD0
A5851-01
Contents
Embedded Ultra-Low Power Intel486 GX Processor
Contents
Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22.
Address Prediction for Burst Transfers (1 of 3) .................................... 25 Address Prediction for Burst Transfers (2 of 3) .................................... 26 Address Prediction for Burst Transfers (3 of 3) .................................... 27 CLK Waveform ............................................................. 37 Input Setup and Hold Timing .................................................. 37 Input Setup and Hold Timing .................................................. 38 Output Valid Delay Timing .................................................... 38 PCHK# Valid Delay Timing ................................................... 39 Maximum Float Delay Timing ................................................. 39 TCK Waveform ............................................................ 40 Test Signal Timing Diagram ................................................... 40 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition ................................................... 41 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition ................................................... 41 Package Mechanical Specifications for the 176-Lead TQFP Package .................. 42
The Embedded Ultra-Low Power Intel486 GX Processor ............................ 3 Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor .... 5 Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor ...................................................... 6 Embedded ULP Intel486 GX Processor Pin Descriptions ........................... 7 Output Pins ............................................................... 13 Input / Output Pins ........................................................... 13 Test Pins ................................................................. 14 Input Pins ................................................................. 14 Valid Byte-Enable Cycles ..................................................... 20 Address Sequence for Cache Line Transfers and Instruction Prefetches ................ 22 Valid Burst Cycle Sequences - I / O Reads and All Writes ............................ 23 CPUID Instruction Description ................................................. 28 Boundary Scan Component Identification Code ................................... 29 Absolute Maximum Ratings ................................................... 30 Operating Supply Voltages ................................................... 31 DC Specifications ........................................................... 31 Active ICC Values ........................................................... 32 Clock Stop, Stop Grant, and Auto HALT Power Down ICC Values ..................... 33 AC Characteristics .......................................................... 34 AC Specifications for the Test Access Port ....................................... 36 Thermal Resistance ......................................................... 43 Maximum Ambient Temperature (TA) ........................................... 43
Embedded Ultra-Low Power Intel486 GX Processor
INTRODUCTION
· On-Chip Cache with Cache Consistency Support - An 8-Kbyte, write-through, internal cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. · External Cache Control - Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency. · On-Chip Memory Management Unit - Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both segmentation and paging are supported. · Burst Cycles - Burst transfers allow a new 16-bit data word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. Burst transfers also occur on some memory write and some I / O data transfers. · Write Buffers - The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. · Bus Backoff - When another bus master needs control of the bus during a processor initiated bus cycle, the embedded ULP Intel486 GX processor floats its bus signals, then restarts the cycle when the bus becomes available again. · Instruction Restart - Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications. · Boundary Scan (JTAG) - Boundary Scan provides in-circuit testing of components on printed circuit boards. The Intel Boundary Scan implementation conforms with the IEEE Standard Test Access Port and Boundary Scan Architecture.
Features
The embedded ULP Intel486 GX processor offers these features of the Intel486 SX processor: · 32-bit RISC-Technology Core - The embedded ULP Intel486 GX processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. · Single Cycle Execution - Many instructions execute in a single clock cycle. · Instruction Pipelining - Overlapped instruction fetching, decoding, address translation and execution.
Embedded Ultra-Low Power Intel486 GX Processor
· Intel System Management Mode (SMM) - A unique Intel architecture operating mode provides a dedicated special purpose interrupt and address space that can be used to implement intelligent power management and other enhanced functions in a manner that is completely transparent to the operating system and applications software. · I / O Restart - An I / O instruction interrupted by a System Management Interrupt (SMI#) can automatically be restarted following the execution of the RSM instruction. · Stop Clock - The embedded ULP Intel486 GX processor has a stop clock control mechanism that provides two low-power states: a Stop Grant state (40-85 mW typical, depending on input clock frequency) and a Stop Clock state (~60 µW typical, with input clock frequency of 0 MHz). · Auto HALT Power Down - After the execution of a HALT instruction, the embedded ULP Intel486 GX processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state (40-85 mW typical, depending on input clock frequency). The embedded ULP Intel486 GX processor differs from the Intel486 SX processor in the following areas: · 16-Bit External Data Bus - The embedded ULP Intel486 GX processor is designed for 16-bit embedded systems, yet internally provides the 32bit architecture of the Intel486 processor family. Two data parity bits are provided. · Processor Upgrade Removed - The UP# signal is not provided. · Dynamic Bus-Sizing Removed - The BS8# signal is not provided.
· Separate Processor-Core Power - While the embedded ULP Intel486 GX processor requires a supply voltage of 3.3 V, the processor core has dedicated VCC pins and operates with a supply voltage as low as 2.0 V. · Small, Low-Profile Package - The 176-Lead Thin Quad Flat Pack (TQFP) package is approximately 26 mm square and only 1.5 mm in height. This is approximately the diameter and thickness of a U.S. quarter. The embedded ULP Intel486 GX processor is ideal for embedded hand-held and battery-powered applications. · Level Keeper Circuits - The embedded ULP Intel486 GX processor has level-keeper circuits for its 16-bit external data bus and parity signals. They retain valid high and low logic voltage levels when the processor is in the Stop Grant and Stop Clock states. The level-keeper circuits for the parity signals are always enabled. This is a power-saving improvement from the floating data bus of the Intel486 SX processor. · Auto Clock Freeze - The embedded ULP Intel486 GX processor monitors bus events and internal activity. The Auto Clock Freeze feature automatically controls internal clock distribution, turning off clocks to internal units when they are idle. This power-saving function is transparent to the embedded system. · Fast Clock Restart - The embedded ULP Intel486 GX processor requires only eight clock periods to synchronize its internal clock with the CLK input signal. This provides for faster transition from the Stop Clock State to the Normal State. For 33-MHz operation, this synchronization time is only 240 ns compared with 1 ms (PLL startup latency) for the Intel486 processor.
Embedded Ultra-Low Power Intel486 GX Processor
Family Members
Table 1 shows the embedded ULP Intel486 GX processor and briefly describes its characteristics. Table 1. The Embedded Ultra-Low Power Intel486 GX Processor Supply Voltage
(VCCP)
Product
Processor Core Supply Voltage
(VCC)
Processor Frequency
(MHz)
Package
2.0 V to 3.3 V FA80486GXSF-33 3.3 V 2.2 V to 3.3 V 2.4 V to 3.3 V 2.7 V to 3.3 V
16 20 25 33 176-Lead TQFP
HOW TO USE THIS DOCUMENT
PIN DESCRIPTIONS Pin Assignments
The following figures and tables show the pin assignments for the 176-pin Thin Quad Flat Pack (TQFP) package of the embedded ULP Intel486 GX processor. Included are: · Figure 2, Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor (pg. 4) · Table 2, Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor (pg. 5) · Table 3, Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor (pg. 6) · Table 4, Embedded ULP Intel486 GX Processor Pin Descriptions (pg. 7) · Table 5, Output Pins (pg. 13) · Table 6, Input / Output Pins (pg. 13) · Table 7, Test Pins (pg. 14) · Table 8, Input Pins (pg. 14) The tables and figures show "no-connects" as "N / C." These pins should always remain unconnected. Connecting N / C pins to VCC, VCCP, VSS, or any other signal pin can result in component malfunction or incompatibility with future steppings of the embedded ULP Intel486 GX processor.
Embedded Ultra-Low Power Intel486 GX Processor
Figure 2. Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor
EADS# A20M# RESET N / C N / C N / C FLUSH# INTR NMI VSS VSS VSS VSS SRESET SMIACT# VCC VSS VCCP N / C N / C SMI# N / C TDO VCC N / C N / C STPCLK# VSS VCC VSS VCCP VSS VCCP VSS VCCP N / C VSS VCC N / C VSS VSS VCCP VSS VSS
BLAST# VCC PLOCK# LOCK# VSS VCCP N / C PCHK# BRDY# BOFF# VCC VSS N / C RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK HLDA W / R# VSS VCCP BREQ BE0# BE1# BE2# BE3# VCC VSS M / IO# D / C# PWT PCD VCCP VSS VCC
ADS# A2 VSS VCCP VSS VSS VCCP A3 A4 A5 RESERVED# A6 A7 A8 VSS VCC A9 A10 VCCP VSS VCC A11 A12 VCC A13 A14 VCCP VSS A15 A16 A17 VSS VCCP TDI TMS A18 A19 A20 VCCP VCCP A21 A22 A23 A24
176-Lead TQFP (top view)
VSS VSS VCCP A25 A26 A27 A28 VCCP A29 A30 A31 DP0 D0 D1 D2 D3 D4 VCC VSS VCC VCC VSS VCC VCC VSS VCCP D5 D6 VCCP N / C D7 DP1 D8 D9 VSS VCC D10 D11 D12 D13 VSS VCCP D14 D15
Embedded Ultra-Low Power Intel486 GX Processor
Table 2. Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor Pin #
Description
BLAST# VCC PLOCK# LOCK# VSS VCCP N / C PCHK# BRDY# BOFF# VCC VSS N / C RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC CLK HLDA W / R# VSS VCCP BREQ BE0# BE1# BE2# BE3# VCC VSS M / IO# D / C# PWT PCD VCCP VSS VCC
Description
EADS# A20M# RESET N / C N / C N / C FLUSH# INTR NMI VSS VSS VSS VSS SRESET SMIACT# VCC VSS VCCP N / C N / C SMI# N / C TDO VCC N / C N / C STPCLK# VSS VCC VSS VCCP VSS VCCP VSS VCCP N / C VSS VCC N / C VSS VSS VCCP VSS VSS
Description
D15 D14 VCCP VSS D13 D12 D11 D10 VCC VSS D9 D8 DP1 D7 N / C VCCP D6 D5 VCCP VSS VCC VCC VSS VCC VCC VSS VCC D4 D3 D2 D1 D0 DP0 A31 A30 A29 VCCP A28 A27 A26 A25 VCCP VSS VSS
Description
A24 A23 A22 A21 VCCP VCCP A20 A19 A18 TMS TDI VCCP VSS A17 A16 A15 VSS VCCP A14 A13 VCC A12 A11 VCC VSS VCCP A10 A9 VCC VSS A8 A7 A6 RESERVED# A5 A4 A3 VCCP VSS VSS VCCP VSS A2 ADS#
Embedded Ultra-Low Power Intel486 GX Processor
Table 3. Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor Address
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
Control
A20M# ADS# AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ CLK D / C# DP0 DP1 EADS# FLUSH# HLDA HOLD INTR KEN# LOCK# M / IO# NMI PCD PCHK# PLOCK# PWT RDY# RESERVED# RESET SMI# SMIACT# SRESET STPCLK# TCK TDI TDO TMS W / R#
Embedded Ultra-Low Power Intel486 GX Processor
Pin Quick Reference
ADDRESS BUS A31-A4 A3-A2 I / O O
BE3# BE2# BE1# BE0#
DP1 DP0
Embedded Ultra-Low Power Intel486 GX Processor
Table 4. Embedded ULP Intel486 GX Processor Pin Descriptions (Sheet 2 of 6) Symbol PCHK# Type O Name and Function Parity Status is driven on the PCHK# pin the clock after ready for read operations. The parity status is for data sampled at the end of the previous clock. A parity error is indicated by PCHK# being LOW. Parity status is only checked for enabled bytes as indicated by the byte enable signals. PCHK# is valid only in the clock immediately after read data is returned to the processor. At all other times PCHK# is inactive (HIGH). PCHK# is never floated. Memory / Input-Output, Data / Control and Write / Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. M / IO# 0 0 0 0 1 1 1 1 D / C# 0 0 1 1 0 0 1 1 HALT / Special Cycle Cycle Name Shutdown HALT Stop Grant bus cycle LOCK# O BE3# - BE0# 1110 1011 1011 A4-A2 000 000 100 W / R# 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge HALT / Special Cycle (see details below) I / O Read I / O Write Code Read Reserved Memory Read Memory Write
BUS CYCLE DEFINITION M / IO# D / C# W / R# O O O
Bus Lock indicates that the current bus cycle is locked. The embedded ULP Intel486 GX processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the embedded ULP Intel486 GX processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits). The embedded ULP Intel486 GX processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold.
PLOCK#
BUS CONTROL ADS# O Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold.
Embedded Ultra-Low Power Intel486 GX Processor
INTERRUPTS RESET I
Embedded Ultra-Low Power Intel486 GX Processor
SRESET
SMIACT#
STPCLK#
BUS ARBITRATION BREQ O
Embedded Ultra-Low Power Intel486 GX Processor
BOFF#
CACHE INVALIDATION AHOLD I
EADS#
CACHE CONTROL KEN# I
FLUSH#
Embedded Ultra-Low Power Intel486 GX Processor
PAGE CACHEABILITY
ADDRESS MASK A20M# I
TEST ACCESS PORT TCK I
RESERVED PINS RESERVED# I
Embedded Ultra-Low Power Intel486 GX Processor
Table 5. Output Pins Output Signal Name BREQ HLDA BE3#-BE0# PWT, PCD W / R#, M / IO#, D / C# LOCK# PLOCK# ADS# BLAST# PCHK# A3-A2 SMIACT# Active Level HIGH HIGH LOW HIGH HIGH / LOW LOW LOW LOW LOW LOW HIGH LOW · · · · · · · · · Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States1 Previous State As per HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State Previous State
NOTES: 1. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Table 6. Input / Output Pins Output Signal Name D15-D0 DP1, DP0 A31-A4 Active Level HIGH HIGH HIGH · Floated During Address Hold Floated During Bus Hold · · · During Stop Grant and Stop Clock States1, 2 Level-Keeper Level-Keeper Previous State
NOTES: 1. The term "Level-Keeper" means that the processor maintains the most recent logic level applied to the signal pin. This conserves power by preventing the signal pin from floating. If a system component, other than the processor, temporarily drives these signal pins and then floats them, the processor forces and maintains the most recent logic levels that were applied by the system component. The level keepers for DP1 and DP0 are always enabled. 2. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Embedded Ultra-Low Power Intel486 GX Processor
Table 7. Test Pins Name TCK TDI TDO TMS Input or Output Input Input Output Input Table 8. Input Pins Name CLK RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# KEN# RDY# BRDY# INTR NMI RESERVED# SMI# STPCLK# TCK TDI TMS HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-Up Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Active Level Synchronous / Asynchronous Internal Pull-Up / Pull-Down Sampled / Driven On N / A Rising Edge of TCK Failing Edge of TCK Rising Edge of TCK
1. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is not used.
Embedded Ultra-Low Power Intel486 GX Processor
ARCHITECTURAL AND FUNCTIONAL OVERVIEW
· The embedded ULP Intel486 GX processor has one pin reserved for possible future use. This pin is an input signal, pin 166. It is called RESERVED# and must be connected to a 10-K pull-up resistor.
Separate Supply Voltages
Embedded Ultra-Low Power Intel486 GX Processor
VCC and VCCP (V)
VCCP min
VCC min
0V TIME
POWER ON POWER OFF
Figure 3. Example of Supply Voltage Power Sequence
Fast Clock Restart
The embedded ULP Intel486 GX processor has an integrated proprietary differential delay line (DDL) circuit for internal clock generation. The DDL is driven by the CLK input signal provided by the external system. During normal operation, the external system must guarantee that the CLK signal maintains its frequency so that the clock period deviates no more than 250 ps / CLK. This state, called the Normal State, is shown in Figure 4. To increase or decrease the CLK frequency more quickly than this, the system must interrupt the processor with the STPCLK# signal. Once the processor indicates that it is in the Stop Grant State, the system can adjust the CLK signal to the new frequency, wait a minimum of eight CLK periods, then force the processor to return to the normal operational state by deactivating the STPCLK#
interrupt. This wait of eight CLK periods is much faster than the 1 ms wait required by earlier Intel486 SX processor products. While in the Stop Grant State, the external system may deactivate the CLK signal to the processor. This forces the processor to the Stop Clock State - the state in which the processor consumes the least power. Once the system reactivates the CLK signal, the processor transitions to the Stop Grant State within eight CLK periods. Normal operation can be resumed by deactivating the STPCLK# interrupt signal. Here again, the embedded ULP Intel486 GX processor recovers from the Stop Clock State much faster than the 1 ms PLL recovery of earlier Intel486 SX processors.
Embedded Ultra-Low Power Intel486 GX Processor
4 Auto HALT Power Down State
CLK Running 40 - 85 mWatts
HALT asserted and HALT bus cycle generated
1 Normal State
Normal Execution
INTR, NMI, SMI# RESET, SRESET STPCLK# asserted and Stop Grant bus cycle generated
EADS# STPCLK# deasserted and HALT bus cycle generated STPCLK# asserted and Stop Grant bus cycle generated
STPCLK# deasserted
EADS#
2 Stop Grant State
CLK Running 40 - 85 mWatts
5 Stop Clock Snoop State
One Clock PowerUp Perform Cache Invalidation
Stop CLK
Start CLK plus DDL Startup Latency
3 Stop Clock State
Internal Powerdown CLK Stopped ~ 60 µWatts
Figure 4. Stop Clock State Diagram with Typical Power Consumption Values
Level-Keeper Circuits
To obtain the lowest possible power consumption during the Stop Grant and Stop Clock states, system designers must ensure that: · input signals with pull-up resistors are not driven LOW · input signals with pull-down resistors are not driven HIGH See Table 8, Input Pins (pg. 14) for the list of signals with internal pull-up and pull-down resistors. All other input pins except A31-A4, D15-D0, DP1, and DP0 must be driven to the power supply rails to ensure lowest possible current consumption.
During the Stop Grant and Stop Clock states, most processor output signals maintain their previous condition, which is the level they held when entering the Stop Grant state. In response to HOLD driven active during the Stop Grant state when the CLK input is running, the embedded ULP Intel486 GX processor generates HLDA and floats all output and input / output signals which are floated during the HOLD / HLDA state. When HOLD is deasserted, processor signals which maintain their previous state return to the state they were in prior to the HOLD / HLDA sequence. The data bus (D15-D0) and parity bits also maintain their previous states during the Stop Grant and Stop Clock states, but do so differently, as described in the following paragraphs. 17
Embedded Ultra-Low Power Intel486 GX Processor
Low-Power Features
As with other Intel486 processors, the embedded ULP Intel486 GX processor minimizes power consumption by providing the Auto HALT Power Down, Stop Grant, and Stop Clock states (see Figure 4). The embedded ULP Intel486 GX processor has an Auto Clock Freeze feature that further conserves power by judiciously deactivating its internal clocks while in the Normal Execution Mode. The power-conserving mechanism is designed such that it does not degrade processor performance or require changes to AC timing specifications. 4.4.1 Auto Clock Freeze
To reduce power consumption, during the following bus cycles - under certain conditions - the processor slows-up or freezes some internal clocks: · Data-Read Wait Cycles (Memory, I / O and Interrupt Acknowledge) · Data-Write Wait Cycles (Memory, I / O) · HOLD / HLDA Cycles · AHOLD Cycles · BOFF Cycles Power is conserved during the wait periods in these cycles until the appropriate external-system signals are sent to the processor. These signals include: · READY · NMI, SMI#, INTR, and RESET · BOFF# · FLUSH# · EADS# · KEN# transitions The embedded ULP Intel486 GX processor also reduces power consumption by temporarily freezing the clocks of its internal logic blocks. When a logic block is idle or in a wait state, its clock is frozen.
Embedded Ultra-Low Power Intel486 GX Processor
Bus Interface and Operation
16-Bit Data Bus
DP1 must meet the setup and hold times, t22 and t23. In systems not using parity, DP0 and DP1 must be connected to VCCP through a pull-up resistor. · The data parity pins have level-keeper circuits which are described later. 4.5.3 Data Transfer Mechanism
The bi-directional lines, D15-D0, form the data bus for the embedded ULP Intel486 GX processor. D7D0 define the least-significant byte and D15-D8 the most-significant byte. Data transfers are possible only to 16-bit devices. Bus-sizing for 8-bit devices (BS8# signal pin) is not supported by the processor. In some cases, external circuitry is needed for the processor to interface with 8-bit devices. An example of when external circuitry is not needed is an 8-bit I / O port that is mapped to a byte address. Here only part of the 16-bit data word is meant for the device and BS8# is not needed. D15-D0 are active HIGH. For reads, D15-D0 must meet the setup and hold times, t22 and t23. D15-D0 are not driven during read cycles and bus hold. 4.5.2 Parity
Parity operation is the same as it is for the rest of the Intel486 processor family, with these exceptions: · DP0 and DP1 are the data parity pins for the processor. There is one parity signal for each byte of the external data bus. Input signals on DP0 and
Data transfers operate in a manner similar to data transfers on the 32-bit data bus members of the Intel486 processor family with the BS16# pin driven active. For 32-bit data-bus family members, such 16bit data transfers involve all 32 bits of their external data busses and all four parity bits. Since the embedded ULP Intel486 GX processor has a 16-bit external data bus, all data transfers occur on the low order data bits, D0 through D15. Parity is generated and checked on DP0 and DP1. Dynamic Data Bus Sizing (BS16#, and BS8#) is not supported. All address bits (A31-A2) and byte enables (BE0#, BE1#, BE2#, and BE3#) are supported. Address bits A1 and A0 can be generated from the byte-enable signals in the same manner as the other Intel486 processors. Typically in 16-bit data bus designs, A1, byte-low enable (BLE), and byte-high enable (BHE) are needed and can be generated from the four byte-enable signals. Figure 5 shows the logic that can be used to generate A1, BHE#, and BLE#.
BE0# BE1#
BE1# BE3#
BE0# BE2# BLE# (or A0)
Figure 5. Logic to Generate A1, BHE# and BLE# 19
Embedded Ultra-Low Power Intel486 GX Processor
Table 9 contains the list of valid byte-enable combinations and how the 16-bit external data bus is interpreted.
Table 9. Valid Byte-Enable Cycles Byte Enables Case BE3# 1 2 3 4 5 6 7 8 9 10 1 1 1 0 1 1 0 1 0 0 BE2# 1 1 0 0 1 0 0 0 0 1 BE1# 1 0 0 0 0 0 0 1 1 1 BE0# 0 0 0 0 1 1 1 1 1 1 A1 0 0 0 0 0 0 0 1 1 1 From External Circuitry (Note 1) A0 0 0 0 0 1 1 1 0 0 1 BHE# 1 0 0 0 0 0 0 1 0 0 External Data Bus D7-D0, DP0 valid valid valid valid valid valid -
BLE# D15(A0) D8, DP1 0 0 0 0 1 1 1 0 0 1 valid valid valid valid valid valid valid valid
NOTES: 1. If the external system indicates to the processor that a read is cacheable, the processor initiates a cacheline fill. In this case, the external system should ignore BE3#, BE2#, BE1#, and BE0# and force A1, A0, and BHE# to a low logic level (0) for the first cycle of the transfer. This forces a memory read to start from a data address having its least significant digit 0, 4, 8, or C (hex). The byte-enable decodes for subsequent cycles of the line fill follow the table information as listed.
Except for the initial transfer of a cache-line fill, the Byte Enables BE3#, BE2#, BE1#, and BE0# for cases 1, 2, 5, 8, 9, and 10 indicate either a one-, or two-byte data transfer that can be accomplished in one 16-bit data cycle. Except for the initial transfer of a cache-line fill, the Byte Enables BE3#, BE2#, BE1#, and BE0# for cases 3, 4, 6, and 7 indicate the transfer of two, three, or four data bytes that cannot be accomplished in one 16-bit data cycle. In these cases, the processor attempts to complete the partial transfer using an additional data cycle. The additional cycle could be burst by the processor (processor could respond with BLAST# unasserted for case 3, 4, 6, or 7). This is true for both memory and I / O reads and writes. There is more information about bursting in later sections.
During write cycles, valid data is only driven onto the external data bus pins corresponding to active byte enables. Other pins of the data bus are driven but do not contain valid data. NOTE: Unlike the Intel386 processor, the embedded ULP Intel486 GX processor does not duplicate write data onto the parts of the data bus for which the corresponding byte enable is inactive.
Embedded Ultra-Low Power Intel486 GX Processor
4.5.3.1 Multiple and Burst Cycle Bus Transfers The embedded ULP Intel486 GX processor, like all other Intel486 processors, requires more than one data cycle to read or write data having bit widths greater than 32. Examples of this data are cache lines (128 bits) and instruction prefetches (128 bits). In addition, the embedded ULP Intel486 GX processor requires multiple data cycles to transfer data having bit widths greater than 16. An example is a doubleword operand (32 bits). Transferring misaligned 16-bit words also requires multiple data cycles. If a multiple data cycle is a memory-read or I / O-read data transfer, the processor could use burst cycles to perform the transfer. The processor could also burst misaligned 16-bit and 32-bit memory-write or I / Owrite data transfers. In designing a memory and I / O port controller for the embedded ULP Intel486 GX processor, knowledge of the address sequence for burst cycles can be used to provide high-speed data access (minimal number of wait states). The following sections describe this sequence.
4.5.3.2 Cacheable Cycles The embedded ULP Intel486 GX processor uses burst cycles to perform a cache line fill. Because of its 16-bit external data bus, the processor bursts eight data cycles to read a 128-bit (16-byte) cache line from system memory. During the first cycle of the cache line transfer, the external system must ignore BE3#, BE2#, BE1#, and BE0# presented by the processor and proceed as if A1, A0, and BHE# were logic-low levels (0). This forces the memory read to start from a data address having its least significant hexadecimal digit 0, 4, 8, or C. The byte enables presented by the processor for subsequent cycles are decoded in the usual way by the external system. The sequences of data addresses are shown in Table 10. Like the rest of the Intel486 processor family, the initial value of A31-A4, M / IO#, W / R#, and D / C# are presented by the processor throughout the cache line fill. Also, the burst sequence can be terminated by the processor at any time by with an active BLAST# signal.
Embedded Ultra-Low Power Intel486 GX Processor
transfer. In some cases, the transfer can be performed entirely by burst cycles. In other cases, a combination of burst cycles and single cycles are required to perform the data transfer. There are also cases for which burst cycles cannot be used and the transfer consists of multiple cycles, each beginning with the ADS# signal. I / O Writes, I / O Reads, and Memory Writes If the processor initiates bursting (BLAST# inactive) during an I / O Write, I / O Read or Memory Write, the duration of the burst is a maximum of four bytes (32 bits). All of the possible burst situations are listed in Table 11. In all cases, the burst is two data cycles. The control signals M / IO#, D / C#, W / R#, address bits A31-A4 as well as A3 and A2 remain constant throughout each two-cycle burst.
Table 11. Valid Burst Cycle Sequences - I / O Reads and All Writes Starting Address (Least significant hexadecimal digit) 0, 4, 8, C Signals from the Processor A3 A2 A3 A2 A3 A2 A3 A2 A3 A2 A3 A2 A3 A2 A3 A2 A3 A2 Byte Enables BE3#-BE0# 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 1 0 0 0 1 0 1 1 A3-A0 (Hex) 0, 4, 8, C 2, 6, A, E 1, 5, 9, D 2, 6, A, E 1, 5, 9, D 2, 6, A, E 0, 4, 8, C 2, 6, A, E BLAST# 1 0 1 0 1 0 1 0 Address of Expected Read Data D15-D8, DP1 2nd 4th 1st 3rd 1st 2nd D7-D-0, DP0 1st 3rd 2nd 2nd 1st 3rd
Embedded Ultra-Low Power Intel486 GX Processor
Non-Cacheable Memory Reads When the processor initiates bursting, the duration of the burst is a maximum of 16 bytes (128 bits). Non-cacheable instruction prefetches can be 16 bytes in duration. The possible burst sequences are the same as for cache-line transfers listed in Table 11. The burst sequence can be terminated at any time with an active BLAST# signal. The length of a burst transfer can be 16, eight, or fewer than eight bytes. For burst lengths of eight or less, the entire burst transfer is confined to a quad-word (eight-byte) data boundary of system memory. A31-A3 remain constant throughout this type of burst transfer.
4.5.3.4 Burst Transfer Address Prediction The processor provides the data address (A31-A2) and byte enables (BE3#-BE0#) for the first data cycle while ADS# is inactive. The initial values for A1, BHE# and BLE# (A0) can be derived from the byte enables. If bursting is anticipated, the next data address can be predicted at this time and can be used by the memory controller to perform burst data transfers with minimal wait states. Rather than list all of the burst mode address combinations, a general algorithm is provided in Figure 6. This algorithm holds true for all burst transfers including cache-line fills, instruction prefetches, I / O and memory-write data transfers described in earlier sections.
Embedded Ultra-Low Power Intel486 GX Processor
Begin when ADS# is active
Define LA3 and LA2 as the initial A3 and A2 values
Indicate "cacheable data" to processor
Continued
Figure 6. Address Prediction for Burst Transfers (1 of 3)
Embedded Ultra-Low Power Intel486 GX Processor
Continued from previous figure
Yes Continued
Figure 7. Address Prediction for Burst Transfers (2 of 3)
Embedded Ultra-Low Power Intel486 GX Processor
Continued from previous figure
Data Cycle This is the last transfer. There is no need to predict the next address
Figure 8. Address Prediction for Burst Transfers (3 of 3)
instruction is available. The actual state of the ID Flag bit is irrelevant and provides no significance to the hardware. This bit is cleared (reset to zero) upon device reset (RESET or SRESET) for compatibility with Intel486 processor designs that do not support the CPUID instruction. CPUID-instruction details are provided here for the embedded ULP Intel486 GX processor. Refer to Intel Application Note AP-485 Intel Processor Identification with the CPUID Instruction (Order No. 241618) for a description that covers all aspects of the CPUID instruction and how it pertains to other Intel processors. 4.6.1 Operation of the CPUID Instruction
CPUID Instruction
The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX.
Embedded Ultra-Low Power Intel486 GX Processor
Table 12. CPUID Instruction Description OP CODE 0F A2 Instruction CPUID Processor Core Clocks 9 14 9 Parameter passed in EAX
(Input Value)
Description Vendor (Intel) ID String Processor Identification Undefined (Do Not Use)
Vendor ID String (ASCII Characters)
EBX EDX ECX
u (75) I (49) l (6C)
n (6E) e (65) e (65)
e (65) n (6E) t (74)
G (47) i (69) n (6E)
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel." Processor Identification - When the parameter passed to EAX is 1 (one), the register values 31--------------14 Processor Signature EAX (Do Not Use) Intel Reserved returned upon instruction execution are: 13, 12 00 Processor Type 11--8 0100 Family 7--4 0010 Model 3--0 XXXX Stepping
(Intel releases information about stepping numbers as needed) 31-------------------------------------------------0 Intel Reserved (Do Not Use) EBX ECX Intel Reserved Intel Reserved 31--------------------------------------2 Feature Flags EDX 0---------------------------------------0 1 1 VME 0 0 FPU
Embedded Ultra-Low Power Intel486 GX Processor
Identification After Reset
31--------------14 Processor Signature EDX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 0010 Model 3--0 XXXX Stepping
Processor Identification - Upon reset, the EDX register contains the processor signature:
(Intel releases information about stepping numbers as needed)
Boundary Scan (JTAG)
Device Identification
Table 13 shows the 32-bit code for the embedded ULP Intel486 GX processor which is loaded into the Device Identification Register. Table 13. Boundary Scan Component Identification Code Version VCC
31--28 XXXX
Boundary Scan Register Bits and Bit Order
· BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W / R#, BE0#, BE1#, BE2#, BE3#, M / IO#, D / C#, PWT, and PCD · MISCCTL controls PCHK#, HLDA, and BREQ
The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N / C) signals of the embedded ULP Intel486 GX processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the direction of bidirectional or three-state output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional. · WRCTL controls D15-D0, DP1 and DP0 · ABUSCTL controls A31-A2
Embedded Ultra-Low Power Intel486 GX Processor
The following is the bit order of the embedded ULP Intel486 GX processor boundary scan register: TDO A2, A3, A4, A5, RESERVED, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, DP0, D0, D1, D2, D3, D4, D5, D6, D7, DP1, D8, D9, D10, D11, D12, D13, D14, D15, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, Reserved, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D / C#, M / IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W / R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, Reserved, Reserved, BOFF#, BRDY#, PCHK#, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, TDI BUSCTL, ABUSCTL, WRCTL
ELECTRICAL SPECIFICATIONS Maximum Ratings
Table 14. Absolute Maximum Ratings Case Temperature under Bias Storage Temperature -65 °C to +110 °C -65 °C to +150 °C -0.5 V to VCCP + 0.5 V -0.5 V to +4.6 V -0.5 V to +4.6 V
Table 14 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the embedded ULP Intel486 GX processor contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications.
DC Voltage on Any Pin with Respect to Ground Supply Voltage VCC with Respect to VSS Supply Voltage VCCP with Respect to VSS
DC Specifications
The following tables show the operating supply voltages, DC I / O specifications, and component power consumption for the embedded ULP Intel486 GX processor.
Embedded Ultra-Low Power Intel486 GX Processor
NOTES: 1. In all cases, VCCP must be VCC. 2. VCC may be set to any voltage within the VCC Range. The setting determines the allowed VCC Fluctuation.
Embedded Ultra-Low Power Intel486 GX Processor
Typical ICC 65 mA 105 mA 85 mA 130 mA 120 mA 165 mA 180 mA 220 mA 5 mA 6 mA 9 mA 12 mA
Max. ICC 105 mA 170 mA 140 mA 210 mA 195 mA 260 mA 280 mA 345 mA 16 mA 20 mA 30 mA 40 mA
Notes
Embedded Ultra-Low Power Intel486 GX Processor
ICCS3
NOTES: 1. The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. For all input signals, the VIH and VIL levels must be equal to VCCP and 0V, respectively, to meet the ICC Stop Clock specifications.
Embedded Ultra-Low Power Intel486 GX Processor
AC Specifications
Symbol Parameter Frequency
Min 0 62.5
Max 16
Max 20
Max 25
Max 33
Unit MHz ns
Notes Note 1 Note 1 Note 2 at 2V at 0.8V 2V to 0.8V Note 3 0.8V to 2V Note 3
t1 t1a t2 t3 t4 t5 t6
CLK Period CLK Period Stability CLK High Time CLK Low Time CLK Fall Time CLK Rise Time A2-A31, PWT, PCD, BE0#-BE3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, SMIACT# Valid Delay A2-A31, PWT, PCD, BE0#-BE3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay BLAST#, PLOCK# Float Delay D0-D15, DP0, DP1 Write Delay D0-D15, DP0, DP1 Float Delay EADS# Setup Time EADS# Hold Time KEN# Setup Time KEN# Hold Time RDY#, BRDY# Setup Time RDY#, BRDY# Hold Time
Note 3
t8 t8a t9 t10 t11 t12 t13 t14 t15 t16 t17
ns ns ns ns ns ns ns ns ns ns ns Note 3 Note 3
Embedded Ultra-Low Power Intel486 GX Processor
Symbol Parameter HOLD, AHOLD Setup Time BOFF# Setup Time HOLD, AHOLD, BOFF# Hold Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Setup Time FLUSH#, A20M#, NMI, INTR, SMI#, STPCLK#, SRESET, RESET Hold Time D0-D15, DP0, DP1, A4A31 Read Setup Time D0-D15, DP0, DP1, A4A31 Read Hold Time
Unit ns ns ns ns
Notes
t18 t18a t19 t20
t22 t23
Embedded Ultra-Low Power Intel486 GX Processor
2.0 V CLK 1.5 V 0.8 V t2 t5 t1 tx ty t4 t3
Tx CLK
EADS#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A4-A31 (READ)
Figure 10. Input Setup and Hold Timing
Embedded Ultra-Low Power Intel486 GX Processor
T2 CLK
RDY#, BRDY#
D15-D0, DP0, DP1
Figure 11. Input Setup and Hold Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID n
VALID n+1
D15-D0, DP0, DP1
VALID n
VALID n+1
BLAST#, PLOCK#
VALID n
VALID n+1
Figure 12. Output Valid Delay Timing
Embedded Ultra-Low Power Intel486 GX Processor
Tx CLK
RDY#, BRDY#
D0-D15 DP0, DP1
VALID
MIN MAX
PCHK#
VALID
Figure 13. PCHK# Valid Delay Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ
VALID
D15-D0, DP0, DP1
VALID
BLAST#, PLOCK#
VALID
Figure 14. Maximum Float Delay Timing
Embedded Ultra-Low Power Intel486 GX Processor
2.0 V t27
0.8 V t28 t26 t29
Figure 15. TCK Waveform
TCK t30 TMS TDI t32 TDO t34 OUTPUT t36 INPUT VALID VALID t37 VALID t35 VALID VALID t33 t31
Figure 16. Test Signal Timing Diagram
Embedded Ultra-Low Power Intel486 GX Processor
Capacitive Derating Curves
nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 Capacitive Load (pF) 125 150
Embedded Ultra-Low Power Intel486 GX Processor
MECHANICAL DATA
This section describes the packaging dimensions and thermal specifications for the embedded ULP Intel486 GX processor.
Package Dimensions
89 0.16 Min o.28 Max 45 88
NOTES: Height measurements same as width measurements Units: mm
A4586-01
Figure 19. Package Mechanical Specifications for the 176-Lead TQFP Package
Embedded Ultra-Low Power Intel486 GX Processor
Package Thermal Specifications
Table 21. Thermal Resistance (°C / W) JC and JA for the 176-Lead TQFP Package JC (°C / W) 4.3 JA (°C / W) with no airflow 33.6
Table 22. Maximum Ambient Temperature (TA) 176-Lead TQFP Package Frequency 16 MHz VCC 2.0 V 3.3 V 2.2 V 3.3 V 2.4 V 3.3 V 2.7 V 3.3 V TA (°C) with no airflow 83 73 80 70 77 66 70 60
20 MHz
25 MHz
33 MHz