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EMBEDDED ULTRA-LOW POWER Intel486 SX PROCESSOR

s Ultra-Low Power Version of the Intel486 s 176-Lead Thin Quad Flat Pack (TQFP)

EMBEDDED ULTRA-LOW POWER Intel486 SX PROCESSOR
s Ultra-Low Power Version of the Intel486 s 176-Lead Thin Quad Flat Pack (TQFP)
SX Processor s - 32-Bit RISC Technology Core s - 8-Kbyte Write-Through Cache s - Four Internal Write Buffers - Burst Bus Cycles s - Dynamic Bus Sizing for 8- and 16-bit Data Bus Devices - Intel System Management Mode (SMM) - Boundary Scan (JTAG)
64-Bit Interunit Transfer Bus
32-Bit Data Bus 32-Bit Data Bus Linear Address 32 32 32 PCD PWT
Separate Voltage Supply for Core Circuitry Fast Core-Clock Restart Auto Clock Freeze Ideal for Embedded Battery-Operated and Hand-Held Applications
Core Clock
Clock Control
CLK Input
Barrel Shifter Register File ALU
Base / Index Bus 32
Segmentation Unit Descriptor Registers Limit and Attribute PLA
Bus Interface
Paging Unit
Cache Unit
Address Drivers Write Buffers 4 x 32 Data Bus
32 Transceivers
A31-A2 BE3#- BE0#
Physical Address Translation Lookaside Buffer
8 Kbyte Cache
D31-D0
Bus Control
Displacement Bus
Prefetcher MicroInstruction 32-Byte Code Queue 2x16 Bytes Request Sequencer
ADS# W / R# D / C# M / IO# PCD PWT RDY# LOCK# PLOCK# BOFF# A20M# BREQ HOLD HLDA RESET SRESET INTR NMI SMI# SMIACT# STPCLK#
Control & Protection Test Unit
Code Stream Instruction Decode Decoded Instruction Path
Burst Bus Control
BRDY# BLAST#
Control ROM
Bus Size Control
BS16# BS8#
Cache Control Boundary Scan Control
KEN# FLUSH# AHOLD EADS#
TCK TMS TDI TD0
A5850-01
Contents
Embedded Ultra-Low Power Intel486 SX Processor
Contents
Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19.
TCK Waveform ............................................................ 30 Test Signal Timing Diagram ................................................... 31 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition ................................................... 32 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition ................................................... 32 Package Mechanical Specifications for the 176 Lead TQFP Package .................. 33
The Embedded Ultra-Low Power Intel486 SX Processor ............................ 2 Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor .... 5 Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor ...................................................... 6 Embedded ULP Intel486 SX Processor Pin Descriptions ........................... 7 Output Pins ............................................................... 12 Input / Output Pins ........................................................... 13 Test Pins ................................................................. 13 Input Pins ................................................................. 14 CPUID Instruction Description ................................................. 19 Boundary Scan Component Identification Code ................................... 21 Absolute Maximum Ratings ................................................... 22 Operating Supply Voltages ................................................... 22 DC Specifications ........................................................... 23 Active ICC Values ........................................................... 24 Clock Stop, Stop Grant, and Auto HALT Power Down ICC Values ..................... 24 AC Characteristics .......................................................... 25 AC Specifications for the Test Access Port ....................................... 27 Thermal Resistance ......................................................... 34 Maximum Ambient Temperature (TA) ........................................... 34
Embedded Ultra-Low Power Intel486 SX Processor
INTRODUCTION
· On-Chip Memory Management Unit - Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both segmentation and paging are supported. · Burst Cycles - Burst transfers allow a new double word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. · Write Buffers - The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. · Bus Backoff - When another bus master needs control of the bus during a processor initiated bus cycle, the embedded ULP Intel486 SX processor floats its bus signals, then restarts the cycle when the bus becomes available again. · Instruction Restart - Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications. · Dynamic Bus Sizing - External controllers can dynamically alter the effective width of the data bus. Bus widths of 8, 16, or 32 bits can be used. · Boundary Scan (JTAG) - Boundary Scan provides in-circuit testing of components on printed circuit boards. The Intel Boundary Scan implementation conforms with the IEEE Standard Test Access Port and Boundary Scan Architecture. · Intel System Management Mode (SMM) - A unique Intel architecture operating mode provides a dedicated special purpose interrupt and address space that can be used to implement intelligent power management and other enhanced functions in a manner that is completely transparent to the operating system and applications software. · I / O Restart - An I / O instruction interrupted by a System Management Interrupt (SMI#) can automatically be restarted following the execution of the RSM instruction. · Stop Clock - The embedded ULP Intel486 SX processor has a stop clock control mechanism that provides two low-power states: a Stop Grant state (40-85 mW typical, depending on input clock frequency) and a Stop Clock state (~60 µW typical, with input clock frequency of 0 MHz).
Features
The embedded ULP Intel486 SX processor offers these features of the Intel486 SX processor: · 32-bit RISC-Technology Core - The embedded ULP Intel486 SX processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. · Single Cycle Execution - Many instructions execute in a single clock cycle. · Instruction Pipelining - Overlapped instruction fetching, decoding, address translation and execution. · On-Chip Cache with Cache Consistency Support - An 8-Kbyte, write-through, internal cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. · External Cache Control - Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency.
Embedded Ultra-Low Power Intel486 SX Processor
· Auto HALT Power Down - After the execution of a HALT instruction, the embedded ULP Intel486 SX processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state (40-85 mW typical, depending on input clock frequency). The embedded ULP Intel486 SX processor differs from the Intel486 SX processor in the following areas: · Processor Upgrade Removed - The UP# signal is not provided. · Parity Signals Removed - The DP3-DP0 and PCHK# signals are not provided. · Separate Processor-Core Power - While the embedded ULP Intel486 SX processor requires a supply voltage of 3.3 V, the processor core has dedicated VCC pins and operates with a supply voltage as low as 2.4 V. · Small, Low-Profile Package - The 176-Lead Thin Quad Flat Pack (TQFP) package is approximately 26 mm square and only 1.5 mm in height. This is approximately the diameter and thickness of a U.S. quarter. The embedded ULP Intel486 SX processor is ideal for embedded hand-held and battery-powered applications.
· Level Keeper Circuits - The embedded ULP Intel486 SX processor has level-keeper circuits for its 32-bit external data bus signals. They retain valid high and low logic voltage levels when the processor is in the Stop Grant and Stop Clock states. This is a power-saving improvement from the floating data bus of the Intel486 SX processor. · Auto Clock Freeze - The embedded ULP Intel486 SX processor monitors bus events and internal activity. The Auto Clock Freeze feature automatically controls internal clock distribution, turning off clocks to internal units when they are idle. This power-saving function is transparent to the embedded system. · Fast Clock Restart - The embedded ULP Intel486 SX processor requires only eight clock periods to synchronize its internal clock with the CLK input signal. This provides for faster transition from the Stop Clock State to the Normal State. For 33-MHz operation, this synchronization time is only 240 ns compared with 1 ms (PLL startup latency) for the Intel486 processor.
Family Members
Table 1 shows the embedded ULP Intel486 SX processor and briefly describes its characteristics.
Table 1. The Embedded Ultra-Low Power Intel486 SX Processor Supply Voltage
(VCCP)
Product
Processor Core Supply Voltage
(VCC)
Processor Frequency
(MHz)
Package
FA80486SXSF-33
176-Lead TQFP
Embedded Ultra-Low Power Intel486 SX Processor
HOW TO USE THIS DOCUMENT
PIN DESCRIPTIONS Pin Assignments
The following figures and tables show the pin assignments for the 176-pin Thin Quad Flat Pack (TQFP) package of the embedded ULP Intel486 SX processor. Included are: · Figure 2, Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor (pg. 4) · Table 2, Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor (pg. 5) · Table 3, Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor (pg. 6) · Table 4, Embedded ULP Intel486 SX Processor Pin Descriptions (pg. 7) · Table 5, Output Pins (pg. 13) · Table 6, Input / Output Pins (pg. 13) · Table 7, Test Pins (pg. 14) · Table 8, Input Pins (pg. 14) The tables and figures show "no-connects" as "N / C." These pins should always remain unconnected. Connecting N / C pins to VCC, VCCP, VSS, or any other signal pin can result in component malfunction or incompatibility with future steppings of the embedded ULP Intel486 SX processor.
Embedded Ultra-Low Power Intel486 SX Processor
Figure 2. Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor
EADS# A20M# RESET VSS FLUSH# INTR NMI SRESET SMIACT# VCC VSS VCCP SMI# TDO VCC STPCLK# D31 D30 D29 D28 VCC VCCP VSS D27 D26 D25 D24 VCCP VSS D23 D22 D21 VCCP VSS D20 D19 D18 VCC D17 VSS VSS VCCP D16 VSS
BLAST# VCC PLOCK# LOCK# VSS VCCP N / C BRDY# BOFF# BS16# BS8# VCC N / C RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC VSS CLK HLDA W / R# VSS VCCP BREQ BE0# BE1# BE2# BE3# VCC M / IO# D / C# PWT PCD VCCP VSS VCC
ADS# A2 VSS VCCP VSS VSS VCCP A3 A4 A5 RESERVED# A6 A7 A8 VSS VCC A9 A10 VCCP VSS VCC A11 A12 VCC A13 A14 VCCP VSS A15 A16 A17 VSS VCCP TDI TMS A18 A19 A20 VCCP VCCP A21 A22 A23 A24
176-Lead TQFP (top view)
VSS VSS VCCP A25 A26 A27 A28 VCCP A29 A30 A31 VSS D0 D1 D2 D3 D4 VCC VSS VCC VCC VSS VCC VCC VSS VCCP D5 D6 VCCP N / C D7 VSS D8 D9 VSS VCC D10 D11 D12 D13 VSS VCCP D14 D15
Embedded Ultra-Low Power Intel486 SX Processor
Table 2. Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor Pin #
Description
BLAST# VCC PLOCK# LOCK# VSS VCCP N / C BRDY# BOFF# BS16# BS8# VCC N / C RDY# KEN# VCC VSS HOLD AHOLD TCK VCC VCC VSS VCC VCC VSS CLK HLDA W / R# VSS VCCP BREQ BE0# BE1# BE2# BE3# VCC M / IO# D / C# PWT PCD VCCP VSS VCC
Description
EADS# A20M# RESET VSS FLUSH# INTR NMI SRESET SMIACT# VCC VSS VCCP SMI# TDO VCC STPCLK# D31 D30 D29 D28 VCC VCCP VSS D27 D26 D25 D24 VCCP VSS D23 D22 D21 VCCP VSS D20 D19 D18 VCC D17 VSS VSS VCCP D16 VSS
Description
D15 D14 VCCP VSS D13 D12 D11 D10 VCC VSS D9 D8 VSS D7 N / C VCCP D6 D5 VCCP VSS VCC VCC VSS VCC VCC VSS VCC D4 D3 D2 D1 D0 VSS A31 A30 A29 VCCP A28 A27 A26 A25 VCCP VSS VSS
Description
A24 A23 A22 A21 VCCP VCCP A20 A19 A18 TMS TDI VCCP VSS A17 A16 A15 VSS VCCP A14 A13 VCC A12 A11 VCC VSS VCCP A10 A9 VCC VSS A8 A7 A6 RESERVED# A5 A4 A3 VCCP VSS VSS VCCP VSS A2 ADS#
Embedded Ultra-Low Power Intel486 SX Processor
Table 3. Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 SX Processor Address
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31
Control
AHOLD BE0# BE1# BE2# BE3# BLAST# BOFF# BRDY# BREQ BS16# BS8# CLK D / C# HLDA HOLD KEN# LOCK# M / IO# PCD PLOCK# PWT RESERVED# RDY# TCK W / R# A20M# EADS# FLUSH# INTR NMI RESET SMI# SMIACT# SRESET STPCLK# TDO ADS# TDI TMS W / R#
Embedded Ultra-Low Power Intel486 SX Processor
Pin Quick Reference
ADDRESS BUS A31-A4 A3-A2 I / O O
BE3# BE2# BE1# BE0#
Embedded Ultra-Low Power Intel486 SX Processor
Table 4. Embedded ULP Intel486 SX Processor Pin Descriptions (Sheet 2 of 6) Symbol M / IO# D / C# W / R# Type O O O Name and Function Memory / Input-Output, Data / Control and Write / Read lines are the primary bus definition signals. These signals are driven valid as the ADS# signal is asserted. M / IO# 0 0 0 0 1 1 1 1 Cycle Name Shutdown HALT Stop Grant bus cycle LOCK# O D / C# 0 0 1 1 0 0 1 1 HALT / Special Cycle BE3# - BE0# 1110 1011 1011 A4-A2 000 000 100 W / R# 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge HALT / Special Cycle (see details below) I / O Read I / O Write Code Read Reserved Memory Read Memory Write
BUS CYCLE DEFINITION
Bus Lock indicates that the current bus cycle is locked. The embedded ULP Intel486 SX processor does not allow a bus hold when LOCK# is asserted (address holds are allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes inactive after the last clock of the last locked bus cycle. The last locked cycle ends when Ready is returned. LOCK# is active LOW and not driven during bus hold. Locked read cycles are not transformed into cache fill cycles when KEN# is returned active. Pseudo-Lock indicates that the current bus transaction requires more than one bus cycle to complete. For the embedded ULP Intel486 SX processor, examples of such operations are segment table descriptor reads (64 bits) and cache line fills (128 bits). The embedded ULP Intel486 SX processor drives PLOCK# active until the addresses for the last bus cycle of the transaction are driven, regardless of whether RDY# or BRDY# have been returned. PLOCK# is a function of the BS8#, BS16# and KEN# inputs. PLOCK# should be sampled only in the clock in which Ready is returned. PLOCK# is active LOW and is not driven during bus hold.
PLOCK#
BUS CONTROL ADS# O Address Status output indicates that a valid bus cycle definition and address are available on the cycle definition lines and address bus. ADS# is driven active in the same clock in which the addresses are driven. ADS# is active LOW and not driven during bus hold.
Embedded Ultra-Low Power Intel486 SX Processor
INTERRUPTS RESET I
Embedded Ultra-Low Power Intel486 SX Processor
SMIACT#
STPCLK#
BUS ARBITRATION BREQ O
Embedded Ultra-Low Power Intel486 SX Processor
CACHE INVALIDATION AHOLD I
EADS#
CACHE CONTROL KEN# I
FLUSH#
PAGE CACHEABILITY PWT PCD O O
Embedded Ultra-Low Power Intel486 SX Processor
BUS SIZE CONTROL
ADDRESS MASK A20M# I
TEST ACCESS PORT TCK I
RESERVED PINS RESERVED# I
Embedded Ultra-Low Power Intel486 SX Processor
Table 5. Output Pins Output Signal Name BREQ HLDA BE3#-BE0# PWT, PCD W / R#, M / IO#, D / C# LOCK# PLOCK# ADS# BLAST# A3-A2 SMIACT# Active Level HIGH HIGH LOW HIGH HIGH / LOW LOW LOW LOW LOW HIGH LOW · · · · · · · · · Floated During Address Hold Floated During Bus Hold During Stop Grant and Stop Clock States1 Previous State As per HOLD Previous State Previous State Previous State HIGH (inactive) HIGH (inactive) HIGH (inactive) Previous State Previous State Previous State
NOTES: 1. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Table 6. Input / Output Pins Output Signal Name D31-D0 A31-A4 Active Level HIGH HIGH · Floated During Address Hold Floated During Bus Hold · · During Stop Grant and Stop Clock States1, 2 Level-Keeper Previous State
NOTES: 1. The term "Level-Keeper" means that the processor maintains the most recent logic level applied to the signal pin. This conserves power by preventing the signal pin from floating. If a system component, other than the processor, temporarily drives these signal pins and then floats them, the processor forces and maintains the most recent logic levels that were applied by the system component. 2. The term "Previous State" means that the processor maintains the logic level applied to the signal pin just before the processor entered the Stop Grant state. This conserves power by preventing the signal pin from floating.
Embedded Ultra-Low Power Intel486 SX Processor
Table 7. Test Pins Name TCK TDI TDO TMS Input or Output Input Input Output Input Table 8. Input Pins Name CLK RESET SRESET HOLD AHOLD EADS# BOFF# FLUSH# A20M# BS16#, BS8# KEN# RDY# BRDY# INTR NMI RESERVED# SMI# STPCLK# TCK TDI TMS LOW LOW HIGH HIGH HIGH Asynchronous Asynchronous Pull-Up Pull-Up1 Pull-Up Pull-Up Pull-Up HIGH HIGH HIGH HIGH LOW LOW LOW LOW LOW LOW LOW LOW HIGH HIGH Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Synchronous Asynchronous Asynchronous Pull-Up Pull-Down Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Up Pull-Down Active Level Synchronous / Asynchronous Internal Pull-Up / Pull-Down Sampled / Driven On N / A Rising Edge of TCK Failing Edge of TCK Rising Edge of TCK
NOTE: 1. Though STPCLK# has an internal pull-up resistor, an external 10-K pull-up resistor is needed if the STPCLK# pin is not used.
Embedded Ultra-Low Power Intel486 SX Processor
ARCHITECTURAL AND FUNCTIONAL OVERVIEW
· The embedded ULP Intel486 SX processor has one pin reserved for possible future use. This pin is an input signal, pin 166. It is called RESERVED# and must be connected to a 10-K pull-up resistor.
Separate Supply Voltages
Embedded Ultra-Low Power Intel486 SX Processor
VCC and VCCP (V)
VCCP min
VCC min
0V TIME
POWER ON POWER OFF
Figure 3. Example of Supply Voltage Power Sequence
Embedded Ultra-Low Power Intel486 SX Processor
Fast Clock Restart
The embedded ULP Intel486 SX processor has an integrated proprietary differential delay line (DDL) circuit for internal clock generation. The DDL is driven by the CLK input signal provided by the external system. During normal operation, the external system must guarantee that the CLK signal maintains its frequency so that the clock period deviates no more than 250 ps / CLK. This state, called the Normal State, is shown in Figure 4. To increase or decrease the CLK frequency more quickly than this, the system must interrupt the processor with the STPCLK# signal. Once the processor indicates that it is in the Stop Grant State, the system can adjust the CLK signal to the new frequency, wait a minimum of eight CLK periods, then force the processor to return to the normal
operational state by deactivating the STPCLK# interrupt. This wait of eight CLK periods is much faster than the 1 ms wait required by earlier Intel486 SX processor products. While in the Stop Grant State, the external system may deactivate the CLK signal to the processor. This forces the processor to the Stop Clock State - the state in which the processor consumes the least power. Once the system reactivates the CLK signal, the processor transitions to the Stop Grant State within eight CLK periods. Normal operation can be resumed by deactivating the STPCLK# interrupt signal. Here again, the embedded ULP Intel486 SX processor recovers from the Stop Clock State much faster than the 1 ms PLL recovery of earlier Intel486 SX processors.
4 Auto HALT Power Down State
CLK Running 40 - 85 mWatts
HALT asserted and HALT bus cycle generated
1 Normal State
Normal Execution
INTR, NMI, SMI# RESET, SRESET STPCLK# asserted and Stop Grant bus cycle generated
EADS# STPCLK# deasserted and HALT bus cycle generated STPCLK# asserted and Stop Grant bus cycle generated
STPCLK# deasserted
EADS#
2 Stop Grant State
CLK Running 40 - 85 mWatts
5 Stop Clock Snoop State
One Clock PowerUp Perform Cache Invalidation
Stop CLK
Start CLK plus DDL Startup Latency
3 Stop Clock State
Internal Powerdown CLK Stopped ~ 60 µWatts
Figure 4. Stop Clock State Diagram with Typical Power Consumption Values
Embedded Ultra-Low Power Intel486 SX Processor
Level-Keeper Circuits
At all other times during the Stop Grant and Stop Clock states, the processor maintains the logic levels of D31-D0. When the external system circuitry drives D31-D0 to different logic levels, the processor flips its D31-D0 logic levels to match the ones driven by the external system. The processor maintains (keeps) these new levels even after the external circuitry stops driving D31-D0. For some system designs, external resistors may not be required on D31- D0 (they are required on previous Intel486 SX processor designs). System designs that never request Bus Hold during the Stop Grant and Stop Clock states might not require external resistors. If the system design uses Bus Hold during these states, the processor disables the level-keepers and floats the data bus. This type of design would require some kind of data bus termination to minimize power consumption. It is strongly recommended that the D31-D0 pins do not have network resistors connected. External resistors used in the system design must be of a sufficient resistance value to "flip" the level-keeper circuitry and eliminate potential DC paths. The level-keeper circuit is designed to allow an external 27-K pull-up resistor to switch the D31-D0 circuits to a logic-HIGH level even though the levelkeeper attempts to keep a logic-LOW level. In general, pull-up resistors smaller than 27 K can be used as well as those greater than or equal to 1 M. Pull-down resistors, when connected to D31-D0, should be least 800 K.
Embedded Ultra-Low Power Intel486 SX Processor
Low-Power Features
As with other Intel486 processors, the embedded ULP Intel486 SX processor minimizes power consumption by providing the Auto HALT Power Down, Stop Grant, and Stop Clock states (see Figure 4). The embedded ULP Intel486 SX processor has an Auto Clock Freeze feature that further conserves power by judiciously deactivating its internal clocks while in the Normal Execution Mode. The power-conserving mechanism is designed such that it does not degrade processor performance or require changes to AC timing specifications. 4.4.1 Auto Clock Freeze
The embedded ULP Intel486 SX processor also reduces power consumption by temporarily freezing the clocks of its internal logic blocks. When a logic block is idle or in a wait state, its clock is frozen.
CPUID Instruction
To reduce power consumption, during the following bus cycles - under certain conditions - the processor slows-up or freezes some internal clocks: · Data-Read Wait Cycles (Memory, I / O and Interrupt Acknowledge) · Data-Write Wait Cycles (Memory, I / O) · HOLD / HLDA Cycles · AHOLD Cycles · BOFF Cycles Power is conserved during the wait periods in these cycles until the appropriate external-system signals are sent to the processor. These signals include: · READY · NMI, SMI#, INTR, and RESET · BOFF# · FLUSH# · EADS# · BS8#, BS16# and KEN# transitions
The CPUID instruction requires the software developer to pass an input parameter to the processor in the EAX register. The processor response is returned in registers EAX, EBX, EDX, and ECX.
Table 9. CPUID Instruction Description OP CODE 0F A2 Instruction CPUID Processor Core Clocks 9 14 9 Parameter passed in EAX
(Input Value)
Description Vendor (Intel) ID String Processor Identification Undefined (Do Not Use)
Embedded Ultra-Low Power Intel486 SX Processor
Vendor ID String (ASCII Characters)
EBX EDX ECX
u (75) I (49) l (6C)
n (6E) e (65) e (65)
e (65) n (6E) t (74)
G (47) i (69) n (6E)
The values in EBX, EDX and ECX indicate an Intel processor. When taken in the proper order, they decode to the string "GenuineIntel." Processor Identification - When the parameter passed to EAX is 1 (one), the register values returned upon instruction execution are: 31--------------14 Processor Signature EAX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 0010 Model 3--0 XXXX Stepping
(Intel releases information about stepping numbers as needed) 31-------------------------------------------------0 Intel Reserved (Do Not Use) EBX ECX Intel Reserved Intel Reserved 31--------------------------------------2 Feature Flags EDX 0---------------------------------------0 1 1 VME 0 0 FPU
Identification After Reset
31--------------14 Processor Signature EDX (Do Not Use) Intel Reserved 13, 12 00 Processor Type 11--8 0100 Family 7--4 0010 Model 3--0 XXXX Stepping
Processor Identification - Upon reset, the EDX register contains the processor signature:
(Intel releases information about stepping numbers as needed)
Embedded Ultra-Low Power Intel486 SX Processor
Boundary Scan (JTAG)
Device Identification
Table 10 shows the 32-bit code for the embedded ULP Intel486 SX processor which is loaded into the Device Identification Register. Table 10. Boundary Scan Component Identification Code Version VCC
31--28 XXXX
Boundary Scan Register Bits and Bit Order
The following is the bit order of the embedded ULP Intel486 SX processor boundary scan register: TDO A2, A3, A4, A5, RESERVED#, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, Reserved, D0, D1, D2, D3, D4, D5, D6, D7, Reserved, D8, D9, D10, D11, D12, D13, D14, D15, Reserved, D16, D17, D18, D19, D20, D21, D22, D23, Reserved, D24, D25, D26, D27, D28, D29, D30, D31, STPCLK#, Reserved, Reserved, SMI#, SMIACT#, SRESET, NMI, INTR, FLUSH#, RESET, A20M#, EADS#, PCD, PWT, D / C#, M / IO#, BE3#, BE2#, BE1#, BE0#, BREQ, W / R#, HLDA, CLK, Reserved, AHOLD, HOLD, KEN#, RDY#, BS8#, BS16#, BOFF#, BRDY#, Reserved, LOCK#, PLOCK#, BLAST#, ADS#, MISCCTL, BUSCTL, ABUSCTL, WRCTL TDI
The boundary scan register contains a cell for each pin as well as cells for control of bidirectional and three-state pins. There are "Reserved" bits which correspond to no-connect (N / C) signals of the embedded ULP Intel486 SX processor. Control registers WRCTL, ABUSCTL, BUSCTL, and MISCCTL are used to select the direction of bidirectional or three-state output signal pins. A "1" in these cells designates that the associated bus or bits are floated if the pins are three-state, or selected as input if they are bidirectional. · WRCTL controls D31-D0 · ABUSCTL controls A31-A2 · BUSCTL controls ADS#, BLAST#, PLOCK#, LOCK#, W / R#, BE0#, BE1#, BE2#, BE3#, M / IO#, D / C#, PWT, and PCD · MISCCTL controls HLDA, and BREQ
Embedded Ultra-Low Power Intel486 SX Processor
ELECTRICAL SPECIFICATIONS Maximum Ratings
Table 11. Absolute Maximum Ratings Case Temperature under Bias Storage Temperature -65 °C to +110 °C -65 °C to +150 °C -0.5 V to VCCP + 0.5 V -0.5 V to +4.6 V -0.5 V to +4.6 V
Table 11 is a stress rating only. Extended exposure to the Maximum Ratings may affect device reliability. Furthermore, although the embedded ULP Intel486 SX processor contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields. Functional operating conditions are given in Section 5.2, DC Specifications and Section 5.3, AC Specifications.
DC Voltage on Any Pin with Respect to Ground Supply Voltage VCC with Respect to VSS Supply Voltage VCCP with Respect to VSS
DC Specifications
The following tables show the operating supply voltages, DC I / O specifications, and component power consumption for the embedded ULP Intel486 SX processor.
NOTES: 1. In all cases, VCCP must be VCC. 2. VCC may be set to any voltage within the VCC Range. The setting determines the allowed VCC Fluctuation.
VCC Fluctuation
Embedded Ultra-Low Power Intel486 SX Processor
NOTES: 1. The ICC Stop Clock specification refers to the ICC value once the processor enters the Stop Clock state. For all input signals, the VIH and VIL levels must be equal to VCCP and 0V, respectively, to meet the ICC Stop Clock specifications.
Embedded Ultra-Low Power Intel486 SX Processor
AC Specifications
Note 3
t8a t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t18a
ns ns ns ns ns ns ns ns ns ns ns ns Note 3 Note 3
Embedded Ultra-Low Power Intel486 SX Processor
t22 t23 NOTES:
Embedded Ultra-Low Power Intel486 SX Processor
2.0 V CLK 1.5 V 0.8 V t2 t5 t1 tx ty t4 t3
Tx CLK
EADS#
BS8#, BS16#, KEN#
BOFF#, AHOLD, HOLD
RESET, FLUSH#, A20M#, INTR, NMI, SMI#, STPCLK#, SRESET A4-A31 (READ)
Figure 6. Input Setup and Hold Timing
Embedded Ultra-Low Power Intel486 SX Processor
T2 CLK
RDY#, BRDY#
D0-D31
Figure 7. Input Setup and Hold Timing
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ, HLDA, SMIACT#
VALID n
VALID n+1
D0-D31
VALID n
VALID n+1
BLAST#, PLOCK#
VALID n
VALID n+1
Figure 8. Output Valid Delay Timing
Embedded Ultra-Low Power Intel486 SX Processor
Tx CLK
A2-A31, PWT, PCD, BE0-3#, M / IO#, D / C#, W / R#, ADS#, LOCK#, BREQ
VALID
D31-D0
VALID
BLAST#, PLOCK#
VALID
Figure 9. Maximum Float Delay Timing
2.0 V t27
0.8 V t28 t26 t29
Figure 10. TCK Waveform
Embedded Ultra-Low Power Intel486 SX Processor
TCK t30 TMS TDI t32 TDO t34 OUTPUT t36 INPUT VALID VALID t37 VALID t35 VALID VALID t33 t31
Figure 11. Test Signal Timing Diagram
Embedded Ultra-Low Power Intel486 SX Processor
Capacitive Derating Curves
nom+5 Delay (ns) nom+4 nom+3 nom+2 nom+1 nom nom-1 nom-2 25 50 75 100 Capacitive Load (pF) 125 150
Embedded Ultra-Low Power Intel486 SX Processor
MECHANICAL DATA
This section describes the packaging dimensions and thermal specifications for the embedded ULP Intel486 SX processor.
Package Dimensions
89 0.16 Min o.28 Max 45 88
NOTES: Height measurements same as width measurements Units: mm
A4586-01
Figure 14. Package Mechanical Specifications for the 176-Lead TQFP Package
Embedded Ultra-Low Power Intel486 SX Processor
Package Thermal Specifications
Table 18. Thermal Resistance (°C / W) JC and JA for the 176-Lead TQFP Package JC (°C / W) 4.3 JA (°C / W) with no airflow 33.6
Table 19. Maximum Ambient Temperature (TA) 176-Lead TQFP Package Frequency 25 MHz VCC 2.4 V 3.3 V 2.7 V 3.3 V TA (°C) with no airflow 76 65 69 59
33 MHz