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Embedded Pentium® Processor with Voltage Reduction Technology

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Embedded Pentium® Processor with Voltage Reduction Technology
Datasheet
Product Features
Compatible with Large Software Base - MS-DOS, Windows, OS / 2, UNIX 32-Bit Processor with 64-Bit Data Bus Superscalar Architecture - Two Pipelined Integer Units are Capable of Two Instructions / Clock - Pipelined Floating-Point Unit Separate Code and Data Caches - 8-Kbyte Code, 8-Kbyte Write-Back Data - MESI Cache Protocol Advanced Design Features - Branch Prediction - Virtual Mode Extensions
Low-Voltage BiCMOS Silicon Technology 4-Mbyte Pages for Increased TLB Hit Rate IEEE 1149.1 Boundary Scan Internal Error Detection Features SL Enhanced Power Management Features - System Management Mode - Clock Control Voltage Reduction Technology - 3.1 V VCC for Core Supply - 3.3 V VCC for I / O Buffer Supply Fractional Bus Operation - 133-MHz Core / 66-MHz Bus (iCOMP® Index 2.0 Rating of 111)
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Order Number: 273203-001 November 1998
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Contents
1.0 2.0 3.0 Introduction ......................................................... 7 Architecture Overview ............................................... 7
2.1 3.1 3.2 Pentium® Processor Family Architecture ............................... 8 Differences from the Pentium Processor...............................10 Pinout .........................................................11 3.2.1 Pin Cross Reference .......................................14 3.2.2 Design Notes.............................................16 3.2.3 Pin Quick Reference .......................................16 3.2.4 Pin Reference Tables.......................................22 3.2.5 Pin Grouping According to Function............................24 Mechanical Specifications ..........................................25 Thermal Specifications ............................................26 3.4.1 Measuring Thermal Values ..................................26 3.4.2 Thermal Equations .........................................27 Absolute Maximum Ratings.........................................28 DC Specifications ................................................28 4.2.1 Power Sequencing .........................................30 AC Specifications ................................................30 4.3.1 Power and Ground .........................................30 4.3.2 Decoupling Recommendations ...............................30 4.3.3 Connection Specifications ...................................31 4.3.4 AC Timings...............................................31 I / O Buffer Models ................................................39 4.4.1 Buffer Model Parameters ....................................41 4.4.2 Signal Quality Specifications .................................43 4.4.2.1 Ringback ..........................................43 4.4.2.2 Settling Time .......................................44
Packaging Information ..............................................10
Electrical Specifications ............................................28
Figures
1 2 3 4 5 6 7 8 9 Pentium® Processor with Voltage Reduction Technology Block Diagram ...... 9 SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Top Side View)............................................12 SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Pin Side View).............................................13 296-Pin Staggered Pin Grid Array Package (SPGA) .....................25 Technique for Measuring Case Temperature (TC) .......................26 Clock Waveform .................................................35 Valid Delay Timings...............................................35 Float Delay Timings...............................................36 Setup and Hold Timings ...........................................36
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Reset and Configuration Timings.................................... 37 Test Timings.................................................... 38 Test Reset Timings ............................................... 38 Input Buffer Model, Except Special Group ............................. 39 Input Buffer Model for Special Group................................. 40 First-Order Output Buffer Model..................................... 41 Overshoot / Undershoot and Ringback Guidelines ........................ 43 Settling Time .................................................... 44
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Signals Removed from the Pentium® Processor with Voltage Reduction Technology ...................................... 11 Pin Cross-Reference by Pin Name - Address and Data Pins .............. 14 Pin Cross-Reference by Pin Name - Control Pins ...................... 15 No Connect, Power and Ground Pins ................................. 16 Pin Quick Reference .............................................. 17 Output Pins ..................................................... 22 Input Pins ...................................................... 23 Input / Output Pins ................................................ 24 Pin Functional Grouping........................................... 24 296-Pin Staggered Pin Grid Array Package Dimensions Key............... 25 Power Dissipation Requirements for Thermal Solution Design ............. 26 Thermal Resistances for Embedded Pentium® Processors with Voltage Reduction Technology.................................. 27 Absolute Maximum Ratings ........................................ 28 DC Specifications................................................ 29 3.3-V (5-V Safe) DC Specifications................................... 29 Input and Output Characteristics..................................... 29 AC Specifications ................................................ 31 Notes for Table 17 ................................................ 34 Parameters Used in the Specification of the First Order Input Buffer Model ... 40 Parameters Used in the Specification of the First-Order Output Buffer Model .. 41 Buffer Selection Chart ............................................. 41 Signal to Buffer Type.............................................. 42 Input, Output and Bidirectional Buffer Model Parameters.................. 42 Input Buffer Model Parameters: D (Diodes) ............................ 42
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Revision History
Date 11 / 12 / 98 Revision 001 Description This is the first publication of this document
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Introduction
The Intel® embedded Pentium® processor with voltage reduction technology is a reduced power version of the embedded Pentium processor. Voltage reduction technology allows the processor to interface with industry standard 3.3-volt components while its inner core, operating at 3.1 volts, consumes less power. The embedded Pentium processor with voltage reduction technology is available in a Staggered Pin Grid Array (SPGA) package. It has all the advanced features of the original Pentium processor except for the differences listed in "Differences from the Pentium Processor" on page 10. The embedded Pentium processor with voltage reduction technology has several features that are ideal for embedded applications, including:
· 3.1-V core and 3.3-V I / O buffer VCC inputs reduce power consumption significantly, while
· The SL Enhanced feature set, which was initially implemented in the Intel486 processor
243191, and 243192)
Architecture Overview
The embedded Pentium processor with voltage reduction technology extends the Intel Pentium family of microprocessors. The embedded Pentium processor family consists of the embedded Pentium processor, the embedded Pentium processor with voltage reduction technology described in this document, the embedded Pentium processor with MMX technology, and the low-power embedded Pentium processor with MMX technology. "Pentium processor" is used in this document to refer to the entire Pentium processor family in general. The embedded Pentium processor family architecture contains all the features of the Intel486 processor family, and provides significant enhancements including the following:
Datasheet
Superscalar architecture Dynamic branch prediction Pipelined floating-point unit Improved instruction execution time Separate 8-Kbyte code and 8-Kbyte data caches Writeback MESI protocol in the data cache 64-Bit data bus Bus cycle pipelining
Embedded Pentium® Processor with Voltage Reduction Technology
Address parity Internal parity checking Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Voltage reduction technology SL Power management features
Pentium® Processor Family Architecture
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Branch Prefetch Target Buffer Address
TLB Code Cache 8 Kbytes
Instruction Pointer 64-Bit Data Bus Branch Verification and Target Address
Prefetch Buffers Instruction Decode
Control ROM
Control Unit
32-Bit Address Bus
Bus Unit
Page Unit
Address Address Generate Generate (U Pipeline) (V Pipeline)
Floating Point Unit
Control Integer Register File ALU ALU (U Pipline) (V Pipline)
64-Bit 64 Data Bus
Control Register File Add Divide 80 Multiply 32 32 32 32 80 32 32
Barrel Shifter
32 32-Bit Addr. Bus
Data Cache 8 Kbytes TLB
A6054-01
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Packaging Information
Differences from the Pentium Processor
To better streamline the processor for embedded applications, the following features have been eliminated from the embedded Pentium processor with voltage reduction technology: Upgrade, Dual Processing (DP), APIC and Master / Checker functional redundancy. Table 1 lists the corresponding pins that exist on the SPGA 3.3-V Pentium processor but have been removed from the embedded Pentium processor with voltage reduction technology.
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 1.
Signals Removed from the Pentium® Processor with Voltage Reduction Technology
BRDYC# CPUTYP D / P#
FRCMC# PBGNT# PBREQ# PHIT# PHITM# PICCLK PICD0 DPEN# PICD1 APICEN
Pinout
The embedded Pentium processor with voltage reduction technology package has a pin array that is mechanically identical to the SPGA version of the 3.3-V Pentium processor, but some pins need to be connected differently. Table 1 lists the SPGA embedded Pentium processor with voltage reduction technology pins that are different from the SPGA 3.3-V Pentium processor. The signals listed in Table 1 are now No Connect pins on the embedded Pentium processor with voltage reduction technology. Leave these pins unconnected. Table 4 includes the list of NC pins. Connection of these pins may result in component failure or incompatibility with processor steppings. Note: The VCC2 pins are 3.1 V for the SPGA embedded Pentium processor with voltage reduction technology. Figure 2 is the pin side SPGA pinout diagram. For a brief functional description of the pins, refer to Table 5. Additional Input and Output pin information is provided in Table 6, Table 7, and Table 8.
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Figure 2. SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Top Side View)
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W V U T S R Q P N M L K J H G F E D C B A NC D9 D11 VCC3 DP0 D10 VCC3 VSS VCC3 VSS VCC3 VSS VCC3 VSS VCC3 VSS VCC3 VSS VCC3 D4 D6 D8 D1 D5 D7 D12 D14 DP1 D19 D23 D26 D28 D30 DP3 D33 D35 D37 D42 D39 D46 D40 D2 NC D3 D53 DP5 D49 D44 NC D0 NC D58 NC VSS A22 VCC3 VSS VCC3 VSS VCC3 VSS NC A24 A21 A23 VSS A28 A25 A26 A27 VSS A30 A3 A29 A31 NC A4 A7 A5 A6 A8 A11 A9 A10 VCC3 VSS A12 A13 VCC3 VSS A14 A15 VCC3 VSS A16 A17 VCC3 VSS A18 A19 VCC3 VSS A20 VCC2 VSS NC VCC2 VSS VCC2 VSS VCC2 VSS VCC2 8 7 6 5 4 3 INC NC INC AP BREQ VSS 2 1 INC AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W V U T S R Q P N M L K J H G F E D INC INC INC 4 3 2 1 C B A
VCC2 FLUSH# INC VSS
W / R# EADS#
SCYC BE6# BE7#
BE4# BE2# BE3#
BE0# BUSCHK# HITM# PWT D / C# HLDA
RESET CLK
BE1# A20M# HIT#
LOCK#
PCD SMIACT# VCC2 PCHK# APCHK# NC PRDY NC NC VSS VCC2 VSS VCC2 VSS VCC2 VSS VCC2 VSS VCC2
INTR R / S# NMI
HOLD WB / WT# NC
VCC3 IGNNE# INIT VSS VCC3 VSS VCC3 NC PEN# NC BF0 BF1 NC
View of Component as Mounted on Board (Pins Down)
BOFF# NA# NC
BRDY#
KEN# EWBE# AHOLD
VSS STPCLK# VSS VCC3
VSS VCC2
INV CACHE# MI / O# BP3 BP2
VCC3 NC NC TRST# TMS TDI TDO NC
VSS VCC2 VSS
PM1BP1
FERR# PM0BP0 VCC2 IERR# DP7 D63 D62 D60 D61 D59 D57 D56 D55 D51 D52 D48 D47 DP6 D54 D50 VSS VCC2 VSS VCC2 VSS VCC2 VSS VCC2
TCK VCC3
D24 VSS
DP2 VSS
D25 VSS
D27 VSS
D29 VSS
D31 VSS
D32 VSS
D34 VSS
D36 VSS
D38 VSS
DP4 VSS
D45 VSS
D13 D15
VCC2 VCC2
A6055-01
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Figure 3. SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Pin Side View)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VCC2 VCC2 VSS VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 A10 A8 A7 A5 A31 A29 A25 A26 A27 A21 A23 NC A24 A22 VCC3 VSS VCC3 VSS VCC3 VSS A6 A4 A3 A28 VSS NC A30 VSS VSS AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W V U T S R Q P N M L K J H G F VCC3 DP0 D10 D11 NC D9 E D C B A
INC FLUSH#
EADS# W / R#
VSS NC
VSS A20
VSS A18 A19
VSS A16 A17
VSS A14 A15
VSS A12 A13
VSS A11 A9
PWT HITM# BUSCHK# BE0# AP D / C#
BE2# BE4# BE3#
BE6# SCYC
HIT# A20M# BE1#
BE5# BE7#
CLK RESET
BREQ HLDA ADS# VSS LOCK#
VCC2 SMIACT# PCD VSS VCC2 VSS VCC2 VSS VCC2 NC PCHK# NC APCHK# NC PRDY
INTR NMI R / S#
HOLD NC WB / WT#
INIT IGNNE# VCC3 PEN# BF0 BF1 NC VSS VCC3 VSS NC VCC3
VSS BOFF# VCC2 NC NA#
VSS BRDY# VCC2 EWBE# KEN# VSS AHOLD VCC2 CACHE# INV VSS VCC2 MI / O# BP3 NC
Pin Side View
STPCLK# VSS VCC3 VSS VCC3 VSS VCC3 VSS NC VCC3 VSS VCC3 VSS NC VCC3 VSS D2 NC D3 DP5 D46 D40 D38 VSS D42 D39 D37 D36 VSS D35 D33 DP3 D30 D27 VSS D28 D26 D23 D19 DP1 D12 D14 D7 D8 D5 D6 D1 D4 VCC3 VSS VCC3
VCC3 NC NC TRST# TMS TDO TDI
VSS PM1BP1 VCC2 PM0BP0 FERR# VSS VCC2 VSS VCC2 VSS VCC2 VSS VCC2 DP6 D54 D50 D47 INC INC 2 3 4 IERR# D63 DP7
D62 D61 D60
TCK VCC3 D0 NC
D59 D57 D58
D56 D55 D53
D51 D52 D49
DP4 VSS VCC2
D34 VSS VCC2
D32 VSS
D31 VSS
D29 VSS
D25 VSS
DP2 VSS
D24 VSS
D21 VSS
D43 D41 5
D13 D15
A6056-01
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 2.
Pin Cross Reference
Pin Cross-Reference by Pin Name - Address and Data Pins
Pin Location Pin Location Pin Location Pin Location Pin Location
Address A3 A4 A5 A6 A7 A8 AL35 AM34 AK32 AN33 AL33 AM32 A9 A10 A11 A12 A13 A14 AK30 AN31 AL31 AL29 AK28 AL27 A15 A16 A17 A18 A19 A20 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C09 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D10 D08 A05 E09 B04 D06 C05 E07 C03 D04 E05 D02 F04 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03 AK26 AL25 AK24 AL23 AK22 AL21 A21 A22 A23 A24 A25 A26 AF34 AH36 AE33 AG35 AJ35 AH34 A27 A28 A29 A30 A31 AG33 AK36 AK34 AM36 AJ33
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 3.
Pin Cross-Reference by Pin Name - Control Pins
Pin Location Pin Location Pin Location Pin Location
A20M# ADS# NC AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY#
AK08 AJ05 AM02 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 S05 X04
NC BREQ BUSCHK# CACHE# NC D / C# NC DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR#
Y03 AJ01 AL07 U03 Q35 AK04 AE35 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05
FLUSH# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK#
AN07 AK06 AL05 AJ03 AB04 P04 AA35 AA33 AD34 U05 W05 AH04 T04 Y05 AC33 AG05 AF04
PEN# PM0 / BP0 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT#
Z34 Q03 R04 AC05 AL03 AC35 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 AM06 AA05
Clock Control CLK AK18 BF0 Y33 BF1 Y35 STPCLK# V34
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 4.
No Connect, Power and Ground Pins
VCC21 A07 A09 A11 A13 A15 A17 G01 J01 L01 N01 Q01 S01 U01 W01 Y01 VCC3 A19 A21 A23 A25 A27 A29 AA37 AC37 AE37 AG37 AN21 AN23 AN25 AN27 AN29 E37 G37 J37 No Connect (NC) A37 AA03 AC03 AD04 AE03 AE35 AL19 AM02 AN35 H34 J33 L35
AA01 AC01 AE01 AN11 AN13
AN19 AN15 AG01 AN09 AN17
L33 L37 N37 Q37 S37 T34
U33 U37 W37 Y37
Q35 R34 S33 S35
W33 W35 Y03
NOTE: 1. These VCC2 pins are 3.3-V VCC pins for the SPGA 3.3-V Pentium® processor. For the SPGA embedded Pentium processor with voltage reduction technology, these pins are 3.1-V VCC2 supplies for the SPGA core. 2. These NC pins should be left unconnected. Connection of these pins may result in component failure or incompatibility with processor steppings.
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to GND (VSS). No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Pin Quick Reference
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 5.
Pin Quick Reference
A20M#
A31-A3
AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
BF1-BF0
BOFF#
BP3-BP2 PM1 / BP1- PM0 / BP0
BRDY#
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 5.
Pin Quick Reference
BUSCHK#
CACHE#
D63-D0
DP7-DP0
EADS#
EWBE#
FERR#
FLUSH#
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 5.
Pin Quick Reference
HITM#
IERR#
IGNNE#
LOCK#
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 5.
Pin Quick Reference
PCHK#
RESET
SMIACT#
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 5.
Pin Quick Reference
STPCLK#
TMS TRST# VCC2 VCC3 VSS
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 6.
Pin Reference Tables
Output Pins
Name ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M / IO#, D / C#, W / R# PCHK# BP3-BP2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO Active Level Low Low Low High Low Low Low Low High Low Low n / a Low High High High High Low n / a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF#
NOTE: All output and input / output pins are floated during three-state test mode (except TDO).
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 7.
Input Pins
Name A20M# AHOLD BF BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT# Active Level Low High High Low Low Low n / a Low Low Low High Low High High High Low Low High Low n / a High Low Low n / a n / a n / a Low n / a Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY# / NA# TCK TCK Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY# Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous Synchronous Synchronous Pullup Pullup Bus State T2, T12, T2P BRDY# Pullup Internal resistor Qualified
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Table 8.
Input / Output Pins
Name A31-A3 AP BE4#-BE0# D63-D0 DP7-DP0 Active Level n / a n / a Low n / a n / a When Floated1 Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# Pulldown2 Internal Resistor
NOTES: 1. All output and input / output pins are floated during three-state test mode (except TDO). 2. BE3#-BE0# have pulldowns during RESET only.
Pin Grouping According to Function
Table 9 organizes the pins with respect to their function.
Table 9.
Pin Functional Grouping
Function Clock Initialization Address Bus Address Mask Data Bus Address Parity Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating-Point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Probe Mode CLK RESET, INIT, BF A31-A3, BE7#-BE0# A20M# D63-D0 AP, APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-BP2 STPCLK# R / S#, PRDY Pins
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Mechanical Specifications
The embedded Pentium processor with voltage reduction technology is offered in an SPGA package without a heat spreader. The package is mechanically equivalent to the package used on the 3.3-V Pentium processor C2 stepping except that the SPGA embedded Pentium processor with voltage reduction technology will use a metal lid instead of a ceramic lid, and has the dimensions shown in Figure 4.
Figure 4. 296-Pin Staggered Pin Grid Array Package (SPGA)
D Seating Plane D1 D3 S1 L
S1 1.65 REF
Pin C3 2.29 1.52 REF. 45° Index Chamfer (Index Corner)
Bottom View (Pin Side Up)
Side View
Table 10. 296-Pin Staggered Pin Grid Array Package Dimensions Key
Millimeters Symbol A A1 A2 B D D1 D3 e1 L N S1 1.52 Min 3.27 0.66 2.62 0.43 49.28 45.59 24.00 2.29 3.05 296 2.54 Max 3.83 0.86 2.97 0.51 49.78 45.85 24.25 2.79 3.30 Total Pins 0.060 Includes Fillet Notes Metal Lid Metal Lid Min 0.129 0.026 0.103 0.017 1.940 1.795 0.945 0.090 0.120 296 0.100 Inches Max 0.151 0.034 0.117 0.020 1.960 1.805 0.955 0.110 1.130 Total Pins Includes Fillet Notes Metal Lid Metal Lid
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Thermal Specifications
The SPGA embedded Pentium processor with voltage reduction technology is specified for proper operation when the case temperature, TCASE (TC), is within the specified range of 0° C to 85° C. The power dissipation specification in Table 11 is provided for designing thermal solutions for operation at a sustained maximum level. This is the worst-case power the device would dissipate in a system for a sustained period of time. This number is provided to assist in the design of a thermal solution for the device.
Table 11. Power Dissipation Requirements for Thermal Solution Design
Parameter Active Power Dissipation Stop Grant and Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation 0.02 Typical1 3.0-4.0 Max2 7.9 1.3 0.05 Unit Watts Watts Watts Note 3 Note 4 Notes
Measuring Thermal Values
To verify that the proper case temperature (TC) is maintained for the embedded Pentium processor with voltage reduction technology, it should be measured at the center of the package top surface (encapsulant). To minimize any measurement errors, the following techniques are recommended:
done using a thermocouple made by Omega (part number: 5TC-TTK-36-36).
· Attach the thermocouple bead or junction to the center of the package top surface using highly
· Attach the thermocouple at a 90° angle as shown in Figure 5.
Figure 5. Technique for Measuring Case Temperature (TC)
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Thermal Equations
Table 12 lists the CA values for the Pentium processor with passive heatsinks. Thermal data collection parameters:
Heatsinks are omnidirectional pin aluminum alloy Features were based on standard extrusion practices for a given height Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Base thickness ranged from 79 to 200 mils Heatsink attach was 0.005" of thermal grease Using an attach thickness of 0.002" improves performance by approximately 0.3 °C / W
Table 12. Thermal Resistances for Embedded Pentium® Processors with Voltage Reduction Technology
Heatsink Height in Inches 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Without Heatsink JC (°C / Watt) 0 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.7 9.4 9.1 8.7 8.4 8.0 7.3 6.6 6.2 5.7 14.5 CA(°C / Watt) vs. Laminar Airflow (Linear ft / min) 100 8.3 7.8 7.3 6.8 6.3 5.6 4.9 4.6 4.2 13.8 200 6.9 6.3 5.6 5.0 4.6 4.2 3.9 3.6 3.3 12.6 400 4.7 4.3 3.9 3.5 3.3 2.9 2.9 2.7 2.5 10.5 600 3.9 3.6 3.2 2.9 2.7 2.5 2.4 2.3 2.2 8.6 800 3.3 3.1 2.8 2.6 2.4 2.3 2.1 2.1 2.0 7.5
Datasheet
Embedded Pentium® Processor with Voltage Reduction Technology
Electrical Specifications
Absolute Maximum Ratings
The following values are stress ratings only. Functional operation at the maximum ratings is not implied nor guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended operation beyond the maximum ratings may affect device reliability. Furthermore, although the embedded Pentium processor with voltage reduction technology contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields.
Table 13. Absolute Maximum Ratings
Parameter Case temperature under bias Storage temperature 3 V Supply voltage with respect to VSS 3.1 V Supply voltage with respect to VSS 3 V Only Buffer DC Input Voltage 5 V Safe Buffer DC Input Voltage Maximum Rating -65° C to 110° C -65° C to 150° C -0.5 V to +4.6 V -0.5 V to +4.1 V -0.5 V to VCC3 +0.5 not to exceed 4.6 V1 -0.5 V to 6.5 V2, 3
NOTES: 1. Applies to all SPGA embedded Pentium® processor with voltage reduction technology inputs except CLK. 2. Applies to CLK. 3. See Table 15.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
DC Specifications
Tables 14, 15 and 16 list the DC specifications that apply to the embedded Pentium processor with voltage reduction technology. The embedded Pentium processor with voltage reduction technology core operates at 3.1 V internally while the I / O interface operates at 3.3 V. The CLK input may be at 3.3 V or 5 V. Since the 3.3-V (5-V safe) input levels defined in Table 15 are the same as the 5-V TTL levels, the CLK input is compatible with existing 5V clock drivers.
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Embedded Pentium® Processor with Voltage Reduction Technology
Table 14. DC Specifications
Table 15. 3.3-V (5-V Safe) DC Specifications
Symbol VIL5 VIH5 Parameter Input Low Voltage Input High Voltage Min -0.3 2.0 Max 0.8 5.55 Unit V V Notes TTL Level applies to CLK only TTL Level applies to CLK only
Table 16. Input and Output Characteristics
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Embedded Pentium® Processor with Voltage Reduction Technology
Power Sequencing
There is no specific sequence required for powering up or powering down the VCC2 and VCC3 power supplies. However, it is recommended that the VCC2 and VCC3 power supplies be either both on or both off within one second of each other.
AC Specifications
Power and Ground
For clean on-chip power distribution, the embedded Pentium processor with voltage reduction technology has 25 VCC2 (3.1-V power), 28 VCC3 (3.3-V power) and 53 VSS (ground) inputs. Power and ground connections must be made to all external VCC2, VCC3 and VSS pins of the processor. On the circuit board, all VCC2 pins must be connected to a 3.1-V VCC2 plane (or island) and all VCC3 pins must be connected to a 3.3-V VCC3 plane. All VSS pins must be connected to a VSS plane. Refer to Table 4 for a list of VCC2 and VCC3 pins.
Decoupling Recommendations
Transient power surges occur as the processor is executing instruction sequences or driving large loads. To mitigate these high frequency transients, liberal high frequency decoupling capacitors should be placed near the processor. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by minimizing the length of circuit board traces between the processor and the decoupling capacitors. These capacitors should be evenly distributed around each component on the 3.3-V plane and the 3.1-V plane (or island). Capacitor values should be chosen to ensure that they eliminate both low and high frequency noise components. Power transients also occur as the processor rapidly transitions from a low power consumption level to a much higher level (or high to low). A typical example would be entering or exiting the Stop Grant state. Other examples include executing a HALT instruction (which causes the processor to enter the Auto HALT Powerdown state) or transitioning from HALT to the Normal state. All of these examples may cause abrupt changes in the power being consumed by the processor. Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Several bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 µF range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point at which the regulated power supply output can react to the change in load. In order to reduce the net ESR, it may be necessary to place several bulk storage capacitors in parallel.
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Embedded Pentium® Processor with Voltage Reduction Technology
These capacitors should be placed near the processor (on the 3.3-V plane and the 3.1-V plane or island) to ensure that these supply voltages stay within specified limits during changes in the power demands of the processor during operation. For more detailed information, please contact Intel or refer to the Pentium® Processor with Voltage Reduction Technology: Power Supply Design Considerations for Mobile Systems application note (order number 242558). Note: Capacitors degrade over time during use. As capacitors age, their capacity to store and hold a charge becomes compromised. Designing a board with below minimum acceptable bypass and bulk capacitors may have future system reliability consequences.
Connection Specifications
All NC pins must remain unconnected. Refer to Table 4 for a list of NC pins. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to ground.
AC Timings
The AC specifications given in Table 17 consist of output delays, input setup requirements and input hold requirements for the 66-MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5 V for both 0 and 1 logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct operation.
Table 17. AC Specifications (Sheet 1 of 4)
NOTE: See Table 18 for table notes.
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Embedded Pentium® Processor with Voltage Reduction Technology
Table 17. AC Specifications (Sheet 2 of 4)
t8a t8b t9a t9b t9c t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17 t18a t18b t19 t20 t21 t22 t23 t24a t24b t25a t25b t26 t27 t28
NOTE: See Table 18 for table notes.
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Embedded Pentium® Processor with Voltage Reduction Technology
Table 17. AC Specifications (Sheet 3 of 4)
t42c t43a t43b t43c t43d t44 t45 t46 t47 t48 t49
mS CLKs CLKs CLKs MHz ns ns ns ns ns
6 6 6 6 6 @2 V, Note 1 @0.8 V, Note 1 2.0 V-0.8 V, Notes 1, 8, 9 0.8 V-2.0 V, Notes 1, 8, 9
NOTE: See Table 18 for table notes.
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Embedded Pentium® Processor with Voltage Reduction Technology
Table 17. AC Specifications (Sheet 4 of 4)
NOTE: See Table 18 for table notes.
Table 18. Notes for Table 17
NOTES: Notes 2, 6 and 14 are general and apply to all standard TTL signals used with the Pentium® processor family. 1. Not 100 percent tested. Guaranteed by design. 2. TTL input test waveforms are assumed to be 0 to 3-V transitions with 1 V / ns rise and fall times. 3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to boundary scan operations. 4. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition without false transitions. 5. 0.8 V / ns CLK input rise / fall time 8 V / ns. 6. 0.3 V / ns input rise / fall time 5 V / ns. 7. Referenced to TCK rising edge. 8. Referenced to TCK falling edge. 9. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz. 10. During probe mode operation, do not use the boundary scan timings (t55-58). 11. Setup time is required to guarantee recognition on a specific clock. 12. Hold time is required to guarantee recognition on a specific clock. 13. All TTL timings are referenced from 1.5 V. 14. To guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a minimum of two clocks before being returned active and must meet the minimum pulse width. 15. This input may be driven asynchronously. 16. When driven asynchronously, RESET, NMI, FLUSH#, R / S#, INIT, and SMI# must be deasserted (inactive) for a minimum of two clocks before being returned active. 17. The D / C#, M / IO#, W / R#, CACHE#, and A31-A5 signals are sampled only on the CLK in which ADS# is active. 18. BF should be strapped to VCC3 or left floating. 19. These signals are measured on the rising edge of adjacent CLKs at 1.5 V. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 KHz and 1 / 3 of the CLK operating frequency. The amount of jitter present must be accounted for as a component of CLK skew between devices. 20. Timing (t14) is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active). 21. BUSCHK# is used as a reset configuration signal to select buffer size. 22. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays.
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Embedded Pentium® Processor with Voltage Reduction Technology
Figure 6. Clock Waveform
Figure 7. Valid Delay Timings
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Embedded Pentium® Processor with Voltage Reduction Technology
Figure 8. Float Delay Timings
Figure 9. Setup and Hold Timings
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Embedded Pentium® Processor with Voltage Reduction Technology
Figure 10. Reset and Configuration Timings
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Embedded Pentium® Processor with Voltage Reduction Technology
Figure 11. Test Timings
TDI TMS
TDO Ty Output Signals
Input Signals
Figure 12. Test Reset Timings
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Embedded Pentium® Processor with Voltage Reduction Technology
I / O Buffer Models
This section describes the I / O buffer models of the embedded Pentium processor with voltage reduction technology. The first-order I / O buffer model is a simplified representation of the complex input and output buffers used in the embedded Pentium processor with voltage reduction technology. Figure 13 and Figure 14 show the structure of the input buffer model and Figure 15 shows the output buffer model. Table 19 and Table 20 show the parameters used to specify these models. Although simplified, these buffer models accurately model flight time and signal quality. For these parameters, there is very little added accuracy in the complete transistor model. The following two models represent the input buffer models. The first model, Figure 13, represents all of the input buffers except for a special group of input buffers. The second model, Figure 14, represents these special buffers: AHOLD, EADS#, KEN#, WB / WT#, INV, NA#, EWBE#, BOFF# and CLK. In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not required for simulation, it may be more difficult to meet specifications without them. Some signal quality specifications require that the diodes be removed from the input model. The series resistors (Rs) are a part of the diode model. Remove these when removing the diodes from the input model.
Figure 13. Input Buffer Model, Except Special Group
Note: VCC refers to the I / O buffer VCC3.
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Embedded Pentium® Processor with Voltage Reduction Technology
Figure 14. Input Buffer Model for Special Group
Table 19. Parameters Used in the Specification of the First Order Input Buffer Model
Parameter Cin Lp Cp Rs D1, D2 Description Minimum and Maximum value of the capacitance of the input buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance Diode Series Resistance Ideal Diodes
Figure 15 shows the structure of the output buffer model. This model is used for all of the output buffers of the embedded Pentium processor with voltage reduction technology.
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Embedded Pentium® Processor with Voltage Reduction Technology
Figure 15. First-Order Output Buffer Model
Table 20. Parameters Used in the Specification of the First-Order Output Buffer Model
Parameter dV / dt Ro Co Lp Cp Description Minimum and maximum value of the rate of change of the open circuit voltage source used in the output buffer model Minimum and maximum value of the output impedance of the output buffer model Minimum and Maximum value of the capacitance of the output buffer model Minimum and Maximum value of the package inductance Minimum and Maximum value of the package capacitance
Buffer Model Parameters
This section gives the parameters for each embedded Pentium processor with voltage reduction technology input, output and bidirectional signal, as well as the settings for the configurable buffers. Some pins on the embedded Pentium processor with voltage reduction technology have selectable buffer sizes. These pins use the configurable output buffer EB2. Table 21 shows the drive level for BRDY# required at the falling edge of RESET to select the buffer strength. The buffer sizes selected should be the appropriate size required otherwise AC timings might not be met, or too much overshoot and ringback may occur. There are no other selection choices all of the configurable buffers get set to the same size during setup initialization. The input, output and bidirectional buffer values of the embedded Pentium processor with voltage reduction technology are listed in Table 23. This table contains listings for all three types do not confuse them during simulation. When a bidirectional pin is operating as an input, use the Cin, Cp and Lp values when it is operating as a driver, use all of the data parameters. Refer to Table 22 for the groupings of the buffers.
Table 21. Buffer Selection Chart
Environment Typical Stand Alone Component Loaded Component BRDY# 1 0 Buffer Selection EB2 EB2A
NOTE: For correct buffer selection, the BUSCHK# signal must be held inactive (high) at the falling edge of RESET.
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Embedded Pentium® Processor with Voltage Reduction Technology
Table 22. Signal to Buffer Type
Signals CLK A20M#, AHOLD, BF, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, R / S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB / WT# APCHK#, BE7#-BE5#, BP3-BP2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0 / BP0, PM1 / BP1, PRDY, PWT, SMIACT#, TDO, U / O# A31-A21, AP, BE4#-BE0#, CACHE#, D / C#, D63-D0, DP8-DP0, HLDA, LOCK#, M / IO#, SCYC A20-A3, ADS#, HITM#, W / R# HIT# Type I Driver Buffer Type Receiver Buffer Type ER0
ED1 EB1 EB2 / EB2A EB3 EB1 EB2 / EB2A EB3
Table 23. Input, Output and Bidirectional Buffer Model Parameters
Buffer Type Transition min ER0 (input) ER1 (input) ED1 (output) EB1 (bidir) EB2 (bidir) EB2A (bidir) EB3 (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 3.0 3 / 2.8 3 / 2.4 3 / 2.4 3 / 3.0 3 / 2.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.8 3.7 / 0.9 3.7 / 0.9 3.7 / 0.9 3.7 / 0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 9.0 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7 dV / dt (V / ns) max Ro (Ohms) min max Cp (pF) min 3.0 3.0 1.1 1.1 1.1 1.1 1.3 1.3 1.3 1.3 1.3 1.3 1.9 1.9 max 5.0 5.0 6.1 6.1 8.2 8.2 8.7 8.7 8.3 8.3 8.3 8.3 7.5 7.5 Lp (nH) min 4.0 4.0 4.7 4.7 4.0 4.0 4.0 4.0 4.4 4.4 4.4 4.4 9.9 9.9 max 7.2 7.2 15.3 15.3 17.7 17.7 18.7 18.7 16.7 16.7 16.7 16.7 14.3 14.3 min 0.8 0.8 0.8 0.8 2.0 2.0 2.0 2.0 9.1 9.1 9.1 9.1 3.3 3.3 Co / Cin (pF) max 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 9.7 9.7 9.7 9.7 3.9 3.9
Table 24. Input Buffer Model Parameters: D (Diodes)
Symbol IS N RS TT VJ CJ0 M Parameter Saturation Current Emission Coefficient Series Resistance Transit Time PN Potential Zero Bias PN Capacitance PN Grading Coefficient D1 1.4e-14 A 1.19 6.5 ohms 3 ns 0.983 V 0.281 pF 0.385 D2 2.78e-16 A 1.00 6.5 ohms 6 ns 0.967 V 0.365 pF 0.376
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Embedded Pentium® Processor with Voltage Reduction Technology
Signal Quality Specifications
Signals driven by the system into the embedded Pentium processor with voltage reduction technology must meet signal quality specifications to guarantee that the components read data properly and to ensure that incoming signals do not affect the reliability of the component. There are two signal quality parameters: ringback and settling time.
Ringback
· The maximum overshoot / undershoot on the 3.3-V embedded Pentium processor with voltage
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Embedded Pentium® Processor with Voltage Reduction Technology
Settling Time
The settling time is defined as the time required at the receiver for the signal to settle to within 10 percent of VCC3 or VSS. Settling time is also the maximum time allowed for a signal to reach within 10 percent of its final value. Most available simulation tools are unable to simulate settling time so that it accurately reflects silicon measurements. On a physical board, second-order effects and other effects can dampen the signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for layout tuning and not a specification. Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times of the signals if the waveform has not settled. Settling time may be simulated with the diodes included or excluded from the input buffer model. If diodes are included, the settling time recommendation will be easier to meet. Although simulated settling time has not shown good correlation with physical, measured settling time, settling time simulations can still be used as a tool to tune layouts. Use the following procedure to verify board simulation and tuning with concerns for settling time. 1. Simulate settling time at the slow corner for a particular signal. 2. If settling time violations occur, simulate signal trace with DC diodes in place at the receiver pin. The DC diode behaves almost identically to the actual (non-linear) diode on the part as long as excessive overshoot does not occur. 3. If settling time violations still occur, simulate flight times for five consecutive cycles for that particular signal. 4. If flight time values are consistent over the five simulations, settling time should not be a concern. If however, flight times are not consistent over the five simulations, tuning of the layout is required. 5. Note that, for signals that are allocated two cycles for flight time, the recommended settling time is doubled. A typical design method would include a settling time that ensures that a signal is within 10 percent of VCC3 or VSS for at least 2.5 ns prior to the end of the CLK period.
Figure 17. Settling Time
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