Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Compatible with Large Software Base MS-DOS, Windows, OS/2, UNIX 32

Datasheet Thumbnail

Top Searches for this datasheet

Embedded Pentium® Processor with Voltage Reduction Technology
Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit Processor with 64-Bit Data Superscalar Architecture Pipelined Integer Units Capable Instructions/Clock Pipelined Floating-Point Unit Separate Code Data Caches 8-Kbyte Code, 8-Kbyte Write-Back Data MESI Cache Protocol Advanced Design Features Branch Prediction Virtual Mode Extension
Low-Voltage BiCMOS Silicon Technology 4-Mbyte Pages Increased Rate IEEE 1149.1 Boundary Scan Internal Error Detection Features Enhanced Power Management Features System Management Mode Clock Control Voltage Reduction Technology Core Supply Buffer Supply Fractional Operation 133-MHz Core/66-MHz (iCOMP® Index Rating 111)
Contact Intel Corporation more information about iCOMP® Index ratings.
embedded Pentium® processor fully compatible with entire installed base applications DOS*, Windows*, OS/2*, UNIX*, other software that runs earlier Intel 8086 family product. embedded Pentium processor's superscalar architecture execute instructions clock cycle. Branch prediction separate caches also increase performance. Separate code data caches reduce cache conflicts while remaining software transparent. embedded Pentium processor with voltage reduction technology million transistors. built Intel's advanced low-voltage BiCMOS silicon technology, full Enhanced power management features, including System Management Mode (SMM) clock control. additional Enhanced features, core operation buffer operation, make embedded Pentium processor with voltage reduction technology ideal embedded designs.
Order Number: 273203-001 November 1998
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor with voltage reduction technology contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1998 *Third-party brands names property their respective owners.
Embedded Pentium® Processor with Voltage Reduction Technology
Content1.0 Introduction Architecture Overview
Pentium® Processor Family Architecture Differences from Pentium Processor.10 Pinout 3.2.1 Cross Reference 3.2.2 Design Notes.16 3.2.3 Quick Reference 3.2.4 Reference Tables.22 3.2.5 Grouping According Function.24 Mechanical Specifications Thermal Specifications 3.4.1 Measuring Thermal Values 3.4.2 Thermal Equations Absolute Maximum Ratings.28 Specifications 4.2.1 Power Sequencing Specifications 4.3.1 Power Ground 4.3.2 Decoupling Recommendations 4.3.3 Connection Specifications 4.3.4 Timings.31 Buffer Models 4.4.1 Buffer Model Parameters 4.4.2 Signal Quality Specifications 4.4.2.1 Ringback 4.4.2.2 Settling Time
Packaging Information
Electrical Specifications
Figure1 Pentium® Processor with Voltage Reduction Technology Block Diagram SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Top Side View).12 SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Pin Side View).13 296-Pin Staggered Grid Array Package (SPGA) Technique Measuring Case Temperature (TC) Clock Waveform Valid Delay Timings.35 Float Delay Timings.36 Setup Hold Timings
Embedded Pentium® Processor with Voltage Reduction Technology
Reset Configuration Timings. Test Timings. Test Reset Timings Input Buffer Model, Except Special Group Input Buffer Model Special Group. First-Order Output Buffer Model. Overshoot/Undershoot Ringback Guidelines Settling Time
Table1 Signals Removed from Pentium® Processor with Voltage Reduction Technology Cross-Reference Name Address Data Pins Cross-Reference Name Control Pins Connect, Power Ground Pins Quick Reference Output Pins Input Pins Input/Output Pins Functional Grouping. 296-Pin Staggered Grid Array Package Dimensions Key. Power Dissipation Requirements Thermal Solution Design Thermal Resistances Embedded Pentium® Processors with Voltage Reduction Technology. Absolute Maximum Ratings Specifications. 3.3-V (5-V Safe) Specifications. Input Output Characteristics. Specifications Notes Table Parameters Used Specification First Order Input Buffer Model Parameters Used Specification First-Order Output Buffer Model Buffer Selection Chart Signal Buffer Type. Input, Output Bidirectional Buffer Model Parameters. Input Buffer Model Parameters: (Diodes)
Embedded Pentium® Processor with Voltage Reduction Technology
Revision History
Date 11/12/98 Revision Description This first publication this document
Embedded Pentium® Processor with Voltage Reduction Technology
Introduction
Intel® embedded Pentium® processor with voltage reduction technology reduced power version embedded Pentium processor. Voltage reduction technology allows processor interface with industry standard 3.3-volt components while inner core, operating volts, consumes less power. embedded Pentium processor with voltage reduction technology available Staggered Grid Array (SPGA) package. advanced features original Pentium processor except differences listed "Differences from Pentium Processor" page embedded Pentium processor with voltage reduction technology several features that ideal embedded applications, including:
3.1-V core 3.3-V buffer inputs reduce power consumption significantly, while
maintaining 3.3-V compatibility externally. family. architecture internal features embedded Pentium processor with voltage reduction technology identical embedded Pentium processor specifications provided Embedded Pentium® Processor Family Developer's Manual (order number 273204), except that several features have been eliminated streamline embedded applications. This document should used conjunction with following related embedded Pentium processor documents.
Enhanced feature set, which initially implemented Intel486processor
Embedded Pentium® Processor Family Developer's Manual (order number: 273204) Intel Architecture Software Developer's Manual, Volumes (order numbers 243190,
243191, 243192)
Architecture Overview
embedded Pentium processor with voltage reduction technology extends Intel Pentium family microprocessors. embedded Pentium processor family consists embedded Pentium processor, embedded Pentium processor with voltage reduction technology described this document, embedded Pentium processor with MMXtechnology, low-power embedded Pentium processor with technology. "Pentium processor" used this document refer entire Pentium processor family general. embedded Pentium processor family architecture contains features Intel486 processor family, provides significant enhancements including following:
Superscalar architecture Dynamic branch prediction Pipelined floating-point unit Improved instruction execution time Separate 8-Kbyte code 8-Kbyte data caches Writeback MESI protocol data cache 64-Bit data cycle pipelining
Embedded Pentium® Processor with Voltage Reduction Technology
Address parity Internal parity checking Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Voltage reduction technology Power management feature
Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 processor family instruction with extensions accommodate some additional functionality Pentium processor. application software written Intel386 Intel486 family microprocessors runs Pentium processors without modification. on-chip memory management unit completely compatible with Intel386 family Intel486 family processors. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, processor prefetch buffers, prefetch code linear fashion, that prefetches code according needed code almost always prefetched before needed execution. floating-point unit (FPU) times faster than used Intel486 processor common operations including add, multiply, load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache Kbytes with 32-byte line size, two-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable write back write through line-by-line basis follows MESI protocol. data cache tags triple-ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags also triple-ported support snooping split-line accesses. Individual pages configured cacheable non-cacheable software hardware. cache enabled disabled software hardware. Pentium processors have 64-bit data fast data transfer. Burst read burst writeback cycles supported. addition, cycle pipelining been added allow cycles occur simultaneously. Memory Management Unit contains optional extensions architecture which allow 2-Mbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception.
Embedded Pentium® Processor with Voltage Reduction Technology
addition, Pentium processors have implemented functional redundancy checking provide maximum error detection processor interface processor. When functional redundancy checking used, second processor, "checker" executes lock-step with "master" processor. checker samples master's outputs, compares those values with values computes internally, asserts error signal mismatch occurs. more more functions integrated on-chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors provide four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor. Figure block diagram embedded Pentium processor with voltage reduction technology. Figure Pentium® Processor with Voltage Reduction Technology Block Diagram
Branch Prefetch Target Buffer Addres
Code Cache Kbyte256
Instruction Pointer 64-Bit Data Branch Verification Target Addres
Prefetch Buffers Instruction Decode
Control
Control Unit
32-Bit Address
Unit
Page Unit
Address Address Generate Generate Pipeline) Pipeline)
Floating Point Unit
Control Integer Register File Pipline) Pipline)
64-Bit Data
Control Register File Divide Multiply
Barrel Shifter
32-Bit Addr.
Data Cache Kbytes
A6054-01
Embedded Pentium® Processor with Voltage Reduction Technology
block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions. separate code data caches shown. data cache ports, each pipes (the tags triple-ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions processor execute instruction. control contains microcode control sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processors contain pipelined floating-point unit that provides significant floating-point performance advantage over previous generations processors. Pentium processor supports clock control. When clock processor stopped, power dissipation virtually eliminated. This makes Pentium processor good choice energyefficient designs. Pentium processor supports fractional operation. This allows processor core operate high frequencies, while communicating with external lower frequencies. Pentium processor contains on-chip Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across processors), multiple subsystem support, 8259A compatibility, inter-processor interrupt support. processor's architectural features more fully described Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Packaging Information
Differences from Pentium Processor
better streamline processor embedded applications, following features have been eliminated from embedded Pentium processor with voltage reduction technology: Upgrade, Dual Processing (DP), APIC Master/Checker functional redundancy. Table lists corresponding pins that exist SPGA 3.3-V Pentium processor have been removed from embedded Pentium processor with voltage reduction technology.
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Signals Removed from Pentium® Processor with Voltage Reduction Technology
Signal ADSC# Function Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy, requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems. APIC Clock. This signal APIC interrupt controller serial data clock. APIC's Programmable Interrupt Controller Data line PICD0 shares with DPEN# (Dual Processing Enable). APIC's Programmable Interrupt Controller Data line PICD1 shares with APICEN (APIC Enable RESET)).
BRDYC# CPUTYP D/P#
FRCMC# PBGNT# PBREQ# PHIT# PHITM# PICCLK PICD0 [DPEN#] PICD1 [APICEN]
Pinout
embedded Pentium processor with voltage reduction technology package array that mechanically identical SPGA version 3.3-V Pentium processor, some pins need connected differently. Table lists SPGA embedded Pentium processor with voltage reduction technology pins that different from SPGA 3.3-V Pentium processor. signals listed Table Connect pins embedded Pentium processor with voltage reduction technology. Leave these pins unconnected. Table includes list pins. Connection these pins result component failure incompatibility with processor steppings. Note: VCC2 pins SPGA embedded Pentium processor with voltage reduction technology. Figure side SPGA pinout diagram. brief functional description pins, refer Table Additional Input Output information provided Table Table Table
Embedded Pentium® Processor with Voltage Reduction Technology
Figure SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Top Side View)
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2 BREQ
VCC2 FLUSH#
W/R# EADS#
SCYC BE6# BE7#
BE4# BE2# BE3#
BE0# BUSCHK# HITM# D/C# HLDA
RESET
BE5#
BE1# A20M# HIT#
ADS#
LOCK#
SMIACT# VCC2 PCHK# APCHK# PRDY VCC2 VCC2 VCC2 VCC2 VCC2
INTR R/S#
SMI#
HOLD WB/WT#
VCC3 IGNNE# INIT VCC3 VCC3 PEN#
View Component Mounted Board (Pins Down)
BOFF#
BRDY#
KEN# EWBE# AHOLD
STPCLK# VCC3
VCC2
CACHE# MI/O#
VCC3 TRST#
VCC2
PM1BP1
FERR# PM0BP0 VCC2 IERR# VCC2 VCC2 VCC2 VCC2
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC2
VCC2
VCC2 VCC2
VCC2
VCC2
A6055-01
Embedded Pentium® Processor with Voltage Reduction Technology
Figure SPGA Pentium® Processor with Voltage Reduction Technology Pinout (Pin Side View)
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
FLUSH#
EADS# W/R#
HITM# BUSCHK# BE0# D/C#
BE2# BE4# BE3#
BE6# SCYC
HIT# A20M# BE1#
BE5# BE7#
RESET
BREQ HLDA ADS# LOCK#
VCC2 SMIACT# VCC2 VCC2 VCC2 PCHK# APCHK# PRDY
INTR R/S#
HOLD WB/WT#
SMI#
INIT IGNNE# VCC3 PEN# VCC3 VCC3
BOFF# VCC2
BRDY# VCC2 EWBE# KEN# AHOLD VCC2 CACHE# VCC2 MI/O#
Side View
STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
VCC3 TRST#
PM1BP1 VCC2 PM0BP0 FERR# VCC2 VCC2 VCC2 VCC2 IERR#
VCC3
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
A6056-01
Embedded Pentium® Processor with Voltage Reduction Technology
3.2.1
Table
Cross Reference
Cross-Reference Name Address Data PinPin Location Location Location Location Location
Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 Data AK26 AL25 AK24 AL23 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Cross-Reference Name Control PinPin Location Location Location Location
A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY#
AK08 AJ05 AM02 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16
BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR#
AJ01 AL07 AK04 AE35 AM04
FLUSH# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK#
AN07 AK06 AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04
PEN# PM0/BP0 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT#
AC05 AL03 AC35 AK20 AL17 AB34 AG03 AM06 AA05
Clock Control AK18 STPCLK#
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Connect, Power Ground PinVCC21 VCC3 AA37 AC37 AE37 AG37 AN21 AN23 AN25 AN27 AN29 Connect (NC) AA03 AC03 AD04 AE03 AE35 AL19 AM02 AN35
AA01 AC01 AE01 AN11 AN13
AN19 AN15 AG01 AN09 AN17
NOTE: These VCC2 pins 3.3-V pins SPGA 3.3-V Pentium® processor. SPGA embedded Pentium processor with voltage reduction technology, these pins 3.1-V VCC2 supplies SPGA core. These pins should left unconnected. Connection these pins result component failure incompatibility with processor steppings.
3.2.2
Design NoteFor reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected (VSS). Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
3.2.3
Quick Reference
This section gives brief functional description each pin. detailed description, "Hardware Interface" chapter Embedded Pentium® Processor Family Developer's Manual (order number 273204). Note that input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level.
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Quick Reference
Symbol Type Function When address mask asserted, Pentium® processor emulates address wraparound Mbyte that occurs 8086. When A20M# asserted, processor masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven processor. response assertion address hold, processor will stop driving address lines (A31-A3), next clock. rest will remain active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock which address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. byte enable pins used determine which bytes must written external memory, which bytes were requested processor current cycle. byte enables driven same clock address lines (A31-A3). Frequency determines bus-to-core ratio. frequency pins sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, must change values while RESET active. proper operation embedded Pentium processor with voltage reduction technology, should strapped high, should strapped low. This sets bus-to-core ratio 1/2. Other combinations reserved. backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. breakpoint pins (BP3-BP0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus.
A20M#
A31-A3
ADS#
AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
BF1-BF0
BOFF#
BP3-BP2 PM1/BP1- PM0/BP0
BRDY#
BREQ
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Quick Reference
Symbol Type Function check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor does cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor's external requires levels. external timing parameters except TDI, TDO, TMS, TRST# specified with respect rising edge CLK. recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device. D/C# data/code output primary cycle definition pins. driven valid same clock which ADS# signal asserted. D/C# distinguishes between data code special cycles. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When processor driving data lines, they driven during clocks that cycle. During reads, processor samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back embedded Pentium processor with voltage reduction technology these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56; applies D7-D0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write EWBE# sampled inactive, processor will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating-point error reporting. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle generated processor indicating completion writeback invalidation. FLUSH# sampled when RESET transitions from high low, three-state test mode entered. indication driven reflect outcome inquire cycle. inquire cycle hits valid line either data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles.
BUSCHK#
CACHE#
D63-D0
DP7-DP0
EADS#
EWBE#
FERR#
FLUSH#
HIT#
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Quick Reference
Symbol Type Function modified line output driven reflect outcome inquire cycle. asserted after inquire cycle that results modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA driven inactive processor resumes driving bus. processor cycle pending, will driven same clock which HLDA deasserted. response hold request, processor will float most output input/output pins assert HLDA after completing outstanding cycles. processor will maintain this state until HOLD deasserted. HOLD recognized during LOCK cycles. processor will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, processor will assert IERR# clock then shutdown. ignore numeric error input effect when When CR0.NE IGNNE# asserted, processor ignores pending unmasked numeric exception continues executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will stop execution wait external interrupt. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, processor will perform built-in self test prior start program execution. active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, processor will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated ensure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock which EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. lock indicates that current cycle locked. processor does allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed deasserted least clock between back-to-back locked cycles.
HITM#
HLDA
HOLD
IERR#
IGNNE#
INIT
INTR
KEN#
LOCK#
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Quick Reference
Symbol M/IO# Type Function memory/input-output primary cycle definition pins. driven valid same clock which ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor will issue ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. page cache disable reflects state CR3, Page Directory Entry Page Table Entry. purpose provide external cacheability indication page-by-page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock, data parity error detected. processor will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", processor will vector machine check exception before beginning next instruction. These pins function part performance monitoring feature. PM1/BP1- PM0/BP0 breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine whether pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output indicates that processor stopped normal execution response R/S# going active Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis. run/stop input asynchronous, edge-sensitive interrupt used stop normal execution processor place into idle state. high transition R/S# will interrupt processor cause stop execution next instruction boundary. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine three-state test mode will entered BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles that locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode.
PCHK#
PEN#
PRDY
R/S#
RESET
SCYC
SMI#
SMIACT#
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Quick Reference
Symbol Type Function Assertion stop clock input signifies request stop internal clock embedded Pentium processor with voltage reduction technology thereby causing core consume less power. When processor recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, processor will still respond external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. These pins power inputs embedded Pentium processor with voltage reduction technology. These pins power inputs embedded Pentium processor with voltage reduction technology. These pins ground inputs embedded Pentium processor with voltage reduction technology. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
STPCLK#
TRST# VCC2 VCC3
W/R#
WB/WT#
Embedded Pentium® Processor with Voltage Reduction Technology
3.2.4
Table
Reference TableOutput PinName ADS# APCHK# BE7#-BE5# BREQ CACHE# FERR# HIT# HITM# HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# Active Level High High High High High High states except Shift-DR Shift-IR Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated Hold, BOFF#
NOTE: output input/output pins floated during three-state test mode (except TDO).
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Input PinName A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level High High High High High High High High Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Synchronous Pullup Pullup State T12, BRDY# Pullup Internal resistor Qualified
Embedded Pentium® Processor with Voltage Reduction Technology
Table
Input/Output PinName A31-A3 BE4#-BE0# D63-D0 DP7-DP0 Active Level When Floated1 Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# Pulldown2 Internal Resistor
NOTES: output input/output pins floated during three-state test mode (except TDO). BE3#-BE0# have pulldowns during RESET only.
3.2.5
Grouping According Function
Table organizes pins with respect their function.
Table
Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating-Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Probe Mode RESET, INIT, A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# R/S#, PRDY
Embedded Pentium® Processor with Voltage Reduction Technology
Mechanical SpecificationThe embedded Pentium processor with voltage reduction technology offered SPGA package without heat spreader. package mechanically equivalent package used 3.3-V Pentium processor stepping except that SPGA embedded Pentium processor with voltage reduction technology will metal instead ceramic lid, dimensions shown Figure
Figure 296-Pin Staggered Grid Array Package (SPGA)
Seating Plane
1.65
2.29 1.52 REF. Index Chamfer (Index Corner)
Bottom View (Pin Side
Side View
Table 296-Pin Staggered Grid Array Package Dimensions
Millimeters Symbol 1.52 3.27 0.66 2.62 0.43 49.28 45.59 24.00 2.29 3.05 2.54 3.83 0.86 2.97 0.51 49.78 45.85 24.25 2.79 3.30 Total Pins 0.060 Includes Fillet Notes Metal Metal 0.129 0.026 0.103 0.017 1.940 1.795 0.945 0.090 0.120 0.100 Inches 0.151 0.034 0.117 0.020 1.960 1.805 0.955 0.110 1.130 Total Pins Includes Fillet Notes Metal Metal
Embedded Pentium® Processor with Voltage Reduction Technology
Thermal SpecificationThe SPGA embedded Pentium processor with voltage reduction technology specified proper operation when case temperature, TCASE (TC), within specified range power dissipation specification Table provided designing thermal solutions operation sustained maximum level. This worst-case power device would dissipate system sustained period time. This number provided assist design thermal solution device.
Table Power Dissipation Requirements Thermal Solution Design
Parameter Active Power Dissipation Stop Grant Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation 0.02 Typical1 3.0-4.0 Max2 0.05 Unit Watts Watts Watts Note Note Note
NOTES: This typical power dissipation system. This value average value measured system using typical device VCC2 VCC3 running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum Active Power Dissipation. determined using worst-case instruction with VCC2 VCC3 nominal this measurement takes into account thermal time constant package. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input.
3.4.1
Measuring Thermal ValueTo verify that proper case temperature (TC) maintained embedded Pentium processor with voltage reduction technology, should measured center package surface (encapsulant). minimize measurement errors, following techniques recommended:
gauge finer diameter type thermocouples. Intel's laboratory testing wadone using thermocouple made Omega (part number: 5TC-TTK-36-36).
Attach thermocouple bead junction center package surface using highly
thermally conductive cements. Intel's laboratory testing done using Omega Bond (part number: OB-100).
Attach thermocouple angle shown Figure
Figure Technique Measuring Case Temperature (TC)
Embedded Pentium® Processor with Voltage Reduction Technology
3.4.2
Thermal EquationFor embedded Pentium processor with voltage reduction technology, ambient temperature, (air temperature around processor), specified directly. only requirement that case temperature (TC) met. calculate values, following equations: where, ambient case temperature (°C) case-to-ambient thermal resistance (°C/W) junction-to-ambient thermal resistance (°C/W) junction-to-case thermal resistance (°C/W) maximum power consumption Watts (see Table
Table lists values Pentium processor with passive heatsinks. Thermal data collection parameters:
Heatsinks omnidirectional aluminum alloy Features were based standard extrusion practices given height size ranged from mils spacing ranged from mils Base thickness ranged from mils Heatsink attach 0.005" thermal grease Using attach thickness 0.002" improves performance approximately °C/W
Table Thermal Resistances Embedded Pentium® Processors with Voltage Reduction Technology
Heatsink Height Inches 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Without Heatsink (°C/Watt) 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 14.5 CA(°C/Watt) Laminar Airflow (Linear ft/min) 13.8 12.6 10.5
Embedded Pentium® Processor with Voltage Reduction Technology
Electrical SpecificationAbsolute Maximum RatingThe following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Extended operation beyond maximum ratings affect device reliability. Furthermore, although embedded Pentium processor with voltage reduction technology contains protective circuitry resist damage from static electric discharge, always take precautions avoid high static voltages electric fields.
Table Absolute Maximum RatingParameter Case temperature under bias Storage temperature Supply voltage with respect Supply voltage with respect Only Buffer Input Voltage Safe Buffer Input Voltage Maximum Rating -65° 110° -65° 150° -0.5 +4.6 -0.5 +4.1 -0.5 VCC3 +0.5; exceed -0.5
NOTES: Applies SPGA embedded Pentium® processor with voltage reduction technology inputs except CLK. Applies CLK. Table
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only.
SpecificationTables list specifications that apply embedded Pentium processor with voltage reduction technology. embedded Pentium processor with voltage reduction technology core operates internally while interface operates input Since 3.3-V (5-V safe) input levels defined Table same levels, input compatible with existing clock drivers.
Embedded Pentium® Processor with Voltage Reduction Technology
Table SpecificationTCASE VCC2 VCC3 Symbol VIL3 VIH3 VOL3 VOH3 ICC2 ICC3 Input Voltage Input High Voltage Output Voltage Output High Voltage Power Supply Current from 3.1-V core supply Power Supply Current from 3.3-V buffer supply 2775 Parameter -0.3 VCC3+0.3 Unit Notes Level, Note Level, Note Level, Note Note Level, Note Note Note Note
NOTES: 3.3-V levels apply signals except CLK. Parameter measured Parameter measured This value should used power supply design. estimated worst-case instruction VCC2 VCC3 Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from stop clock full active modes.
Table 3.3-V (5-V Safe) SpecificationSymbol VIL5 VIH5 Parameter Input Voltage Input High Voltage -0.3 5.55 Unit Notes Level; applies only Level; applies only
Table Input Output CharacteristicSymbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current -400 Unit Notes Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. VCC3 (for input without pull pull down resistors) VCC3 (for input without pull pull down resistors) (for input with pull down resistors) (for input with pull resistors)
Embedded Pentium® Processor with Voltage Reduction Technology
4.2.1
Power Sequencing
There specific sequence required powering powering down VCC2 VCC3 power supplies. However, recommended that VCC2 VCC3 power supplies either both both within second each other.
SpecificationThe specifications embedded Pentium processor with voltage reduction technology consist setup times, hold times, valid delays embedded Pentium processors with voltage reduction technology specifications valid VCC2 VCC3 TCASE
4.3.1
Power Ground
clean on-chip power distribution, embedded Pentium processor with voltage reduction technology VCC2 (3.1-V power), VCC3 (3.3-V power) (ground) inputs. Power ground connections must made external VCC2, VCC3 pins processor. circuit board, VCC2 pins must connected 3.1-V VCC2 plane island) VCC3 pins must connected 3.3-V VCC3 plane. pins must connected plane. Refer Table list VCC2 VCC3 pins.
4.3.2
Decoupling RecommendationTransient power surges occur processor executing instruction sequences driving large loads. mitigate these high frequency transients, liberal high frequency decoupling capacitors should placed near processor. inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced minimizing length circuit board traces between processor decoupling capacitors. These capacitors should evenly distributed around each component 3.3-V plane 3.1-V plane island). Capacitor values should chosen ensure that they eliminate both high frequency noise components. Power transients also occur processor rapidly transitions from power consumption level much higher level high low). typical example would entering exiting Stop Grant state. Other examples include executing HALT instruction (which causes processor enter Auto HALT Powerdown state) transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Several bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point which regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel.
Embedded Pentium® Processor with Voltage Reduction Technology
These capacitors should placed near processor 3.3-V plane 3.1-V plane island) ensure that these supply voltages stay within specified limits during changes power demands processor during operation. more detailed information, please contact Intel refer Pentium® Processor with Voltage Reduction Technology: Power Supply Design Considerations Mobile Systems application note (order number 242558). Note: Capacitors degrade over time during use. capacitors age, their capacity store hold charge becomes compromised. Designing board with below minimum acceptable bypass bulk capacitors have future system reliability consequences.
4.3.3
Connection SpecificationAll pins must remain unconnected. Refer Table list pins. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected ground.
4.3.4
TimingThe specifications given Table consist output delays, input setup requirements input hold requirements 66-MHz external bus. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct operation.
Table Specifications (Sheet
VCC2 ±165 VCC3 ±165 TCASE Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, BE7#-BE0#, D/C#, W/R#, CACHE#, SCYC Valid Delay Valid Delay LOCK# Valid Delay ADS# Valid Delay A31-A3 Valid Delay M/IO# Valid Delay 0.15 0.15 Parameter 33.33 15.0 66.6 30.0 ±250 Unit Note @0.8 Note V-0.8 Note V-2.0 Note Figure Note
NOTE: Table table notes.
Embedded Pentium® Processor with Voltage Reduction Technology
Table Specifications (Sheet
VCC2 ±165 VCC3 ±165 TCASE Symbol Parameter ADS#, A31-A3, PWT, PCD, BE7#-BE0#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM1-PM0, BP3-BP0 Valid Delay PRDY Valid Delay D63-D0, DP7-DP0 Write Data Valid Delay D63-D0, DP3-DP0 Write Data Float Delay A31-A5 Setup Time A31-A5 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time Unit Figure Note
10.0
t10a t10b t11a t11b t16a t16b t18a t18b t24a t24b t25a t25b
10.0 10.0
NOTE: Table table notes.
Embedded Pentium® Processor with Voltage Reduction Technology
Table Specifications (Sheet
VCC2 ±165 VCC3 ±165 TCASE Symbol t42a t42b Parameter INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D63-D0, DP7-DP0 Read Data Setup Time D63-D0, DP7-DP0 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDY#, BUSCHK#) Hold Time, Async. Reset Configuration Signal (BRDY#, BUSCHK#) Setup Time, Async. Setup Time Hold Time BE4# Setup Time BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time 15.0 Unit CLKs CLKs CLKs CLKs Power RESET falling edge, Note RESET falling edge, Note RESET falling edge, Note RESET falling edge, Note RESET falling edge, Note RESET falling edge RESET falling edge Figure Notes
t42c t43a t43b t43c t43d
62.5 25.0 25.0 16.0
CLKs CLKs CLKs
Note @0.8 Note V-0.8 Notes V-2.0 Notes
NOTE: Table table notes.
Embedded Pentium® Processor with Voltage Reduction Technology
Table Specifications (Sheet
VCC2 ±165 VCC3 ±165 TCASE Symbol Parameter TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 40.0 13.0 20.0 25.0 20.0 25.0 Unit Figure Notes Asynchronous, Note
NOTE: Table table notes.
Table Notes Table
NOTES: Notes general apply standard signals used with Pentium® processor family. percent tested. Guaranteed design. input test waveforms assumed transitions with V/ns rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions. V/ns input rise/fall time V/ns. V/ns input rise/fall time V/ns. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. During probe mode operation, boundary scan timings (t55-58). Setup time required guarantee recognition specific clock. Hold time required guarantee recognition specific clock. timings referenced from guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. This input driven asynchronously. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must deasserted (inactive) minimum clocks before being returned active. D/C#, M/IO#, W/R#, CACHE#, A31-A5 signals sampled only which ADS# active. should strapped VCC3 left floating. These signals measured rising edge adjacent CLKs ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. Timing (t14) required external snooping (e.g., address setup which EADS# sampled active). BUSCHK# used reset configuration signal select buffer size. Each valid delay specified load. system designer should buffer modeling account signal flight time delays.
Embedded Pentium® Processor with Voltage Reduction Technology
Figure Clock Waveform
Figure Valid Delay Timing
Embedded Pentium® Processor with Voltage Reduction Technology
Figure Float Delay Timing
Figure Setup Hold Timing
Embedded Pentium® Processor with Voltage Reduction Technology
Figure Reset Configuration Timing
Embedded Pentium® Processor with Voltage Reduction Technology
Figure Test Timing
Output SignalTr
Input SignalTr
Figure Test Reset Timing
Embedded Pentium® Processor with Voltage Reduction Technology
Buffer ModelThis section describes buffer models embedded Pentium processor with voltage reduction technology. first-order buffer model simplified representation complex input output buffers used embedded Pentium processor with voltage reduction technology. Figure Figure show structure input buffer model Figure shows output buffer model. Table Table show parameters used specify these models. Although simplified, these buffer models accurately model flight time signal quality. these parameters, there very little added accuracy complete transistor model. following models represent input buffer models. first model, Figure represents input buffers except special group input buffers. second model, Figure represents these special buffers: AHOLD, EADS#, KEN#, WB/WT#, INV, NA#, EWBE#, BOFF# CLK. addition input output buffer parameters, input protection diode models provided added accuracy. These diodes have been optimized provide protection provide some level clamping. Although diodes required simulation, more difficult meet specifications without them. Some signal quality specifications require that diodes removed from input model. series resistors (Rs) part diode model. Remove these when removing diodes from input model.
Figure Input Buffer Model, Except Special Group
Note: refers buffer VCC3.
Embedded Pentium® Processor with Voltage Reduction Technology
Figure Input Buffer Model Special Group
Vcc2
Table Parameters Used Specification First Order Input Buffer Model
Parameter Description Minimum Maximum value capacitance input buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance Diode Series Resistance Ideal Diode
Figure shows structure output buffer model. This model used output buffers embedded Pentium processor with voltage reduction technology.
Embedded Pentium® Processor with Voltage Reduction Technology
Figure First-Order Output Buffer Model
Table Parameters Used Specification First-Order Output Buffer Model
Parameter dV/dt Description Minimum maximum value rate change open circuit voltage source used output buffer model Minimum maximum value output impedance output buffer model Minimum Maximum value capacitance output buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance
4.4.1
Buffer Model ParameterThis section gives parameters each embedded Pentium processor with voltage reduction technology input, output bidirectional signal, well settings configurable buffers. Some pins embedded Pentium processor with voltage reduction technology have selectable buffer sizes. These pins configurable output buffer EB2. Table shows drive level BRDY# required falling edge RESET select buffer strength. buffer sizes selected should appropriate size required; otherwise timings might met, much overshoot ringback occur. There other selection choices; configurable buffers same size during setup initialization. input, output bidirectional buffer values embedded Pentium processor with voltage reduction technology listed Table This table contains listings three types; confuse them during simulation. When bidirectional operating input, Cin, values; when operating driver, data parameters. Refer Table groupings buffers.
Table Buffer Selection Chart
Environment Typical Stand Alone Component Loaded Component BRDY# Buffer Selection EB2A
NOTE: correct buffer selection, BUSCHK# signal must held inactive (high) falling edge RESET.
Embedded Pentium® Processor with Voltage Reduction Technology
Table Signal Buffer Type
Signals A20M#, AHOLD, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE7#-BE5#, BP3-BP2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, TDO, U/O# A31-A21, BE4#-BE0#, CACHE#, D/C#, D63-D0, DP8-DP0, HLDA, LOCK#, M/IO#, SCYC A20-A3, ADS#, HITM#, W/R# HIT# Type Driver Buffer Type Receiver Buffer Type
EB2/EB2A EB2/EB2A
Table Input, Output Bidirectional Buffer Model ParameterBuffer Type Transition (input) (input) (output) (bidir) (bidir) EB2A (bidir) (bidir) Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling Rising Falling 3/3.0 3/2.8 3/3.0 3/2.8 3/3.0 3/2.8 3/2.4 3/2.4 3/3.0 3/2.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.8 3.7/0.9 3.7/0.9 3.7/0.9 3.7/0.8 21.6 17.5 21.6 17.5 21.6 17.5 10.1 21.6 17.5 53.1 50.7 53.1 50.7 53.1 50.7 22.4 21.2 53.1 50.7 dV/dt (V/ns) (Ohms) (pF) (nH) 15.3 15.3 17.7 17.7 18.7 18.7 16.7 16.7 16.7 16.7 14.3 14.3 Co/Cin (pF)
Table Input Buffer Model Parameters: (Diodes)
Symbol Parameter Saturation Current Emission Coefficient Series Resistance Transit Time Potential Zero Bias Capacitance Grading Coefficient 1.4e-14 1.19 ohms 0.983 0.281 0.385 2.78e-16 1.00 ohms 0.967 0.365 0.376
Embedded Pentium® Processor with Voltage Reduction Technology
4.4.2
Signal Quality SpecificationSignals driven system into embedded Pentium processor with voltage reduction technology must meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect reliability component. There signal quality parameters: ringback settling time.
4.4.2.1
Ringback
Excessive ringback contribute long-term degradation reliability embedded Pentium processor with voltage reduction technology, cause false signal detection. Ringback simulated input component using input buffer model. Ringback simulated with without diodes that input buffer model. Ringback absolute value maximum voltage receiving below VCC3 above VSS) relative VCC3 VSS) level after signal reached maximum voltage level. input diodes assumed present. Maximum Ringback Inputs (with diodes) simulated without input diodes, follow maximum overshoot/undershoot specification. meeting overshoot/undershoot specification, signal guaranteed ringback excessively. simulated with diodes present input model, follow maximum ringback specification. Overshoot (undershoot) absolute value maximum voltage above VCC3 (below VSS). guideline assumes absence diodes input.
maximum overshoot/undershoot 3.3-V embedded Pentium processor with voltage
reduction technology inputs (not CLK) above VCC3 (without diodes) Figure Overshoot/Undershoot Ringback Guideline
Embedded Pentium® Processor with Voltage Reduction Technology
4.4.2.2
Settling Time
settling time defined time required receiver signal settle within percent VCC3 VSS. Settling time also maximum time allowed signal reach within percent final value. Most available simulation tools unable simulate settling time that accurately reflects silicon measurements. physical board, second-order effects other effects dampen signal receiver. Because these concerns, settling time recommendation tool layout tuning specification. Settling time simulated slow corner, make sure that there impact flight times signals waveform settled. Settling time simulated with diodes included excluded from input buffer model. diodes included, settling time recommendation will easier meet. Although simulated settling time shown good correlation with physical, measured settling time, settling time simulations still used tool tune layouts. following procedure verify board simulation tuning with concerns settling time. Simulate settling time slow corner particular signal. settling time violations occur, simulate signal trace with diodes place receiver pin. diode behaves almost identically actual (non-linear) diode part long excessive overshoot does occur. settling time violations still occur, simulate flight times five consecutive cycles that particular signal. flight time values consistent over five simulations, settling time should concern. however, flight times consistent over five simulations, tuning layout required. Note that, signals that allocated cycles flight time, recommended settling time doubled. typical design method would include settling time that ensures that signal within percent VCC3 least prior period.
Figure Settling Time