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Embedded Pentium® Processor
MHz, MHz,
Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit Processor with 64-Bit Data Superscalar Architecture Pipelined Integer Units Capable Instructions/Clock Pipelined Floating-Point Unit Separate Code Data Caches 8-Kbyte Code, 8-Kbyte Write-Back Data MESI Cache Protocol Advanced Design Features Branch Prediction Virtual Mode Extensions BiCMOS Silicon Technology 4-Mbyte Pages Increased Rate IEEE 1149.1 Boundary Scan Dual Processing Configuration Functional Redundancy Checking Support
Internal Error Detection Features Multiprocessor Support Multiprocessor Instructions Support Second-level Cache On-Chip Local APIC Controller Multiprocessor Interrupt Management 8259 Compatible Power Management Features System Management Mode Clock Control Fractional Operation 166-MHz Core/66-MHz 133-MHz Core/66-MHz 100-MHz Core/66-MHz iCOMP® Index Rating
Contact Intel Corporation more information about iCOMP® Index ratings.
embedded Pentium® processor provides high performance embedded applications. Pentium processor compatible with entire installed base applications DOS*, Windows*, OS/2*, UNIX*. Pentium processor superscalar architecture execute instructions clock cycle. Branch prediction separate code data caches also increase performance. pipelined floating-point unit delivers high level performance. Separate code data caches reduce cache conflicts while remaining software transparent. Pentium processor million transistors built Intel's advanced BiCMOS silicon technology. Pentium processor on-chip dual processing support, local multiprocessor interrupt controller, power management features.
Order Number: 273202-001 November 1998
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1993, 1996, 1997, 1998 *Third-party brands names property their respective owners.
Embedded Pentium® Processor
Contents
Architecture Overview
Pentium® Processor Family Architecture Pentium® Processors with Voltage Reduction Technology.10 Pentium® Processor Pinout.11 2.1.1 Cross Reference 2.1.2 Design Notes.15 2.1.3 Quick Reference 2.1.4 Reference Tables.21 2.1.5 Grouping According Function.24 Mechanical Specifications Thermal Specifications 2.3.1 Measuring Thermal Values 2.3.2 Thermal Equations Data Power Supply.29 Inputs Outputs.29 Absolute Maximum Ratings.29 Specifications Specifications 3.5.1 Private 3.5.2 Power Ground 3.5.3 Decoupling Recommendations 3.5.4 Connection Specifications 3.5.5 Timing Tables.32
Packaging Information
Electrical Specifications
Embedded Pentium® Processor
Figures
Embedded Pentium® Processor Block Diagram Pentium® Processor SPGA Package Pinout (Top Side View) Pentium® Processor SPGA Package Pinout (Pin Side View) SPGA Package Dimensions Technique Measuring Case Temperature (TC). Clock Waveform. Valid Delay Timings Float Delay Timings Setup Hold Timings. Reset Configuration Timings. Test Timings. Test Reset Timings Measurement Flight Time.
Tables
Cross-Reference Name Address Data Pins Cross-Reference Name Control Pins Cross-Reference Name Power, Ground Connect Pins Quick Reference Frequency Selections Output Pins Input Pins Input/Output Pins Inter-processor Input/Output Pins Functional Grouping. Package Information Summary Pentium® Processor SPGA Package Dimensions Power Dissipation Requirements Thermal Solution Design Thermal Resistances Embedded Pentium® Processors. Absolute Maximum Ratings Specifications V-Safe) Specifications Input Output Characteristics. Specifications Dual Processor Mode Specifications Notes Tables
Embedded Pentium® Processor
Revision History
Date 11/12/98 Revision Description This first publication this document.
Embedded Pentium® Processor
Architecture Overview
Intel® embedded Pentium® processor binary compatible with 8086/88, 80286, Intel386DX, Intel386 Intel486DX, Intel486 IntelDX2TM, IntelDX4and 60/66 Pentium processors. embedded Pentium processor family consists following products:
Embedded Pentium processors (described this document).
Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating Pentium processor MHz, iCOMP Index rating
Pentium processor with Voltage Reduction Technology (described separate datasheet,
order number 273203). Pentium processor with Voltage Reduction Technology MHz, iCOMP Index rating Pentium processor features include:
Superscalar architecture Dynamic branch prediction Pipelined floating-point unit Improved instruction execution time Separate 8-Kbyte code 8-Kbyte data caches Writeback MESI protocol data cache 64-Bit data cycle pipelining Address parity Internal parity checking Functional redundancy checking Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Fractional operation allowing higher core frequency operation Dual processing support power management features On-chip local APIC device
Embedded Pentium® Processor
Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 processor family instruction with extensions accommodate some additional functionality Pentium processor. application software written Intel386 Intel486 family microprocessors runs Pentium processors without modification. on-chip memory management unit completely compatible with Intel386 family Intel486 family processors. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, processor prefetch buffers: prefetches code linear fashion other prefetches code according needed code almost always prefetched before needed execution. floating-point unit (FPU) times faster than used Intel486 processor common operations including add, multiply, load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache Kbytes with 32-byte line size, two-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable write back write through line-by-line basis follows MESI protocol. data cache tags triple-ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags also triple-ported support snooping split-line accesses. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware. Pentium processors have 64-bit data fast data transfer. Burst read burst write back cycles supported. addition, cycle pipelining allows cycles occur simultaneously. Memory Management Unit contains optional extensions architecture which allow 2-Mbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. Pentium processors offer functional redundancy checking provide maximum error detection processor interface processor. When functional redundancy checking used, second processor, "checker" executes lock-step with "master" processor. checker samples master's outputs, compares those values with values computes internally, asserts error signal when mismatch occurs. more more functions integrated on-chip, complexity board level testing increased. address this, Pentium processors provide test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors provide four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken.
Embedded Pentium® Processor
System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor. Figure block diagram embedded Pentium processor. Figure Embedded Pentium® Processor Block Diagram
Control
Logic
Branch Prefetch Target Buffer Address
Code Cache Kbytes
Instruction Pointer 64-Bit Data Branch Verification Target Address
Prefetch Buffers Instruction Decode
Control
Control Unit
32-Bit Address
Unit
Page Unit
Address Address Generate Generate Pipeline) Pipeline)
Floating Point Unit
Control Integer Register File Pipline) Pipline)
64-Bit Data
Control Register File Divide Multiply
Barrel Shifter
32-Bit Addr.
Data APIC Control
Data Cache Kbytes
A6053-01
block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions. separate code data caches shown block diagram. data cache ports, each pipes (the tags triple-ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache.
Embedded Pentium® Processor
decode unit decodes prefetched instructions processor execute instruction. control contains microcode control sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processors contain pipelined floating-point unit that provides significant floating-point performance advantage over previous generations processors. Symmetric dual processing system supported with Pentium processors. processors appear system single processor. Operating systems with dual processing support properly schedule computing tasks between processors. This scheduling tasks transparent software applications end-user. Logic built into processors supports "glueless" interface easy system design. Through private bus, Pentium processors arbitrate external maintain cache coherency. Dual processing supported system only both processors operating identical core frequencies. this document, order distinguish between Pentium processors dual processing mode, processor "Primary" processor other "Dual" processor. Note that this different concept than that "master" "checker" processors described discussion functional redundancy page Pentium processor supports clock control. When clock processor stopped, power dissipation virtually eliminated. This makes Pentium processor good choice energyefficient designs. Pentium processor supports fractional operation. This allows processor core operate high frequencies, while communicating with external lower frequencies. Pentium processor contains on-chip Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across processors), multiple subsystem support, 8259A compatibility, inter-processor interrupt support. Pentium processor architectural features described more detail Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Pentium® Processors with Voltage Reduction Technology
Embedded Pentium processor with Voltage Reduction Technology described Embedded Pentium® Processor with Voltage Reduction Technology datasheet (order number 273203).
Embedded Pentium® Processor
Packaging Information
Pentium® Processor Pinout
Figure Pentium® Processor SPGA Package Pinout (Top Side View)
D/P#
FLUSH#
W/R# EADS# ADSC# BREQ
SCYC BE6# BE7#
BE4# BE2# BE3#
BE0# BUSCHK# HITM# D/C# HLDA
RESET
BE5#
BE1# A20M# HIT#
ADS#
LOCK#
SMIACT# PCHK#
APCHK# PBREQ# PBGNT#
INTR R/S#
PRDY PHITM# HOLD
SMI#
IGNNE# INIT PEN#
WB/WT# PHIT#
FRCMC#
View Component Mounted Board (Pins Down)
BOFF#
BRDYC# BRDY#
KEN# EWBE# AHOLD
STPCLK#
CACHE# MI/O#
PM1BP1
CPUTYP TRST#
FERR# PM0BP0 IERR#
PICD1
PICD0
PICCLK
A5498-01
Embedded Pentium® Processor
Figure Pentium® Processor SPGA Package Pinout (Pin Side View)
D/P#
FLUSH#
ADSC# EADS# W/R#
HITM# BUSCHK# BE0# D/C#
BE2# BE4# BE3#
BE6# SCYC
HIT# A20M# BE1#
BE5# BE7#
RESET
BREQ HLDA ADS# LOCK#
SMIACT# PCHK#
PBREQ# APCHK# PBGNT# PHITM# PRDY HOLD
INTR R/S#
SMI#
PHIT# WB/WT# BOFF#
INIT IGNNE# PEN#
BRDYC# BRDY#
FRCMC#
EWBE# KEN# AHOLD CACHE# MI/O#
Side View
STPCLK#
PM1BP1 PM0BP0 FERR# IERR#
TRST# CPUTYP
PICD1 PICD0
PICCLK
A5499-01
Embedded Pentium® Processor
2.1.1
Table
Cross Reference
Cross-Reference Name Address Data Pins
Location Location Location Location Location
Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 Data AK26 AL25 AK24 AL23 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33
Embedded Pentium® Processor
Table
Cross-Reference Name Control Pins
Location Location Location Location
A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY#
AK08 AJ05 AM02 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16
BRDYC# BREQ BUSCHK# CACHE# CPUTYP D/C# D/P# EADS# EWBE# FERR#
AJ01 AL07 AK04 AE35 AM04 APIC
FLUSH# FRCMC# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/ LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK#
AN07 AK06 AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04
PEN# PM0/BP0 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT#
AC05 AL03 AC35 AK20 AL17 AB34 AG03 AM06 AA05
PICCLK
PICD0/ [DPEN#]
PICD1/ [APICEN]
Clock Control AK18 STPCLK#
Dual Processor Private Interface PBGNT# AD04 PBREQ# AE03 PHIT# AA03 PHITM# AC03
Embedded Pentium® Processor
Table
Cross-Reference Name Power, Ground Connect Pins
AA01 AA37
AC01 AC37 AE01 AE37 AG01 AG37
AN09 AN11 AN13 AN15 AN17 AN19
AN21 AN23 AN25 AN27 AN29
NC/INC
AB02 AB36 AD02 AD36 AF02
AF36 AH02 AJ37 AL37 AM08 AM10
AM12 AM14 AM16 AM18 AM20 AM22
AM24 AM26 AM28 AM30 AN37
AL01
AL19 AN01
AN03 AN05
AN35
These pins should left unconnected. Connection these pins result component failure incompatibility with processor steppings.
2.1.2
Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC. Unused active high inputs should connected GND. Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
2.1.3
Quick Reference
This section gives brief functional description each pins. detailed description, Pentium® Processor Family Developer's Manual (order number 273204). Note: input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active, asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. following pins become pins when Pentium processors operating dual processing environment:
ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#, M/IO#, D/C#, W/R#, SCYC
Embedded Pentium® Processor
Table
Quick Reference (Sheet
Symbol Type Name Function When address mask asserted, processor emulates address wraparound Mbyte that occurs 8086 masking physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. A20M# internally masked processor when configured Dual processor. A31-A3 ADS# ADSC# AHOLD outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address strobe indicates that valid cycle currently being driven processor. additional address strobe signal functionally identical ADS#. This signal used relieve tight board timings easing load ADS# signal. response assertion address hold, processor stops driving address lines (A31-A3), next clock. rest remains active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock which address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated processor. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# remains active clock each time parity error detected (including during dual processing private snooping). Advanced programmable interrupt controller enable enables disables chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. byte enable pins determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-A3). lower four byte enable pins (BE3#-BE0#) used APIC inputs sampled RESET. dual processing mode, BE4# used input during Flush cycles. BF1-BF0 frequency determines bus-to-core frequency ratio. BF1-BF0 sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF1-BF0 must change values while RESET active. Table frequency selections. backoff input used abort outstanding cycles that have completed. response BOFF#, processor floats pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. breakpoint pins (BP3-BP0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring.
A20M#
APCHK#
[APICEN] PICD1
BE7#-BE5# BE4#-BE0#
BOFF#
BP3-BP2 PM1/BP1- PM0/BP0
pins classified Input Output based their function Master Mode. Pentium® Processor Family Developer's Manual (order number 273204) more information.
Embedded Pentium® Processor
Table
Quick Reference (Sheet
Symbol Type Name Function burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. additional burst ready signal same functionality BRDY#. This signal used relieve tight board timings easing load Burst Ready signal. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. When this sampled active, processor latches address control signals machine check registers. When BUSCHK# asserted set, processor vectors machine check exception. BUSCHK# ensure that BUSCHK# always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. When BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, normally (when MCE=1) processor vectors exception after STPCLK# deasserted. When another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cacheability indicates internal cacheability cycle read), indicates burst write back cycle write). When this driven inactive during read cycle, processor does cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor's external bus, requires levels. external timing parameters except TDI, TDO, TMS, TRST#, PICD1-PICD0 specified with respect rising edge CLK. recommended that begin toggling within after reaches proper operating level. This recommendation ensure long-term reliability device. CPUTYP type distinguishes Primary processor from Dual processor. single processor environment, when processor acting Primary processor dual processing system, CPUTYP should strapped VSS. Dual processor should have CPUTYP strapped VCC. data/code output primary cycle definition pins. driven valid same clock which ADS# signal asserted. D/C# distinguishes between data code special cycles. dual/primary processor indication. Primary processor drives this when driving bus, otherwise drives this high. D/P# always driven. D/P# sampled current cycle with ADS# (like status pin). This defined only Primary processor. Dual processing supported system only both processors operating identical core frequencies. Within these restrictions, processors different steppings operate together system. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during T12, clocks that cycle. During reads, samples data when BRDY# returned.
BRDY#
BRDYC#
BREQ
CACHE#
D/C#
D/P#
D63-D0
pins classified Input Output based their function Master Mode. Pentium® Processor Family Developer's Manual (order number 273204) more information.
Embedded Pentium® Processor
Table
Quick Reference (Sheet
Symbol Type Name Function These data parity pins processor. There each byte data bus. They driven Pentium processor with even parity information writes same clock write data. Even parity information must driven back processor these pins same clock data ensure that correct parity check status indicated Pentium processor. applies D63-D56, applies D7-D0. Dual processing enable output Dual processor input Primary processor. Dual processor drives DPEN# Primary processor RESET indicate that Primary processor should enable dual processor mode. DPEN# sampled system falling edge RESET determine dual-processor socket occupied. DPEN# shares with PICD0. external address strobe signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write, EWBE# sampled inactive, processor holds subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating-point error reporting. FERR# never driven active Dual processor. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle generated processor indicate completion write back invalidation. When FLUSH# sampled when RESET transitions from high low, three-state test mode entered. FLUSH# Pentium processors operating dual processing mode FLUSH# asserted, Dual processor performs flush first (without flush acknowledge cycle), then Primary processor performs flush followed flush acknowledge cycle. When FLUSH# signal asserted dual processing mode, must deasserted least clock prior BRDY# FLUSH Acknowledge cycle avoid arbitration problems. functional redundancy checking master/checker mode input used determine whether processor configured master mode checker mode. When configured master, processor drives output pins required protocol. When configured checker, processor three-states outputs (except IERR# TDO) samples output pins. configuration master/checker after RESET changed other than subsequent RESET. inquire cycle hit/miss indication driven reflect outcome inquire cycle. inquire cycle hits valid line either processor data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses processor cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. inquire cycle hit/miss modified line output driven reflect outcome inquire cycle. asserted after inquire cycle that results modified line data cache. used inhibit another master from accessing data until line completely written back.
DP7-DP0
[DPEN#] PICD0
EADS#
EWBE#
FERR#
FRCMC#
HIT#
HITM#
pins classified Input Output based their function Master Mode. Pentium® Processor Family Developer's Manual (order number 273204) more information.
Embedded Pentium® Processor
Table
Quick Reference (Sheet
Symbol Type Name Function hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA driven inactive processor resumes driving bus. When processor cycle pending, driven same clock which HLDA deasserted. response hold request, processor floats most output input/output pins asserts HLDA after completing outstanding cycles. processor maintains this state until HOLD deasserted. HOLD recognized during LOCK cycles. processor recognizes HOLD during reset. internal error used indicate types errors, internal parity errors functional redundancy errors. When parity error occurs read from internal array, processor asserts IERR# clock then shuts down. When processor configured checker mismatch occurs between value sampled pins corresponding value computed internally, processor asserts IERR# clocks after mismatched value returned. lock indicates that current cycle locked. processor does allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed deasserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock which ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor issues ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. When local APIC enabled, this becomes LINT1. PBGNT# When Pentium processors configured dual processing mode, Private grant grant line that used perform private arbitration. PBGNT# should left unconnected only Pentium processor exists system. When Pentium processors configured dual processing mode, Private request request line that used perform private arbitration. PBREQ# should left unconnected only Pentium processor exists system. page cacheability disable reflects state CR3, Page Directory Entry, Page Table Entry. purpose provide external cacheability indication page-by-page basis. data parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. When Pentium processors operating dual processing mode, PCHK# driven three clocks after BRDY# returned. parity enable input (along with CR4.MCE) determines whether machine check exception taken result data parity error read cycle. When this sampled active clock during which data parity error detected, processor latches address control signals cycle with parity error machine check registers. When PEN# active machine check enable "1", processor vectors machine check exception before beginning next instruction.
HLDA
HOLD
IERR#
LOCK#
M/IO#
NMI/LINT1
PBREQ#
PCHK#
PEN#
pins classified Input Output based their function Master Mode. Pentium® Processor Family Developer's Manual (order number 273204) more information.
Embedded Pentium® Processor
Table
Quick Reference (Sheet
Symbol PHIT# Type Name Function Private inquire cycle hit/miss indication used maintain local cache coherency when Pentium processors configured dual processing mode. PHIT# should left unconnected only Pentium processor exists system. Private inquire cycle hit/miss modified line indication used maintain local cache coherency when Pentium processors configured dual processing mode. PHITM# should left unconnected only Pentium processor exists system. APIC interrupt controller serial data clock driven into processor interrupt controller clock input processor. Processor interrupt controller data lines processor comprise data portion APIC 3-wire bus. They open-drain outputs that require external pull-up resistors. These signals share pins with DPEN# APICEN respectively. These pins function part performance monitoring feature. PM1/BP1- PM0/BP0 breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine whether pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output indicates that processor stopped normal execution response R/S# going active, Probe Mode being entered. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock processor, which causes core consume less power. When processor recognizes STPCLK#, processor stops execution next instruction boundary, unless superseded higher priority interrupt, generates stop grant acknowledge cycle. When STPCLK# asserted, processor still responds interprocessor external snoop requests. testability clock input provides clocking function Pentium processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Pentium processor power inputs. Pentium processor ground inputs. Write/read primary cycle definition pins. driven valid same clock which ADS# signal asserted. W/R# distinguishes between write read cycles. write back/write through input allows data cache line defined write back write through line-by-line basis. result, determines whether cache line initially state data cache.
PHITM#
PICCLK PICD1/[DPEN#]- PICD0/[APICEN]
PRDY SMIACT#
STPCLK#
TRST# W/R#
WB/WT#
pins classified Input Output based their function Master Mode. Pentium® Processor Family Developer's Manual (order number 273204) more information.
Embedded Pentium® Processor
Table
Frequency Selections
Pentium® Processor Core Frequency (max) External Frequency (max) Bus/Core Ratio
2.1.4
Table
Reference Tables
Output Pins
Name ADS#2 ADSC# APCHK# BE7#-BE5# BREQ CACHE#2 D/P#3 FERR#3 HIT#2 HITM#2 HLDA2 IERR# LOCK#2 M/IO#2, D/C#2, W/R#2 PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC2 SMIACT# Active Level1 High High High High High High states except Shift-DR Shift-IR Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated Hold, BOFF# Hold, BOFF#
NOTES: output input/output pins floated during three-state test mode checker mode (except IERR#). These signals when Pentium processors operating dual processing mode. These signals undefined when processor configured dual processor.
Embedded Pentium® Processor
Table
Input Pins
Name A20M# AHOLD BF1-BF0 BOFF# BRDY# BRDYC# BUSCHK# CPUTYP EADS# EWBE# FLUSH# FRCMC# HOLD IGNNE# INIT INTR KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT#
Active Level High High High High High High High High High High
Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Synchronous Synchronous
Internal Resistor
Qualified
Pullup
State T12, Pullup Pullup State T12, BRDY#
Synchronous/RESET Synchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Pullup Pullup Pullup First BRDY#/NA# Pullup Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY#
Undefined when processor configured dual processor.
Embedded Pentium® Processor
Table
Input/Output Pins
Name A31-A3 BE4#-BE0# D63-D0 DP7-DP0 PICD0[DPEN#] PICD1[APICEN] Active Level When Floated1 Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown2 Internal Resistor
NOTES: output input/output pins floated during three-state test mode (except TDO) checker mode (except IERR# TDO). BE3#-BE0# have pulldowns during RESET only.
Table
Inter-processor Input/Output Pins
Name PHIT# PHITM# PBGNT# PBREQ# Active Level Internal Resistor Pullup Pullup Pullup Pullup
proper interprocessor operation, system cannot load these signals.
Embedded Pentium® Processor
2.1.5
Grouping According Function
Table Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Dual Processing Private Control Interrupts Floating-point Error Reporting System Management Mode Functional Redundancy Checking Port Breakpoint/Performance Monitoring Power Management Miscellaneous Dual Processing Probe Mode Pins RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD1-PICD0 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, FERR#, IGNNE# SMI#, SMIACT# FRCMC# (IERR#) TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# CPUTYP, D/P# R/S#, PRDY
Embedded Pentium® Processor
Mechanical Specifications
embedded Pentium processor packaged 296-pin ceramic staggered grid array (SPGA) package. pins arranged matrix package dimensions 1.95" 1.95" (Table 11). Figure Table show package dimensions.
Table Package Information Summary Pentium® Processor
Package Type Ceramic Staggered Grid Array SPGA Total Pins Array Package Size 1.95" 1.95" 4.95 4.95
Figure SPGA Package Dimensions
01.65 Ref. Seating Plane
2.29 Ref. 1.52 Chamfer (index corner)
Table SPGA Package Dimensions
Millimeters Symbol 1.52 2.62 0.69 3.31 0.43 49.28 45.59 2.29 3.05 2.54 2.97 0.84 3.81 0.51 49.78 45.85 2.79 3.30 Lead Count 0.060 Metal Metal Notes 0.103 0.027 0.130 0.017 1.940 1.795 0.090 0.120 0.100 0.117 0.033 0.150 0.020 1.960 1.805 0.110 0.130 Lead Count Metal Metal Notes Inches
Embedded Pentium® Processor
Thermal Specifications
Pentium processor specified proper operation when case temperature, TCASE (TC), within specified range power dissipation specification Table provided designing thermal solutions operation sustained maximum level. This worst-case power device would dissipate system. This number used design thermal solution device.
Table Power Dissipation Requirements Thermal Solution Design
Parameter Active Power Dissipation Stop Grant Auto Halt Powerdown Power Dissipation Stop Clock Power Dissipation 0.02 Typical1 14.52 11.23 10.1 1.55 <0.3 Unit Watts Notes MHz, Note MHz, Note MHz, Note Note
Watts Watts
NOTES: This typical power dissipation system. This value average value measured system using typical device nominal (3.3 processors processors) running typical applications. This value highly dependent upon specific system configuration. Systems must designed thermally dissipate maximum active power device. determined using worst-case instruction with VCC=3.5 also takes into account thermal time constants package. Systems must designed thermally dissipate maximum active power device. determined using worst case instruction with also takes into account thermal time constants package. Stop Grant/Auto Halt Powerdown power dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock power dissipation determined asserting STPCLK# then removing external input.
2.3.1
Measuring Thermal Values
verify that proper (case temperature) maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (0.150" diameter smaller) should drilled through heatsink allow probe touch center package. Figure illustration measure minimize measurement errors, following approach:
36-gauge finer diameter type thermocouples. Attach thermocouple bead junction center package surface using high
thermal conductivity cements.
Attach thermocouple 90-degree angle shown Figure hole size should 0.150" less diameter.
Embedded Pentium® Processor
Figure Technique Measuring Case Temperature (TC)
2.3.2
Thermal Equations Data
Pentium processor, ambient temperature, (air temperature around processor), specified directly. only restriction that case temperature (TC) met. calculate values, following equations: where: ambient case temperature (°C) case-to-ambient thermal resistance (°C/W) junction-to-ambient thermal resistance (°C/W) junction-to-case thermal resistance (°C/W) maximum power consumption Watts (see Table
Table lists values Pentium processor with passive heatsinks. Thermal data collection parameters:
Heatsinks omnidirectional aluminum alloy Features were based standard extrusion practices given height size ranged from mils spacing ranged from mils Base thickness ranged from mils Heatsink attach 0.005" thermal grease Using attach thickness 0.002" improves performance approximately °C/W
Embedded Pentium® Processor
Table Thermal Resistances Embedded Pentium® Processors
Heatsink Height Inches 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Without Heatsink (°C/Watt) 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 14.5 CA(°C/Watt) Laminar Airflow (Linear ft/min) 13.8 12.6 10.5
Embedded Pentium® Processor
Electrical Specifications
This section describes specifications embedded Pentium processor.
Power Supply
processor 3.3-V inputs. PICCLK inputs tolerate input signal. This allows processor 3.3-V clock drivers.
Inputs Outputs
inputs outputs processor JEDEC standard levels. Both inputs outputs also TTL-compatible, although inputs cannot tolerate voltage swings above max. PICCLK inputs processor tolerant. This allows clock driver drive processor. other pins only. processor outputs, system support components TTL-compatible inputs, components will interface processor without extra logic. This because processor drives according specification (but beyond processor inputs, voltage must exceed VIH3 maximum specification. System support components consist devices open-collector devices. open-collector configuration, external resistor biased with processor's VCC. processor's changes from does this signal's maximum drive.
Absolute Maximum Ratings
Functional operating conditions given specification tables. Functional operation maximums implied guaranteed. Extended operation beyond maximum ratings affect device reliability. Furthermore, although Pentium processor contains protective circuitry resist damage from static electric discharge, always take precautions avoid high static voltages electric fields.
Warning:
Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. These stress ratings only.
Embedded Pentium® Processor
Table Absolute Maximum Ratings
Parameter
Case temperature under bias Storage temperature Supply voltage with respect Only Buffer Input Voltage Safe Buffer Input Voltage NOTES: Applies Pentium® processor inputs except PICCLK. Applies PICCLK. overshoot/undershoot transient specification.
Maximum Rating
-65° 110° -65° 150° -0.5 +4.6 -0.5 0.5; exceed VCC3 max1 -0.5 V2,3
Specifications
Tables 16-18 list specifications that apply Pentium processor. Pentium processor part internally. PICCLK inputs inputs. Since V-safe) input levels defined Table same levels, PICCLK inputs compatible with existing clock drivers.
Table Specifications
TCASE 3.135 devices TCASE (VRE device) Symbol VIL3 VIH3 VOL3 VOH3 ICC3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage 4250 3400 3250 -0.3 VCC+0.3 Unit Notes Level, Note Level, Note Level, Note Note Level, Note Note MHz, Note MHz, Note MHz, Note
Power Supply Current
NOTES: levels apply signals except PICCLK. Parameter measured Parameter measured This value should used power supply design. determined using worst-case instruction Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from stop clock full active modes. more information, refer "Decoupling Recommendations" page
Table V-Safe) Specifications
Symbol VIL5 VIH5 Parameter Input Voltage Input High Voltage -0.3 5.55 Unit Notes Level Level
Applies PICCLK only.
Embedded Pentium® Processor
Table Input Output Characteristics
Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Unit Notes Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. Guaranteed design. VCC3, This parameter input without pullup pulldown. VCC3, This parameter input without pullup pulldown. -400 This parameter input with pulldown. This parameter input with pullup.
Output Leakage Current Input Leakage Current Input Leakage Current
Specifications
specifications Pentium processor consist setup times, hold times, valid delays
3.5.1
Private
When Pentium processor operating dual processor mode, "private bus" exists arbitrate processor maintain local cache coherency. private consists pinout changes: Five pins added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#. output pins become pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#, HITM#, HLDA, SCYC. pins given specifications valid delays setup times, hold times. Simulate with these parameters their respective buffer models guarantee that proper timings met. specification gives input setup hold times signals that become pins. These setup hold times must only when dual processor present system.
3.5.2
Power Ground
clean on-chip power distribution, Pentium processor (power) (ground) inputs. Power ground connections must made external pins processor. circuit board pins must connected plane. pins must connected plane.
Embedded Pentium® Processor
3.5.3
Decoupling Recommendations
Liberal decoupling capacitance should placed near processor. Transient power surges occur when processor driving address data buses high frequencies. This most common when driving large capacitive loads. inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced minimizing length circuit board traces between processor decoupling capacitors. These capacitors should evenly distributed around each component plane. Capacitor values should chosen ensure that they eliminate both high frequency noise components. Pentium processor, power consumption transition from power level much higher level high-to-low power) very rapidly. typical example when entering exiting Stop Grant state. Other examples when executing HALT instruction (causing processor enter Auto HALT Powerdown state) when transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point which regulated power supply output reacts change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near processor plane) ensure that supply voltage stays within specified limits during changes supply current during operation.
3.5.4
Connection Specifications
pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC. Unused active high inputs should connected ground.
3.5.5
Timing Tables
specifications given Table Table consist output delays, input setup requirements input hold requirements 66-MHz external bus. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct processor operation. Each valid delay specified load. system designer should buffer models account signal flight time delays. following applies standard signals used with Pentium processor family:
input test waveforms assumed transitions with V/ns rise fall
times.
V/ns input rise/fall time V/ns.
Embedded Pentium® Processor
Table Specifications (Sheet
TCASE 3.135 devices, TCASE (VRE device), Symbol Frequency t10a t10b t11a t11b t16a t16b t18a t18b Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay BE7#-BE0#, LOCK# Valid Delay ADS# Valid Delay ADSC#, D/C#, W/R#, SCYC, Valid Delay M/IO# Valid Delay A16-A3 Valid Delay A31-A17 Valid Delay ADS#, ADSC#, A31-A3, PWT, PCD, BE7#-BE0#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM1-PM0, BP3-BP0 Valid Delay PRDY Valid Delay D63-D0, DP7-DP0 Write Data Valid Delay D63-D0, DP3-DP0 Write Data Float Delay A31-A5 Setup Time A31-A5 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time 0.15 0.15 10.0 10.0 10.0 Parameter 33.33 15.0 66.6 30.0 Unit Adjacent Clocks, Notes Note Note V-0.8 Note V-2.0 Note Figure Notes
NOTE: Table notes.
Embedded Pentium® Processor
Table Specifications (Sheet
TCASE 3.135 devices, TCASE (VRE device), Symbol t24a t24b t25a t25b t42a t42b t42d t43a t43b Parameter KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D63-D0, DP7-DP0 Read Data Setup Time D63-D0, DP7-DP0 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#, FRCMC#) Setup Time Reset Configuration Signals (INIT, FLUSH#, FRCMC#) Hold Time Reset Configuration Signals (INIT, FLUSH#, FRCMC#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, FRCMC#, BRDYC#, BUSCHK#) Hold Time, Async. Reset Configuration Signal BRDYC# Hold Time, RESET driven synchronously CPUTYP Setup Time CPUTYP Hold Time 15.0 Unit CLKs CLKs CLKs CLKs Power RESET falling edge, Note RESET falling edge, Note RESET falling edge, RESET falling edge, Note RESET falling edge, Note Figure Notes
CLKs
CLKs
NOTE: Table notes.
Embedded Pentium® Processor
Table Specifications (Sheet
TCASE 3.135 devices, TCASE (VRE device), Symbol t43c t43d Parameter APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 APIC Specifications t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD1-PICD0 Setup Time PICD1-PICD0 Hold Time PICD1-PICD0 Valid Delay (LtoH) PICD1-PICD0 Valid Delay (HtoL) PICCLK Setup Time PICCLK Hold Time PICCLK Ratio (CLK/PICCLK) 60.0 15.0 15.0 0.15 0.15 38.0 22.0 16.66 500.0 PICCLK PICCLK From PICCLK, Notes From PICCLK, Notes CLK, Note CLK, Note 40.0 13.0 20.0 25.0 20.0 25.0 62.5 25.0 25.0 16.0 Unit CLKs CLKs Note Note V-0.8 Notes 1,5,6 V-2.0 Notes 1,5,6 Asynchronous, Note Figure Notes RESET falling edge RESET falling edge
NOTE: Table notes.
Embedded Pentium® Processor
Table Dual Processor Mode Specifications
TCASE 3.135 devices, TCASE (VRE device), Symbol t80a t80b t83a t83b t83c t83d t83e Parameter PBREQ#, PBGNT#, PHIT# Flight Time PHITM# Flight Time A31-A5 Setup Time D/C#, W/R#, CACHE#, LOCK#, SCYC Setup Time ADS#, M/IO# Setup Time HIT#, HITM# Setup Time HLDA Setup Time ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, A31-A5, HLDA, HIT#, HITM#, SCYC Hold Time DPEN# Valid Time DPEN# Hold Time APIC (BE3#-BE0#) Setup Time 10.0 CLKs CLKs CLKs RESET falling edge, Note From RESET falling edge, Note Primary Processor Only Unit Figure Notes
APIC (BE3#-BE0#) Hold Time
CLKs
D/P# Valid Delay
NOTE: Table table notes.
Embedded Pentium® Processor
Table Notes Tables
100% tested. Guaranteed design/characterization. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. During probe mode operation, boundary scan timings (t55-58). FRCMC# should tied (high) ensure proper operation Pentium processor primary processor. Setup time required guarantee recognition specific clock. Pentium processor must meet this specification dual processor operation FLUSH# RESET signals. 10.Hold time required guarantee recognition specific clock. Pentium processor must meet this specification dual processor operation FLUSH# RESET signals. guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. 12.This input driven asynchronously. However, when operating processors dual processing mode, FLUSH# RESET must asserted synchronously both processors. 13.When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must deasserted (inactive) minimum clocks before being returned active. 14.Timings valid only when dual processor present. 15.Maximum time DPEN# valid from rising edge RESET. 16.Minimum time DPEN# valid after falling edge RESET. 17.The D/C#, M/IO#, W/R#, CACHE#, A31-A5 signals sampled only during which ADS# active. 18.BF CPUTYP should strapped VSS. 19.RESET synchronous dual processing mode functional redundancy checking mode. signals that have setup hold time with respect falling rising edge RESET mode should measured with respect first processor clock edge which RESET sampled either active inactive dual processing functional redundancy checking modes. 20.The PHIT# PHITM# signals operate core frequency. 21.These signals measured rising edge adjacent CLKs ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. 22.In dual processing mode, timing replaced t83a. Timing required external snooping (e.g., address setup which EADS# sampled active) both uniprocessor dual processor modes. 23.BRDYC# BUSCHK# used reset configuration signals select buffer size. 24.This assumes external pullup resistor lumped capacitive load. pullup resistor must between Ohms KOhms, capacitance must between product must between PICD1-PICD0 0.55 25.This flight time specification that includes both flight time clock skew. flight time time from when unloaded driver crosses (50% min. VCC), when receiver crosses level (50% min. VCC). Figure 26.This lock-step operation component only. This guarantees that APIC interrupts will recognized specific clocks support processors running lock step fashion, including mode. APIC pins supported mismatches these pins will result mismatch other pins CPU. 27.The PICCLK ratio lock-step operation must integer ratio (CLK/PICCLK) cannot smaller than 4:1.
Embedded Pentium® Processor
Figure Clock Waveform
Figure Valid Delay Timings
1.5V max. Signal 1.5V VALID min.
t10, t11, t12, t60i, t80a,
Figure Float Delay Timings
Embedded Pentium® Processor
Figure Setup Hold Timings
Figure Reset Configuration Timings
Embedded Pentium® Processor
Figure Test Timings
Figure Test Reset Timings
Embedded Pentium® Processor
Figure Measurement Flight Time