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Embedded Pentium® Processor

100 MHz, 133 MHz, 166 MHz

Embedded Pentium® Processor
100 MHz, 133 MHz, 166 MHz
Datasheet
Product Features
Compatible with Large Software Base - MS-DOS, Windows, OS / 2, UNIX 32-Bit Processor with 64-Bit Data Bus Superscalar Architecture - Two Pipelined Integer Units are Capable of Two Instructions / Clock - Pipelined Floating-Point Unit Separate Code and Data Caches - 8-Kbyte Code, 8-Kbyte Write-Back Data - MESI Cache Protocol Advanced Design Features - Branch Prediction - Virtual Mode Extensions 3.3 V BiCMOS Silicon Technology 4-Mbyte Pages for Increased TLB Hit Rate IEEE 1149.1 Boundary Scan Dual Processing Configuration Functional Redundancy Checking Support
Internal Error Detection Features Multiprocessor Support - Multiprocessor Instructions - Support for Second-level Cache On-Chip Local APIC Controller - Multiprocessor Interrupt Management - 8259 Compatible Power Management Features - System Management Mode - Clock Control Fractional Bus Operation - 166-MHz Core / 66-MHz Bus - 133-MHz Core / 66-MHz Bus - 100-MHz Core / 66-MHz Bus iCOMP® Index 2.0 Rating - 127 at 166 MHz - 111 at 133 MHz - 90 at 100 MHz
Contact Intel Corporation for more information about iCOMP® Index 2.0 ratings.
Order Number: 273202-001 November 1998
Datasheet
Embedded Pentium® Processor
Contents
1.0 Architecture Overview ............................................... 7
1.1 1.2 Pentium® Processor Family Architecture ............................... 8 Pentium® Processors with Voltage Reduction Technology.................10 Pentium® Processor Pinout.........................................11 2.1.1 Pin Cross Reference .......................................13 2.1.2 Design Notes.............................................15 2.1.3 Pin Quick Reference .......................................15 2.1.4 Pin Reference Tables.......................................21 2.1.5 Pin Grouping According to Function............................24 Mechanical Specifications ..........................................25 Thermal Specifications ............................................26 2.3.1 Measuring Thermal Values ..................................26 2.3.2 Thermal Equations And Data .................................27 3.3 V Power Supply...............................................29 3.3 V Inputs and Outputs...........................................29 Absolute Maximum Ratings.........................................29 DC Specifications ................................................30 AC Specifications ................................................31 3.5.1 Private Bus ...............................................31 3.5.2 Power and Ground .........................................31 3.5.3 Decoupling Recommendations ...............................32 3.5.4 Connection Specifications ...................................32 3.5.5 AC Timing Tables..........................................32
Packaging Information ..............................................11
Electrical Specifications ............................................29
Datasheet
Embedded Pentium® Processor
Figures
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Cross-Reference by Pin Name - Address and Data Pins .............. 13 Pin Cross-Reference by Pin Name - Control Pins ...................... 14 Pin Cross-Reference by Pin Name - Power, Ground and No Connect Pins .. 15 Pin Quick Reference ............................................. 16 Bus Frequency Selections ......................................... 21 Output Pins ..................................................... 21 Input Pins ...................................................... 22 Input / Output Pins ................................................ 23 Inter-processor Input / Output Pins .................................... 23 Pin Functional Grouping........................................... 24 Package Information Summary for Pentium® Processor .................. 25 SPGA Package Dimensions Key .................................... 25 Power Dissipation Requirements for Thermal Solution Design ............. 26 Thermal Resistances for Embedded Pentium® Processors................ 28 Absolute Maximum Ratings ........................................ 30 3.3 V DC Specifications ........................................... 30 3.3 V (5 V-Safe) DC Specifications ................................... 30 Input and Output Characteristics..................................... 31 AC Specifications ................................................ 33 Dual Processor Mode AC Specifications .............................. 36 Notes for Tables 19 and 20......................................... 37
Datasheet
Embedded Pentium® Processor
Revision History
Date 11 / 12 / 98 Revision 001 Description This is the first publication of this document.
Datasheet
Embedded Pentium® Processor
Architecture Overview
The Intel® embedded Pentium® processor is binary compatible with the 8086 / 88, 80286, Intel386 DX, Intel386 SX, Intel486 DX, Intel486 SX, IntelDX2TM, IntelDX4 and 60 / 66 MHz Pentium processors. The embedded Pentium processor family consists of the following products:
· Embedded Pentium processors (described in this document).
· Pentium processor with Voltage Reduction Technology (described in a separate datasheet,
Superscalar architecture Dynamic branch prediction Pipelined floating-point unit Improved instruction execution time Separate 8-Kbyte code and 8-Kbyte data caches Writeback MESI protocol in the data cache 64-Bit data bus Bus cycle pipelining Address parity Internal parity checking Functional redundancy checking Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Fractional bus operation allowing higher core frequency operation Dual processing support SL power management features On-chip local APIC device
Datasheet
Embedded Pentium® Processor
Pentium® Processor Family Architecture
Datasheet
Embedded Pentium® Processor
System Management Mode (SMM) has been implemented along with some extensions to the SMM architecture. Enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. Figure 1 is a block diagram of the embedded Pentium processor. Figure 1. Embedded Pentium® Processor Block Diagram
Control
DP Logic
Branch Prefetch Target Buffer Address
TLB Code Cache 8 Kbytes
Instruction Pointer 64-Bit Data Bus Branch Verification and Target Address
Prefetch Buffers Instruction Decode
Control ROM
Control Unit
32-Bit Address Bus
Bus Unit
Page Unit
Address Address Generate Generate (U Pipeline) (V Pipeline)
Floating Point Unit
Control Integer Register File ALU ALU (U Pipline) (V Pipline)
64-Bit 64 Data Bus
Control Register File Add Divide 80 Multiply 32 32 80 32 32
Barrel Shifter
32 32-Bit Addr. Bus
Data APIC Control
Data Cache 8 Kbytes TLB
A6053-01
The block diagram shows the two instruction pipelines, the "u" pipe and the "v" pipe. The u-pipe can execute all integer and floating-point instructions. The v-pipe can execute simple integer instructions and the FXCH floating-point instructions. The separate code and data caches are shown in the block diagram. The data cache has two ports, one for each of the two pipes (the tags are triple-ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache. The code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units. Instructions are fetched from the code cache or from the external bus. Branch addresses are remembered by the branch target buffer. The code cache TLB translates linear addresses to physical addresses used by the code cache.
Datasheet
Embedded Pentium® Processor
Pentium® Processors with Voltage Reduction Technology
The Embedded Pentium processor with Voltage Reduction Technology is described in the Embedded Pentium® Processor with Voltage Reduction Technology datasheet (order number 273203).
Datasheet
Embedded Pentium® Processor
Packaging Information
Pentium® Processor Pinout
Figure 2. Pentium® Processor SPGA Package Pinout (Top Side View)
37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W V U T S R Q P N M L K J H G F E D C B A NC D9 D11 VCC DP0 D10 VSS VCC D4 D6 D8 VCC VCC VSS VCC VSS VCC VSS VCC VCC VCC VCC VSS VCC VSS VSS A22 VCC VSS A24 A21 D / P# A23 VSS A28 A25 A26 A27 VSS A30 A3 A29 A31 NC A4 A7 A5 A6 A8 A11 A9 A10 VCC VSS A12 A13 VCC VSS A14 A15 VCC VSS A16 A17 VCC VSS A18 A19 VCC VSS A20 VCC VSS NC VCC VSS VCC VSS VCC VSS VCC VSS 8 7 6 5 4 3 INC 2 1 INC AN AM AL AK AJ AH AG AF AE AD AC AB AA Z VCC Y X W V VCC U T S R VCC Q P VCC VSS VCC VSS VCC VSS VCC DP6 D54 D50 INC INC INC 4 3 2 1 N M L K J H G F E D C B A
VCC FLUSH# INC VSS VSS
W / R# EADS# ADSC# INC AP BREQ VSS
SCYC BE6# BE7#
BE4# BE2# BE3#
BE0# BUSCHK# HITM# PWT D / C# HLDA
RESET CLK
BE1# A20M# HIT#
LOCK#
PCD SMIACT# VCC PCHK# VSS
APCHK# PBREQ# VCC PBGNT# VSS VCC
INTR R / S# NMI
PRDY PHITM# HOLD VSS
IGNNE# INIT VSS PEN#
WB / WT# PHIT#
FRCMC# BF0 VSS NC BF1 NC
View of Component as Mounted on Board (Pins Down)
BOFF#
NA# BRDYC# BRDY# VSS
KEN# EWBE# AHOLD VSS
VSS STPCLK# VSS VCC NC NC NC VCC
INV CACHE# MI / O# BP3 BP2 VSS
VSS VCC
PM1BP1
VCC CPUTYP TRST# VSS TMS TDI TDO
FERR# PM0BP0 IERR# DP7 D63 D62 D60 D61 D59 D58 D57 D56 D53 DP5 D55 D51 D52 D48 D47 VSS
TCK VCC
PICD1 VSS D2 D0
PICD0
PICCLK D1 D5 D7 D12 D14 DP1 D19 D23 D26 D28 D30 DP3 D33 D35 D37 D42 D39 D46 D40 D3
D49 D44
D24 VSS
DP2 VSS VCC
D25 VSS VCC
D27 VSS VCC
D29 VSS VCC
D31 VSS VCC
D32 VSS VCC
D34 VSS
D36 VSS
D38 VSS VCC
DP4 VSS VCC
D45 VSS
D13 D15
D20 VCC
A5498-01
Datasheet
Embedded Pentium® Processor
Figure 3. Pentium® Processor SPGA Package Pinout (Pin Side View)
1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Z Y X W V U T S R Q P N M L K J H G F E D C B A 1 2 INC INC INC 3 4 VCC DP6 D54 D50 D47 VCC VSS VCC VSS VCC VSS VCC VCC INC 2 3 INC 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VCC VSS VCC VSS VCC VCC VSS VSS VCC VCC VSS NC VSS A20 A19 VCC VSS A18 A17 VCC VCC VCC VSS A14 A15 A13 VCC VSS A12 A9 A10 VSS A11 A5 A31 A8 A7 A29 A25 A26 A27 A21 A23 D / P# VSS VCC VSS VCC A24 VSS VCC A22 VCC A6 A4 A3 A28 VSS NC A30 VSS VSS AN AM AL AK AJ AH AG AF AE AD AC AB AA Z VCC Y X W V U T S R VCC Q P N M VCC L K J H G F VCC DP0 D10 D11 NC D9 E D C B A
INC FLUSH# VSS
ADSC# EADS# W / R# INC AP
VSS A16
PWT HITM# BUSCHK# BE0# D / C#
BE2# BE4# BE3#
BE6# SCYC
HIT# A20M# BE1#
BE5# BE7#
CLK RESET
BREQ HLDA ADS# VSS LOCK#
VCC SMIACT# PCD VSS PCHK#
VCC PBREQ# APCHK# VSS PBGNT# VCC PHITM# PRDY VSS HOLD
INTR NMI R / S#
PHIT# WB / WT# VSS BOFF#
INIT IGNNE# PEN#
VCC BRDYC# NA# VSS BRDY#
BF0 FRCMC# BF1 VSS NC
VCC EWBE# KEN# VSS AHOLD VCC CACHE# INV VSS MI / O# BP3
Pin Side View
STPCLK# VSS VCC VSS VCC VSS VCC VSS
VCC NC NC NC
VSS PM1BP1 VCC PM0BP0 FERR# VSS IERR# D63 DP7
TRST# CPUTYP TMS TDO TDI
VSS VCC VSS
D62 D61 D60
VCC PICD1 D0 PICD0 D2 VSS
D59 D57 D58
VCC VSS VCC D4
D56 D55 D53 DP5 D46 D40 D38 VSS VCC D42 D39 D37 D36 VSS D35 D33 DP3 D30 D27 VSS VCC D28 D26 D23 D19 DP1 D12
PICCLK D3 D5 D7 D8 D6 D1
D51 D52 D49
DP4 VSS VCC
D34 VSS
D32 VSS VCC
D31 VSS VCC
D29 VSS VCC
D25 VSS VCC
DP2 VSS VCC
D24 VSS VCC
D21 VSS
D43 D41 5
D20 VCC
D13 D15
A5499-01
Datasheet
Embedded Pentium® Processor
Table 1.
Pin Cross Reference
Pin Cross-Reference by Pin Name - Address and Data Pins
Pin Location Pin Location Pin Location Pin Location Pin Location
Address A3 A4 A5 A6 A7 A8 AL35 AM34 AK32 AN33 AL33 AM32 A9 A10 A11 A12 A13 A14 AK30 AN31 AL31 AL29 AK28 AL27 A15 A16 A17 A18 A19 A20 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C09 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D10 D08 A05 E09 B04 D06 C05 E07 C03 D04 E05 D02 F04 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03 AK26 AL25 AK24 AL23 AK22 AL21 A21 A22 A23 A24 A25 A26 AF34 AH36 AE33 AG35 AJ35 AH34 A27 A28 A29 A30 A31 AG33 AK36 AK34 AM36 AJ33
Datasheet
Embedded Pentium® Processor
Table 2.
Pin Cross-Reference by Pin Name - Control Pins
Pin Location Pin Location Pin Location Pin Location
A20M# ADS# ADSC# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY#
AK08 AJ05 AM02 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 S05 X04
BRDYC# BREQ BUSCHK# CACHE# CPUTYP D / C# D / P# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR#
Y03 AJ01 AL07 U03 Q35 AK04 AE35 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05 APIC
FLUSH# FRCMC# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK#
AN07 Y35 AK06 AL05 AJ03 AB04 P04 AA35 AA33 AD34 U05 W05 AH04 T04 Y05 AC33 AG05 AF04
PEN# PM0 / BP0 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT#
Z34 Q03 R04 AC05 AL03 AC35 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 AM06 AA05
PICCLK
PICD0 / DPEN#
PICD1 / APICEN
Clock Control CLK AK18 BF0 Y33 BF1 X34 STPCLK# V34
Dual Processor Private Interface PBGNT# AD04 PBREQ# AE03 PHIT# AA03 PHITM# AC03
Datasheet
Embedded Pentium® Processor
Table 3.
Pin Cross-Reference by Pin Name - Power, Ground and No Connect Pins
A07 A09 A11 A13 A15 A17
A19 A21 A23 A25 A27 A29
E37 G01 G37 J01 J37 L01
L33 L37 N01 N37 Q01 Q37
S01 S37 T34 U01 U33 U37 VSS
W01 W37 Y01 Y37 AA01 AA37
AC01 AC37 AE01 AE37 AG01 AG37
AN09 AN11 AN13 AN15 AN17 AN19
AN21 AN23 AN25 AN27 AN29
B06 B08 B10 B12 B14 B16
B18 B20 B22 B24 B26 B28
H02 H36 K02 K36 M02 M36
P02 P36 R02 R36 T02 T36
U35 V02 V36 X02 X36 Z02 NC / INC
Z36 AB02 AB36 AD02 AD36 AF02
AF36 AH02 AJ37 AL37 AM08 AM10
AM12 AM14 AM16 AM18 AM20 AM22
AM24 AM26 AM28 AM30 AN37
B02 C01
R34 S33
S35 W33
W35 AL01
AL19 AN01
AN03 AN05
These pins should be left unconnected. Connection of these pins may result in component failure or incompatibility with processor steppings.
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC. Unused active high inputs should be connected to GND. No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Pin Quick Reference
· ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#, M / IO#, D / C#, W / R#, SCYC
Datasheet
Embedded Pentium® Processor
Table 4.
Pin Quick Reference (Sheet 1 of 5)
A20M#
APCHK#
APICEN PICD1
BE7#-BE5# BE4#-BE0#
BOFF#
BP3-BP2 PM1 / BP1- PM0 / BP0
Datasheet
Embedded Pentium® Processor
Table 4.
Pin Quick Reference (Sheet 2 of 5)
BRDY#
BRDYC#
CACHE#
D63-D0
Datasheet
Embedded Pentium® Processor
Table 4.
Pin Quick Reference (Sheet 3 of 5)
DP7-DP0
DPEN# PICD0
EADS#
EWBE#
FERR#
FRCMC#
HITM#
Datasheet
Embedded Pentium® Processor
Table 4.
Pin Quick Reference (Sheet 4 of 5)
IERR#
LOCK#
NMI / LINT1
PBREQ#
PCHK#
Datasheet
Embedded Pentium® Processor
Table 4.
Pin Quick Reference (Sheet 5 of 5)
PHITM#
PICCLK PICD1 / DPEN#- PICD0 / APICEN
PRDY SMIACT#
STPCLK#
TDO TMS TRST# VCC VSS W / R#
Datasheet
Embedded Pentium® Processor
Table 5.
Bus Frequency Selections
Pentium® Processor Core Frequency (max) 166 MHz 133 MHz 100 MHz External Bus Frequency (max) 66 MHz 66 MHz 66 MHz Bus / Core Ratio 2 / 5 1 / 2 2 / 3 BF1 0 1 1 BF0 0 0 1
Table 6.
Pin Reference Tables
Output Pins
Name ADS#2 ADSC# APCHK# BE7#-BE5# BREQ CACHE#2 D / P#3 FERR#3 HIT#2 HITM#2 HLDA2 IERR# LOCK#2 M / IO#2, D / C#2, W / R#2 PCHK# BP3-BP2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC2 SMIACT# TDO Active Level1 Low Low Low Low High Low n / a Low Low Low High Low Low n / a Low High High High High Low n / a All states except Shift-DR and Shift-IR Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated Bus Hold, BOFF# Bus Hold, BOFF#
NOTES: 1. All output and input / output pins are floated during three-state test mode and checker mode (except IERR#). 2. These are I / O signals when two Pentium processors are operating in dual processing mode. 3. These signals are undefined when the processor is configured as a dual processor.
Datasheet
Embedded Pentium® Processor
Table 7.
Input Pins
Name A20M# AHOLD BF1-BF0 BOFF# BRDY# BRDYC# BUSCHK# CLK CPUTYP EADS# EWBE# FLUSH# FRCMC# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# PICCLK R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT#
Active Level Low High High Low Low Low Low n / a High Low Low Low Low High Low High High High Low Low High Low High n / a High Low Low n / a n / a n / a Low n / a
Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous Synchronous Synchronous Synchronous
Internal Resistor
Qualified
Pullup
Bus State T2, T12, T2P Pullup Pullup Bus State T2, T12, T2P BRDY#
Synchronous / RESET Synchronous Synchronous Asynchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Pullup Pullup Pullup First BRDY# / NA# TCK TCK Pullup Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY#
Undefined when the processor is configured as a dual processor.
Datasheet
Embedded Pentium® Processor
Table 8.
Input / Output Pins
Name A31-A3 AP BE4#-BE0# D63-D0 DP7-DP0 PICD0DPEN# PICD1APICEN Active Level n / a n / a Low n / a n / a When Floated1 Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown2 Internal Resistor
NOTES: 1. All output and input / output pins are floated during three-state test mode (except TDO) and checker mode (except IERR# and TDO). 2. BE3#-BE0# have pulldowns during RESET only.
Table 9.
Inter-processor Input / Output Pins
Name PHIT# PHITM# PBGNT# PBREQ# Active Level Low Low Low Low Internal Resistor Pullup Pullup Pullup Pullup
For proper interprocessor operation, the system cannot load these signals.
Datasheet
Embedded Pentium® Processor
Pin Grouping According to Function
Table 10. Pin Functional Grouping
Function Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Dual Processing Private Bus Control Interrupts Floating-point Error Reporting System Management Mode Functional Redundancy Checking TAP Port Breakpoint / Performance Monitoring Power Management Miscellaneous Dual Processing Probe Mode Pins CLK RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD1-PICD0 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, NMI FERR#, IGNNE# SMI#, SMIACT# FRCMC# (IERR#) TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-BP2 STPCLK# CPUTYP, D / P# R / S#, PRDY
Datasheet
Embedded Pentium® Processor
Mechanical Specifications
The embedded Pentium processor is packaged in a 296-pin ceramic staggered pin grid array (SPGA) package. The pins are arranged in a 37 x 37 matrix and the package dimensions are 1.95" x 1.95" (Table 11). Figure 4 and Table 12 show the package dimensions.
Table 11. Package Information Summary for Pentium® Processor
Package Type Ceramic Staggered Pin Grid Array SPGA Total Pins 296 Pin Array 37 x 37 Package Size 1.95" x 1.95" 4.95 cm x 4.95 cm
Figure 4. SPGA Package Dimensions
D D1 S1 01.65 Ref. L Seating Plane
2.29 Ref. 1.52 45° Chamfer (index corner)
Pin C3
Table 12. SPGA Package Dimensions Key
Millimeters Symbol Min A A1 A2 B D D1 e1 L N S1 1.52 2.62 0.69 3.31 0.43 49.28 45.59 2.29 3.05 296 2.54 Max 2.97 0.84 3.81 0.51 49.78 45.85 2.79 3.30 Lead Count 0.060 Metal Lid Metal Lid Notes Min 0.103 0.027 0.130 0.017 1.940 1.795 0.090 0.120 296 0.100 Max 0.117 0.033 0.150 0.020 1.960 1.805 0.110 0.130 Lead Count Metal Lid Metal Lid Notes Inches
Datasheet
Embedded Pentium® Processor
Thermal Specifications
The Pentium processor is specified for proper operation when case temperature, TCASE (TC), is within the specified range of 0° C to 70° C. The power dissipation specification in Table 13 is provided for designing thermal solutions for operation at a sustained maximum level. This is the worst-case power the device would dissipate in a system. This number is used for design of a thermal solution for the device.
Table 13. Power Dissipation Requirements for Thermal Solution Design
Watts Watts
Measuring Thermal Values
To verify that the proper TC (case temperature) is maintained, it should be measured at the center of the package top surface (opposite of the pins). The measurement is made in the same way with or without a heatsink attached. When a heatsink is attached, a hole (0.150" diameter or smaller) should be drilled through the heatsink to allow a probe to touch the center of the package. See Figure 5 for an illustration of how to measure TC. To minimize the measurement errors, use the following approach:
· Use 36-gauge or finer diameter K, T, or J type thermocouples. · Attach the thermocouple bead or junction to the center of the package top surface using high
thermal conductivity cements.
· Attach the thermocouple at a 90-degree angle as shown in Figure 5. · The hole size should be 0.150" or less in diameter.
Datasheet
Embedded Pentium® Processor
Figure 5. Technique for Measuring Case Temperature (TC)
Thermal Equations And Data
Table 14 lists the CA values for the Pentium processor with passive heatsinks. Thermal data collection parameters:
Heatsinks are omnidirectional pin aluminum alloy Features were based on standard extrusion practices for a given height Pin size ranged from 50 to 129 mils Pin spacing ranged from 93 to 175 mils Base thickness ranged from 79 to 200 mils Heatsink attach was 0.005" of thermal grease Using an attach thickness of 0.002" improves performance by approximately 0.3 °C / W
Datasheet
Embedded Pentium® Processor
Table 14. Thermal Resistances for Embedded Pentium® Processors
Heatsink Height in Inches 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Without Heatsink JC (°C / Watt) 0 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.7 9.4 9.1 8.7 8.4 8.0 7.3 6.6 6.2 5.7 14.5 CA(°C / Watt) vs. Laminar Airflow (Linear ft / min) 100 8.3 7.8 7.3 6.8 6.3 5.6 4.9 4.6 4.2 13.8 200 6.9 6.3 5.6 5.0 4.6 4.2 3.9 3.6 3.3 12.6 400 4.7 4.3 3.9 3.5 3.3 2.9 2.9 2.7 2.5 10.5 600 3.9 3.6 3.2 2.9 2.7 2.5 2.4 2.3 2.2 8.6 800 3.3 3.1 2.8 2.6 2.4 2.3 2.1 2.1 2.0 7.5
Datasheet
Embedded Pentium® Processor
Electrical Specifications
This section describes the DC and AC specifications for the embedded Pentium processor.
3.3 V Power Supply
The processor has all VCC 3.3-V inputs. The CLK and PICCLK inputs can tolerate a 5-V input signal. This allows the processor to use 5-V or 3.3-V clock drivers.
3.3 V Inputs and Outputs
Absolute Maximum Ratings
Functional operating conditions are given in the AC and DC specification tables. Functional operation at the maximums is not implied or guaranteed. Extended operation beyond the maximum ratings may affect device reliability. Furthermore, although the Pentium processor contains protective circuitry to resist damage from static electric discharge, always take precautions to avoid high static voltages or electric fields.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only.
Datasheet
Embedded Pentium® Processor
Table 15. Absolute Maximum Ratings
Parameter
Case temperature under bias Storage temperature 3 V Supply voltage with respect to VSS 3 V Only Buffer DC Input Voltage 5 V Safe Buffer DC Input Voltage NOTES: 1. Applies to all Pentium® processor inputs except CLK and PICCLK. 2. Applies to CLK and PICCLK. 3. See overshoot / undershoot transient specification.
Maximum Rating
-65° C to 110° C -65° C to 150° C -0.5 V to +4.6 V -0.5 V to VCC + 0.5 not to exceed VCC3 max1 -0.5 V to 6.5 V2, 3
DC Specifications
Tables 16-18 list the DC specifications that apply to the Pentium processor. The Pentium processor is a 3.3 V part internally. The CLK and PICCLK inputs may be 3.3 V or 5 V inputs. Since the 3.3 V (5 V-safe) input levels defined in Table 16 are the same as the 5 V TTL levels, the CLK and PICCLK inputs are compatible with existing 5 V clock drivers.
Table 16. 3.3 V DC Specifications
Power Supply Current
Table 17. 3.3 V (5 V-Safe) DC Specifications
Symbol VIL5 VIH5 Parameter Input Low Voltage Input High Voltage Min -0.3 2.0 Max 0.8 5.55 Unit V V Notes TTL Level TTL Level
Applies to CLK and PICCLK only.
Datasheet
Embedded Pentium® Processor
Table 18. Input and Output Characteristics
ILO IIH IIL
Output Leakage Current Input Leakage Current Input Leakage Current
AC Specifications
The AC specifications of the Pentium processor consist of setup times, hold times, and valid delays at 0 pF.
Private Bus
When two Pentium processor are operating in dual processor mode, a "private bus" exists to arbitrate for the processor bus and maintain local cache coherency. The private bus consists of two pinout changes: 1. Five pins are added: PBREQ#, PBGNT#, PHIT#, PHITM#, D / P#. 2. Ten output pins become I / O pins: ADS#, D / C#, W / R#, M / IO#, CACHE#, LOCK#, HIT#, HITM#, HLDA, SCYC. The new pins are given AC specifications of valid delays at 0 pF, setup times, and hold times. Simulate with these parameters and their respective I / O buffer models to guarantee that proper timings are met. The AC specification gives input setup and hold times for the ten signals that become I / O pins. These setup and hold times must only be met when a dual processor is present in the system.
Power and Ground
For clean on-chip power distribution, the Pentium processor has 53 VCC (power) and 53 VSS (ground) inputs. Power and ground connections must be made to all external VCC and VSS pins of the processor. On the circuit board all VCC pins must be connected to a VCC plane. All VSS pins must be connected to a VSS plane.
Datasheet
Embedded Pentium® Processor
Decoupling Recommendations
Liberal decoupling capacitance should be placed near the processor. Transient power surges can occur when the processor is driving its address and data buses at high frequencies. This is most common when driving large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by minimizing the length of the circuit board traces between the processor and the decoupling capacitors. These capacitors should be evenly distributed around each component on the 3.3 V plane. Capacitor values should be chosen to ensure that they eliminate both low and high frequency noise components. For the Pentium processor, the power consumption can transition from a low power level to a much higher level (or high-to-low power) very rapidly. A typical example is when entering or exiting the Stop Grant state. Other examples are when executing a HALT instruction (causing the processor to enter the Auto HALT Powerdown state) or when transitioning from HALT to the Normal state. All these examples may cause abrupt changes in the power being consumed by the processor. Note that the Auto HALT Powerdown feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low ESR (Effective Series Resistance) in the 10 to 100 µF range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point at which the regulated power supply output reacts to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel. These capacitors should be placed near the processor (on the 3.3 V plane) to ensure that the supply voltage stays within specified limits during changes in the supply current during operation.
Connection Specifications
All NC and INC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC. Unused active high inputs should be connected to ground.
AC Timing Tables
The AC specifications given in Table 19 and Table 20 consist of output delays, input setup requirements and input hold requirements for a 66-MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5 V for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct processor operation. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer models to account for signal flight time delays. The following applies to all standard TTL signals used with the Pentium processor family:
· TTL input test waveforms are assumed to be 0 to 3 V transitions with 1 V / ns rise and fall
times.
· 0.3 V / ns input rise / fall time 5 V / ns.
Datasheet
Embedded Pentium® Processor
Table 19. AC Specifications (Sheet 1 of 3)
NOTE: See Table 21 for notes.
Datasheet
Embedded Pentium® Processor
Table 19. AC Specifications (Sheet 2 of 3)
ns ms CLKs
NOTE: See Table 21 for notes.
Datasheet
Embedded Pentium® Processor
Table 19. AC Specifications (Sheet 3 of 3)
NOTE: See Table 21 for notes.
Datasheet
Embedded Pentium® Processor
Table 20. Dual Processor Mode AC Specifications
APIC ID (BE3#-BE0#) Hold Time
D / P# Valid Delay
NOTE: See Table 21 for table notes.
Datasheet
Embedded Pentium® Processor
Table 21. Notes for Tables 19 and 20
Datasheet
Embedded Pentium® Processor
Figure 6. Clock Waveform
Figure 7. Valid Delay Timings
1.5V Tx max. Signal 1.5V VALID Tx min.
Figure 8. Float Delay Timings
Datasheet
Embedded Pentium® Processor
Figure 9. Setup and Hold Timings
Figure 10. Reset and Configuration Timings
Datasheet
Embedded Pentium® Processor
Figure 11. Test Timings
Figure 12. Test Reset Timings
Datasheet
Embedded Pentium® Processor
Datasheet