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Extended Temperature Pentium® Processor with MMXTechnology
Advance Information Datasheet
Support MMXTechnology Low-Power 0.25 Micron Process Technology Core Supply HLPBGA Interface 32-Bit with 64-Bit Data Fractional Operation 166-MHz Core/66-MHz Superscalar Architecture Enhanced Pipelines Pipelined Integer Units Capable Instructions/Clock Pipelined Technology Pipelined Floating-Point Unit
Separate Code Data Caches 16-Kbyte Code, 16-Kbyte Write-Back Data MESI Cache Protocol Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 4-Mbyte Pages Increased Rate IEEE 1149.1 Boundary Scan Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions Internal Error Detection Features On-Chip Local APIC Controller Power Management Features System Management Mode Clock Control 352-ball HL-PBGA
Notice: This document contains information products sampling initial production phases development. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 273232-001 February, 1999
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Extended Temperature Pentium® Processor with MMXTechnology contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999 *Third-party brands names property their respective owners.
Extended Temperature Pentium® Processor with MMXTechnology
Contents
Introduction. Processor Features Pentium® Processor Family Architecture Pentium® Processor with MMXTechnology 2.2.1 Full Support Intel MMXTechnology 2.2.2 16-Kbyte Code Data Caches.12 2.2.3 Improved Branch Prediction 2.2.4 Enhanced Pipeline 2.2.5 Deeper Write Buffers.12 0.25 Micron Technology Architecture Overview
Extended Temperature Pentium® Processor with MMXTechnology Packaging Information 3.10 3.11 Differences from Desktop Processors.13 HL-PBGA Pinout Descriptions Design Notes.18 Quick Reference Fraction (BF) Selection CPUID Instruction Boundary Scan Chain List.27 Reference Tables.28 Grouping According Function.30 Mechanical Specifications 3.10.1 HL-PBGA Package Mechanical Diagrams Thermal Specifications 3.11.1 Measuring Thermal Values 3.11.2 Thermal Equations Data.32 3.11.3 Airflow Calculations Maximum Typical Power.33 3.11.4 HL-PBGA Package Thermal Resistance Information.34
Extended Temperature Pentium® Processor with MMXTechnology Electrical Specifications Absolute Maximum Ratings.35 Specifications 4.2.1 Power Sequencing Specifications 4.3.1 Power Ground 4.3.2 Decoupling Recommendations 4.3.3 Connection Specifications 4.3.4 Timings.39 Buffer Models 4.4.1 Buffer Model Parameters Signal Quality Specifications 4.5.1 Overshoot.49
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Extended Temperature Pentium® Processor with MMXTechnology Errata Information Nomenclature. Summary Table Changes 5.2.1 Codes Used Summary Table 5.2.2 Documentation Changes.
10.0
Extended Temperature Pentium® Processor with MMXTechnology Specification Changes. Extended Temperature Pentium® Processor with MMXTechnology Errata Extended Temperature Pentium® Processor with MMXTechnology Specification Clarifications. Extended Temperature Pentium® Processor with MMXTechnology Documentation Changes. Pentium® Processor Related Technical Collateral
Figures
Pentium® Processor with MMXTechnology Block Diagram. HL-PBGA Package Side View HL-PBGA Package Side View Assignments CPUID. Assignments CPUID. HL-PBGA Package Dimensions. Technique Measuring Thermal Resistance Airflow HL-PBGA Package. Clock Waveform. Valid Delay Timings Float Delay Timings Setup Hold Timings. Reset Configuration Timings. Test Timings. Test Reset Timings First Order Input Buffer Model. First Order Output Buffer Model. Pending Cycle Timing Diagram Snoop Writeback Cycle Timing Diagram
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Tables
Signals Removed from Extended Temperature Pentium® Processor with MMXTechnology Cross Reference Name Connect, Power Supply Ground Cross Reference Quick Reference Frequency Selection Assignment Definitions CPUID.26 Output Pins.28 Input Pins Input/Output Pins.30 Functional Grouping.30 HL-PBGA Package Dimensions.31 Thermal Resistances HL-PBGA Packages.34 Absolute Maximum Ratings.35 TCASE Specifications.36 Specifications Specifications Power Dissipation Requirements Thermal Design.37 Input Output Characteristics.37 Extended Temperature Specifications APIC Specifications.43 Notes Tables 20.43 Parameters Used Specification First Order Input Buffer Model.47 Parameters Used Specification First Order Output Buffer Model.48 Signal Buffer Type.48 Preliminary Input, Output Bidirectional Buffer Model Parameters HL-PBGA Package.49 Input Buffer Model Parameters: (Diodes) Overshoot Specification Summary Specification Changes.53 Errata.53 Specification Clarifications Documentation Changes.55 Pentium® Processor Related Technical Collateral
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Introduction
Extended Temperature Pentium® Processor with MMXTechnology extends Pentium processor family, providing additional performance extended temperature applications. Furthermore, Extended Temperature Pentium processor with technology superscalar architecture which execute instructions clock cycle, enhanced branch prediction separate caches also increase performance. pipelined floating-point unit delivers workstation level performance. Separate code data caches reduce cache conflicts while remaining software transparent. Extended Temperature Pentium processor with technology million transistors, built Intel's 0.25 micron manufacturing process technology full Enhanced power management features including System Management Mode (SMM) clock control. Extended Temperature Pentium processor with technology available 352-ball HighThermal Low-Profile-Plastic Ball Grid Array (HL-PBGA). HL-PBGA package allows designers surface mount technology create small form-factor designs. additional Enhanced features extended temperature HL-PBGA package make Extended Temperature Pentium processor with technology ideal automotive multimedia designs.
Processor Features
Extended Temperature Pentium processor with technology advanced architectural internal features desktop version Pentium processor with technology, except that several features have been eliminated. differences specified "Differences from Desktop Processors" page Extended Temperature Pentium processor with technology several features which allow automotive multimedia designs. These features include following:
core buffer VCC3 inputs reduce power consumption Enhanced feature
This document should used conjunction with Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Architecture Overview
Extended Temperature Pentium processor with technology extends family Pentium processors with technology. binary compatible with 8086/88, 80286, Intel386DX, Intel386 Intel486SX, IntelDX2TM, IntelDX4TM, Pentium processors with voltage reduction technology (75-150 MHz). Extended Temperature Pentium processor with technology contains features previous Intel architecture processors provides significant enhancements additions, including following:
Support MMXTechnology Superscalar Architecture Enhanced Branch Prediction Algorithm Pipelined Floating-Point Unit Improved Instruction Execution Time Separate 16-Kbyte Code Cache 16-Kbyte Data Cache Writeback MESI Protocol Data Cache 64-Bit Data Enhanced Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions 0.25 Micron Process Technology Power Management Features Pool Four Write Buffers Used Both Pipes
Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 family instruction with extensions accommodate some additional functionality Pentium processors. application software written Intel386 Intel486 family microprocessors will Pentium processors without modification. on-chip memory management unit (MMU) completely compatible with Intel386 Intel486 families processors.
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit Pentium processors capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, Pentium processors implement prefetch buffers, that prefetches code linear fashion, that prefetches code according Branch Target Buffer (BTB) that code almost always prefetched before needed execution. floating-point unit been completely redesigned over Intel486 processor. Faster algorithms provide speed-up common operations including add, multiply, load. Pentium processors include separate code data caches integrated on-chip meet performance goals. Each cache 32-byte line size 4-way associative. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable writeback writethrough line-by-line basis follows MESI protocol. data cache tags triple ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags also triple ported support snooping split line accesses. Individual pages configured cacheable non-cacheable software hardware. caches enabled disabled software hardware. Pentium processors have increased data bits improve data transfer rate. Burst read burst writeback cycles supported Pentium processors. addition, cycle pipelining been added allow cycles progress simultaneously. Pentium processors' contains optional extensions architecture that allow 4-Kbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. more more functions integrated on-chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors have specified four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor. Figure shows block diagram Pentium processor with technology. block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions.
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
separate code data caches shown. data cache ports, each pipes (the tags triple ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. Figure Pentium® Processor with MMXTechnology Block Diagram
Branch Prefetch Target Buffer Address
Code Cache Kbytes
Instruction Pointer Branch Verif. Target Addr.
Prefetch Buffers Instruction Decode Control
64-Bit Data 32-Bit Address
Control Unit Page Unit Unit
Pipeline Connection Pipeline Connection
Floating-Point Unit Control
Control
Address Generate
Address Generate
MMXTechnology Unit
Register File Divide Multiply
Pipeline) Pipeline)
Integer Register File
Pipeline) Barrel Shifter 64-Bit Data Data Control 32-Bit Address
Pipeline)
Data Cache Kbytes
APIC
A5920-01
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
code cache, branch target buffer prefetch buffers responsible getting instructions into execution units Pentium processor. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache. decode unit decodes prefetched instructions Pentium processor execute instruction. control contains microcode which controls sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processor contains pipelined floating-point unit that provides significant floatingpoint performance advantage over previous generations processors. addition features described above, Pentium processor supports clock control. When clock processor stopped, power dissipation virtually eliminated. combination these improvements makes Pentium processor good choice low-power designs. Pentium processor supports fractional operation. This allows internal processor core operate high frequencies, while communicating with external lower frequencies. Extended Temperature Pentium processor with technology contains on-chip advanced programmable interrupt controller (APIC). This function reserved future multiprocessing function. architectural features introduced this section more fully described Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Pentium® Processor with MMXTechnology
Pentium processor with technology high-performance extended temperature designs significant addition Pentium processor family. Available MHz, first extended temperature microprocessor support Intel technology. Pentium processor with technology both software compatible with previous members Pentium processor family. contains million transistors manufactured 0.25 micron CMOS process, which allows voltage reduction technology power high density. addition architecture described previous section Pentium processor family, Pentium processor with technology several additional micro-architectural enhancements, which described next section.
2.2.1
Full Support Intel MMXTechnology
technology based SIMD technique (Single Instruction, Multiple Data) which enables increased performance wide variety multimedia communications applications. Fifty-seven instructions four 64-bit data types supported Pentium processor with technology. existing operating system application software fullycompatible.
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
2.2.2
16-Kbyte Code Data Caches
On-chip level-1 data code cache sizes Kbytes each 4-way associative Pentium processor with technology. Large separate internal caches improve performance reducing average memory access time providing fast access recently-used instructions data. instruction data caches accessed simultaneously while data cache supports data references simultaneously. data cache supports write-back alternatively, writethrough, line-by-line basis) policy memory updates.
2.2.3
Improved Branch Prediction
Dynamic branch prediction uses Branch Target Buffer (BTB) boost performance predicting most likely instructions executed. been improved Pentium processor with technology increase accuracy. This processor four prefetch buffers that hold four successive code streams.
2.2.4
Enhanced Pipeline
additional pipeline stage been added pipeline been enhanced improve performance. integration technology pipeline with integer pipeline very similar that floating-point pipeline. Under some circumstances, instructions integer instruction paired issued clock cycle increase throughput. enhanced pipeline described more detail Embedded Pentium® Processor Family Developer's Manual (order number 273204).
2.2.5
Deeper Write Buffers
pool four write buffers shared between dual pipelines improve memory write performance.
0.25 Micron Technology
0.25 micron technology state-of-the-art CMOS manufacturing process Intel unveiled April 1997, enabling lower core supply sub-2 result, Extended Temperature Pentium processor with technology consumes significantly less power even higher speeds.
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Extended Temperature Pentium® Processor with MMXTechnology Packaging Information
Differences from Desktop Processors
following features have been eliminated Extended Temperature Pentium processor with technology: Upgrade, Dual Processing (DP), Master/Checker functional redundancy. Table lists corresponding pins that exist Pentium processor with technology have been removed Extended Temperature Pentium processor with technology.
Table
Signals Removed from Extended Temperature Pentium® Processor with MMXTechnology
Signal ADSC# Function Additional Address Status. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Additional Burst Ready. This signal mainly used large standalone cache memory subsystem support required high-performance desktop server models. Type. This signal used dual processing systems. Dual/Primary processor identification. This signal only used upgrade processor. Functional Redundancy Checking. This signal only used error detection processor redundancy requires Pentium processors (master/checker). Private Grant. This signal only used dual processing systems. Private Request. This signal used only dual processing systems. Private Hit. This signal only used dual processing systems. Private Modified Hit. This signal only used dual processing systems.
BRDYC# CPUTYP D/P# FRCMC# PBGNT# PBREQ# PHIT# PHITM#
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
HL-PBGA Pinout Descriptions
Figure HL-PBGA Package Side View
LOCK#
HOLD
BOFF# KEN# AHOLD M/IO# PM1/BP1 IERR# WB/WT# EWBE# PM0/BP0 VCC2 BRDY# VCC2 CACHE# FERR#
APCHK# PRDY
SMIACT#
VCC3
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
HLDA
BREQ PCHK# VCC2 VCC3 VCC2 VCC3 VCC3
VCC2 VCC3
VCC2 VCC3 VCC2
VCC2 VCC3 VCC3
VCC2 VCC2
VCC3 VCC2 VCC3 VCC2
VCC3 VCC2
D/C#
EADS#
W/R#
ADS#
FLUSH# HIT# HITM# VCC3 BE0# BE2# VCC3 VCC3 VCC3 VCC2 VCC3 VCC2 VCC3 VCC3
BUSCHK#
BE1# A20M#
BE3# BE5#
BE4# BE7#
BE6#
View
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
SCYC RESET VCC2
VCC3 VCC3
VCC2 VCC2 VCC2
VCC2
VCC3 VCC2 VCC3
VCC3 VCC2
VCC3 VCC3
VCC3
VCC2
VCC2
VCC2 VCC2
VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC3 VCC2
PICD[0]
SMI# NMI/LINT1
INIT
BF[0] BF[2]
VCC2 VCC2
PICCLK
IGNNE# PEN# BF[1] STPCLK# INTR/LINT0
TRST#
PICD[1]
A4694-01
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Figure HL-PBGA Package Side View
IERR#
PM1/BP1 M/IO# EWBE# AHOLD KEN# BOFF# HOLD PM0/BP0 WB/WT# CACHE# BRDY# VCC2 VCC2 VCC2 VCC2 SMIACT#
VCC2
FERR#
PRDY APCHK# BREQ VCC2
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2
VCC2 VCC3
PCHK# VCC3 VCC2 VCC3 VCC3
HLDA
VCC3 VCC2
VCC3 VCC2 VCC3 VCC2 VCC2 VCC3 VCC3
VCC3 VCC2
LOCK#
D/C#
EADS#
ADS#
W/R#
VCC3 HITM# HIT# FLUSH# VCC3 VCC3 BE0# BUSCHK# BE2#
A20M# BE1#
BE4# BE7#
BE3# BE5#
Bottom View
VCC3
BE6#
VCC2 VCC2 RESET SCYC VCC3 VCC2 VCC3 VCC3
VCC2 VCC3 VCC3
VCC3 VCC2 VCC2 VCC2
VCC2
VCC3
VCC2
VCC2 VCC2 VCC2 VCC2
VCC3 VCC2 VCC2 VCC2
VCC2 VCC2
VCC3 VCC3
VCC3 VCC2 VCC3
VCC2 VCC3 VCC3
VCC2
PICD[0]
PICCLK
VCC2
BF[2]
BF[0]
INIT
SMI#
NMI/LINT1
PICD[1]
TRST#
STPCLK# BF[1] PEN# IGNNE# INTR/LINT0
A4695-01
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Table
Cross Reference Name (Sheet
Location Location Address Data AC24 AC25 AB24 AB25 AA24 AA25 Control A20M# ADS# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/ LINT0 KEN# LOCK# M/IO# NMI/LINT1 PCHK# AF14 AE14 AF13 AE12 PM1/BP1 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# W/R# WB/WT# AF12 AE13 AE22 AE21 AF21 AF20 AF19 AF11 AE11 AF10 AE10 Location Location
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Table
Cross Reference Name (Sheet
BRDY# Location FLUSH# HIT# Location PEN# PM0/BP0 APIC PICCLK AE23 PICD0 AD23 PICD1 [APICEN] AF22 Location AF15 Location
Clock Control STPCLK# AE15 AF17 AF16 AE16
Table
Connect, Power Supply Ground Cross Reference
VCC2 VCC3 AA23 AD10 AD11 AD13 AD14 AD15 AD16 AD17 AD18 AD20 AD21 AD22 AD24 AE19 AE20 AC10 AC11 AC17 AC22 AB23 AC13 AC14 AC15 AC16 AC18 AC19 AC20 AC21 AC23 AD19 AE17 AE18
Connect (NC) AF18 Internal Connect (INC) AA26 AB26 AC12 AC26 AD12 AD25 AD26 AE24 AE25 AE26 AF23 AF24 AF25 AF26
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Extended Temperature Pentium® Processor with MMXTechnology
Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected (VSS). Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with processor steppings.
Quick Reference
This section gives brief functional description each pin. detailed description, Hardware Interface chapter Embedded Pentium® Processor Family Developer's Manual. Note: input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. pins classified Input Output based their function Master Mode. Error Detection chapter Embedded Pentium® Processor Family Developer's Manual (order number 273204) further information.
Table
Quick Reference (Sheet
Symbol Type Name Function When address mask asserted, Pentium® processor with MMXtechnology emulates address wraparound Mbyte, which occurs 8086. When A20M# asserted, processor masks physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address status indicates that valid cycle currently being driven processor. response assertion address hold, processor will stop driving address lines (A31-A3) next clock. rest will remain active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated. address parity check status asserted clocks after EADS# sampled active processor detected parity error address during inquire cycles. APCHK# will remain active clock each time parity error detected. byte enable pins used determine which bytes must written external memory, which bytes were requested current cycle. byte enables driven same clock address lines (A31-3).
A20M#
A31-A3
ADS#
AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function Frequency pins determine bus-to-core frequency ratio. [2:0] sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF[2:0] must change values while RESET active. Table Frequency Selection. BF2-BF0 order override internal defaults guarantee that BF[2:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. During power RESET should asserted prior ramped simultaneously with core voltage supply processor. backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. BUSCHK# assure that BUSCHK# will always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor will vector exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external requires levels. external timing parameters except TDI, TDO, TMS, TRST# PICD0-1 specified with respect rising edge CLK. This V-tolerant-only Extended Temperature Pentium processor with technology. recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device.
BOFF#
[APICEN] PICD1
BP3-BP2 PM/BP1-BP0
BRDY#
BREQ
CACHE#
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Extended Temperature Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function Frequency pins determine bus-to-core frequency ratio. [2:0] sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF[2:0] must change values while RESET active. Table Frequency Selection. BF2-BF0 order override internal defaults guarantee that BF[2:0] inputs remain stable while RESET active, these pins should strapped directly through pullup/pulldown resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. During power RESET should asserted prior ramped simultaneously with core voltage supply processor. backoff input used abort outstanding cycles that have completed. response BOFF#, processor will float pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. breakpoint pins (BP3-0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor will latch address control signals machine check registers. addition, set, processor will vector machine check exception. BUSCHK# assure that BUSCHK# will always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor will vector exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst writeback cycle write). this driven inactive during read cycle, processor will cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external requires levels. external timing parameters except TDI, TDO, TMS, TRST# PICD0-1 specified with respect rising edge CLK. This V-tolerant-only Extended Temperature Pentium processor with technology. recommended that begin after reaches proper operating level. This recommendation only assure long term reliability device.
BOFF#
[APICEN] PICD1
BP3-BP2 PM/BP1-BP0
BRDY#
BREQ
CACHE#
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Extended Temperature Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol D/C# Type Name Function data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When driving data lines, they driven during clocks that cycle. During reads, samples data when BRDY# returned. These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back Pentium processor with voltage reduction technology these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56; applies D7-D0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write EWBE# sampled inactive, processor will hold subsequent writes M-state lines data cache until write cycles have completed, indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using MS-DOS type floating-point error reporting. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicating completion writeback invalidation. FLUSH# sampled when RESET transitions from high low, three-state test mode entered. indication driven reflect outcome inquire cycle. inquire cycle hits valid line either data instruction cache, this asserted clocks after EADS# sampled asserted. inquire cycle misses cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive processor will resume driving bus. processor cycle pending, will driven same clock that HLDA de-asserted. response hold request, processor will float most output input/output pins assert HLDA after completing outstanding cycles. processor will maintain this state until HOLD de-asserted. HOLD recognized during LOCK cycles. processor will recognize HOLD during reset. internal error used indicate internal parity errors. parity error occurs read from internal array, processor will assert IERR# clock then shutdown.
D63-D0
DP7-DP0
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IERR#
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Extended Temperature Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor will ignore pending unmasked numeric exception continue executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will execute instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor will stop execution wait external interrupt. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used lieu RESET after power INIT sampled high when RESET transitions from high low, processor will perform built-in self test prior start program execution. active maskable interrupt input indicates that external interrupt been generated. EFLAGS register set, processor will generate locked interrupt acknowledge cycles vector interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated assure that interrupt recognized. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle will transformed into burst line fill cycle. lock indicates that current cycle locked. processor will allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed de-asserted least clock between back-to-back locked cycles. memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor will issue ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. page cache disable reflects state CR3; Page Directory Entry Page Table Entry. purpose provide external cacheability indication page-by-page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned.
IGNNE#
INIT
INTR
KEN#
LOCK#
M/IO#
PCHK#
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Table
Quick Reference (Sheet
Symbol Type Name Function parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. this sampled active clock, data parity error detected. processor will latch address control signals cycle with parity error machine check registers. addition, machine check enable "1", processor will vector machine check exception before beginning next instruction. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input Pentium processor with technology. Programmable interrupt controller data lines Pentium processor with technology comprise data portion APIC 3-wire bus. They opendrain outputs that require external pull-up resistor. These signals multiplexed with APICEN. These pins function part performance monitoring feature. PM/BP[1:0] breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output indicates that processor stopped normal execution response R/S# going active Probe Mode being entered. page writethrough reflects state CR3, page directory entry, page table entry. used provide external writeback indication page-by-page basis. run/stop input provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (Order Number 273204) more details. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine three-state test mode will entered BIST will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock Pentium processor with voltage reduction technology thereby causing core consume less power. When recognizes STPCLK#, processor will stop execution next instruction boundary, unless superseded higher priority interrupt, generate Stop Grant Acknowledge cycle. When STPCLK# asserted, processor will still respond external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state.
PEN#
PICCLK PICD0- PICD1 [APICEN]
PRDY
R/S#
RESET
SCYC
SMI#
SMIACT#
STPCLK#
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Table
Quick Reference (Sheet
Symbol Type Name Function test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Differentiate between Pentium Processor with technology Extended Temperature Pentium processor with technology. This Internal Connect (INC) Extended Temperature Pentium processor with technology. This defined HL-PBGA package. These pins power inputs core: input 166/266 PPGA; HL-PBGA; HL-PBGA. These pins power inputs I/O. These pins ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. writeback/writethrough input allows data cache line defined writeback writethrough line-by-line basis. result, determines whether cache line initially state data cache.
TRST#
VCC2DET#
VCC2 VCC3 W/R#
WB/WT#
Fraction (BF) Selection
Each Extended Temperature Pentium processor with technology must externally configured with BF2-BF0 pins operate specified fraction mode. Operation specification supported. example, Extended Temperature Pentium processor with technology supports only mode. configuration pins provided select allowable bus/core ratio 2/5. Extended Temperature Pentium processor with technology multiplies input achieve higher internal core frequencies. internal clock generator requires constant frequency input within ±250 therefore, input cannot changed dynamically. external frequency during power-up Reset through pin. Extended Temperature Pentium processor with technology samples BF0, pins falling edge RESET determine which bus/core ratio use. Table summarizes operation pins Extended Temperature Pentium processor with technology. Note: pins must meet setup time falling edge RESET must change value while RESET active. Once frequency selected, changed with warm reset. Changing this speed ratio requires "power RESET pulse initialization.
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Table
Frequency Selection
Bus/Core Ratio Bus/Core Frequency (MHz) 66/166
NOTE: other BF2-BF0 settings reserved Extended Temperature Pentium processor with technology.
CPUID Instruction
CPUID instruction allows software determine type features processor which executing. When executing CPUID, Extended Temperature Pentium processor with technology behaves like Pentium processor Pentium processor with technology follows:
value `0', then 12-byte ASCII string "Genuine Intel" (little endian)
returned EBX, ECX. Also, returned EAX.
value `1', then processor version returned processor
capabilities returned EDX. values Extended Temperature Pentium processor with technology given below.
value neither `1', Extended Temperature Pentium processor with
technology writes registers. following values defined CPUID instruction executed with `1'. processor version assignments given Figure assignments shown Figure Figure Assignments CPUID
(Reserved)
Type Family
Model Stepping
000250
Figure Assignments CPUID
Rsvd
000251
Reserved
Reserved
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Extended Temperature Pentium® Processor with MMXTechnology
type field Extended Temperature Pentium processor with technology same Pentium processor with technology (type 00H). family field same other Pentium processors (family 5H). However, model field different: Pentium processor model number Pentium processor with technology model number Extended Temperature Pentium processor with technology model number stepping field indicates revision number model. stepping A-step Extended Temperature Pentium processor with technology Stepping will documented Extended Temperature Pentium processor with technology stepping information. After masking reserve bits, Extended Temperature Pentium processor with technology-based products will value 0x008003BF (assuming APIC enabled boot), 0x008001BF (when APIC disabled, using APICEN boot pin) upon completion CPUID instruction. Table Assignment Definitions CPUID
10-11 15-22 24-31 Value Comments FPU: Floating-point Unit on-chip VME: Virtual-8086 Mode Enhancements Debugging Extensions PSE: Page Size Extension TSC: Time Stamp Counter Pentium® Processor PAE: Physical Address Extension MCE: Machine Check Exception CX8: CMPXCHG8B Instruction APIC: APIC on-chip Reserved write these bits rely their values MTRR: Memory Type Range Registers PGE: Page Global Enable MCA: Machine Check Architecture Reserved write these bits rely their values Intel Architecture with MMXtechnology supported Reserved write these bits rely their values
Indicates that APIC present hardware enabled (software disabling does affect this bit).
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Boundary Scan Chain List
boundary scan chain list Extended Temperature Pentium processor with technology different than Pentium processor with technology removal some pins. boundary scan register Extended Temperature Pentium processor with technology contains cell each pin. Following order Extended Temperature Pentium processor with technology boundary scan register (left right, bottom): disapsba, PICD1, PICD0, Reserved, PICCLK, DP0, D10, D11, D12, D13, D14, D15, DP1, D16, D17, D18, D19, D20, D21, D22, D23, DP2, D24, D25, D26, D27, D28, D29, D30, D31, DP3, D32, D33, D34, D35, D36, D37, D38, D39, DP4, D40, D41, D42, D43, D44, D45, D46, diswr D47, DP5, D48, D49, D50, D51, D52, D53, D54, D55, DP6, D56, D57, D58, D59, D60, D61, D62, D63, DP7, IERR#, FERR#, PM0BP0, PM1BP1, BP2, BP3, MIO#, CACHE#, EWBE#, INV, AHOLD, KEN#, BRDYC#, BRDY#, BOFF#, NA#, WBWT#, HOLD, disbus, disbusl, dismisc, dismisca, SMIACT#, PRDY, PCHK#, APCHK#, BREQ, HLDA, LOCK#, PCD, PWT, DC#, EADS#, ADS#, HITM#, HIT#, WR#, BUSCHK#, FLUSH#, A20M#, BE0#, BE1#, BE2#, BE3#, BE4#, BE5#, BE6#, BE7#, SCYC, CLK, RESET, disabus A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A31, A30, A29, A28, A27, A26, A25, A24, A23, A22, A21, NMI, RS#, INTR, SMI#, IGNNE#, INIT, PEN#, Reserved, BF0, BF1, BF2, STPCLK#, Reserved, Reserved, Reserved, Reserved "Reserved" includes connect "NC" signals Extended Temperature Pentium processor with technology. cells marked with dagger control cells that used select direction bidirectional pins three-state output pins. loaded into control cell, associated pin(s) three-stated selected input. following lists control cells their corresponding pins: Disabus: Disbus: Disbusl: Dismisc: Dismisca: Diswr: Disapsba: A31-A3, BE7#-BE0#, CACHE#, SCYC, M/IO#, D/C#, W/R#, PWT, ADS#, LOCK#, ADSC# APCHK#, PCHK#, PRDY, BP3, BP2, PM1/BP1, PM0/BP0, FERR#, SMIACT#, BREQ, HLDA, HIT#, HITM# IERR# D63-D0, DP7-DP0 PICD1-PICD0
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Table
Reference Tables
Output Pins
Name ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM#(2) HLDA IERR# LOCK# M/IO#, D/C#, W/R# PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC SMIACT# VCC2DET#(3) Active Level High High High High High High states except Shift-DR Shift-IR Differentiates between Pentium® processor with MMXtechnology Extended Temperature Pentium processor with technology Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# When Floated
NOTE: output input/output pins floated during three-state test mode (except TDO). HITM# internal pull-up resistor. This HL-PBGA pinout.
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Table
Input Pins
Name A20M# AHOLD BOFF# BRDY# BUSCHK# EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY#/NA# Pullup Pullup BRDY# EADS# First BRDY#/NA# State T2,TD,T2P BRDY# Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Pullup Pullup State T2,T12,T2P BRDY# Pulldown Pullup Pulldown Internal Resistor Qualified
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Table
Input/Output Pins
Name A31-A3 BE3#-BE0# D63-D0 DP7-DP0 PICD0 PICD1[APICEN] Active Level When Floated(1) Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown(2) Internal Resistor
NOTE: output input/output pins floated during three-state test mode (except TDO). BE3#-BE0# have pulldowns during RESET only.
Grouping According Function
Table Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Interrupts Floating-point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Clock Control Debugging RESET, INIT, BF[2:0] A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD0-PICD1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# R/S#, PRDY Pins
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3.10
Mechanical Specifications
HL-PBGA package Extended Temperature Pentium processor with technology package type Pentium processor family. Package summary information HLPBGA device provided Table Figure shows package dimensions.
3.10.1
HL-PBGA Package Mechanical Diagrams
Figure shows HL-PBGA package. dimensions listed Table
Figure HL-PBGA Package Dimensions
Corner Corner
I.D. Dia. View
Bottom View
Side View
Seating Plane
Note: Dimensions Millimeters
A5830-01
Table HL-PBGA Package Dimensions (Sheet
Millimeters Symbol 1.41 0.56 0.60 0.85 34.90 1.67 0.70 0.90 0.97 35.10
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Table HL-PBGA Package Dimensions (Sheet
Millimeters Symbol
35.10 1.27 1.63
34.90
3.11
Thermal Specifications
Extended Temperature Pentium processor with technology HL-PBGA package specified proper operation with case temperature, TCASE range 115°
3.11.1
Measuring Thermal Values
verify that proper maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (smaller than 0.150" diameter) should drilled through heatsink allow probing center package. Figure illustration measure minimize measurement errors, recommended following approach:
36-gauge finer diameter type thermocouples. laboratory testing done
using thermocouple made Omega* (part number 5TC-TTK-36-36).
Attach thermocouple bead junction center package surface using high
thermal conductivity cements. laboratory testing done using Omega Bond (part number OB-101).
thermocouple should attached 90-degree angle shown Figure hole size should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heatsink base. contact
will affect thermocouple reading.
3.11.2
Thermal Equations Data
Extended Temperature Pentium processor with technology, ambient temperature, (air temperature around processor), specified directly. only restriction that met. equation used calculate
Where: Ambient case temperature (°C)
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Case-to-ambient thermal resistance (°C/Watt) Maximum power consumption (Watt)
thermal resistance from package case. values shown Table typical values. actual values depend actual thermal conductivity process attach. thermal resistance from package case ambient. values shown these tables typical values. actual values depend heatsink design, interface between heatsink package, airflow system, thermal interactions between processor surrounding components through ambient. Figure Technique Measuring
000262
3.11.3
Airflow Calculations Maximum Typical Power
Below example determining airflow required during maximum power consumption Extended Temperature Pentium processor with technology assuming ambient temperature +85° 115° PHL-PBGA (HL-PBGA, without heat sink) 7.3° Figure indicates that this example would require about without heat sink, about with heat sink vertical orientation. Below example determining airflow required during typical power consumption Extended Temperature Pentium processor with technology assuming ambient temperature +85° 115° PHL-PBGA (HL-PBGA, without heat sink) 10.34° Figure indicates that this example would require about without heat sink, about with heat sink vertical orientation, typical power ambient conditions.
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3.11.4
HL-PBGA Package Thermal Resistance Information
Table lists values Extended Temperature Pentium processor with technology HL-PBGA package. thermal data collection conditions were:
bidirectional anodized aluminum alloy heat sink used. Heat sink height 7mm. horizontal orientation component mounted flush with motherboard. vertical orientation component mounted add-in card perpendicular motherboard.
Table Thermal Resistances HL-PBGA Packages
Heatsink/ Orientation Heat Sink Horizontal Vertical (°C/watt) 0.76 0.76 0.76 (°C/watt) Laminar Airflow (linear ft/min) 15.66 12.09 11.33 12.33 8.57 8.34 10.3 6.52 6.38 8.85 4.82 4.69 7.89 4.06 3.95
Figure Thermal Resistance Airflow HL-PBGA Package
Airflow (LFM) Horizontal Heat Sink Vertical Heat Sink Heat Sink
(°C/W)
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Extended Temperature Pentium® Processor with MMXTechnology Electrical Specifications
This section contains preliminary information products production. specifications subject change without notice.
Warning:
Absolute Maximum Ratings
following values stress ratings only. Functional operation maximum ratings implied guaranteed. Functional operating conditions given specification tables. Stressing device beyond "Absolute Maximum Ratings" cause permanent damage. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor with technology contains protective circuitry resist damage from Electrostatic Discharge (ESD), always take precautions avoid high static voltages electric fields.
Table Absolute Maximum Ratings
Parameter Case temperature under bias Storage temperature VCC3 supply voltage with respect VCC2 supply voltage with respect only buffer input voltage -65° 125° -65° 150° -0.5 +3.2 -0.5 +2.8 -0.5 VCC3+0.5 (not exceed VCC3 max) Maximum Rating
Specifications
Tables list specifications which apply Extended Temperature Pentium processor with technology.
4.2.1
Power Sequencing
There specific sequence required powering powering down VCC2 VCC3 power supplies. However, recommended that VCC2 VCC3 power supplies either both both within second each other. voltage VCC3 core voltage VCC2 HL-PBGA package type (166 MHz).
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Table TCASE Specifications
Package TCASE Supply VCC2 VCC3 Voltage 1.665 2.375 Voltage 1.935 2.625 Voltage Tolerance 7.5% Frequency
HL-PBGA
-40°C 115°C
Table Specifications
Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage VCC3 VCC3 VCC3 Unit Level Level, Level, Level, Notes
-0.3
VCC3
NOTES: Parameter measured Parameter measured Parameter measured 100% tested, guaranteed design.
values Table should used power supply design. values were determined using worst case instruction maximum VCC. Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes. Table Specifications
Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current 2.35 (HL-PBGA) 0.38 Unit Notes
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Table Power Dissipation Requirements Thermal Design
Parameter Thermal Design Power Active Power
Typical(1) 0.70 0.06
Max(2)
Unit Watts Watts Watts Watts
Frequency
Stop Grant/Auto Halt Powerdown Power Dissipation(4) Stop Clock Power(5)
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device specified voltage running typical applications. This value dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum thermal design power unless system uses thermal feedback limit processor's maximum power. maximum thermal design power determined using worst-case instruction also takes into account thermal time constant package. Active power average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. Stop Grant/Auto Halt Powerdown Power Dissipation determined asserting STPCLK# executing HALT instruction. When this mode, processor feature which allows power down additional circuitry enable lower power dissipation. This power without snooping specified voltage with TR12 set. order enable this feature, TR12 must (the default disabled). Stop grant/Auto Halt Powerdown power dissipation without TR12 higher. rating changed future specification updates. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input. This specified TCASE
Table Input Output Characteristics
Symbol CI/O CCLK CTIN CTOUT CTCK Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input High Leakage Current Input Leakage Current -400 Unit 0<VIN<VIL, VIH< VIN<VCC3, 0<VIN<VIL, VIH< VIN<VCC3, VCC3 Notes
NOTES: This parameter inputs/outputs without internal pull pull down. This parameter inputs with internal pull This parameter inputs with internal pull down. Guaranteed design. This specification applies HITM# when driven input (e.g., JTAG mode).
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Specifications
specifications Extended Temperature Pentium processor with technology consist setup times, hold times, valid delays
4.3.1
Power Ground
clean on-chip power distribution, there VCC3, VCC2 inputs. Power ground connections must made external VCC2, VCC3 pins. circuit board, VCC2 pins must connected proper voltage VCC2 plane island (core voltage determined package type/frequency). VCC3 pins must connected VCC3, plane. pins must connected plane. Please refer Table page list VCC2, VCC3 pins.
4.3.2
Decoupling Recommendations
Liberal decoupling capacitance should placed near processor. processor's large address data buses cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high frequency electrical performance. Inductance reduced shortening circuit board traces between processor decoupling capacitors much possible. These capacitors should evenly distributed around each component power plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Power transients also occur processor rapidly transitions from level power consumption high level high power transition). typical example would entering exiting Stop Grant state. Another example would executing HALT instruction, causing processor enter Auto HALT Powerdown state, transitioning from HALT Normal state. these examples cause abrupt changes power being consumed processor. Note that Auto HALT Powerdown feature always enabled even when other power management features implemented. Bulk storage capacitors with (Effective Series Resistance) range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel. These capacitors should placed near processor both VCC2 plane VCC3 plane ensure that supply voltages stay within specified limits during changes supply current during operation.
4.3.3
Connection Specifications
NC/INC pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected ground.
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4.3.4
Timings
specifications given Table consist output delays, input setup requirements input hold requirements standard external bus. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced VCC3/VCC2 both logic levels unless otherwise specified. Within sampling window, asynchronous inputs must stable correct operation. Each valid delay specified load. system designer should buffer modeling account signal flight time delays. select fraction clock speed which will cause processor exceed internal maximum frequency. following specifications apply standard signals used with Pentium processor family:
input test waveforms assumed transitions with V/ns rise fall
times
V/ns input rise/fall time V/ns timings referenced from VCC3/VCC2
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Table Extended Temperature Pentium® Processor with MMXTechnology Specifications (Sheet
Symbol Parameter Frequency Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay LOCK#, Valid Delay ADS# Valid Delay A31-A3 Valid Delay M/IO# Valid Delay BE7#-BE0#, D/C#, SCYC Valid Delay ADS#, A31-A3, PWT, PCD, BE7#-BE0#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM1-PM0, BP3-BP0 Valid Delay PRDY Valid Delay D63-D0, DP7-DP0 Write Data Valid Delay D63-D0, DP3-0 Write Data Float Delay A31-A5 Setup Time A31-A5 Hold Time INV, Setup Time EADS# Setup Time 0.15 0.15 33.33 15.0 66.6 30.0 ±250 Unit @VCC3 @0.5 VCC3 VCC3 -0.7 Figure Notes (see Table
10.0
t10a t10b t11a t11b t16a t16b
10.0 10.0
Refer Table TCASE assumptions.
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Table Extended Temperature Pentium® Processor with MMXTechnology Specifications (Sheet
Symbol t18a t18b t24a t24b t25a t25b Parameter EADS#, INV, Hold Time KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D63-D0, DP7-0 Read Data Setup Time D63-D0, DP7-0 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable 4.75 Unit Figure Notes (see Table
15.0
CLKs CLKs CLKs
(10, (10,
(10) Power
Refer Table TCASE assumptions.
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Table Extended Temperature Pentium® Processor with MMXTechnology Specifications (Sheet
Symbol Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. BF2-BF0 Setup Time BF2-BF0 Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 40.0 13.0 20.0 25.0 20.0 25.0 Unit Figure Notes (see Table
t42a
CLKs
RESET falling edge,
t42b t43a t43b t43c t43d
CLKs
RESET falling edge RESET falling edge, (10) RESET falling edge, (12) RESET falling edge RESET falling edge
62.5 25.0 25.0 16.0
CLKs CLKs CLKs
@VCC3 -0.7 @0.5 VCC3 -0.7 VCC3 -0.7 Asynchronous, (15) (15) (13) (13, (15, (15,
Refer Table TCASE assumptions.
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Table APIC Specifications
Symbol t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay PICD0-1 High Time PICCLK Setup Time PICCLK Hold Time PICCLK Ratio (CLK/PICCLK) 0.15 0.15 16.66 Unit PICCLK PICCLK From PICCLK, (18) From PICCLK, (18) (19) Figure Notes
Table Notes Tables
input frequency must either 33.33 MHz) 66.6 MHz). Operation range between 33.33 66.6 supported. percent tested. Guaranteed design. These signals measured rising edge adjacent CLKs VCC3/VCC2. ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. internal clock generator requires constant frequency input within +250 therefore input cannot changed dynamically. 0.87 V/ns input rise/fall time V/ns. APCHK#, FERR#, HLDA, IERR#, LOCK#, PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions. Timing (t14) required external snooping (e.g., address setup which EADS# sampled active). Setup time required guarantee recognition specific clock. This input driven asynchronously. Hold time required guarantee recognition specific clock. 10.When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, SMI# must de-asserted (inactive) minimum clocks before being returned active. 11.To guarantee proper asynchronous recognition, signal must have been de-asserted (inactive) minimum clocks before being returned active must meet minimum pulse width. 12.BF2-BF0 should strapped VCC3 VSS. 13.Referenced falling edge. 14.1 added maximum rise fall times every frequency below MHz. 15.Referenced rising edge. 16.Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TDO, TMS). These timings correspond response these signals boundary scan operations. 17.During probe mode operation, boundary scan timings (t55-t58). 18.This assumes external pull-up resistor lumped capacitive load. pull-up resistor must between capacitance must between product must between 19.The PICCLK ratio integer ratio (CLK/PICCLK) cannot smaller than
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Figure Clock Waveform
Vcc3-0.7V 0.5V t49, t60e t48, t60f t46, t60c t45, t60b t47, t60d
PP0051
Figure Valid Delay Timings
Vcc3/2
max.
Signal Vcc3/2 VALID
min.
t10, t11, t12, t60i
PP0052
Figure Float Delay Timings
Vcc3/2
Signal
t6min, t12min
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Figure Setup Hold Timings
Vcc3/2
Signal
VALID
t14, t16, t18, t20, t22, t24, t26, t28, t31, t34, t60g PICCLK), t15, t17, t19, t21, t23, t25, t27, t29, t32, t35, t60h PICCLK),
Figure Reset Configuration Timings
RESET
Vcc3/2
Vcc3/2
Config =t42, t43c, t43e, t43b, t43d, t43f, t38, VALID
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Figure Test Timings
Vcc3/2
Output Signals
Input Signals
Figure Test Reset Timings
TRST#
Vcc3/2
Buffer Models
This section describes buffer models Extended Temperature Pentium processor with technology. first order buffer model simplified representation complex input output buffers used. Figure shows structure input buffer model Figure shows output buffer model. Table show parameters used specify these models. Although simplified, these buffer models will accurately model flight time signal quality. these parameters, there very little added accuracy complete transistor model.
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addition input output buffer parameters, input protection diode models provided added accuracy. These diodes have been optimized provide protection provide some level clamping. Although diodes required simulation, more difficult meet specifications without them. Note, however, some signal quality specifications require that diodes removed from input model. series resistors (RS) part diode model. Remove these when removing diodes from input model. Figure First Order Input Buffer Model
Table Parameters Used Specification First Order Input Buffer Model
Parameter Description Minimum Maximum value capacitance input buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance Diode Series Resistance Ideal Diodes
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Figure First Order Output Buffer Model
Table Parameters Used Specification First Order Output Buffer Model
Parameter dV/dt Description Minimum maximum value rate change open circuit voltage source used output buffer model Minimum maximum value output impedance output buffer model Minimum Maximum value capacitance output buffer model Minimum Maximum value package inductance Minimum Maximum value package capacitance
4.4.1
Buffer Model Parameters
This section gives parameters each input, output bidirectional buffers. Tables contain listings three buffer model types; them confused during simulation. When bidirectional operating input, CIN, values; operating driver, data parameters. Please refer Table groupings buffers. input, output bidirectional buffer's values listed below. These tables contain listings three types. When bidirectional operating input, just CIN, values, operating driver data parameters.
Table Signal Buffer Type
Signals A20M#, AHOLD, BOFF#, BRDY#, BUSCHK#, EADS#, EWBE#, FLUSH#, HOLD, IGNNE#, INIT, INTR, INV, KEN#, NA#, NMI, PEN#, PICCLK, R/S#, RESET, SMI#, STPCLK#, TCK, TDI, TMS, TRST#, WB/WT# APCHK#, BE7-BE5#, BP3-BP2, BREQ, FERR#, IERR#, PCD, PCHK#, PM0/BP0, PM1/BP1, PRDY, PWT, SMIACT#, A31-A3, BE4#-BE0#, CACHE#, D/C#, D63-D0, DP8-DP0, HLDA, LOCK#, M/IO#, SCYC, ADS#, HITM#, HIT#, W/R#, PICD0, PICD1 Type Driver Buffer Type Receiver Buffer Type
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Table Preliminary Input, Output Bidirectional Buffer Model Parameters HL-PBGA Package
Buffer Type Transition dV/dt (V/nsec) (input) (output) (bidir) Rising Falling Rising Falling Rising Falling 2.2/2.2 2.2/2.9 2.2/2.2 2.2/2.9 2.7/0.15 2.7/0.22 2.7/0.15 2.7/0.22 21.6 17.5 21.6 17.5 (Ohms) (pF) (nH) 11.3 11.3 11.7 11.7 10.3 10.3 CO/CIN (pF)
NOTE: data this table based preliminary design information. Input, output bidirectional buffer values being characterized this time.
Table Input Buffer Model Parameters: (Diodes)
Symbol Parameter Saturation Current Emission Coefficient Series Resistance Transit Time Potential Zero Bias Capacitance Grading Coefficient 1.4e-14A 1.19 0.983 0.281 0.385 2.78e-16A 1.00 0.967 0.365 0.376
Signal Quality Specifications
Signals driven system into Extended Temperature Pentium processor with technology must meet signal quality specifications guarantee that components read data properly ensure that incoming signals affect reliability component.
4.5.1
Overshoot
maximum overshoot overshoot threshold duration specifications inputs Extended Temperature Pentium processor with technology described follows:
Maximum overshoot specification: maximum overshoot CLK/PICCLK signals
should exceed VCC2, nominal +0.6 maximum overshoot other input signals should exceed VCC3, nominal +1.0
Overshoot threshold duration specification: overshoot threshold duration defined
time during which input signal above VCC3, nominal +0.3 within single clock period. overshoot threshold duration must exceed period.
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Refer Table summary overshoot specifications Extended Temperature Pentium processor with technology. Table Overshoot Specification Summary
Specification Name Threshold Level Maximum Overshoot Level (CLK PICCLK) Maximum Overshoot Level (all other inputs) Maximum Threshold Duration Maximum Ringback NOTES: VCC3, nominal refers voltage measured VCC3 pins. Value VCC3, nominal +0.3 VCC3, nominal +0.6 VCC3, nominal +1.0 clock period above threshold voltage VCC3, nominal -0.7 Units Notes
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Extended Temperature Pentium® Processor with MMXTechnology Errata Information
This section update specifications contained Pentium® Processor Family Developer's Manual, (order number 273204), Intel Architecture Software Developer's Manual, Volume (order numbers 243190, 243191, 243192); Embedded Pentium® Processor (order number 273202), Embedded Pentium® Processor with Voltage Reduction Technology (order number 273203), Embedded Pentium® Processor with MMXTechnology (order number 273214), Low-Power Embedded Pentium® Processor with MMXTechnology (order number 273184) datasheets. intended hardware system manufacturers software developers applications, operating systems, tools. contains Specification Changes, S-Specs, Errata, Specification Clarifications Documentation Changes Pentium processors high-performance extended temperature applications. following processors included this Specification Update:
Pentium® Processor Pentium® Processor Pentium® Processor with Voltage Reduction Technology Pentium® Processor Pentium Processor with Technology Pentium Processor with Technology Low-Power Pentium Processor with Technology Low-Power Pentium Processor with Technology
information pertaining processors listed above, refer Pentium® Processor Specification Update (order number 242480).
Nomenclature
Specification Changes modifications current published specifications. These changes will incorporated next release specifications. S-Specs exceptions published specifications apply only units assembled under that s-spec. Errata design defects errors. Errata cause Pentium® processor's behavior deviate from published specifications. Hardware software designed used with given stepping must assume that errata documented that stepping present devices. Specification Clarifications describe specification greater detail further highlight specification's impact complex design situation. These clarifications will incorporated next release specifications. Documentation Changes include typos, errors, omissions from current published specifications. These changes will incorporated next release specifications.
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Summary Table Changes
following table indicates Specification Changes, S-Specs, Errata, Specification Clarifications Documentation Changes, which apply Pentium processor. Intel intends some errata future stepping component, account other outstanding issues through documentation specification changes noted. This table uses following notations:
5.2.1
Codes Used Summary Table
Doc: Fix: Fixed: NoFix: Document change update that will implemented. This erratum intended fixed future stepping component. This erratum been previously fixed. There plans this erratum.
mark) (Blank Box):This erratum fixed listed stepping specification change does apply listed stepping. APIC related errata.
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Table Specification Changes
Plans Specification Changes limit violation causes fault, interrupt
Table Errata (Sheet
Plans NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix NoFix Errata INIT during HALT within cause large amount activity Single-step debug exception breaks HALT Second assertion FLUSH# ignored Segment limit violation operand corrupt state exception inside with pending hangs system Data breakpoint deviations Event monitor counting discrepancies VERR type instructions causing page fault task switch with corrupt CS:EIP BUSCHK# interrupt wrong priority Matched disabled data breakpoint lost STPCLK# assertion STPCLK# ignored when INIT pending fault causing page fault cause instruction execute twice Machine check exception pending, then HLT, cause skipped incorrect instruction, hang FBSTP stores operand incorrectly address wrap error both occur interrupt routine illegal privilege level cause spurious pushes stack Corrupted flag cause skipped incorrect instruction, hang Benign exceptions erroneously cause double fault Double fault counter increment correctly Short form pair Turning paging result prefetch random location STPCLK#, FLUSH# SMI# after string instruction interruptible STPCLK# Single step reported first instruction after FLUSH# Double fault generate illegal cycle TRST# asynchronous STPCLK# causes non-standard behavior Code cache dump cause wrong IERR# Asserting TRST# issuing JTAG instructions does exit Hi-Z state ADS# delayed after HLDA deassertion Stack underflow IRET gives #GP, Performance monitoring pins PM[1:0] count events incorrectly
NOTE: This item does apply Pentium processors extended temperature applications. full text this item, refer Pentium® Processor Specification Update, order number 242480.
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Table Errata (Sheet
1AP. 2AP. Plans NoFix Fixed NoFix NoFix NoFix NoFix NoFix NoFix NoFix Errata Branch trace messages cause system hang Event monitor counting discrepancies (fix) Event monitor counting discrepancies (Nofix) update blocked after specific sequence events with misaligned descriptor Erroneous debug exception POPF/IRET instructions with fault Content upon Return from Invalid operand with locked CMPXCHG8B instruction Event monitor counting discrepancy FBSTP instruction incorrectly sets Accessed Dirty bits Page Table entry INIT APIC three-wire lost PICCLK must toggle least twenty cycles before RESET
NOTE: This item does apply Pentium processors extended temperature applications. full text this item, refer Pentium® Processor Specification Update, order number 242480.
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Table Specification Clarifications
Plans Specification Clarifications Only SMI# latched during APIC 8-bit access LOCK prefix excludes APIC memory space SMI# activation cause nested handling Code breakpoints meaningless prefixes guaranteed recognized Resume flag should software Data breakpoints delayed iteration When cache disabled, inquire cycles blocked Serializing operation required when modifies another CPU's code correct translations, should flushed after Extra code break occur instruction coincides FYL2XP1 does generate exceptions range Enabling inside BF[1:0] must change values while RESET active Active A20M# during POP[ESP] with 16-bit stack size Line fill order optimization revision Test Parity Check Mechanism Clarification
NOTE: This item does apply Pentium processors extended temperature applications. full text this item, refer Pentium® Processor Specification Update, order number 242480.
5.2.2
Documentation Changes
Table Documentation Changes
Plans Documentation Changes Cannot Nested Task Switch, Volume Page 13-12 Interrupt Sampling Window, Volume Page 23-39 FSETPM Like NOP, Like FNOP Errors Three Tables Special Descriptor Types Invalid Arithmetic Operations Masked Responses Them Relative FIST/FISTP Instruction Incorrect Sequence Registers Stored PUSHA/PUSHAD One-Byte Opcode Correction
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Extended Temperature Pentium® Processor with MMXTechnology Specification Changes
Specification Changes listed this section apply documents listed Preface this Specification Update. Specification Changes incorporated into future versions appropriate document(s).
Limit Violation Causes Fault, Interrupt
last sentence Section Pentium® Processor Family Developer's Manual, Volume says about exception handling Real Mode: interrupt occurs entry interrupt table beyond limit stored IDTR register, double-fault exception generated." fact, Pentium processor, there difference between Real Protected Mode when limit violation occurs. generates interrupt General Protection Fault both modes.
Extended Temperature Pentium® Processor with MMXTechnology Errata
INIT During HALT Within Cause Large Amount Activity
HALT (repeat string instruction) instruction executed while processor System Management mode (SMM), INIT asserted prior interrupt initialization, processor continuously re-execute HALT, generate HALT special cycle, will perform iterations instruction that executed. Normally processor would ignore INIT while SMM. However, INIT will enabled inside interrupts have been enabled then INTR signal received. Also, exceptions, when taken, enable INIT inside SMM, this behavior part Intel Architecture. processor continuously same cycle until non-masked interrupt detected. There other problems associated with erratum, component resumes correct operation this time. This impacts "low power operation" that might have been expected with HALT while SMM. following: HALT while SMM. system must HALT SMM, system required initialize interrupt vector tables prior interrupts, doing will ensure error will occur. system must ensure that INIT asserted while processor HALTed System Management mode, prior interrupt vector initialization.
Problem:
Implication:
Workaround:
Status:
steppings affected Summary Table Changes.
Problem:
Single Step Debug Exception Breaks HALT
When Single Stepping enabled (i.e., flag set) instruction executed processor does stay HALT state should. Instead, exits HALT state immediately begins servicing Single Step exception. behavior described above identical Intel486 behavior. None identified this time.
Implication: Workaround:
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Status:
steppings affected Summary Table Changes beginning this section.
Problem:
Second Assertion FLUSH# Ignored
FLUSH# asserted while processor servicing existing flush request, second flush operation will follow after first completes. Proper operation second assertion FLUSH# ignored between time first FLUSH# asserted completion Flush Acknowledge cycle. system that asserts FLUSH# during flush that's already progress will flush cache second time. Flushing cache again necessary results slight performance degradation. best performance, system hardware should assert subsequent FLUSH# while flush already being serviced. steppings affected Summary Table Changes.
Implication:
Workaround: Status:
Problem:
Segment Limit Violation Operand Corrupt State
Intel486TM, Intel386and earlier processors, operand FSTENV/FLDENV instructions, FSAVE/FRSTOR instructions, exceeds segment limit during execution, resulting General Protection fault blocks completion instruction. (Actually, interrupt generated 80386 earlier.) This leaves state (with FLDENV, FRSTOR) image memory (with FSTENV, FSAVE) partly updated, thus corrupted, instruction generally non-restartable. stated Intel Architecture Software Developer's Manual, Volume Chapter that Pentium processor fixes this problem starting these instructions with test read first last bytes operand. Thus there segment limit violation, triggered before actual data transfer begins, partial updates cannot occur. This improvement works intended large majority segment limit violations. There however special case which beginning operand within segment, endpoints pass initial test, part operand exceeds segment limit. Thus part through data transfer, limit violated, fault occurs, thus state corrupted. Note that this subset cases which will cause same problem with Intel486 earlier CPUs, code that executes correctly those CPUs will correctly Pentium processor. This erratum will happen when both segment limit addressing wrap around boundary falls within range operand, with segment limit below wrap boundary. wrap boundary course, must executing code using addressing.) upper endpoint operand wraps near bottom segment, passes initial test. part through data transfer tries access memory above segment limit below wrap boundary, causing fault with state partly copied. This erratum also happen segment limit above addressing wrap boundary, with both straddled operand that aligned byte boundary. Test upper endpoint wraps thus passes. When instruction actually transferring data, misalignment forces calculate extra addresses special cycles. This special address calculation does support wrap, fault triggered when segment limit crossed. Note that Intel Architecture Software Developer's Manual, Volume Chapter warns general that Pentium processor store only part operands which generate memory fault crossing either segment page limit. This erratum just case that general problem, cases will avoided following recommended programming practice never
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straddling segment page boundaries with operands. Note also that handling operands which straddle such boundaries processor specific, code which uses such straddling will behave differently when different Intel Architecture processors.
Implication:
This erratum corrupt that state will cause fault. This generally will require that task using restarted, will cause unflagged errors results. Code written following Intel recommendations, code which runs Intel486 earlier) CPUs, will cause this erratum. case where Pentium processor will experience this erratum small subset cases which Intel486 (and earlier) CPUs will corrupted.
Workaround:
code which operands wrap around their segments. must operands which wrap their segments, make sure that they aligned byte boundary, that segment limit below wrap boundary.
Status:
steppings affected Summary Table Changes.
Problem:
Exception Inside with Pending Hangs System
previous instruction caused unmasked exception, instruction executed inside with pending, system will hang unless system both compatible (CR0.NE=0), external interrupts enabled. standard PC-AT systems, typically used all) indicate parity error, response required system reset, preserve data integrity. this erratum will only occur when system already suffered parity error; effect erratum only force reset inside SMM, instead after when would normally serviced. system where used error that requires shutdown, workaround should implemented. properly designed system should experience hang-up. such system BIOS checks pending interrupts before issuing FSAVE FRSTOR. interrupt pending, BIOS will exit handle interrupt. interrupt present, BIOS will disable interrupts (for example, will disable writing chip set) only then will issue instruction.
Implication:
Workaround: Status:
instructions used SMM, used other than error that requires shutdown, should blocked from outside during SMM. steppings affected Summary Table Changes.
Data Breakpoint Deviations
following three problems deviations from data breakpoint specification when fault occurs during instruction while data breakpoint waiting serviced. They share same workaround. first case breakpoint serviced, incorrectly, before actual data access that should trigger takes place; other cases breakpoint serviced when should
Problem:
PROBLEM First, debug registers must that instructions which read from memory (except FRSTOR, FNRSTOR, FLDENV FNLDENV) will trigger data breakpoint upon accessing memory operand. Second, there must unmasked exception pending from previous instruction when load store instruction enters execution stage. This would cause, specification, branch exception handler. data breakpoint would triggered until/ unless memory access made after return from exception handler. third, either external interrupts INTR asserted after instruction enters execution stage, before branch exception handler occurs, this erratum generated. this situation, processor should branch external interrupt
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handler, instead goes data breakpoint handler. This incorrect because data access that should trigger breakpoint occurred yet.
Problem: PROBLEM Interrupts blocked instruction after allow complete stack switch before interrupt). triggers data breakpoint, normally serviced after following instruction executed. However, following instruction instruction there pending error from preceding instruction (even error masked), delayed data breakpoint forgotten. PROBLEM sequence memory accesses during execution FSAVE FSTENV their counterparts FNSAVE FNSTENV) touches enabled data breakpoint location, data breakpoint exception (interrupt occurs instruction. however sequence memory accesses cross segment limit after touching data breakpoint location, General Protection (GP) fault will occur. This erratum that processor branches fault handler, valid data breakpoint forgotten.
Problem:
Implication:
This erratum will only seen software hardware developers using data breakpoint feature debug registers. cause data breakpoints both lost, asserted prematurely, long contributing errors remain uncorrected. following: General solution: problems occur, error must caused preceding instruction, problem operand causes segment limit violation. These errors indicated normal way, despite this erratum. Eliminate them this erratum disappears, allowing data breakpoint debugging proceed normally. Since debugging usually done successive stages, this workaround usually performed part debugging process. Problem also handled blocking INTR during debugging.
Workaround:
Status:
steppings affected Summary Table Changes.
Problem:
Event Monitor Counting Discrepancies
Pentium processor contains registers which count occurrence specific events used measure monitor various parameters which contribute performance processor. There several conditions where counters operate specified. some cases possible same instruction cause "Breakpoint match" (event 100011, 100100, 100101 100110) event counter incremented multiple times same instruction. Instructions which generate exceptions stalled restarted several times causing counter incremented every time instruction restarted. addition, FLUSH# STPCLK# asserted during matched breakpoint data breakpoint instruction, counter will incremented twice. counter will (incorrectly) incremented matched instruction generates exception exception handler does IRET which sets resume flag. counter will also incremented data breakpoint match u-pipe instruction paired instruction v-pipe generates exception. "Hardware interrupts" (event 100111) event counter counts number taken INTR NMIs. event that both INTR/NMI higher priority interrupt present same instruction boundary, higher priority interrupt correctly gets processed first. However, counter prematurely counts INTR/NMI taken count incorrectly gets incremented. "Code breakpoint match" (event 100011, 100100, 100101 100110) event counter also fail incremented some cases. there code breakpoint match instruction there also single-step data breakpoint interrupt pending, code breakpoint match counter will incremented.
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"Non-cacheable memory reads" (event 0111110) event counter defined count noncacheable instruction data memory read cycles. Reads memory space supposed counted. However, counter incorrectly gets incremented reads memory space. "Instructions executed" (event 010110) "Instructions executed v-pipe" (event 010111) event counters both supposed incremented when exception recognized. However, instruction v-pipe generates exception second exception occurs before execution first instruction exception handler first exception, counter incorrectly does incremented first exception. "Stall write state line" (event 011011) event counter counts number clocks processor stalled data memory write state line internal data cache while either write buffers empty EWBE# asserted. However, does count stalls while write buffers empty, only counts number clocks stalled while EWBE# asserted. "Code miss" (event 001101) "Data miss" (event 000010) event counters incorrectly incremented twice instruction that misses code data that misses data also causes exception. "Data read miss" (event 000011) "Data write miss" (event 000100) event counters incorrectly incremented twice access cache misaligned. "Bank conflicts" (event 001010) event counter incremented more than once v-pipe access takes more than clock execute. "Misaligned data memory References" (event 001011) incorrectly gets incremented twice access caused FSTP instruction. "Pipeline flushes" (event 010101) event counter incorrectly incremented some segment descriptor loads VERR instruction. "Pipeline stalled waiting data memory read" (event 011010) event counter incorrectly counts misaligned access clocks instead clocks, unless misses TLB.
Implication: Workaround: Status:
event monitor counters report inaccurate count certain events. None identified this time. steppings affected Summary Table Changes.
Problem:
VERR Type Instructions Causing Page Fault Task Switch with Corrupt CS:EIP
This erratum only occur during debugging with Page Fault Handler's TSS. requires following very specific sequence events: descriptor read caused VERR type instruction must trigger page fault. (These instructions VERR, VERW, LSL. They each selector access selected descriptor perform some checks it.) must have page fault handler separate task, page fault causes task switch. page fault handler's must set, which would normally cause branch interrupt (debug exception) handler. interrupt handler must present code segment.
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present code segment should cause branch interrupt However, because this erratum, execution begins invalid location selected from page fault handler with value pointing instruction just beyond VERR type instruction.
Implication:
This erratum will only seen software hardware developers setting page fault handler's debugging. requires that page fault handler separate task, which done standard Even when these conditions met, other conditions will cause this erratum occur only infrequently. When does occur, processor will execute invalid erroneous instructions. Depending software system configuration, developer will typically application error message system reset. debugging system which page fault handler separate task, following: page fault handler's TSS. Ensure that code segment where debug exception handler starts always present system memory during debugging.
Workaround:
Status:
steppings affected Summary Table Changes.
Problem:
BUSCHK# Interrupt Wrong Priority
Section Pentium® Processor Family Developer's Manual lists priorities external interrupts, with BUSCHK# highest BUSCHK# interrupt, machine check exception, enabled setting CR4), INTR lowest. also specified that STPCLK# very lowest priority external interrupt those Pentium processors provided with (all CPUs with core frequency above). Consistently with this specification, blocks other external interrupts once execution BUSCHK# exception handler begins. However this erratum change effective priority given assertion BUSCHK# following cases: CASE 1:An additional external interrupt (except INTR) debug exception occurs during narrow window after begins transfer control BUSCHK# handler, before first instruction handler begins execution. this case, other interrupt serviced before BUSCHK# serviced. Thus other interrupts that occur during this narrow window, BUSCHK# effectively treated next lowest priority interrupt instead highest. CASE following conditions must apply this case cause erratum: machine check request (INT pending FLUSH# SMI# request pending single step data breakpoint exception (INT pending IO_Restart feature enabled (i.e., TR12 set) Given above conditions, interrupt priority logic does recognize machine check exception highest priority. processor will service FLUSH#/SMI# debug exception (INT Instead, will generate illegal opcode exception (INT
Implication:
Most systems BUSCHK# thus unaffected this erratum. those that BUSCHK#, allows system signal unsuccessful completion cycle. This would only occur defective system. (Since BUSCHK# "abort" type exception, cannot used handle problem from which intends recover; BUSCHK# always requires system reset.)
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this erratum, BUSCHK# interrupt would either occasionally displaced another interrupt (which incorrectly would serviced first) unexpected illegal opcode exception (INT would generated pending machine check would skipped. Depending system also severity defect, this delay BUSCHK# interrupt (case above) could cause system hang reset before cycle error message displayed BUSCHK# interrupt. case above where illegal opcode exception (INT generated instead machine check exception, properly architected handler will usually require reset since this handler erroneously entered without illegal opcode. event, normal outcome cycle error require system reset, practical result this erratum just occasional loss proper error message defective system. Another problem occur this erratum system using instruction restart feature. This problem requires improbable coincidence: SMI# signal caused restart event must occur essentially simultaneously with BUSCHK#, such that SMI# interrupt hits narrow window described above) just before first instruction BUSCHK# handler begins execution. This could happen same instruction that triggers SMI# (usually turn back device that's been turned save power) also generates failure system suddenly going defective, thus signaling BUSCHK#. result that SMI# interrupt serviced after already been switched point first instruction BUSCHK# handler, instead instruction. code that services restart feature well image SMRAM state save memory inspect instruction, example determine what address it's trying access. this case, restart part code will find correct instruction. well written, will execute when determines there valid access service. Then execution returns BUSCHK# handler with deleterious impact. less robust code might turn wrong device, hang begin executing from random location.
Workaround:
design system which relies BUSCHK# highest priority interrupt. using SMM, BUSCHK# all. Note that Case does apply steppings 66-MHz Pentium processors.
Status:
steppings affected Summary Table Changes.
Problem:
Matched Disabled Data Breakpoint Lost STPCLK# Assertion
Assertion STPCLK# interfere with feature described Intel Architecture Software Developer's Manual, Volume Section 14.2.3: "The processor sets bits breakpoints which match conditions present time debug exception generated, whether they enabled." When debug exception generated, breakpoints which match conditions present that time flagged temporary register. STPCLK# asserted after this, before control transferred debug exception handler (interrupt matched disabled data breakpoint transferred from temporary register. That result STPCLK# assertion, corresponding that breakpoint DR6. This feature (defining disabled breakpoints) used debugging; e.g., disabled data breakpoint memory location then check corresponding DR6, location been accessed most recent (main code) instruction, time debug handler some other reason. This erratum will sometimes cause this debug feature fail bit, when STPCLK# also being used. following: only enabled data breakpoints when STPCLK# asserted.
Implication:
Workaround:
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Disable assertion STPCLK# while this debug feature being used.
Status:
steppings affected Summary Table Changes.
Problem:
STPCLK# Ignored When INIT Pending
INIT pending while mode, STPCLK# asserted, stop clock interrupt serviced. correct operation stop clock request serviced while SMM, regardless pending INIT. stop clock request blocked until after processor exits services pending INIT. processor then services lower priority stop clock interrupt. None identified this time. steppings affected Summary Table Changes.
Implication: Workaround: Status:
Problem:
Fault Causing Page Fault Cause Instruction Execute Twice
When processor encounters exception while trying begin handler prior exception, should able handle serially (i.e., second fault handled then faulting instruction restarted, which causes first fault again, whose handler should begin properly); not, signals double-fault exception. "contributory" exception followed another contributory exception causes double-fault, contributory exception followed page fault both handled. (See Intel Architecture Software Developer's Manual, Volume Section 5.12, Interrupt list contributory exceptions other details.) This erratum occurs under following circumstances: these three contributory faults: (stack fault), (General Protection), (alignment check), caused instruction v-pipe. Then page fault occurs before first instruction contributory fault handler fetched. (This means that page fault that occurs because handler starts present page will cause this erratum.) result that execution correctly branches page fault handler, incorrect return address pushed stack: address (immediately preceding) u-pipe instruction, instead v-pipe instruction that caused faults. This causes u-pipe instruction executed extra time, after page fault handler finished.
Implication:
When this erratum occurs, instruction will (incorrectly) executed, effectively, twice row. many instructions (e.g., MOV, AND, will have effect, some instructions cause incorrect answer (e.g., would increase destination double correct amount). However, page fault (during transfer handler fault #12, #17) required this erratum occur happen only three unusual cases: alignment check fault handler placed privilege level push return address could cause page fault, thus causing this erratum. (Fault only invoked from level legal have handler level Fault handlers must always level since they invoked from level push return address level stack must cause page fault, because allowed that happen, push return address regular page fault could cause second page fault, which causes double-fault crashes OS.) descriptor fault handler's code segment either current LDT) present page, page fault occurs which causes this erratum. defined fault handler separate task, page fault occurs while bringing initial segments, this erratum will occur.
Advance Information Datasheet
Extended Temperature Pentium® Processor with MMXTechnology
Workaround:
following steps must taken (but part normal strategy, done order optimize speed access elements, minimize chances bugs): allowing alignment fault (#17), place handler level allow current "swapped out" during virtual memory management paging. separate task interrupts steppings affected Summary Table Changes.
Status:
Problem:
Machine Check Exception Pending, then HLT, Cause Skipped Incorrect Instruction, Hang
This erratum occur machine check exception pending when encounters instruction, occurs while state. (the BUSCHK# error could caused executing previous instruction, code prefetch.) Before checking pending interrupts, instruction issues special cycle, sets special internal flag indicate that state. machine check exception (MCE) then detected, present branches handler, without clearing special flag source this erratum. when other interrupts break into HLT, return address that next instruction after HLT, execution continues there after return from handler. Except (and some cases debug interrupt), interrupts clear special flag before executing their handlers. erratum that causes logic clear flag this case have following consequences: NMI, INTR enabled, occurs while flag set, logic assumes instruction immediately following interrupt HLT. places address instruction after that stack, which means that upon return from interrupt, instruction immediately following interrupt occurrence skipped over. FLUSH asserted while flag set, flushes cache then returns state. extracted from state INTR, logic assumes that current CS:EIP points instruction, pushes address next instruction stack, instruction immediately following FLUSH# assertion skipped over. executed while flag set, again logic assumes that must have been interrupted SMI, this case) while state. Normally, would cause branch back instruction that aborted when entering SMM. thi
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