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Low-Power Embedded Pentium® Processor with MMX Technology

Order Number: 273184-003 September, 1999

Low-Power Embedded Pentium® Processor with MMX Technology
Datasheet
Product Features
Support for MMX Technology Low-Power 0.25 Micron Process Technology - 1.9 V (166 / 266 MHz) Core Supply for PPGA - 1.8 V (166 MHz) or 2.0 V (266 MHz) Core Supply for HL-PBGA - 2.5 V I / O Interface (166 / 266 MHz) 32-Bit CPU with 64-Bit Data Bus Fractional Bus Operation - 166-MHz Core / 66-MHz Bus - 266-MHz Core / 66-MHz Bus Superscalar Architecture - Enhanced Pipelines - Two Pipelined Integer Units Capable of Two Instructions / Clock - Pipelined MMX Technology - Pipelined Floating-Point Unit
Separate Code and Data Caches - 16-Kbyte Code, 16-Kbyte Write-Back Data - MESI Cache Protocol Compatible with Large Software Base - MS-DOS, Windows, OS / 2, UNIX 4-Mbyte Pages for Increased TLB Hit Rate IEEE 1149.1 Boundary Scan Advanced Design Features - Deeper Write Buffers - Enhanced Branch Prediction Feature - Virtual Mode Extensions Internal Error Detection Features On-Chip Local APIC Controller Power Management Features - System Management Mode - Clock Control 296-pin PPGA or 352-ball HL-PBGA
The Low-Power Embedded Pentium Processor with MMX Technology in the HL-PBGA package is also available in extended temperature ranges from -40°C to +115°C. For more information, see the Extended Temperature Pentium® Processor with MMX Technology datasheet, order number 273232.
Order Number: 273184-003 September, 1999
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Contents
1.0 2.0 Introduction ......................................................... 7
Architecture Overview ............................................... 8
Packaging Information ..............................................14
Electrical Specifications ............................................43
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
4.5.2 Undershoot............................................... 59 4.5.3 Ringback ................................................ 60 4.5.4 Settling Time ............................................. 61 4.5.5 Measurement Methodology.................................. 62 Measuring Maximum Overshoot, Undershoot and Ringback............... 63 Measuring Overshoot Threshold Duration ............................. 63 Measuring Undershoot Threshold Duration ............................ 63
Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pentium® Processor with MMX Technology Block Diagram.............. 11 PPGA Package Top Side View ...................................... 15 PPGA Package Pin Side View ...................................... 16 HL-PBGA Package Top Side View ................................... 19 HL-PBGA Package Pin Side View ................................... 20 EAX Bit Assignments for CPUID..................................... 30 EDX Bit Assignments for CPUID..................................... 30 PPGA Package Dimensions ........................................ 36 HL-PBGA Package Dimensions..................................... 38 Technique for Measuring TC ........................................ 40 Thermal Resistance vs. Heatsink Height, PPGA Packages ................ 41 Thermal Resistance vs. Airflow for HL-PBGA Package................... 42 Clock Waveform................................................. 52 Valid Delay Timings .............................................. 52 Float Delay Timings .............................................. 52 Setup and Hold Timings........................................... 53 Reset and Configuration Timings.................................... 53 Test Timings.................................................... 54 Test Reset Timings ............................................... 54 First Order Input Buffer Model....................................... 55 First Order Output Buffer Model..................................... 56 Maximum Overshoot Level, Overshoot Threshold Level and Overshoot Threshold Duration ...................................... 59 Maximum Undershoot Level, Undershoot Threshold Level and Undershoot Threshold Duration .................................. 60 Maximum Ringback Associated with the Signal High State................ 61 Maximum Ringback Associated with the Signal Low State................. 61 Settling Time .................................................... 62
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Tables
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Introduction
Processor Features
The low-power embedded Pentium processors with MMX technology for high performance embedded applications (166 and 266 MHz) are fully compatible with the existing Pentium processors with MMX technology (200 and 233 MHz) with the following differences: voltage supplies, power consumption, and performance. Additionally, Pentium processors with MMX technology are socket compatible with the Pentium processor (100, 133, and 166 MHz), making it possible to design a flexible motherboard that supports both the Pentium processor and the embedded Pentium processors with MMX technology (166-266 MHz). The low-power embedded Pentium processor with MMX technology has all the advanced architectural and internal features of the desktop version of the Pentium processor with MMX technology, except that several features have been eliminated. The differences are specified in "Differences from Desktop Processors" on page 14. The low-power embedded Pentium processor with MMX technology has several features which allow for high-performance embedded designs. These features include the following:
1.9 V core (PPGA - 166 / 266 MHz) 1.8 V core (HL-PBGA - 166), 2.0 V core (HL-PBGA - 266) 2.5 V I / O buffer VCC3 inputs to reduce power consumption SL Enhanced feature set
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Architecture Overview
The low-power embedded Pentium processor with MMX technology extends the family of Pentium processors with MMX technology. It is binary compatible with the 8086 / 88, 80286, Intel386 DX, Intel386 SX, Intel486 SX, IntelDX2TM, IntelDX4TM, and Pentium processors with voltage reduction technology (75-150 MHz). The embedded Pentium processor family consists of the embedded Pentium processor (100, 133, and 166 MHz), the embedded Pentium processor with voltage reduction technology (133 MHz), the embedded Pentium processor with MMX technology (200, 233 MHz), and the low-power embedded Pentium processor with MMX technology (166, 266 MHz). The low-power embedded Pentium processor with MMX technology contains all of the features of previous Intel architecture processors and provides significant enhancements and additions, including the following:
Support for MMX Technology Superscalar Architecture Enhanced Branch Prediction Algorithm Pipelined Floating-Point Unit Improved Instruction Execution Time Separate 16-Kbyte Code Cache and 16-Kbyte Data Cache Writeback MESI Protocol in the Data Cache 64-Bit Data Bus Enhanced Bus Cycle Pipelining Address Parity Internal Parity Checking Execution Tracing Performance Monitoring IEEE 1149.1 Boundary Scan System Management Mode Virtual Mode Extensions 0.25 Micron Process Technology SL Power Management Features Pool of Four Write Buffers Used by Both Pipes
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Pentium® Processor Family Architecture
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
As more and more functions are integrated on-chip, the complexity of board level testing is increased. To address this, the Pentium processors have increased test and debug capability. The Pentium processors implement IEEE Boundary Scan (Standard 1149.1). In addition, the Pentium processors have specified four breakpoint pins that correspond to each of the debug registers and externally indicate a breakpoint match. Execution tracing provides external indications when an instruction has completed execution in either of the two internal pipelines, or when a branch has been taken. System Management Mode (SMM) has been implemented along with some extensions to the SMM architecture. Enhancements to virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. Figure 1 shows a block diagram of the Pentium processor with MMX technology. The block diagram shows the two instruction pipelines, the "u" pipe and "v" pipe. The u-pipe can execute all integer and floating-point instructions. The v-pipe can execute simple integer instructions and the FXCH floating-point instructions. The separate code and data caches are shown. The data cache has two ports, one for each of the two pipes (the tags are triple ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Figure 1. Pentium® Processor with MMX Technology Block Diagram
Branch Prefetch Target Buffer Address
TLB Code Cache 16 Kbytes
Instruction Pointer Branch Verif. & Target Addr.
Prefetch Buffers Instruction Decode Control ROM
64-Bit Data Bus 32-Bit Address Bus
Control Unit Page Unit Bus Unit
V Pipeline Connection U Pipeline Connection
Floating-Point Unit Control
Control
Address Generate
MMX Technology Unit
Register File Add Divide Multiply 80 80
(U Pipeline) (V Pipeline)
Integer Register File ALU
(U Pipeline) Barrel Shifter 64 64-Bit Data Bus Data Control 32-Bit Address Bus
(V Pipeline)
Data Cache 16 Kbytes TLB
A5920-01
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Pentium® Processor with MMX Technology
Full Support for Intel MMX Technology
MMX technology is based on the SIMD technique (Single Instruction, Multiple Data) which enables increased performance on a wide variety of multimedia and communications applications. Fifty-seven new instructions and four new 64-bit data types are supported in the Pentium processor with MMX technology. All existing operating system and application software are fullycompatible.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
16-Kbyte Code and Data Caches
On-chip level-1 data and code cache sizes are 16 Kbytes each and are 4-way set associative on the Pentium processor with MMX technology. Large separate internal caches improve performance by reducing average memory access time and providing fast access to recently-used instructions and data. The instruction and data caches can be accessed simultaneously while the data cache supports two data references simultaneously. The data cache supports a write-back (or alternatively, writethrough, on a line-by-line basis) policy for memory updates.
Improved Branch Prediction
Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by predicting the most likely set of instructions to be executed. The BTB has been improved on the Pentium processor with MMX technology to increase its accuracy. This processor has four prefetch buffers that can hold up to four successive code streams.
Enhanced Pipeline
Deeper Write Buffers
A pool of four write buffers is now shared between the dual pipelines to improve memory write performance.
0.25 Micron Technology
The 0.25 micron technology is the state-of-the-art CMOS manufacturing process Intel unveiled on April 12, 1997, enabling the use of lower core supply to sub-2 V. As a result, the low-power embedded Pentium processor with MMX technology consumes significantly less power at even higher speeds.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Packaging Information
Differences from Desktop Processors
The following features have been eliminated in the low-power embedded Pentium processor with MMX technology: Upgrade, Dual Processing (DP), and Master / Checker functional redundancy. Table 1 lists the corresponding pins that exist on the Pentium processor with MMX technology but have been removed on the low-power embedded Pentium processor with MMX technology.
Table 1.
Signals Removed from the Low-Power Embedded Pentium® Processor with MMX Technology
Signal ADSC# Function Additional Address Status. This signal is mainly used for large or standalone L2 cache memory subsystem support required for high-performance desktop or server models. Additional Burst Ready. This signal is mainly used for large or standalone L2 cache memory subsystem support required for high-performance desktop or server models. CPU Type. This signal is used for dual processing systems. Dual / Primary processor identification. This signal is only used for an upgrade processor. Functional Redundancy Checking. This signal is only used for error detection via processor redundancy and requires two Pentium processors (master / checker). Private Bus Grant. This signal is only used for dual processing systems. Private Bus Request. This signal is used only for dual processing systems. Private Hit. This signal is only used for dual processing systems. Private Modified Hit. This signal is only used for dual processing systems.
BRDYC# CPUTYP D / P# FRCMC# PBGNT# PBREQ# PHIT# PHITM#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
PPGA Pinout and Pin Descriptions
The text orientation on the top side view drawings in this section represents the orientation of the ink mark on the actual packages. (Note that the text shown in this section is not the actual text that will be marked on the packages).
Figure 2. PPGA Package Top Side View
NC D9 D11 D15 VCC3 DP0 D10 D13 D18 VSS A22 VCC3 VSS VCC3 VSS VCC3 NC INTR NMI A24 A21 A23 VSS A28 A25 A26 A27 VSS A30 A3 A29 A31 NC A4 A7 A5 A6 A8 A11 A9 A10 VCC3 VSS A12 A13 VCC3 VCC3 VCC3 VCC3 VCC2 VCC2 VCC2 VCC2 VCC2
VCC2 FLUSH# VSS W / R#
VSS A14
VSS A16 A15
VSS A18 A17
VSS A20 A19
VSS NC
EADS#
SCYC CLK
BE0# BUSCHK# HITM# A20M# HIT#
PWT VCC2DET AP BREQ
RESET
LOCK#
PCD SMIACT# VCC2 PCHK# APCHK# VC NC PRDY NC NC VSS VCC2 VSS VCC2
SMI# INIT
HOLD BUSCHK# VSS
WB / WT# NC VCC2 VSS
VCC3 IGNNE# VSS VCC3 VSS VCC3 NC NC BF1
PEN# BF0
BOFF# BOFF#
NC BRDYC# VCC2
VSS VCC2
BRDY# BF2 KEN#
EWBE#
VSS STPCLK# VCC3 VSS VCC3 VSS VCC3 VSS VCC3 VSS VCC3 TDI TCK VCC3 NC NC NC TRST# TMS TDO VSS VCC3
AHOLD#
Top Side View
CACHE# VCC2 VSS VCC2 VSS
VCC3 NC
MI / O# BP3 BP2
PM1BP1
FERR# PM0BP0# VCC2 IERR# DP7 D62 D60 D59 D58 D56 D53 DP5 D51 D49 D44 DP4 VSS VSS D41 D45 D43 NC D48 D47 NC D52 D50 NC D55 D57 D61 D63 VSS VCC2 VSS VCC2 VSS VCC2 VSS VCC2 DP6 D54
PICD1 D0 D2
VSS VCC3 VSS VCC3 D4 D6
PICD0
PICCLK D1 D5 D7 D8 D14 D16 D22 D12 D17 DP1 D42 D46 D40 D38 VSS D3
D19 DP19
D21 D24 VSS
D23 DP2 VSS
D26 D25 VSS
D28 D27 VSS
D30 D29 VSS
DP3 D31 VSS
D33 D32 VSS
D35 D34 VSS
D37 D36 VSS
D20 D29
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Figure 3. PPGA Package Pin Side View
NC NC NC D54 D50 D47 D43 D41 BREQ NC NC
VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC3 VCC3 VCC3 VSS A12 A13 A9 A11 A5 A31 A26 A27 A21 A23 INTR NC A24 A10 A8 A7 A29 A25 A22 VCC3 VSS VCC3 VSS VCC3 VSS VCC3 A6 A4 A3 A28 VSS NC A30 VSS VSS
FLUSH# VCC2 W / R# VSS
EADS#
VSS NC
VSS A20
VSS A18 A19
VSS A16 A17
VSS A14 A15
VCC2DET PWT
HITM# BUSCHK# BE0# HIT# A20M#
SCYC CLK
RESET
LOCK#
VCC2 SMIACT# PCD VSS VCC2 VSS VCC2 NC PCHK# NC APCHK# VC NC PRDY
VSS BUSCHK# HOLD VCC2 VSS NC WB / WT#
SMI# INIT
IGNNE#
BOFF# NA#
PEN# BF0 BF1 BF2 NC NC
VSS VCC3 VSS VCC3
NC VCC2 BRDYC#
VSS VCC2
BRDY# KEN#
EWBE#
AHOLD# INV#
STPCLK# VSS
VCC2 CACHE# VSS VCC2 VSS
Pin Side View
VCC3 VSS
MI / O# BP2 BP3
VCC3 NC NC TRST# TMS TDO TCK NC NC
VCC3 VSS VCC3 VSS
PM1BP1
VCC2 PM0BP0# FERR# VSS VCC2 VSS VCC2 VSS VCC2 VSS VCC2 DP6 D52 D48 D45 VSS D55 D51 D49 D44 DP4 VSS D57 D56 D53 DP5 D46 D40 D38 VSS D42 D39 D36 VSS D37 D34 VSS D35 D32 VSS D33 D31 VSS DP3 D29 VSS D30 D27 VSS D28 D25 VSS D26 DP2 VSS D23 D61 D59 D58 IERR# D63 D62 D60 DP7
IDT TDI
VCC3 VSS VCC3
VCC3 D0 PICD0
PICD1
VSS D2 VCC3 VSS VCC3 D4 D6 VCC3 DP0 D10 D9 D11 D15 NC
PICCLK D3 D5 D7 D1
D19 DP19
D24 VSS D21
DP1 D17
D12 D14 D16 D22 D18
D20 D29
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 2.
Pin Cross Reference by Pin Name (PPGA Package) (Sheet 1 of 2)
Pin Location Pin Location Address A3 A4 A5 A6 A7 A8 A9 A10 AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 A11 A12 A13 A14 A15 A16 A17 A18 AL31 AL29 AK28 AL27 AK26 AL25 AK24 AL23 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 B34 C33 A35 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 D24 C21 D22 C19 D20 C17 Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 AK08 AJ05 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# AJ01 AL07 U03 AK04 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05 HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# AL05 AJ03 AB04 P04 AA35 AA33 AD34 U05 W05 AH04 T04 Y05 AC33 AG05 AF04 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# VCC2DET# W / R# R04 AC05 AL03 AC35 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 AL01 AM06 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 C15 D16 C13 D14 C11 D12 C09 D10 D08 A05 E09 B04 D06 C05 E07 C03 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D04 E05 D02 F04 E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03 A19 A20 A21 A22 A23 A24 A25 A26 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 A27 A28 A29 A30 A31 AG33 AK36 AK34 AM36 AJ33 Pin Location Pin Location
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 2.
Pin Cross Reference by Pin Name (PPGA Package) (Sheet 2 of 2)
Pin BP3 BRDY# Location S05 X04 Pin FLUSH# HIT# Location AN07 AK06 Pin PEN# PM0 / BP0 APIC PICCLK H34 PICD0 J33 PICD1 APICEN BF2 L35 Location Z34 Q03 Pin WB / WT# Location AA05
Clock Control BF0 STPCLK# Y33 V34 BF1 X34 W33 CLK AK18
Table 3.
No Connect, Power Supply and Ground Pin Cross Reference (PPGA Package)
VCC2 A07 A09 A11 A13 VCC3 A19 A21 A23 A25 A27 A29 E37 G37 J37 L37 L33 N37 Q37 S37 T34 U33 VSS B06 B08 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 H02 H36 K02 K36 M02 M36 P02 P36 R02 R36 T02 T36 U35 V02 V36 X02 X36 Z02 Z36 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37 U37 W37 Y37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21 A15 A17 G01 J01 L01 N01 Q01 S01 U01 W01 Y01 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
No Connect (NC) A03 A37 B02 C01 Q35 R34 S33 S35 W35 Y03 Y35 AA03 AC03 AD04 AE03 AE35 AL19 AM02 AN01 AN03 AN05 AN35
NOTE: Shaded pins differ functionally from the Pentium® Processor with MMX Technology pinout.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
HL-PBGA Pinout and Pin Descriptions
Figure 4. HL-PBGA Package Top Side View
LOCK# INC
D61 D59 D57 DP6 D54 D52 D51 INC INC INC INC
BOFF# KEN# AHOLD M / IO# PM1 / BP1 IERR# WB / WT# EWBE# PM0 / BP0 VSS VCC2 NA# VSS BRDY# VCC2 VSS INV VSS CACHE# VSS VSS BP2 FERR# VSS VSS DP7 VSS
INC APCHK# PRDY
SMIACT# VSS
D62 VSS
D60 VSS
D58 VSS
D56 VSS
D55 VSS
D53 VCC3 VSS
D48 DP5 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VSS
D47 VSS
D46 D44
D43 D41
BREQ VSS PCHK# VSS VSS VCC2 VCC3 VCC2 VCC3 VCC3
VCC2 VCC3 VSS VSS
AP VSS VSS
VCC2 VCC3 VCC2
VCC2 VCC3 VCC3
VCC2 VCC2
VCC3 VCC2 VCC3 VCC2
VCC3 VCC2
D45 VSS VSS VSS VSS VSS
D40 D39
D38 D37
EADS#
PCD VSS
D35 D32
D36 D34
FLUSH# HIT# HITM# VCC3 BE0# BE2# V BUSCHK# SS BE1# A20M# VSS VSS VSS VCC3 INC VCC3 VCC3 VSS VCC2 VCC3 VCC2 VSS VSS VSS VCC3 VCC3
D26 VSS
D29 D27
DP3 D30
BE3# BE5#
BE4# BE7#
Top View
VCC3 VSS VCC3 VCC3 VCC3 VCC3 VSS VCC3 VSS VCC2
D21 VSS VSS VSS
D20 D17 DP1 D13
D19 D18 D16 D15 D14
SCYC RESET VCC2 NC A19 VSS VSS
VCC3 V CC2 VSS VCC3
VCC2 V CC3 VSS VCC2 VCC2 VSS
D8 INC
A12 INC
A11 A10
VSS VSS
VCC2 VSS
VCC3 VCC2 VCC3 VSS
VCC3 VCC2 VSS VSS
VCC3 VCC3 VSS VSS
VCC3 VSS
INC INC
VCC2 VSS
VCC2 VCC2 VSS VSS
VCC3 VCC2 VCC2 VSS VSS VCC2 VSS
VCC2 VCC2 VSS VSS VSS
VCC3 VCC2
D1 INC
INC INC
VSS PICD0 VSS
SMI# NMI / LINT1 RS#
BF0 BF2
VCC2 VCC2
TCK PICCLK INC
IGNNE# PEN# BF1 STPCLK# NC INTR / LINT0
TRST#
PICD1
A4694-01
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Figure 5. HL-PBGA Package Pin Side View
DP4 D42 D45 VSS VSS VSS VSS VSS INC INC INC INC D51 D52 D54 DP6 D57 D59 D61 D63 IERR#
INC INC
PM1 / BP1 M / IO# EWBE# AHOLD KEN# BOFF# HOLD PM0 / BP0 WB / WT# VSS CACHE# VSS INV BRDY# VSS VCC2 VCC2 VSS NA# VSS VCC2 VSS VCC2 SMIACT#
D43 D41
D46 D44
D47 VSS
D55 VSS VCC2
D56 VSS
D58 VSS
D60 VSS
D62 VSS
DP7 FERR# BP2 VSS VSS VSS
PRDY APCHK# INC VSS BREQ VSS VSS VCC2
DP5 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC2 VSS VCC3 VSS VCC3 VCC3 VCC3 VCC3 VSS VCC3 VSS VCC2 VSS
VCC2 VCC3 VSS VSS
VSS PCHK# VCC3 VCC2 VCC3 VCC3
VCC3 VCC2
VCC3 VCC2 VCC3 VCC2 VCC2 VCC3 VCC3
VCC3 VCC2
AP VSS VSS
LOCK# INC
D38 D40 D39
D36 D34
D35 D32
PCD VSS
EADS#
VCC3 HITM# HIT# FLUSH# VCC3 INC VCC3 VSS BE0# BUSCHK# BE2#
DP3 D30
D29 D27
D26 VSS
A20M# BE1# VSS VSS VSS
BE4# BE7#
BE3# BE5#
D19 D18 D16 D15 D14
D20 D17 DP1 D13
D21 VSS VSS VSS
Bottom View
VCC3 VSS
VCC2 VCC2 RESET SCYC VCC3 VCC2 VSS VSS VSS VCC3 VCC3 VSS VSS A19 NC
VCC2 VCC3 VCC3 VSS
D8 INC
VCC3 VCC2 VCC2 VSS VSS VCC2
INC INC
D1 INC
VCC2 VSS
VCC2 VCC2 VCC2 VSS VCC2 VSS
VCC3 VCC2 VCC2 VSS VCC2 VSS VSS
VCC2 VCC2 VSS VSS
VCC3 VCC3 VSS VSS
VCC3 VCC2 VCC3 VSS VSS VSS
VCC2 VCC3 VSS VCC3
VCC2 VSS
VSS VSS
A11 A10
A12 INC
VSS PICD0 VSS
INC PICCLK TCK
VSS VCC2
NMI / LINT1
INC PICD1 TD0
TRST#
NC STPCLK# BF1 PEN# IGNNE# RS# INTR / LINT0
A4695-01
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 4.
Pin Cross Reference by Pin Name (HL-PBGA Package) (Sheet 1 of 2)
Pin Location Pin Location Address A3 A4 A5 A6 A7 A8 A9 A10 AE6 AF5 AE5 AF4 AE4 AE3 AE2 AD2 A11 A12 A13 A14 A15 A16 A17 A18 AC2 AC1 AB1 AA1 Y1 W1 V1 U2 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 AC24 AC25 AB24 AB25 AA24 Y24 AA25 Y25 Y26 V24 W25 V25 W26 U25 V26 U26 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 T26 R25 R26 P26 P25 P24 N24 N25 M24 M25 K24 L25 M26 K25 L26 J25 Control A20M# ADS# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 L3 H2 A9 D2 B3 K1 L2 L1 M1 M2 N1 P1 N2 A7 B12 BREQ BUSCHK# CACHE# D / C# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# C2 K2 B10 F1 W24 T25 N26 K26 D26 C23 A19 B14 G1 A10 B13 HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# J3 C1 A5 A14 AF14 AE14 AF13 B9 A8 D1 A11 B7 AE12 G3 C4 PM1 / BP1 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# W / R# WB / WT# A12 B4 G2 AF12 R2 R1 AE13 B5 AE22 AE21 AF21 AF20 AF19 H1 A6 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 H25 J26 H26 G25 G26 F26 E26 F25 E25 C26 D25 B26 C25 D24 B25 B24 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 B23 B22 B21 A22 A21 B20 A20 B19 B18 A18 B17 A17 B16 A16 B15 A15 A19 A20 A21 A22 A23 A24 A25 A26 T2 U1 AF11 AE11 AF10 AF9 AE10 AF8 A27 A28 A29 A30 A31 AE9 AF7 AE8 AF6 AE7 Pin Location Pin Location
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 4.
Pin Cross Reference by Pin Name (HL-PBGA Package) (Sheet 2 of 2)
Pin BP3 BRDY# Location C11 B8 Pin FLUSH# HIT# Location J1 J2 Pin PEN# PM0 / BP0 APIC PICCLK AE23 PICD0 AD23 PICD1 APICEN AF22 Location AF15 A13 Pin Location
Clock Control BF0 STPCLK# AE15 AF17 BF1 AF16 BF2 AE16 CLK P2
Table 5.
No Connect, Power Supply and Ground Pin Cross Reference (HL-PBGA Package)
VCC2 C6 C8 C21 D5 D7 D9 D12 D13 D15 D17 D19 E4 F3 L23 R3 R4 U4 V3 Y2 AA3 VCC3 C20 C22 D4 D6 D10 D11 D14 D16 D18 D23 E23 F4 VSS B6 B11 C3 C5 C7 C9 C10 C12 C13 C14 C15 C16 C17 C18 C19 C24 D3 D8 D20 D21 D22 E2 E3 E24 F2 F24 G24 H3 H24 J24 K3 L24 M3 M23 N3 P3 P4 P23 R24 T3 T24 U3 U24 V4 W2 W4 W23 Y4 AA2 AA23 AB3 AC3 AD3 AD4 AD6 AD7 AD8 AD9 AD10 AD11 AD13 AD14 AD15 AD16 AD17 AD18 AD20 AD21 AD22 AD24 AE19 AE20 F23 G4 G23 H23 J4 J23 K4 K23 M4 N4 N23 R23 T4 T23 U23 V2 V23 W3 Y3 Y23 AA4 AB4 AC5 AC7 AC9 AC10 AC11 AC17 AC22 AD5 AB2 AB23 AC4 AC6 AC8 AC13 AC14 AC15 AC16 AC18 AC19 AC20 AC21 AC23 AD19 AE17 AE18
No Connect (NC) AF18 T1 Internal No Connect (INC) A1 A2 A3 A4 A23 A24 A25 A26 B1 B2 E1 H4 L4 AA26 AB26 AC12 AC26 AD1 AD12 AD25 AD26 AE1 AE24 AE25 AE26 AF1 AF2 AF3 AF23 AF24 AF25 AF26
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to GND (VSS). No Connect (NC) pins must remain unconnected. Connection of NC pins may result in component failure or incompatibility with processor steppings.
Pin Quick Reference
Table 6.
Quick Pin Reference (Sheet 1 of 6)
Symbol Type Name and Function When the address bit 20 mask pin is asserted, the Pentium® processor with MMX technology emulates the address wraparound at 1 Mbyte, which occurs on the 8086. When A20M# is asserted, the processor masks physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus. The effect of A20M# is undefined in protected mode. A20M# must be asserted only when the processor is in real mode. As outputs, the address lines of the processor along with the byte enables define the physical area of memory or I / O accessed. The external system drives the inquire address to the processor on A31-A5. The address status indicates that a new valid bus cycle is currently being driven by the processor. In response to the assertion of address hold, the processor will stop driving the address lines (A31-A3) and AP in the next clock. The rest of the bus will remain active so data can be returned or driven for previously issued bus cycles. Address parity is driven by the processor with even parity information on all processor generated cycles in the same clock that the address is driven. Even parity must be driven back to the processor during inquire cycles on this pin in the same clock as EADS# to ensure that correct parity check status is indicated. The address parity check status pin is asserted two clocks after EADS# is sampled active if the processor has detected a parity error on the address bus during inquire cycles. APCHK# will remain active for one clock each time a parity error is detected. The byte enable pins are used to determine which bytes must be written to external memory, or which bytes were requested by the CPU for the current cycle. The byte enables are driven in the same clock as the address lines (A31-3).
A20M#
A31-A3
AHOLD
APCHK#
BE7#-BE5# BE4#-BE0#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 6.
Quick Pin Reference (Sheet 2 of 6)
BOFF#
APICEN PICD1
BP3-BP2 PM / BP1-BP0
BRDY#
CACHE#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 6.
Quick Pin Reference (Sheet 3 of 6)
D63-D0
DP7-DP0
EADS#
EWBE#
FERR#
FLUSH#
HITM#
IERR#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 6.
Quick Pin Reference (Sheet 4 of 6)
IGNNE#
LOCK#
PCHK#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 6.
Quick Pin Reference (Sheet 5 of 6)
PICCLK PICD0- PICD1 APICEN
RESET
SMIACT#
STPCLK#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 6.
Quick Pin Reference (Sheet 6 of 6)
TMS TRST#
VCC2DET#
VCC2 VCC3 VSS W / R#
Bus Fraction (BF) Selection
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 7.
Bus Frequency Selection
BF2 0 1 BF1 0 0 BF0 0 0 Bus / Core Ratio 2 / 5 1 / 4 Max Bus / Core Frequency (MHz) 66 / 166 66 / 266
NOTE: All other BF2-BF0 settings are reserved on the low-power embedded Pentium processor with MMX technology.
The CPUID Instruction
The CPUID instruction allows software to determine the type and features of the processor on which it is executing. When executing CPUID, the low-power embedded Pentium processor with MMX technology behaves like the Pentium processor and the Pentium processor with MMX technology as follows:
capabilities are returned in EDX. The values of EAX and EDX for the low-power embedded Pentium processor with MMX technology are given below.
31 0 (Reserved) 14 13 12 11 87 43 0
Type Family
Model Stepping
Figure 7. EDX Bit Assignments for CPUID
Reserved
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Bit 0 1 2 3 4 5 6 7 8 9 10-11 12 13 14 15-22 23 24-31 Value 1 1 1 1 1 1 0 1 1 1 R 0 0 0 R 1 R Comments FPU: Floating-point Unit on-chip VME: Virtual-8086 Mode Enhancements DE: Debugging Extensions PSE: Page Size Extension TSC: Time Stamp Counter MSR Pentium® Processor MSR PAE: Physical Address Extension MCE: Machine Check Exception CX8: CMPXCHG8B Instruction APIC: APIC on-chip Reserved - Do not write to these bits or rely on their values MTRR: Memory Type Range Registers PGE: Page Global Enable MCA: Machine Check Architecture Reserved - Do not write to these bits or rely on their values Intel Architecture with MMX technology supported Reserved - Do not write to these bits or rely on their values
Indicates that APIC is present and hardware enabled (software disabling does not affect this bit).
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Boundary Scan Chain List
The boundary scan chain list for the low-power embedded Pentium processor with MMX technology is different than the Pentium processor with MMX technology due to the removal of some pins. The boundary scan register for the low-power embedded Pentium processor with MMX technology contains a cell for each pin. Following is the bit order of the low-power embedded Pentium processor with MMX technology boundary scan register (left to right, top to bottom): TDI disapsba, PICD1, PICD0, Reserved, PICCLK, D0, D1, D2, D3, D4, D5, D6, D7, DP0, D8, D9, D10, D11, D12, D13, D14, D15, DP1, D16, D17, D18, D19, D20, D21, D22, D23, DP2, D24, D25, D26, D27, D28, D29, D30, D31, DP3, D32, D33, D34, D35, D36, D37, D38, D39, DP4, D40, D41, D42, D43, D44, D45, D46, diswr , D47, DP5, D48, D49, D50, D51, D52, D53, D54, D55, DP6, D56, D57, D58, D59, D60, D61, D62, D63, DP7, IERR#, FERR#, PM0BP0, PM1BP1, BP2, BP3, MIO#, CACHE#, EWBE#, INV, AHOLD, KEN#, BRDYC#, BRDY#, BOFF#, NA#, WBWT#, HOLD, disbus, disbusl, dismisc, dismisca, SMIACT#, PRDY, PCHK#, APCHK#, BREQ, HLDA, AP, LOCK#, PCD, PWT, DC#, EADS#, ADS#, HITM#, HIT#, WR#, BUSCHK#, FLUSH#, A20M#, BE0#, BE1#, BE2#, BE3#, BE4#, BE5#, BE6#, BE7#, SCYC, CLK, RESET, disabus , A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A31, A30, A29, A28, A27, A26, A25, A24, A23, A22, A21, NMI, RS#, INTR, SMI#, IGNNE#, INIT, PEN#, Reserved, BF0, BF1, BF2, STPCLK#, Reserved, Reserved, Reserved, Reserved TDO "Reserved" includes the no connect "NC" signals on the low-power embedded Pentium processor with MMX technology. The cells marked with a dagger () are control cells that are used to select the direction of bidirectional pins or three-state the output pins. If "1" is loaded into the control cell, the associated pin(s) are three-stated or selected as input. The following lists the control cells and their corresponding pins: Disabus: Disbus: Disbusl: Dismisc: Dismisca: Diswr: Disapsba: A31-A3, AP BE7#-BE0#, CACHE#, SCYC, M / IO#, D / C#, W / R#, PWT, PCD ADS#, LOCK#, ADSC# APCHK#, PCHK#, PRDY, BP3, BP2, PM1 / BP1, PM0 / BP0, FERR#, SMIACT#, BREQ, HLDA, HIT#, HITM# IERR# D63-D0, DP7-DP0 PICD1-PICD0
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 9.
Pin Reference Tables
Output Pins
Name ADS# APCHK# BE7#-BE4# BREQ CACHE# FERR# HIT# HITM#(2) HLDA IERR# LOCK# M / IO#, D / C#, W / R# PCHK# BP3-BP2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC SMIACT# TDO VCC2DET#(3) (1) Active Level Low Low Low High Low Low Low Low High Low Low N / A Low High High High High Low N / A N / A All states except Shift-DR and Shift-IR Differentiates between the Pentium® processor with MMX technology and the low-power embedded Pentium processor with MMX technology Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# When Floated
NOTE: 1. All output and input / output pins are floated during three-state test mode (except TDO). 2. HITM# pin has an internal pull-up resistor. 3. This pin is not on the HL-PBGA pinout.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 10. Input Pins
Name A20M# AHOLD BF0 BF1 BF2 BOFF# BRDY# BUSCHK# CLK EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV KEN# NA# NMI PEN# PICCLK R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT# Active Level LOW HIGH N / A N / A N / A LOW LOW LOW N / A LOW LOW LOW HIGH LOW HIGH HIGH HIGH LOW LOW HIGH LOW HIGH N / A HIGH LOW LOW N / A N / A N / A LOW N / A Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pullup Pullup Pullup Pullup Pullup Pullup First BRDY# / NA# TCK TCK Pullup Pullup BRDY# EADS# First BRDY# / NA# Bus State T2, TD, T2P BRDY# Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous / RESET Synchronous / RESET Synchronous Synchronous Synchronous Pullup Pullup Bus State T2, T12, T2P BRDY# Pulldown Pullup Pulldown Internal Resistor Qualified
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 11. Input / Output Pins
Name A31-A3 AP BE3#-BE0# D63-D0 DP7-DP0 PICD0 PICD1APICEN Active Level N / A N / A LOW N / A N / A N / A N / A When Floated(1) Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# Pullup Pulldown Pulldown(2) Internal Resistor
NOTE: 1. All output and input / output pins are floated during three-state test mode (except TDO). 2. BE3#-BE0# have pulldowns during RESET only.
Pin Grouping According to Function
Table 12. Pin Functional Grouping
Function Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Interrupts Floating-point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Clock Control Debugging CLK RESET, INIT, BF2:0 A31-A3, BE7#-BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD0-PICD1 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, BRDY#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-BP2 STPCLK# R / S#, PRDY Pins
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Mechanical Specifications
In mechanical terms, the low-power embedded Pentium processor with MMX technology 296-lead Plastic Staggered Pin Grid Array (PPGA) is completely identical to the Pentium processor with MMX technology PPGA package. The pins are arranged in a 37x37 matrix and the package dimensions are 1.95" x 1.95" (4.95 cm x 4.95 cm). Package summary information for the PPGA device is provided in Table 13. Figure 8 shows the package dimensions. The HL-PBGA version of the low-power embedded Pentium processor with MMX technology is a new package type for the Pentium processor family. Package summary information for the HLPBGA device is provided in Table 14. Figure 9 shows the package dimensions.
PPGA Package Mechanical Diagrams
Figure 8. PPGA Package Dimensions
Seating Plane D D1 L S1
Solder Resist A2 Chip Capacitor
F1 B 1.65 (Ref) D D2 F2
A 2.29 1.52 45 Chamfer (Index Corner)
Pin C3
Heat Slug
measurements in mm
A5771-01
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 13. PPGA Package Dimensions
Millimeters Symbol Min A A1 A2 B D D1 D2 el L N S1 1.52 0.40 49.43 45.59 23.44 2.29 3.05 296 2.54 0.060 2.72 1.83 1.00 Nominal 0.51 49.63 45.85 23.95 2.79 3.30 0.016 1.946 1.795 0.923 0.090 0.120 296 0.100 Max 3.33 2.23 Min 0.107 0.072 0.039 Nominal 0.020 1.954 1.805 0.943 0.110 0.130 Max 0.131 0.088 Inches
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
HL-PBGA Package Mechanical Diagrams
Figure 9 shows the ceramic HL-PBGA package. The dimensions are listed in Table 14.
Figure 9. HL-PBGA Package Dimensions
D Pin #1 Corner b Pin #1 Corner
Pin #1 I.D. 1.0 Dia. Top View A C
S1 Bottom View
Side View
Seating Plane
Note: 1. All Dimensions are in Millimeters
A5830-01
Table 14. HL-PBGA Package Dimensions
Millimeters Symbol Min A A1 b c D E
Max 1.67 0.70 0.90 0.97 35.10 35.10 1.27 1.63 REF
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Thermal Specifications
The low-power embedded Pentium processor with MMX technology is specified for proper operation when case temperature, TCASE (TC), is within the specified range of 0° C to 85° C for the PPGA package, and 0° C to 95° C for the HL-PBGA package. The Low-Power Embedded Pentium Processor with MMX Technology in the HL-PBGA package is also available in extended temperature ranges from -40°C to +115°C. For more information, see the Extended Temperature Pentium® Processor with MMX Technology datasheet, order number 273232.
Measuring Thermal Values
To verify that the proper TC is maintained, it should be measured at the center of the package top surface (opposite of the pins). The measurement is made in the same way with or without a heatsink attached. When a heatsink is attached, a hole (smaller than 0.150" diameter) should be drilled through the heatsink to allow probing the center of the package. See Figure 10 for an illustration of how to measure TC. To minimize the measurement errors, it is recommended to use the following approach:
· Use 36-gauge or finer diameter K, T, or J type thermocouples. The laboratory testing was done
using a thermocouple made by Omega (part number 5TC-TTK-36-36).
· Attach the thermocouple bead or junction to the center of the package top surface using high
thermal conductivity cements. The laboratory testing was done by using Omega Bond (part number OB-101).
· The thermocouple should be attached at a 90-degree angle as shown in Figure 10. · The hole size should be smaller than 0.150" in diameter. · Make sure there is no contact between thermocouple cement and heatsink base. The contact
will affect the thermocouple reading.
Thermal Equations and Data
For the low-power embedded Pentium processor with MMX technology, an ambient temperature, TA (air temperature around the processor), is not specified directly. The only restriction is that TC is met. The equation used to calculate CA is:
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
JC is thermal resistance from die to package case. JC values shown in Tables 15 and 16 are typical values. The actual JC values depend on actual thermal conductivity and process of die attach. CA is thermal resistance from package case to the ambient. CA values shown in these tables are typical values. The actual CA values depend on the heatsink design, interface between heatsink and package, airflow in the system, and thermal interactions between processor and surrounding components through PCB and the ambient. Figure 10. Technique for Measuring TC
Airflow Calculations for Maximum and Typical Power
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
PPGA Package Thermal Resistance Information
Table 15 lists the JC and CA values for the low-power embedded Pentium processor with MMX technology in the PPGA package with passive heatsinks.
Table 15. Thermal Resistances for PPGA Packages
Heatsink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None JC (°C / watt) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.3 0 8.9 8.6 8.2 7.9 7.5 6.8 6.1 5.7 5.2 12.9 CA (°C / watt) vs. Laminar Airflow (linear ft / min) 100 7.8 7.3 6.8 6.3 5.8 5.1 4.5 4.1 3.7 12.2 200 6.4 5.8 5.1 4.5 4.1 3.7 3.4 3.1 2.8 11.2 400 4.3 3.8 3.4 3.0 2.8 2.6 2.4 2.2 2.0 7.7 600 3.4 3.1 2.7 2.4 2.2 2.0 1.9 1.8 1.7 6.3 800 2.8 2.6 2.3 2.1 1.9 1.8 1.6 1.6 1.5 5.4
NOTES: 1. Heatsinks are omni-directional pin aluminum alloy. 2. Features were based on standard extrusion practices for a given height: pin size ranged from 50 to 129 mils pin spacing ranged from 93 to 175 mils base thickness ranged from 79 to 200 mils. 3. Heatsink attach was 0.005" of thermal grease. Attach thickness of 0.002" will improve performance by approximately 0.3 watt.
Figure 11. Thermal Resistance vs. Heatsink Height, PPGA Packages
CA (°C / watt) Airflow Rate (LFM) 0 100 200 400 600 800
Heatsink Height (inches)
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
HL-PBGA Package Thermal Resistance Information
Table 16 lists the JC values for the low-power embedded Pentium processor with MMX technology in the HL-PBGA package. The thermal data collection conditions were:
A bidirectional anodized aluminum alloy heat sink was used. Heat sink height was 7mm. In the horizontal orientation the component was mounted flush with the motherboard. In the vertical orientation the component was mounted on an add-in card perpendicular to the motherboard.
Table 16. Thermal Resistances for HL-PBGA Packages
Heatsink / Orientation No Heat Sink Horizontal Vertical JC (°C / watt) 0.76 0.76 0.76 CA (°C / watt) vs. Laminar Airflow (linear ft / min) 0 15.66 12.09 11.33 100 12.33 8.57 8.34 200 10.3 6.52 6.38 400 8.85 4.82 4.69 600 7.89 4.06 3.95
Figure 12. Thermal Resistance vs. Airflow for HL-PBGA Package
18 16 14 12 10 8 6 4 2 0 0 100 200 300 Airflow (LFM) Horizontal Heat Sink Vertical Heat Sink No Heat Sink 400 500 600
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Electrical Specifications
This section contains preliminary information on new products in production. The specifications are subject to change without notice.
Warning:
Absolute Maximum Ratings
The following values are stress ratings only. Functional operation at the maximum ratings is not implied nor guaranteed. Functional operating conditions are given in the AC and DC specification tables. Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Pentium processor with MMX technology contains protective circuitry to resist damage from Electrostatic Discharge (ESD), always take precautions to avoid high static voltages or electric fields.
Table 17. Absolute Maximum Ratings
Parameter Case temperature under bias Storage temperature VCC3 supply voltage with respect to VSS VCC2 supply voltage with respect to VSS 2.5 V only buffer DC input voltage -65° C to 110° C -65° C to 150° C -0.5 V to +3.2 V -0.5 V to +2.8 V -0.5 V to VCC3+0.5 V (not to exceed VCC3 max) Maximum Rating
NOTE: The Low-Power Embedded Pentium Processor with MMX Technology in the HL-PBGA package is also available in extended temperature ranges from -40°C to +115°C. For more information, see the Extended Temperature Pentium® Processor with MMX Technology datasheet, order number 273232.
DC Specifications
Tables 19, 20, 21 and 22 list the DC specifications which apply to the low-power embedded Pentium processor with MMX technology.
Power Sequencing
There is no specific sequence required for powering up or powering down the VCC2 and VCC3 power supplies. However, it is recommended that the VCC2 and VCC3 power supplies be either both ON or both OFF within one second of each other. The I / O voltage VCC3 is 2.5 V. The core voltage VCC2 is 1.9 V for PPGA. The core voltage VCC2 for the HL-PBGA package type is 1.8 V (166 MHz) or 2.0 V (266 MHz).
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 18. VCC and TCASE Specifications
0°C to 85°C
Table 19. DC Specifications
Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VCC3 - 0.4 VCC3 - 0.2 Min Max 0.5 VCC3 + 0.3 0.4 Unit V V V V V TTL Level TTL Level, (1) TTL Level, (2) TTL Level, (3) Notes
VCC3 - 0.7
The values in Table 20 should be used for power supply design. The values were determined using a worst case instruction mix and maximum VCC. Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from Stop Clock to full Active modes. Table 20. ICC Specifications
Symbol ICC2 ICC3 Parameter Power Supply Current Min Max 2.35 (HL-PBGA) 2.5 (PPGA) 4.00 0.38 0.38 Unit A A A A A Notes 166 MHz 166 MHz 266 MHz 166 MHz 266 MHz
Power Supply Current
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 21. Power Dissipation Requirements for Thermal Design
Parameter Thermal Design Power Active Power(3) Stop Grant / Auto Halt Powerdown Power Dissipation(4) Stop Clock Power(5) 2.9 4.5 0.70 0.70 0.06 0.06 Typical(1) Max(2) 4.1 (HL-PBGA) 4.5 (PPGA) 7.6 Unit Watts Watts Watts Watts Watts Watts Watts Watts Watts Frequency 166 MHz 166 MHz 266 MHz 166 MHz 266 MHz 166 MHz 266 MHz 166 MHz 266 MHz
Table 22. Input and Output Characteristics
NOTES: 1. This parameter is for inputs / outputs without an internal pull up or pull down. 2. This parameter is for inputs with an internal pull up. 3. This parameter is for inputs with an internal pull down. 4. Guaranteed by design. 5. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
AC Specifications
The AC specifications of the low-power embedded Pentium processor with MMX technology consist of setup times, hold times, and valid delays at 0 pF.
Power and Ground
For clean on-chip power distribution, the PPGA has 25 VCC2 (core power), 28 VCC3 (I / O power) and 53 VSS (ground) inputs. For the HL-PBGA package, there are 42 VCC3, 37 VCC2 and 72 VSS inputs. Power and ground connections must be made to all external VCC2, VCC3 and VSS pins. On the circuit board, all VCC2 pins must be connected to a proper voltage VCC2 plane or island (core voltage determined by package type / frequency). All VCC3 pins must be connected to a 2.5 V VCC3, plane. All VSS pins must be connected to a VSS plane. Please refer to Table 2 on page 17 for the list of VCC2, VCC3 and VSS pins.
Decoupling Recommendations
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Connection Specifications
All NC / INC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to ground.
AC Timings
The AC specifications given in Table 23 consist of output delays, input setup requirements and input hold requirements for the standard 66 MHz external bus. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to VCC3 / VCC2 for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, asynchronous inputs must be stable for correct operation. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays. Do not select a bus fraction and clock speed which will cause the processor to exceed its internal maximum frequency. The following specifications apply to all standard TTL signals used with the Pentium processor family:
· TTL input test waveforms are assumed to be 0 to 2.5 V transitions with 1.0 V / ns rise and fall
times.
· 0.3 V / ns input rise / fall time 5 V / ns. · All TTL timings are referenced from VCC3 / VCC2.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 23. Low-Power Embedded Pentium® Processor with MMX Technology AC Specifications (Sheet 1 of 3)
t8a t8b t9a t9b t9c t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 23. Low-Power Embedded Pentium® Processor with MMX Technology AC Specifications (Sheet 2 of 3)
(See Table 18 for VCC and TCASE assumptions.) Symbol t18a t18b t19 t20 t21 t22 t23 t24a t24b t25a t25b t26 t27 t28 Parameter KEN# Setup Time NA#, WB / WT# Setup Time KEN#, WB / WT#, NA# Hold Time BRDY# Setup Time BRDY# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD, Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R / S# Setup Time R / S# Hold Time R / S# Pulse Width, Async. D63-D0, DP7-0 Read Data Setup Time D63-D0, DP7-0 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, VCC & CLK Stable RESET Active After VCC & CLK Stable Min 5.0 4.5 1.0 4.75 1.0 5.5 1.0 5.0 4.8 1.0 1.5 5.0 1.0 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 16 16 16 16 16 16 16 16 16 16 16 16 16 (7, 8) (9) Notes (see Table 25)
t30 t31 t32 t33 t34 t35 t36 t37 t38 t39
CLKs ns ns CLKs ns ns ns ns CLKs mS
(7, 8) (9) (10) Power up
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 23. Low-Power Embedded Pentium® Processor with MMX Technology AC Specifications (Sheet 3 of 3)
(See Table 18 for VCC and TCASE assumptions.) Symbol t40 Parameter Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. BF2-BF0 Setup Time BF2-BF0 Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time TCK Frequency TCK Period TCK High Time TCK Low Time TCK Fall Time TCK Rise Time TRST# Pulse Width TDI, TMS Setup Time TDI, TMS Hold Time TDO Valid Delay TDO Float Delay All Non-Test Outputs Valid Delay All Non-Test Outputs Float Delay All Non-Test Inputs Setup Time All Non-Test Inputs Hold Time 5.0 13.0 3.0 40.0 5.0 13.0 3.0 20.0 25.0 20.0 25.0 Min 5.0 Max Unit ns Figure 17 Notes (see Table 25) (7, 8, 10)
To RESET falling edge, (8)
t42b t43a t43b t43c t43d t44 t45 t46 t47 t48 t49 t50 t51 t52 t53 t54 t55 t56 t57 t58
To RESET falling edge To RESET falling edge, (10) To RESET falling edge, (12) To RESET falling edge To RESET falling edge
mS CLKs CLKs CLKs MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
13 13 13 13 13 19 19 19 19 19 19 19 19 19 @VCC3 -0.7 V, (2) @0.5 V, (2) VCC3 -0.7 V to 0.5 V (2, 13, 14) 0.5 V to VCC3 -0.7 V, (2, 13, 14) Asynchronous, (2) (15) (15) (13) (2, 13) (13, 16, 17) (2, 13, 16, 17) (15, 16, 17) (15, 16, 17)
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Table 24. APIC AC Specifications
Symbol t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j t61 t62 t63 Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time PICD0-1 Setup Time PICD0-1 Hold Time PICD0-1 Valid Delay (L to H) PICD0-1 High Time (H to L) PICCLK Setup Time PICCLK Hold Time PICCLK Ratio (CLK / PICCLK) Min 2 60 15 15 0.15 0.15 3 2.5 4 4 5.0 2.0 4 38 22 2.5 2.5 Max 16.66 500 Unit MHz ns ns ns ns ns ns ns ns ns 13 13 13 13 13 16 16 14 14 16 16 To PICCLK To PICCLK From PICCLK, (18) From PICCLK, (18) To CLK To CLK (19) Figure Notes
Table 25. Notes to Tables 23 and 24
1. CLK input frequency must be either 33.33 MHz (+1 MHz) or 66.6 MHz (-1 MHz). Operation in the range between 33.33 MHz and 66.6 MHz is not supported. 2. Not 100 percent tested. Guaranteed by design. 3. These signals are measured on the rising edge of adjacent CLKs at VCC3 / VCC2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum should not have any power spectrum peaking between 500 KHz and 1 / 3 of the CLK operating frequency. The amount of jitter present must be accounted for as a component of CLK skew between devices. The internal clock generator requires a constant frequency CLK input to within +250 ps, and therefore the CLK input cannot be changed dynamically. 4. 0.87 V / ns CLK input rise / fall time 8.7 V / ns. 5. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals monotonically transition without false transitions. 6. Timing (t14) is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled active). 7. Setup time is required to guarantee recognition on a specific clock. 8. This input may be driven asynchronously. 9. Hold time is required to guarantee recognition on a specific clock. 10.When driven asynchronously, RESET, NMI, FLUSH#, R / S#, INIT, and SMI# must be de-asserted (inactive) for a minimum of two clocks before being returned active. 11. To guarantee proper asynchronous recognition, the signal must have been de-asserted (inactive) for a minimum of two clocks before being returned active and must meet the minimum pulse width. 12.BF2-BF0 should be strapped to VCC3 or VSS. 13.Referenced to TCK falling edge. 14.1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz. 15.Referenced to TCK rising edge. 16.Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and TMS). These timings correspond to the response of these signals due to boundary scan operations. 17.During probe mode operation, do not use the boundary scan timings (t55-t58). 18.This assumes an external pull-up resistor to VCC and a lumped capacitive load. The pull-up resistor must be between 300 and 1 K, the capacitance must be between 20 pF and 120 pF, and the RC product must be between 6 ns and 36 ns. 19.The CLK to PICCLK ratio has to be an integer and the ratio (CLK / PICCLK) cannot be smaller than 4.
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Figure 13. Clock Waveform
PP0051
Figure 14. Valid Delay Timings
Tx max.
Signal Signal Vcc3 / 2 VALID
Tx min.
PP0052
Figure 15. Float Delay Timings
Tx Ty Signal
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Figure 16. Setup and Hold Timings
Vcc3 / 2 CLK Tx Ty
Signal
VALID
Figure 17. Reset and Configuration Timings
CLK Tz RESET
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
Figure 18. Test Timings
TDI TMS
TDO Ty Output Signals
Input Signals
Figure 19. Test Reset Timings
TRST#
Datasheet
Low-Power Embedded Pentium® Processor with MMX Technology
I / O Buffer Models
This section describes the I / O buffer models of the low-power embedded Pentium processor with MMX technology. The first order I / O buffer model is a simplified representation of the complex input and output buffers used. Figure 20 shows the structure of the input buffer model and Figure 21 shows the output buffer model. Table 26 and 27 show the parameters used to specify these models. Although simplified, these buffer models will accurately model flight time and signal quality. For these parameters, there is very little added accuracy in a complete transistor model. In addition to the input and output buffer parameters, input protection diode models are provided for added accuracy. These diodes have been optimized to provide ESD protection and provide some level of clamping. Although the diodes are not require