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Embedded Pentium® Processor with MMXTechnology
MHz,
Support MMXTechnology Compatible with Large Software Base MS-DOS*, Windows*, OS/2*, UNIX* 32-Bit Processor with 64-Bit Data Superscalar Architecture Enhanced Pipelines Pipelined Integer Units Capable Instructions Clock Pipelined Technology Unit Pipelined Floating-Point Unit Separate Code Data Caches 16-Kbyte Code, 16-Kbyte Write Back Data MESI Cache Protocol Advanced Design Features Deeper Write Buffers Enhanced Branch Prediction Feature Virtual Mode Extensions Enhanced CMOS Silicon Technology
4-Mbyte Pages Increased Rate IEEE 1149.1 Boundary Scan Dual Processing Configuration Internal Error Detection Features Multiprocessor Support Multiprocessor Instructions Support Second Level Cache On-Chip Local APIC Controller Multiprocessor Interrupt Management 8259 Compatible Power Management Features System Management Mode Clock Control Fractional Operation Core/66 (iCOMP® Index rating=203) Core/66 (iCOMP® Index rating=182) Plastic Grid Array Package
Contact Intel Corporation more information about iCOMP® Index ratings.
Pentium® processor with MMXtechnology provides performance needed embedded applications. Pentium processor with technology compatible with entire installed base applications MS-DOS*, Windows*, OS/2* UNIX*. Pentium processor with technology supports Intel's technology. Pentium processor with technology superscalar architecture execute instructions clock cycle. Enhanced branch prediction, pipelined floating-point unit separate caches provide high performance. Separate code data caches reduce cache conflicts while remaining software transparent. Pentium processor with technology million transistors built Intel's enhanced CMOS silicon technology.
Order Number: 273214-001 November 1998
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium processor with MMXtechnology contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1998 *Third-party brands names property their respective owners.
Embedded Pentium® Processor with MMXTechnology
Contents
Architecture Overview
Pentium® Processor Family Architecture Embedded Pentium® Processor with MMXTechnology. 1.2.1 Full Support Intel's MMXTechnology 1.2.2 16-Kbyte Code Data Cache 1.2.3 Improved Branch Prediction 1.2.4 Enhanced Pipeline 1.2.5 Deeper Write Buffers
Packaging Information
Pinout 2.1.1 Cross Reference 2.1.2 Design Notes 2.1.3 Quick Reference 2.1.4 Reference Tables. 2.1.5 Grouping According Function. Mechanical Specifications Thermal Specifications Measuring Thermal Values 2.4.1 Thermal Equations
Electrical Specifications
Electrical Characteristics 3.1.1 Power Supplies 3.1.2 Power Supply Sequencing 3.1.3 Connection Specifications 3.1.3.1 Power Ground 3.1.3.2 VCC2 VCC3 Measurement Specification. 3.1.3.3 Decoupling Recommendations 3.1.3.4 3.3-V Inputs Outputs 3.1.3.5 NC/INC Unused Inputs 3.1.3.6 Private 3.1.4 Buffer Models Absolute Maximum Ratings. Specifications Specifications
Figures
Pentium® Processor with MMXTechnology Block Diagram. Pentium® Processor with MMXTechnology PPGA Package Pinout Side View Pentium® Processor with MMXTechnology PPGA Package Pinout Bottom Side View. PPGA Package Dimensions. Technique Measuring PPGA Packages.31
Embedded Pentium Processor with MMXTechnology
Thermal Resistance Heatsink Height, PPGA Packages Clock Waveform Valid Delay Timings Float Delay Timings Setup Hold Timings Reset Configuration Timings Test Timings. Test Reset Timings Percent Measurement Flight Time.
Tables
Cross-Reference Name Address Data Pins Cross-Reference Name Control Pins Cross-Reference Name Power, Ground Connect Pins Quick Reference Frequency Selections Output Pins Input Pins Input/Output Pins Inter-processor Input/Output Pins Functional Grouping. PPGA Package Information PPGA Package Dimensions Power Dissipation Requirements Thermal Design Thermal Resistance PPGA Packages Absolute Maximum Ratings TCASE Specifications Specifications Specifications Input Output Characteristics. Specifications Notes Table
Embedded Pentium® Processor with MMXTechnology
Revision History
Date 11/98 Revision Description This first publication this document.
Pentium® Processor with MMXTechnology
Architecture Overview
embedded Pentium processor with MMXtechnology binary compatible with 8086/8088, 80286, Intel386TM, Intel486processor families, with other Pentium processors. embedded Pentium processor family includes following products.
Pentium processor Pentium processor with Voltage Reduction Technology Pentium processor with technology Low-Power embedded Pentium processor with technology
Pentium processor family supports features previous Intel Architecture processors, provides significant enhancements additions including following:
Superscalar architecture Dynamic branch prediction Pipelined floating-point unit Improved instruction execution time Separate code data caches Writeback MESI protocol data cache 64-bit data cycle pipelining
Address parity Internal parity checking Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Dual processing support On-chip local APIC device
addition features listed above, Pentium processor with technology offers following enhancements over Pentium processor:
Support Intel® technology Doubled code data cache sizes Kbytes each Improved branch prediction Enhanced pipeline Deeper write buffers
following features supported Pentium processor, these features supported Pentium processor with technology:
Functional redundancy check Lock-Step operation. Support Intel 82498/82493 82497/82492 cache chipset products Split-line accesses code cache
more detailed description Pentium processor family products, please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Pentium® Processor with MMXTechnology
Pentium® Processor Family Architecture
application instruction Pentium processor family includes complete Intel486 processor family instruction with extensions accommodate some additional functionality Pentium processor. application software written Intel386 Intel486 family microprocessors runs Pentium processors without modification. on-chip memory management unit (MMU) completely compatible with Intel386 family Intel486 family processors. Pentium processors implement several enhancements increase performance. instruction pipelines floating-point unit capable independent operation. Each pipeline issues frequently used instructions single clock. Together, dual pipes issue integer instructions clock, floating-point instruction (under certain circumstances, floating-point instructions) clock. Branch prediction implemented Pentium processors. support this, processor prefetch buffers: prefetches code linear fashion other prefetches code according needed code almost always prefetched before needed execution. floating-point unit (FPU) times faster than used Intel486 processor common operations including add, multiply, load. Pentium processors include separate code data caches that integrated on-chip meet performance goals. Each cache 32-byte line size. Each cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses. data cache configurable write back write through line-by-line basis follows MESI protocol. data cache tags triple-ported support data transfers inquire cycle same clock. code cache inherently write-protected cache. code cache tags multi-ported support snooping. Individual pages configured cacheable noncacheable software hardware. caches enabled disabled software hardware. Pentium processors have 64-bit data fast data transfer. Burst read burst writeback cycles supported. addition, cycle pipelining allows cycles occur simultaneously. Memory Management Unit contains optional extensions architecture which allow 4-Kbyte 4-Mbyte page sizes. Pentium processors have added significant data integrity error detection capability. Data parity checking still supported byte-by-byte basis. Address parity checking internal parity checking features have been added along with exception, machine check exception. more more functions integrated chip, complexity board level testing increased. address this, Pentium processors have increased test debug capability. Pentium processors implement IEEE Boundary Scan (Standard 1149.1). addition, Pentium processors provide four breakpoint pins that correspond each debug registers externally indicate breakpoint match. Execution tracing provides external indications when instruction completed execution either internal pipelines, when branch been taken. System Management Mode (SMM) been implemented along with some extensions architecture. Enhancements virtual 8086 mode have been made increase performance reducing number times necessary trap virtual 8086 monitor. Figure block diagram embedded Pentium processor with technology.
Pentium® Processor with MMXTechnology
Figure Pentium® Processor with MMXTechnology Block Diagram
Control
Logic
Branch Prefetch Target Buffer Address
Code Cache Kbytes
Instruction Pointer 64-Bit Data 32-Bit Address Unit Branch Verification Target Address
Prefetch Buffers Instruction Decode
Control
Control Unit
V-Pipeline Connection U-Pipeline Connection
Page Unit Address Address Generate Generate Pipeline) Pipeline)
MMXUnit
Floating Point Unit
Control Register File
Control
Integer Register File
64-Bit Data
Divide Multiply
Pipline)
32-Bit Addr.
Pipline)
Barrel Shifter
Data APIC Control
Data Cache Kbytes
A6180-01
block diagram shows instruction pipelines, pipe pipe. u-pipe execute integer floating-point instructions. v-pipe execute simple integer instructions FXCH floating-point instructions. separate code data caches shown block diagram. data cache ports, each pipes (the tags triple-ported allow simultaneous inquire cycles). data cache dedicated Translation Lookaside Buffer (TLB) translate linear addresses physical addresses used data cache. code cache, branch target buffer prefetch buffers responsible getting instructions into execution units. Instructions fetched from code cache from external bus. Branch addresses remembered branch target buffer. code cache translates linear addresses physical addresses used code cache.
Pentium® Processor with MMXTechnology
decode unit decodes prefetched instructions processor execute instruction. control contains microcode control sequence operations that must performed implement Pentium processor architecture. control unit direct control over both pipelines. Pentium processors contain pipelined floating-point unit that provides significant floating-point performance advantage over previous generations processors. Symmetric dual processing system supported with Pentium processors. processors appear system single Pentium processor. Operating systems with dual processing support properly schedule computing tasks between processors. This scheduling tasks transparent software applications end-user. Logic built into processors support "glueless" interface easy system design. Through private bus, Pentium processors arbitrate external maintain cache coherency. Dual processing supported system only both processors operating identical core frequencies. this document, order distinguish between Pentium processors dual processing mode, processor "Primary" processor other "Dual" processor. Pentium processor supports clock control. When clock processor stopped, power dissipation virtually eliminated. combination these improvements makes Pentium processor good choice energy-efficient designs. Pentium processor supports fractional operation. This allows internal processor core operate high frequencies, while communicating with external lower frequencies. Pentium processor contains on-chip Advanced Programmable Interrupt Controller (APIC). This APIC implementation supports multiprocessor interrupt management (with symmetric interrupt distribution across processors), multiple subsystem support, 8259A compatibility, inter-processor interrupt support. architectural features introduced this chapter more fully described Embedded Pentium® Processor Family Developer's Manual (order number 273204).
Embedded Pentium® Processor with MMXTechnology
embedded Pentium processor with technology software compatible with other members embedded Pentium processor family. contains million transistors manufactured lntel's enhanced 0.35 micron CMOS process which allows voltage reduction technology power high density. This enables embedded Pentium processor with technology remain within thermal envelope embedded Pentium processor while providing significant performance increase. Pentium processor with technology several additional micro-architectural enhancements compared Pentium processor. additions described following sections.
Pentium® Processor with MMXTechnology
1.2.1
Full Support Intel's MMXTechnology
technology based Single Instruction Multiple Data (SIMD) technique which enables increased performance wide variety multimedia communications applications. Fifty-seven instructions four 64-bit data types supported embedded Pentium processor with technology. existing operating system application software fullycompatible with embedded Pentium processor with technology.
1.2.2
16-Kbyte Code Data Cache
On-chip, level-one (L1) data code cache sizes have been doubled Kbytes each. These caches 4-way associative. Larger separate internal caches improve performance reducing average memory access time providing fast access recently-used instructions data. instruction data caches accessed simultaneously. data cache supports data references simultaneously. data cache supports write back policy alternatively, writethrough, line-by-line basis) memory updates. default, code cache write-protected.
1.2.3
Improved Branch Prediction
Dynamic branch prediction uses Branch Target Buffer (BTB) boost performance predicting most likely instructions executed. been improved increase accuracy. embedded Pentium processor with technology four prefetch buffers that hold four successive code streams.
1.2.4
Enhanced Pipeline
additional pipeline stage been added pipeline been enhanced improve performance. integration technology pipeline with integer pipeline very similar that floating-point pipeline. Under some circumstances, instructions integer instruction paired issued clock cycle increase throughput. enhanced pipeline described more detail Embedded Pentium® Processor Family Developer's Manual (order number 273204).
1.2.5
Deeper Write Buffers
pool four write buffers shared between dual pipelines improve memory write performance.
Pentium® Processor with MMXTechnology
Packaging Information
Pinout
Figure Pentium® Processor with MMXTechnology PPGA Package Pinout Side View
VCC3 VCC3 VCC3 VCC3 STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 PICCLK PICD0 PICD1 VCC3 VCC3 CPUTYP TRST# VCC3 VCC3 VCC3 VCC3 PEN# IGNNE# INIT SMI# VCC3 INTR D/P# VCC3 VCC3 VCC3
VCC3 VCC3
VCC2
VCC2 VCC2 VCC2
VCC2
VCC2 FLUSH# W/R#
EADS# ADSC#
VCC2 DET#
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
RESET
BE7#
BE5#
BE3#
BE1#
D/C#
ADS#
HLDA BREQ
LOCK#
SMIACT# VCC2 PCHK#
APCHK# PBREQ# VCC2
PBGNT# PRDY PHITM# VCC2 HOLD BRDYC# VCC2 BRDY# KEN# EWBE# VCC2 AHOLD
R/S#
WB/WT# PHIT# VCC2 BOFF#
Side View
CACHE# VCC2
MI/O#
VCC2
PM1BP1
FERR# PM0BP0 VCC2
IERR#
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3 VCC3
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
A6174-01
Pentium® Processor with MMXTechnology
Figure Pentium® Processor with MMXTechnology PPGA Package Pinout Bottom Side View
VCC2 VCC2
VCC2
VCC2 VCC3 VCC3
VCC3
VCC3 VCC3 INTR VCC3 D/P# VCC3 R/S# VCC3
FLUSH# VCC2 VCC2
ADSC# EADS#
VCC2 DET#
W/R#
HITM# BUSCHK# BE0# HIT# A20M#
BE2#
BE4#
BE6#
SCYC
D/C#
BE1#
BE3#
BE5#
BE7#
RESET
BREQ HLDA
ADS#
LOCK#
VCC2 SMIACT# PCHK#
VCC2 PBREQ# APCHK# PBGNT#
VCC2 PHITM# PRDY VCC2 HOLD
SMI#
PHIT# WB/WT# BOFF#
INIT IGNNE# VCC3 PEN#
VCC3 VCC3
VCC2 BRDYC# BRDY#
VCC2 EWBE# KEN# VCC2 VCC2 VCC2 VCC2 VCC2 VCC3 VCC3 VCC2 PM1BP1 VCC2 CACHE# MI/O# AHOLD
Side View
STPCLK# VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 PICD1 VCC3 PICD0 VCC3 PICCLK VCC3 VCC3
VCC2 PM0BP0 FERR# IERR#
TRST# CPUTYP
VCC2
VCC2
VCC2
VCC2
VCC2
VCC3
VCC3
VCC3
VCC3
A6173-01
Pentium® Processor with MMXTechnology
2.1.1
Table
Cross Reference
Cross-Reference Name Address Data Pins
Location Location Location Location Location
Address AL35 AM34 AK32 AN33 AL33 AM32 AK30 AN31 AL31 AL29 AK28 AL27 Data AK26 AL25 AK24 AL23 AK22 AL21 AF34 AH36 AE33 AG35 AJ35 AH34 AG33 AK36 AK34 AM36 AJ33
Pentium® Processor with MMXTechnology
Table
Cross-Reference Name Control Pins
Location Location Control A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BRDYC# AK08 AJ05 AM02 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 BREQ BUSCHK# CACHE# CPUTYP D/C# D/P# EADS# EWBE# FERR# FLUSH# FRCMC# AJ01 AL07 AK04 AE35 AM04 AN07 HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR/LINT KEN# LOCK# M/IO# NMI/LINT1 PCHK# PEN# PM0/BP0 PM1/BP1 APIC PICCLK H342 PICD0/[DP EN#] PICD1/[API CEN] AK06 AL05 AJ03 AB04 AA35 AA33 AD34 AH04 AC33 AG05 AF04 PRDY R/S# RESET SCYC SMI# SMIACT# TRST# VCC2DET# W/R# WB/WT# AC05 AL03 AC35 AK20 AL17 AB34 AG03 AL01 AM06 AA05 Location Location
Clock Control AK182 [BF0] [BF1] STPCLK#
Dual Processor Private Interface PBGNT# AD04 PBREQ# AE03 PHIT# AA03 PHITM# AC03
NOTES: FRCMC# defined Pentium® processor with MMXtechnology. This should left "NC" tied VCC3 external pull-up resistor Pentium processor with technology. PICCLK V-tolerant-only Pentium processor with technology. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) PICCLK signal quality specification.
Pentium® Processor with MMXTechnology
Table
Cross-Reference Name Power, Ground Connect Pins
VCC2 VCC3 AN01 AN03 AN05 AL19 AN35 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
2.1.2
Design Notes
reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected GND. Note: Connect (NC) pins must remain unconnected. Connection pins result component failure incompatibility with future processor steppings.
2.1.3
Quick Reference
This section gives brief functional description each pins. detailed description, Hardware Interface chapter Embedded Pentium® Processor Family Developer's Manual (order number 273204). Note: input pins must meet their AC/DC specifications guarantee proper functional behavior. symbol signal name indicates that active, asserted state occurs when signal voltage. When symbol present after signal name, signal active, asserted high voltage level. Square brackets around signal name indicate that signal defined only RESET. following pins become pins when Pentium processors with technology operating dual processing environment: ADS#, CACHE#, HIT#, HITM#, HLDA#, LOCK#, M/IO#, D/C#, W/R#, SCYC, BE4#
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function When address mask asserted, processor emulates address wraparound Mbyte which occurs 8086 masking physical address (A20) before performing lookup internal caches driving memory cycle bus. effect A20M# undefined protected mode. A20M# must asserted only when processor real mode. A20M# internally masked processor when configured Dual processor. A31-A3 outputs, address lines processor along with byte enables define physical area memory accessed. external system drives inquire address processor A31-A5. address strobe indicates that valid cycle currently being driven processor. address strobe (copy) functionally identical ADS#. response assertion address hold, Pentium® processor with MMXtechnology stops driving address lines (A31-A3) next clock. rest remains active data returned driven previously issued cycles. Address parity driven processor with even parity information processor generated cycles same clock that address driven. Even parity must driven back processor during inquire cycles this same clock EADS# ensure that correct parity check status indicated processor. address parity check status asserted clocks after EADS# sampled active when processor detected parity error address during inquire cycles. APCHK# remains active clock each time parity error detected (including during dual processing private snooping). Advanced Programmable Interrupt Controller Enable enables disables on-chip APIC interrupt controller. When sampled high falling edge RESET, APIC enabled. APICEN shares with PICD1 signal. byte enable pins used determine which bytes must written external memory which bytes were requested processor current cycle. byte enables driven same clock address lines (A31- A3). Additionally, lower 4-byte enables (BE3#-BE0#) used Pentium processor with technology APIC inputs sampled RESET. dual processing mode, BE4# used input during Flush cycles. frequency pins determine bus-to-core frequency ratio. BF1-BF0 sampled RESET, cannot changed until another non-warm assertion RESET. Additionally, BF1-BF0 must change values while RESET active. Table Frequency Selections. backoff input used abort outstanding cycles that have completed. response BOFF#, processor floats pins normally floated during hold next clock. processor remains hold until BOFF# negated, which time processor restarts aborted cycle(s) their entirety. breakpoint pins (BP3-BP0) correspond debug registers, DR3-DR0. These pins externally indicate breakpoint match when debug registers programmed test breakpoint matches. multiplexed with performance monitoring pins (PM1 PM0). bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring.
A20M#
ADS# ADSC#
AHOLD
APCHK#
[APICEN] PICD1
BE7#-BE4# BE3#-BE0#
BF1-BF0
BOFF#
BP3-BP2 PM1-PM0/ BP1-BP0
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function burst ready input indicates that external system presented valid data data pins response read that external system accepted processor data response write request. This signal sampled states. burst ready (copy) functionally identical BRDY#. request output indicates external system that processor internally generated request. This signal always driven whether processor driving bus. check input allows system signal unsuccessful completion cycle. this sampled active, processor latches address control signals machine check registers. When BUSCHK# active, processor vectors machine check exception. BUSCHK# assure that BUSCHK# always recognized, STPCLK# must deasserted time BUSCHK# asserted system, before system allows another external cycle. When BUSCHK# asserted system snoop cycle while STPCLK# remains asserted, usually MCE=1) processor vectors exception after STPCLK# deasserted. another snoop same line occurs during STPCLK# assertion, processor lose BUSCHK# request. processor-initiated cycles, cache indicates internal cacheability cycle read), indicates burst write back cycle (when write). When this driven inactive during read cycle, processor does cache returned data, regardless state KEN# pin. This also used determine cycle length (number transfers cycle). clock input provides fundamental timing processor. frequency operating frequency processor external bus, requires levels. external timing parameters except TDI, TDO, TMS, TRST#, PICD0-PICD1 specified with respect rising edge CLK. This 3.3-V-tolerant-only Pentium processor with technology. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) PICCLK signal quality specification. recommended that begin toggling within after reaches proper operating level. This recommendation ensure long-term reliability device. type distinguishes Primary processor from Dual processor. single processor environment, when processor acting Primary processor dual processing system, CPUTYP should strapped VSS. Dual processor should have CPUTYP strapped VCC3. data/code output primary cycle definition pins. driven valid same clock ADS# signal asserted. D/C# distinguishes between data code special cycles. dual/primary processor indication. Primary processor drives this when driving bus, otherwise drives this high. D/P# always driven. D/P# sampled current cycle with ADS# (like status pin). This defined only Primary processor. Dual processing supported system only both processors operating identical core frequencies. Within these restrictions, processors different steppings operate together system. These data lines processor. Lines D7-D0 define least significant byte data bus; lines D63-D56 define most significant byte data bus. When processor driving data lines, they driven during T12, clocks that cycle. During reads, processor samples data when BRDY# returned.
BRDY#
BRDYC# BREQ
CACHE#
CPUTYP
D/C#
D/P#
D63-D0
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function These data parity pins processor. There each byte data bus. They driven processor with even parity information writes same clock write data. Even parity information must driven back processor these pins same clock data ensure that correct parity check status indicated processor. applies D63-D56, applies D7-D0. Dual processing enable output Dual processor input Primary processor. Dual processor drives DPEN# Primary processor RESET indicate that Primary processor should enable dual processor mode. DPEN# sampled system falling edge RESET determine dual-processor socket occupied. DPEN# multiplexed with PICD0. This signal indicates that valid external address been driven onto processor address pins used inquire cycle. external write buffer empty input, when inactive (high), indicates that write cycle pending external system. When processor generates write, EWBE# sampled inactive, processor holds subsequent writes M-state lines data cache until write cycles have completed, which indicated EWBE# being active. floating-point error driven active when unmasked floating-point error occurs. FERR# similar ERROR# Intel387math coprocessor. FERR# included compatibility with systems using DOS-type floating-point error reporting. FERR# never driven active Dual processor. When asserted, cache flush input forces processor write back modified lines data cache invalidate internal caches. Flush Acknowledge special cycle will generated processor indicate completion write back invalidation. When FLUSH# sampled when RESET transitions from high low, threestate test mode entered. FLUSH# When Pentium processors with technology operating dual processing mode FLUSH# asserted, Dual processor performs flush first (without flush acknowledge cycle), then Primary processor performs flush followed flush acknowledge cycle. When FLUSH# signal asserted dual processing mode, must deasserted least clock prior BRDY# FLUSH Acknowledge cycle avoid arbitration problems. indication driven reflect outcome inquire cycle. When inquire cycle hits valid line processor data instruction cache, this asserted clocks after EADS# sampled asserted. When inquire cycle misses processor cache, this negated clocks after EADS#. This changes value only result inquire cycle retains value between cycles. modified line output driven reflect outcome inquire cycle. asserted after inquire cycles which resulted modified line data cache. used inhibit another master from accessing data until line completely written back. hold acknowledge goes active response hold request driven processor HOLD pin. indicates that processor floated most output pins relinquished another local master. When leaving hold, HLDA will driven inactive Pentium processor with technology will resume driving bus. processor cycle pending, will driven clock cycle after HLDA deasserted.
DP7-DP0
[DPEN#] PICD0
EADS#
EWBE#
FERR#
HIT#
HITM#
HLDA
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function response hold request, processor floats most output input/output pins asserts HLDA after completing outstanding cycles. processor maintains this state until HOLD deasserted. HOLD recognized during LOCK cycles. processor recognizes HOLD during reset. internal error used indicate internal parity errors. When parity error occurs read from internal array, processor asserts IERR# clock then shuts down. This ignore numeric error input. This effect when When CR0.NE IGNNE# asserted, processor ignores pending unmasked numeric exception continues executing floating-point instructions entire duration that this asserted. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor executes instruction spite pending exception. When CR0.NE IGNNE# asserted, pending unmasked numeric exception exists (SW.ES floating-point instruction other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, FSETPM, processor stops execution waits external interrupt. IGNNE# internally masked when processor configured Dual processor. processor initialization input forces processor begin execution known state. processor state after INIT same state after RESET except that internal caches, write buffers, floating-point registers retain values they prior INIT. INIT used instead RESET after power-up. When INIT sampled high when RESET transitions from high low, processor performs built-in self test prior start program execution. active maskable interrupt input indicates that external interrupt been generated. When EFLAGS register set, processor generates locked interrupt acknowledge cycles vectors interrupt handler after current instruction execution completed. INTR must remain active until first interrupt acknowledge cycle generated ensure that interrupt recognized. When local APIC enabled, this becomes LINT0. invalidation input determines final cache line state case inquire cycle hit. sampled together with address inquire cycle clock EADS# sampled active. cache enable used determine whether current cycle cacheable consequently used determine cycle length. When processor generates cycle that cached (CACHE# asserted) KEN# active, cycle transformed into burst line fill cycle. When APIC enabled, this local interrupt When APIC disabled, this INTR. When APIC enabled, this local interrupt When APIC disabled, this NMI. lock indicates that current cycle locked. Pentium processor with technology does allow hold when LOCK# asserted (but AHOLD BOFF# allowed). LOCK# goes active first clock first locked cycle goes inactive after BRDY# returned last locked cycle. LOCK# guaranteed deasserted least clock between back-to-back locked cycles.
HOLD
IERR#
IGNNE#
INIT
INTR/LINT0
KEN#
LINT0/INTR LINT1/NMI
LOCK#
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol M/IO# Type Name Function memory/input-output primary cycle definition pins. driven valid same clock ADS# signal asserted. M/IO# distinguishes between memory cycles. active next address input indicates that external memory system ready accept cycle although data transfers current cycle have completed. processor issues ADS# pending cycle clocks after asserted. processor supports outstanding cycles. non-maskable interrupt request signal indicates that external nonmaskable interrupt been generated. When local APIC enabled, this becomes LINT1. Private grant grant line that used when Pentium processors with technology configured dual processing mode, order perform private arbitration. PBGNT# should left unconnected only Pentium processor with technology exists system. Private request request line that used when Pentium processors with technology configured dual processing mode, order perform private arbitration. PBREQ# should left unconnected when only processor exists system. page cache disable reflects state CR3, Page Directory Entry, Page Table Entry. provides external cacheability indication page page basis. parity check output indicates result parity check data read. driven with parity status clocks after BRDY# returned. PCHK# remains clock each clock which parity error detected. Parity checked only bytes which valid data returned. When Pentium processors with technology operating dual processing mode, PCHK# driven three clocks after BRDY# returned. parity enable input (along with CR4.MCE) determines whether machine check exception will taken result data parity error read cycle. When this sampled active clock data parity error detected, processor latches address control signals cycle with parity error machine check registers. When PEN# sampled active machine check enable "1", processor vectors machine check exception before beginning next instruction. Private indication used when Pentium processors with technology configured dual processing mode, order maintain local cache coherency. PHIT# should left unconnected when only processor exists system. Private modified modified cache line indication used when Pentium processors with technology configured dual processing mode, order maintain local cache coherency. PHITM# should left unconnected only processor exists system. APIC interrupt controller serial data clock driven into programmable interrupt controller clock input processor. PICCLK This 3.3-V-tolerant-only Pentium processor with technology. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) PICCLK signal quality specification. Programmable interrupt controller data lines Pentium processor with technology comprise data portion APIC 3-wire bus. They open-drain outputs that require external pull-up resistors. These signals multiplexed with DPEN# APICEN respectively.
NMI/LINT1
PBGNT#
PBREQ#
PCHK#
PEN#
PHIT#
PHITM#
PICD0/[DPEN#]- PICD1/[APICEN]
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol Type Name Function These pins function part performance monitoring feature. PM1/BP1- PM0/BP0 breakpoint pins multiplexed with performance monitoring pins. bits Debug Mode Control Register determine pins configured breakpoint performance monitoring pins. pins come RESET configured performance monitoring. probe ready output provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) more details. page write through reflects state CR3, page directory entry, page table entry. used provide external write back indication page-by-page basis. run/stop input provided with Intel debug port. Please refer Embedded Pentium® Processor Family Developer's Manual (order number 273204) more details. RESET forces processor begin execution known state. processor internal caches will invalidated upon RESET. Modified lines data cache written back. FLUSH# INIT sampled when RESET transitions from high determine three-state test mode checker mode will entered, Built-In Self-Test (BIST) will run. split cycle output asserted during misaligned LOCKed transfers indicate that more than cycles will locked together. This signal defined locked cycles only. undefined cycles which locked. system management interrupt causes system management interrupt request latched internally. When latched SMI# recognized instruction boundary, processor enters System Management Mode. active system management interrupt active output indicates that processor operating System Management Mode. Assertion stop clock input signifies request stop internal clock processor, thereby causing core consume less power. When processor recognizes STPCLK#, processor stops execution next instruction boundary, unless superseded higher priority interrupt, generates stop grant acknowledge cycle. When STPCLK# asserted, processor still responds interprocessor external snoop requests. testability clock input provides clocking function processor boundary scan accordance with IEEE Boundary Scan interface (Standard 1149.1). used clock state information data into processor during boundary scan. test data input serial input test logic. instructions data shifted into processor rising edge when controller appropriate state. test data output serial output test logic. instructions data shifted processor TCK's falling edge when controller appropriate state. value test mode select input signal sampled rising edge controls sequence controller state changes. When asserted, test reset input allows controller asynchronously initialized. Pentium processor with technology power inputs. Pentium processor with technology power inputs. detect used flexible motherboard implementations configure voltage output set-point appropriately VCC2 inputs processor.
PRDY
R/S#
RESET
SCYC
SMI#
SMIACT#
STPCLK#
TRST# VCC2 VCC3 VCC2DET#
Pentium® Processor with MMXTechnology
Table
Quick Reference (Sheet
Symbol W/R# Type Name Function Pentium processor with technology ground inputs. Write/read primary cycle definition pins. driven valid same clock ADS# signal asserted. W/R# distinguishes between write read cycles. write back/write through input allows data cache line defined write back write through line-by-line basis. result, determines whether cache line initially state data cache.
WB/WT#
Core frequencies according Table Each Pentium processor with technology specified operate within single bus-to-core ratio specific minimum-tomaximum bus-frequency range (corresponding minimum-to-maximum core-frequency range). Operation other bus-to-core ratios outside specified operating frequency range supported advocated. example, Pentium processor with technology does operate beyond frequency only supports bus-to-core ratio; does support 1/3, 1/2, bus-to-core ratios. Table Frequency Selections
Bus/Core Ratio 1/2(1,2) Bus/Core Frequency (MHz) 66/200
Bus/Core Frequency (MHz) 33/100 33/117
N/A(2) 66/233
NOTES: This default core ratio Pentium® processor with MMXtechnology. pins left floating, processor will configured core frequency ratio. Currently, there embedded products that support these fractions.
Pentium® Processor with MMXTechnology
2.1.4
Table
Reference Tables
Output Pins
Name ADS# ADSC# APCHK# BE7#-BE4# BREQ CACHE#(1) D/P#
Active Level High High
When Floated Hold, BOFF# Hold, BOFF#
Hold, BOFF#
Hold, BOFF#
FERR# HIT# HITM# HLDA
IERR# LOCK# M/IO# D/C# W/R# PCHK# BP3-BP2, PM1/BP1, PM0/BP0 PRDY PWT, SCYC
Hold, BOFF# Hold, BOFF#
High High High High
Hold, BOFF# Hold, BOFF#
SMIACT# VCC2DET# NOTES:
states except Shift-DR Shift-IR
output input/output pins floated during three-state test mode (except IERR#). These signals when Pentium® processors with MMXtechnology operating dual processing mode. These signals undefined when processor configured Dual processor. internal pull-up resistor.
Pentium® Processor with MMXTechnology
Table
Input Pins
Name A20M# AHOLD APICEN BOFF# BRDY# BRDYC# BUSCHK# CPUTYP EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR LINT1-LINT0 KEN# PEN# PICCLK R/S# RESET SMI# STPCLK# TRST# WB/WT# Active Level High High High High High High High High High High High Synchronous/TCK Synchronous/TCK Asynchronous Synchronous Synchronous/RESET Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up First BRDY#/NA# Pull-up Pull-up BRDY# EADS# APICEN RESET First BRDY#/NA# State BRDY# Pull-down Synchronous/ Asynchronous Asynchronous Synchronous Synchronous/RESET Synchronous/RESET Synchronous/RESET Synchronous Synchronous Synchronous Synchronous Pull-up Pull-up Pull-up State T12, State T12, BRDY# Pull-up Pull-down Pull-up Internal Resistor Qualified
Undefined when processor configured Dual processor.
Pentium® Processor with MMXTechnology
Table
Input/Output Pins
Name(1) A31-A3 BE3#-BE0# D63-D0 DP7-DP0 DPEN# PICD0 PICD1 Active Level When Floated Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Address Hold, Hold, BOFF# Hold, BOFF# Hold, BOFF# Qualified (when input) EADS# EADS# RESET BRDY# BRDY# RESET Pull-up Pull-up Pull-down Pull-down(2) Internal Resistor
NOTES: output input/output pins floated during three-state test mode (except TDO, IERR# TDO). BE3#-BE0# have Pull-downs during RESET only.
Table
Inter-processor Input/Output Pins
Name PHIT# PHITM# PBGNT# PBREQ# Active Level Internal Resistor Pull-up Pull-up Pull-up Pull-up
NOTE: proper inter-processor operation, system cannot load these signals.
Pentium® Processor with MMXTechnology
2.1.5
Grouping According Function
Table organizes pins with respect their function.
Table Functional Grouping
Function Clock Initialization Address Address Mask Data Address Parity APIC Support Data Parity Internal Parity Error System Error Cycle Definition Control Page Cacheability Cache Control Cache Snooping/Consistency Cache Flush Write Ordering Arbitration Dual Processing Private Control Interrupts Floating-Point Error Reporting System Management Mode Port Breakpoint/Performance Monitoring Power Management Miscellaneous Dual Processing Debugging Voltage Detection RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 APCHK# PICCLK, PICD1-PICD0 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, PCD, KEN#, WB/WT# AHOLD, EADS#, HIT#, HITM#, FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0/BP0, PM1/BP1, BP3-BP2 STPCLK# CPUTYP, D/P# R/S#, PRDY VCC2DET# Pins
Pentium® Processor with MMXTechnology
Mechanical Specifications
Package summary information provided Table mechanical specifications Pentium processor with technology provided Table Figure
Table PPGA Package Information
Package Type Plastic Staggered Grid Array (PPGA) Total Pins Array Package Size 1.95" 1.95" 4.95 4.95
Figure PPGA Package Dimensions
Table PPGA Package Dimensions
Millimeters Symbol 1.52 3.05 2.54 0.40 49.43 45.59 23.44 2.29 17.56 23.04 3.30 Lead Count 0.060 0.120 0.100 2.72 1.83 1.00 0.51 49.63 45.85 23.95 2.79 0.016 1.946 1.795 0.923 0.090 0.692 0.907 0.130 Lead Count 3.33 2.23 Notes 0.107 0.072 0.039 0.020 1.954 1.805 0.943 0.110 0.131 0.088 Notes Inches
Pentium® Processor with MMXTechnology
Thermal Specifications
Pentium processor with technology specified proper operation when case temperature, TCASE, (TC) within range power dissipation specification Table provided designing thermal solutions operation sustained maximum level. This worst-case power device would dissipate system sustained period time. This number provided assist design thermal solution device.
Table Power Dissipation Requirements Thermal Design
Measured VCC2=2.8 VCC3=3.3 Parameter Active Power Stop Grant/Auto Halt Powerdown Power Stop Clock Power 0.03 Typical 7.9(3)
17.0(4) 15.7(4) 2.61 2.41
Unit Watts Watts Watts Watts Watts
Notes MHz, Note MHz, Note frequencies, Note
NOTES: This typical power dissipation system. This value expected average value that will measured system using typical device VCC2 running typical applications. This value highly dependent upon specific system configuration. Typical power specifications tested. Systems must designed thermally dissipate maximum active power dissipation. determined using worst case instruction with VCC2 VCC3 also takes into account thermal time constants package. Active Power (typ) average power measured system using typical device running typical applications under normal operating conditions nominal room temperature. Active Power (max) maximum power dissipation under normal operating conditions nominal VCC2, worst-case temperature, while executing worst case power instruction mix. Active power (max) equivalent Thermal Design Power (max). Stop Grant/Auto Halt Power Down Power Dissipation determined asserting STPCLK# executing HALT instruction. Stop Clock Power Dissipation determined asserting STPCLK# then removing external input.
Measuring Thermal Values
verify that proper maintained, should measured center package surface (opposite pins). measurement made same with without heatsink attached. When heatsink attached, hole (smaller than 0.150" diameter) should drilled through heatsink allow probing center package. Figure illustration measure minimize measurement errors, following approach:
36-gauge finer diameter type thermocouples. laboratory testing done
using thermocouple made Omega (part number 5TC-TTK-36-36).
Attach thermocouple bead junction center package surface using high
thermal conductivity cements. laboratory testing done using Omega Bond* (part number OB-100).
Attach thermocouple 90-degree angle shown Figure
Pentium® Processor with MMXTechnology
hole size should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heatsink base. contact
will affect thermocouple reading.
2.4.1
Thermal Equations
Pentium processor with technology, ambient temperature, (air temperature around processor), specified directly. only restriction that met. calculate values, following equations: Where: =Ambient case temperature (°C) Case-to-ambient thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Maximum power consumption (Watt)
Table lists values Pentium processor with technology passive heatsink. thermal resistance from package case. values shown these tables typical values. actual values depend actual thermal conductivity process attach. thermal resistance from package case ambient. values shown these tables typical values. actual values depend heatsink design, interface between heatsink package, flow system, thermal interactions between processor surrounding components through printed-circuit board ambient air. Figure graph data from Table Thermal data collection parameters:
Heatsinks omni-directional aluminum alloy Features were based standard extrusion practices given height size ranged from mils spacing ranged from mils Base thickness ranged from mils Heatsink attach 0.005" thermal grease Attach thickness 0.002" will improve performance approximately C/Watt
Pentium® Processor with MMXTechnology
Figure Technique Measuring PPGA Packages
Table Thermal Resistance PPGA Packages
Heat Sink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None (°C/Watt) 12.9 (°C/Watt) Laminar Airflow (linear ft/min) 12.2 11.2
Figure Thermal Resistance Heatsink Height, PPGA Packages
0.25 0.35 0.45 0.55 0.65
Flow Rate (LFM)
(°C/W)
Heatsink Height (inches)
Pentium® Processor with MMXTechnology
Electrical Specifications
This section describes electrical differences between Pentium processor with technology Pentium processor, specifications Pentium processor with technology.
Electrical Characteristics
When creating Pentium processor with technology design based existing Pentium processor design, there number electrical differences that require attention. following sections highlight electrical issues pertaining Pentium processor with technology power supplies, connection specifications buffer models. Note that possible design single motherboard that supports more than member Pentium processor family. Refer Pentium® Processor Flexible Motherboard Design Guidelines (order number 243187) more information specific implementation examples.
3.1.1
Power Supplies
main electrical difference between Pentium processor with technology Pentium processor operating voltage. Pentium processor with technology requires separate voltage inputs, VCC2 VCC3. pins supply power Pentium processor with technology core, while VCC3 pins supply power processor pins. Pentium processor, other hand, requires single voltage supply pins. This single supply powers both core pins Pentium processor. connecting VCC2 pins together pins together separate power islands, Pentium processor designs easily converted support Pentium processor with technology. order maintain compatibility with Pentium processor-based platforms, Pentium processor with technology supports standard 3.3-V specification VCC3 pins.
3.1.2
Power Supply Sequencing
There specific power sequence required powering powering down separate VCC3 supplies Pentium processor with technology. recommended that VCC2 VCC3 supplies turned within second each other.
3.1.3
Connection Specifications
Connection specifications power ground inputs, 3.3-V inputs outputs, NC/INC unused inputs discussed following sections.
Pentium® Processor with MMXTechnology
3.1.3.1
Power Ground
clean on-chip power distribution, embedded Pentium processor with technology VCC3 (I/O power), VCC2 (core power) (ground) inputs. Power ground connections must made external pins Pentium processor with technology. circuit board, pins must connected 3.3-V plane. VCC3 pins must connected 2.8-V plane. pins must connected plane.
3.1.3.2
VCC2 VCC3 Measurement Specification
values VCC2 VCC3 should measured bottom side processor pins using oscilloscope with bandwidth least (100 MS/s digital sampling rate). There should short isolation ground lead attached processor bottom side board. measurement should taken following VCC/VSS pairs: AN13/AM10, AN21/AM18, AN29/ AM26, AC37/Z36, U37/R36, L37/H36, A25/B28, A17/B20, A7/B10, G1/K2, S1/V2, AC1/Z2. One-half these pins while others VCC3; operating ranges VCC2 VCC3 pins specified different voltages. Table specification. display should show continuous sampling voltage line, mV/div, ns/div with trigger point center point range. Slowly move trigger high ends specification, verify that excursions beyond these limits observed. There allowances crossing high limits voltage specification. more information measurement techniques, Voltage Guidelines Pentium® Processors with MMXTechnology (order number 243186).
3.1.3.3
Decoupling Recommendations
Liberal decoupling capacitance should placed near Pentium processor with technology. Pentium processor with technology, when driving large address data buses high frequencies, cause transient power surges, particularly when driving large capacitive loads. inductance capacitors interconnects recommended best high-frequency electrical performance. Inductance reduced shortening circuit board traces between Pentium processor with technology decoupling capacitors much possible. These capacitors should evenly distributed around each component power plane. Capacitor values should chosen ensure they eliminate both high frequency noise components. Pentium processor with technology, power consumption transition from level power much higher level high power) very rapidly. typical example would entering exiting Stop Grant State. Another example would executing HALT instruction, causing Pentium processor with technology enter AutoHALT Power Down State, transitioning from HALT Normal State. these examples cause abrupt changes power being consumed Pentium processor with technology. Note that AutoHALT Power Down feature always enabled even when other power management features implemented. Bulk storage capacitors with Effective Series Resistance (ESR) 100- range required maintain regulated supply voltage during interval between time current load changes point that regulated power supply output react change load. order reduce ESR, necessary place several bulk storage capacitors parallel.
Pentium® Processor with MMXTechnology
These capacitors should placed near Pentium processor with technology both VCC2 plane ensure that supply voltage stays within specified limits during changes supply current during operation. Detailed decoupling recommendations provided Flexible Motherboard Design Guidelines (order number 243187). Note: Reducing available bulk capacitance could degrade long term system reliability.
3.1.3.4
3.3-V Inputs Outputs
inputs outputs Pentium processor with technology comply with 3.3-V JEDEC standard levels. Both inputs outputs also TTL-compatible, although inputs cannot tolerate voltage swings above VIN3 (max) specification. System support components which TTL-compatible inputs will interface Pentium processor with technology without extra logic. This because Pentium processor drives according specification (but beyond Pentium processor with technology inputs, voltage must exceed 3.3-V (max) specification. System support components consist 3.3-V devices open-collector devices. open-collector configuration, external resistor should biased VCC3. pins, including PICCLK Pentium processor with technology, V-tolerant-only. When 8259A interrupt controller used, example, system must provide level converters between 8259A Pentium processor with technology.
3.1.3.5
NC/INC Unused Inputs
Important: pins must remain unconnected. reliable operation, always connect unused inputs appropriate signal level. Unused active inputs should connected VCC3. Unused active high inputs should connected (ground).
3.1.3.6
Private
When Pentium processors with technology operating dual processor mode, "private bus" exists arbitrate processor maintain local cache coherency. private consists pinout changes:
Five pins added: PBREQ#, PBGNT#, PHIT#, PHITM#, D/P#. output pins become pins: ADS#, D/C#, W/R#, M/IO#, CACHE#, LOCK#, HIT#,
HITM#, HLDA, SCYC, BE4#. pins given specifications valid delays setup times hold times. Simulate with these parameters their respective buffer models guarantee that proper timings met. specification gives input setup hold times signals that become pins. These setup hold times must only when dual processor present system.
Pentium® Processor with MMXTechnology
3.1.4
Buffer Models
structure buffer models Pentium processor with technology Pentium processor identical. Some values components have changed reflect minor manufacturing process package differences between processors. system should insignificant differences between behavior Pentium processor with technology Pentium processor. Simulation timings using Pentium processor with technology buffer models recommended ensure robust system designs. specific attention signal quality restrictions imposed 3.3-V buffers.
Absolute Maximum Ratings
Table provides stress ratings only. Functional operation Absolute Maximum Ratings implied guaranteed. Functional operating conditions given specification tables. Extended exposure maximum ratings affect device reliability. Furthermore, although Pentium processor with technology contains protective circuitry resist damage from electrostatic discharge, always take precautions avoid high static voltages electric fields.
Table Absolute Maximum Ratings
Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC2 VIN3 VCC3 Supply Voltage with respect VCC2 Supply Voltage with respect Only Buffer Input Voltage -0.5 -0.5 -0.5 +0.5 (not exceed VCC3 max) Unit
Warning:
Stressing device beyond Absolute Maximum Ratings cause permanent damage. These stress ratings only. Operation beyond specifications recommended guaranteed extended exposure beyond specifications affect device reliability.
Pentium® Processor with MMXTechnology
Specifications
Tables through list specifications Pentium processor with technology.
Table TCASE Specifications
Symbol TCASE VCC2 VCC3 Parameter Case Temperature Voltage Voltage 3.135 Nom. Unit Range 3.57% Range -5%, +9.09% Notes
"VCC2 VCC3 Measurement Specification" page
Table Specifications
Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Voltage Input High Voltage Output Voltage Output High Voltage -0.3 VCC3 +0.3 Unit Notes Level Level Level Level(4)
NOTES: Parameter measured nominal VCC3 which Parameter measured dual processing systems, load from second processor observed PCHK# signal. Based silicon characterization data, VOL3 PCHK# will remain less than even with load. PCHK# VOL3 will increase approximately with load (worst case system with system load). Parameter measured
Table Specifications
Measured VCC2=2.9 VCC3=3.6 Symbol ICC2 ICC3 Parameter Power Supply Current Power Supply Current 6500 5700 Unit Notes
This value should used power supply design. determined using worst case instruction maximum Power supply transient response decoupling capacitors must sufficient handle instantaneous current changes occurring during transitions from Stop Clock full Active modes.
Pentium® Processor with MMXTechnology
Table Input Output Characteristics
Symbol CI/O CCLK CTIN CTOUT Parameter Input Capacitance Output Capacitance Capacitance Input Capacitance Test Input Capacitance Test Output Capacitance Test Clock Capacitance Input Leakage Current Output Leakage Current Input Leakage Current Input Leakage Current -400 Unit Notes Guaranteed design Guaranteed design Guaranteed design Guaranteed design Guaranteed design Guaranteed design Guaranteed design VIL, Note VIL, VCC, Note Note Notes
NOTES: This parameter inputs/outputs without internal pull-up pull-down. This parameter inputs with internal pull-down. This parameter inputs with internal pull-up. This specification applies HITM# when driven input (e.g., JTAG mode).
Specifications
specifications consist output delays, input setup requirements input hold requirements. specifications (with exception those signals APIC signals) relative rising edge input. timings referenced volts both logic levels unless otherwise specified. Within sampling window, synchronous input must stable correct Pentium processor with technology operation. Each valid delay specified load. system designer should buffer modeling account signal flight time delays. Each Pentium processor with technology specified operate within single bus-to-core ratio specific minimum maximum frequency range (corresponding minimum maximum core frequency range). Operation other bus-to-core ratios outside specified operating frequency range supported. example, Pentium processor with technology does operate beyond frequency only supports bus-to-core ratio; does support 1/3, 1/2, bus-to-core ratios. Table summarizes these specifications.
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol Frequency Period Period Stability High Time Time Fall Time Rise Time PWT, PCD, CACHE# Valid Delay Valid Delay BE7#-BE0#, LOCK# Valid Delay ADS# Valid Delay ADSC#, D/C#, W/R#, SCYC, Valid Delay M/IO# Valid Delay A16-A3 Valid Delay A31-A17 Valid Delay ADS#, ADSC#, A31-A3, PWT, PCD, BE7#-BE0#, M/IO#, D/C#, W/R#, CACHE#, SCYC, LOCK# Float Delay APCHK#, IERR#, FERR# Valid Delay PCHK# Valid Delay BREQ Valid Delay SMIACT# Valid Delay HLDA Valid Delay HIT# Valid Delay HITM# Valid Delay PM1-PM0, BP3-BP0 Valid Delay PRDY Valid Delay D63-D0, DP7-DP0 Write Data Valid Delay D63-D0, DP3-DP0 Write Data Float Delay A31-A5 Setup Time A31-A5 Hold Time INV, Setup Time EADS# Setup Time EADS#, INV, Hold Time 0.15 0.15 10.0 Parameter 33.33 15.0 66.6 30.0 ±250 Unit Figure Adjacent Clocks, Notes Note Note Notes Notes Notes
t10a t10b t11a t11b t16a t16b
10.0 10.0
NOTE: Table notes.
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol t18a t18b t24a t24b t25a t25b t42a Parameter KEN# Setup Time NA#, WB/WT# Setup Time KEN#, WB/WT#, Hold Time BRDY#, BRDYC# Setup Time BRDY#, BRDYC# Hold Time AHOLD, BOFF# Setup Time AHOLD, BOFF# Hold Time BUSCHK#, EWBE#, HOLD Setup Time PEN# Setup Time BUSCHK#, EWBE#, PEN# Hold Time HOLD Hold Time A20M#, INTR, STPCLK# Setup Time A20M#, INTR, STPCLK# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Setup Time INIT, FLUSH#, NMI, SMI#, IGNNE# Hold Time INIT, FLUSH#, NMI, SMI#, IGNNE# Pulse Width, Async R/S# Setup Time R/S# Hold Time R/S# Pulse Width, Async. D0-D63, DP0-7 Read Data Setup Time D0-D63, DP0-7 Read Data Hold Time RESET Setup Time RESET Hold Time RESET Pulse Width, Stable RESET Active After Stable Reset Configuration Signals (INIT, FLUSH#) Setup Time Reset Configuration Signals (INIT, FLUSH#) Hold Time Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. Reset Configuration Signals (INIT, FLUSH#, BRDYC#, BUSCHK#) Hold Time, Async. 15.0 Unit Notes Power Notes RESET falling edge, Note RESET falling edge, Note Figure Notes Notes Notes Notes Notes Notes
t42b
NOTE: Table notes.
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol t42c t43a t43b t43c t43d Parameter Reset Configuration Signals (BRDYC#, BUSCHK#) Setup Time, Async. BF0, BF1, CPUTYP Setup Time BF0, BF1, CPUTYP Hold Time APICEN, BE4# Setup Time APICEN, BE4# Hold Time Frequency Period High Time Time Fall Time Rise Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 APIC Specifications t60a t60b t60c t60d t60e t60f t60g t60h t60i t60j t80a PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD1-PICD0 Setup Time PICD1-PICD0 Hold Time PICD1-PICD0 Valid Delay (LtoH) PICD1-PICD0 Valid Delay (HtoL) PBREQ#, PBGNT#, PHIT# Flight Time 60.0 15.0 15.0 0.15 0.15 38.0 22.0 16.66 500.0 PICCLK PICCLK From PICCLK, Note From PICCLK, Note Notes 40.0 13.0 20.0 25.0 20.0 25.0 62.5 25.0 25.0 16.0 Unit Note Note Notes Notes Asynchronous, Note Notes Notes Notes Notes Notes Figure Notes RESET falling edge, Note RESET falling edge, Note RESET falling edge, Note RESET falling edge RESET falling edge
NOTE: Table notes.
Pentium® Processor with MMXTechnology
Table Specifications (Sheet
Table TCASE specifications, Symbol t80b t83a t83b t83c t83d t83e t84a t84b t84c t84d Parameter PHITM# Flight Time A31-A5 Setup Time D/C#, W/R#, CACHE#, LOCK#, SCYC Setup Time ADS#, M/IO# Setup Time HIT#, HITM# Setup Time HLDA Setup Time CACHE#, HIT# Hold Time ADS#, D/C#, W/R#, M/IO#, A31-A5, HLDA, SCYC Hold Time LOCK# Hold Time HITM# Hold Time DPEN# Valid Time DPEN# Hold Time APIC (BE3#-BE0#) Setup Time APIC (BE3#-BE0#) Hold Time D/P# Valid Delay 10.0 Unit Figure Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes falling Edge RESET, Note From Falling Edge RESET, Note Primary Processor Only
NOTE: Table notes.
Pentium® Processor with MMXTechnology
Table Notes Table
NOTES: Notes general apply standard signals used with Pentium® processor family. Each valid delay specified load. system designer should buffer models account signal flight time delays. 100% tested. Guaranteed design/characterization. input test waveforms assumed transitions with V/ns rise fall times. Non-test outputs inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. APCHK#, FERR#, HLDA, IERR#, LOCK# PCHK# glitch-free outputs. Glitch-free signals monotonically transition without false transitions. V/ns input rise/fall time V/ns. V/ns input rise/fall time V/ns. Referenced rising edge. Referenced falling edge. added maximum rise fall times every frequency below MHz. 10.During debugging, boundary scan timings (t55 t58). 11.This flight time specification, that includes both flight time clock skew. flight time time from where unloaded driver crosses (50% where receiver crosses level (50% Figure minimum flight time minus clock skew must greater than zero. 12.Setup time required guarantee recognition specific clock. Pentium® processor with MMXtechnology must meet this specification dual processor operation FLUSH# RESET signals. 13.Hold time required guarantee recognition specific clock. Pentium processor with technology must meet this specification dual processor operation FLUSH# RESET signals. 14.All timings referenced from 15.To guarantee proper asynchronous recognition, signal must have been deasserted (inactive) minimum clocks before being returned active must meet minimum pulse width. 16.This input driven asynchronously. However, when operating processors dual processing mode, FLUSH# RESET must asserted synchronously both processors. 17.When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT SMI# must deasserted (inactive) minimum clocks before being returned active. 18.Timings valid only when dual processor present. 19.Maximum time DPEN# valid from rising edge RESET. 20.Minimum time DPEN# valid after falling edge RESET. 21.The D/C#, M/IO#, W/R#, CACHE# A31-A5 signals sampled only that ADS# active. 22.In order override internal defaults guarantee that BF1-BF0 inputs remain stable while RESET active, these pins should strapped directly through pull-up/pull-down resistor VCC3 ground. Driving these pins with active logic recommended unless stability during RESET guaranteed. Similarly, CPUTYP should also strapped directly through pull-up/pull-down resistor VCC3 ground. 23.RESET synchronous dual processing mode. signals which have setup hold time with respect falling rising edge RESET mode, should measured with respect first processor clock edge which RESET sampled either active inactive dual processing mode. 24.The PHIT# PHITM# signals operate core frequency. 25.These signals measured rising edge adjacent CLKs ensure relationship between amplitude input jitter internal external clocks, jitter frequency spectrum should have power spectrum peaking between operating frequency. amount jitter present must accounted component skew between devices. internal clock generator requires constant frequency input within ±250 Therefore, input cannot changed dynamically. 26.In dual processing mode, timing replaced t83a. Timing required external snooping (e.g., address setup which EADS# sampled active) both uniprocessor dual processor modes. 27.BRDYC# BUSCHK# used reset configuration signals select buffer size. 28.This assumes external pull-up resistor lumped capacitive load. pull-up resistor must between capacitance must between product must between PICD1-PICD0 0.55
Pentium® Processor with MMXTechnology
Figure Clock Waveform
2.0V 0.8V T25, (Rise Time) T26, (Fall Time) T23, (High Time) T24, (Low Time) T22, (BLCK, TCK, PICCLK Period)
P6CB761a
1.5V
Figure Valid Delay Timings
1.5V max. Signal 1.5V VALID min.
t10, t11, t12, t60i, t60j, t80a,
Figure Float Delay Timings
Pentium® Processor with MMXTechnology
Figure Setup Hold Timings
Figure Reset Configuration Timings
Pentium® Processor with MMXTechnology
Figure Test Timings
Figure Test Reset Timings
Pentium® Processor with MMXTechnology
Figure Percent Measurement Flight Time
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