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Embedded Pentium® Processor with MMX Technology

200 MHz, 233 MHz

Embedded Pentium® Processor with MMX Technology
200 MHz, 233 MHz
Datasheet
Product Features
Support for MMX Technology Compatible with Large Software Base - MS-DOS, Windows, OS / 2, UNIX 32-Bit Processor with 64-Bit Data Bus Superscalar Architecture - Enhanced Pipelines - Two Pipelined Integer Units Capable of Two Instructions per Clock - Pipelined MMX Technology Unit - Pipelined Floating-Point Unit Separate Code and Data Caches - 16-Kbyte Code, 16-Kbyte Write Back Data - MESI Cache Protocol Advanced Design Features - Deeper Write Buffers - Enhanced Branch Prediction Feature - Virtual Mode Extensions Enhanced CMOS Silicon Technology
Contact Intel Corporation for more information about iCOMP® Index 2.0 ratings.
Order Number: 273214-001 November 1998
Datasheet
Embedded Pentium® Processor with MMX Technology
Contents
1.0 Architecture Overview ............................................... 7
Packaging Information .............................................. 12
2.1 Pinout ......................................................... 12 2.1.1 Pin Cross Reference .......................................14 2.1.2 Design Notes .............................................16 2.1.3 Pin Quick Reference .......................................16 2.1.4 Pin Reference Tables....................................... 24 2.1.5 Pin Grouping According to Function............................ 27 Mechanical Specifications .......................................... 28 Thermal Specifications ............................................ 29 Measuring Thermal Values ......................................... 29 2.4.1 Thermal Equations ......................................... 30
Electrical Specifications ............................................ 32
3.1 Electrical Characteristics ...........................................32 3.1.1 Power Supplies ........................................... 32 3.1.2 Power Supply Sequencing ................................... 32 3.1.3 Connection Specifications ................................... 32 3.1.3.1 Power and Ground .................................. 33 3.1.3.2 VCC2 and VCC3 Measurement Specification............... 33 3.1.3.3 Decoupling Recommendations ......................... 33 3.1.3.4 3.3-V Inputs and Outputs ............................. 34 3.1.3.5 NC / INC and Unused Inputs ............................ 34 3.1.3.6 Private Bus ........................................ 34 3.1.4 Buffer Models ............................................. 35 Absolute Maximum Ratings......................................... 35 DC Specifications ................................................ 36 AC Specifications ................................................ 37
Figures
1 2 3 4 5 Pentium® Processor with MMX Technology Block Diagram............... 9 Pentium® Processor with MMX Technology PPGA Package Pinout - Top Side View ............................................ 12 Pentium® Processor with MMX Technology PPGA Package Pinout - Bottom Side View.......................................... 13 PPGA Package Dimensions........................................ 28 Technique for Measuring TC on PPGA Packages........................31
Datasheet
Embedded Pentium ® Processor with MMX Technology
Thermal Resistance vs. Heatsink Height, PPGA Packages ................ 31 Clock Waveform ................................................. 43 Valid Delay Timings .............................................. 43 Float Delay Timings .............................................. 43 Setup and Hold Timings ........................................... 44 Reset and Configuration Timings .................................... 44 Test Timings.................................................... 45 Test Reset Timings ............................................... 45 50 Percent VCC Measurement of Flight Time........................... 46
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Cross-Reference by Pin Name - Address and Data Pins .............. 14 Pin Cross-Reference by Pin Name - Control Pins ...................... 15 Pin Cross-Reference by Pin Name - Power, Ground and No Connect Pins .. 16 Quick Pin Reference .............................................. 17 Bus Frequency Selections ......................................... 23 Output Pins ..................................................... 24 Input Pins ...................................................... 25 Input / Output Pins ................................................ 26 Inter-processor Input / Output Pins .................................... 26 Pin Functional Grouping........................................... 27 PPGA Package Information ........................................ 28 PPGA Package Dimensions ........................................ 28 Power Dissipation Requirements for Thermal Design .................... 29 Thermal Resistance for PPGA Packages .............................. 31 Absolute Maximum Ratings ........................................ 35 VCC and TCASE Specifications ...................................... 36 3.3 V DC Specifications ........................................... 36 ICC Specifications ................................................ 36 Input and Output Characteristics..................................... 37 AC Specifications ................................................ 38 Notes for Table 20 ................................................ 42
Datasheet
Embedded Pentium® Processor with MMX Technology
Revision History
Date 11 / 98 Revision 001 Description This is the first publication of this document.
Datasheet
Pentium® Processor with MMX Technology
Architecture Overview
The embedded Pentium ® processor with MMX technology is binary compatible with the 8086 / 8088, 80286, Intel386TM, and Intel486 processor families, and with other Pentium processors. The embedded Pentium processor family includes the following products.
Pentium processor Pentium processor with Voltage Reduction Technology Pentium processor with MMX technology Low-Power embedded Pentium processor with MMX technology
The Pentium processor family supports the features of previous Intel Architecture processors, and provides significant enhancements and additions including the following:
Superscalar architecture Dynamic branch prediction Pipelined floating-point unit Improved instruction execution time Separate code and data caches Writeback MESI protocol in the data cache 64-bit data bus Bus cycle pipelining
Address parity Internal parity checking Execution tracing Performance monitoring IEEE 1149.1 boundary scan System Management Mode Virtual Mode extensions Dual processing support On-chip local APIC device
In addition to the features listed above, the Pentium processor with MMX technology offers the following enhancements over the Pentium processor:
Support for Intel® MMX technology Doubled code and data cache sizes to 16 Kbytes each Improved branch prediction Enhanced pipeline Deeper write buffers
The following features are supported by the Pentium processor, but these features are not supported by the Pentium processor with MMX technology:
· Functional redundancy check and Lock-Step operation. · Support for Intel 82498 / 82493 and 82497 / 82492 cache chipset products · Split-line accesses to the code cache
Datasheet
Pentium® Processor with MMX Technology
Pentium® Processor Family Architecture
Datasheet
Pentium® Processor with MMX Technology
Figure 1. Pentium® Processor with MMX Technology Block Diagram
Control
DP Logic
Branch Prefetch Target Buffer Address
TLB Code Cache 16 Kbytes
Instruction Pointer 64-Bit Data Bus 32-Bit Address Bus Bus Unit Branch Verification and Target Address
Prefetch Buffers Instruction Decode
Control ROM
Control Unit
V-Pipeline Connection U-Pipeline Connection
Page Unit Address Address Generate Generate (U Pipeline) (V Pipeline)
MMX Unit
Floating Point Unit
Control Register File
Control
Integer Register File
64-Bit 64 Data Bus
Add Divide 80 Multiply 80
ALU (U Pipline)
32 32-Bit Addr. Bus
ALU (V Pipline)
Barrel Shifter
Data APIC Control
Data Cache 16 Kbytes TLB
A6180-01
The block diagram shows the two instruction pipelines, the "u" pipe and the "v" pipe. The u-pipe can execute all integer and floating-point instructions. The v-pipe can execute simple integer instructions and the FXCH floating-point instructions. The separate code and data caches are shown in the block diagram. The data cache has two ports, one for each of the two pipes (the tags are triple-ported to allow simultaneous inquire cycles). The data cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to the physical addresses used by the data cache. The code cache, branch target buffer and prefetch buffers are responsible for getting raw instructions into the execution units. Instructions are fetched from the code cache or from the external bus. Branch addresses are remembered by the branch target buffer. The code cache TLB translates linear addresses to physical addresses used by the code cache.
Datasheet
Pentium® Processor with MMX Technology
Embedded Pentium® Processor with MMX Technology
Datasheet
Pentium® Processor with MMX Technology
MMX technology is based on the Single Instruction Multiple Data (SIMD) technique which enables increased performance on a wide variety of multimedia and communications applications. Fifty-seven new instructions and four new 64-bit data types are supported in the embedded Pentium processor with MMX technology. All existing operating system and application software are fullycompatible with the embedded Pentium processor with MMX technology.
16-Kbyte Code and Data Cache
On-chip, level-one (L1) data and code cache sizes have been doubled to 16 Kbytes each. These caches are 4-way set associative. Larger separate internal caches improve performance by reducing average memory access time and providing fast access to recently-used instructions and data. The instruction and data caches can be accessed simultaneously. The data cache supports two data references simultaneously. The data cache supports a write back policy (or alternatively, writethrough, on a line-by-line basis) for memory updates. By default, the code cache is write-protected.
Improved Branch Prediction
Dynamic branch prediction uses the Branch Target Buffer (BTB) to boost performance by predicting the most likely set of instructions to be executed. The BTB has been improved to increase its accuracy. The embedded Pentium processor with MMX technology has four prefetch buffers that can hold up to four successive code streams.
Enhanced Pipeline
Deeper Write Buffers
A pool of four write buffers is now shared between the dual pipelines to improve memory write performance.
Datasheet
Pentium® Processor with MMX Technology
Packaging Information
Pinout
Figure 2. Pentium® Processor with MMX Technology PPGA Package Pinout - Top Side View
37 36 35 34 33 32 31 30 29 28 27 26 25 AN AM AL VSS AK A28 AJ VSS AH A22 AG VCC3 AF VSS AE VCC3 AD VSS AC AB VSS AA VCC3 Z VSS Y X W VCC3 V VSS STPCLK# U VCC3 T S VCC3 R VSS Q P N M VSS L VCC3 K VSS J VCC3 H VSS G VCC3 F D4 E VCC3 D C D9 B A NC D15 D18 D22 VCC3 VCC3 VCC3 D11 D10 D13 D14 D16 D17 D20 D21 D24 VSS DP2 VSS DP0 D6 D8 D7 D12 DP1 D19 D23 D5 D1 D3 PICCLK D2 D0 PICD0 PICD1 VCC3 TCK VCC3 CPUTYP TRST# VSS VCC3 TDI TMS TDO NC NC NC VSS VCC3 VSS VCC3 NC NC VCC3 NC BF0 BF1 PEN# IGNNE# INIT SMI# VCC3 INTR NMI D / P# A23 A21 A24 A27 A26 A25 A31 A29 A5 A9 A13 A15 A3 A7 A11 A12 A14 A16 VSS A30 NC A4 A6 A8 A10 VCC3 VSS VCC3 VCC3
24 23 22 21 20 19 VCC3 VSS A18 A17 A19 VCC3
18 17 VCC2
16 15 14 13 12 11 VCC2 VSS VCC2 VCC2
VCC2 FLUSH# INC VSS W / R#
VSS A20
VSS NC
EADS# ADSC# PWT
VCC2 DET#
BE0# BUSCHK# HITM# A20M# HIT#
RESET CLK
HLDA BREQ VSS AG AF
LOCK#
PCD SMIACT# VCC2 PCHK# VSS AE
APCHK# PBREQ# VCC2
AD PBGNT# VSS PRDY PHITM# VCC2 HOLD VSS AA Z Y NA# BRDYC# VCC2 X BRDY# VSS W KEN# EWBE# VCC2 V AHOLD
WB / WT# PHIT# VCC2 BOFF# VSS
Top Side View
CACHE# VCC2
MI / O# BP3 BP2
R PM1BP1 VSS
FERR# PM0BP0 VCC2
IERR# DP7 D62 D60 D59 D58 D56 D53 DP5 D42 D26 D25 VSS D28 D27 D30 D29 VSS DP3 D31 VSS D33 D32 VSS D35 D34 D37 D36 VSS D39 D38 D40 D46 D44 DP4 D45 D43 D49 D48 D47 D51 D52 D55 D57 D61 D63
DP6 D54 D50
VCC3 VCC3
VCC2 7
A6174-01
Datasheet
Pentium® Processor with MMX Technology
Figure 3. Pentium® Processor with MMX Technology PPGA Package Pinout - Bottom Side View
10 11 12 13 14 15 16 VCC2 VCC2
17 18 VCC2
19 20 21 22 23 24 VCC2 VCC3 VCC3
25 26 VCC3
27 28 29 30 31 32 33 34 35 36 37 AN VCC3 VCC3 A10 A8 A7 A5 A31 A26 A27 A21 A23 INTR NMI A24 A29 A25 A22 VCC3 AF VSS D / P# VCC3 AE AD VSS R / S# AC VCC3 AB AA Z A6 A4 A3 A28 AJ VSS AH AG NC A30 AL VSS AK VSS AM
FLUSH# VCC2 VCC2 VSS VSS
ADSC# EADS#
VCC2 DET#
VSS NC
VSS A20
VSS A18 A19
VSS A16 A17
VSS A14 A15
VSS A12 A13
VSS A11 A9
HITM# BUSCHK# BE0# HIT# A20M#
SCYC CLK
RESET
BREQ HLDA VSS
LOCK#
VCC2 SMIACT# PCD VSS PCHK#
VCC2 PBREQ# APCHK# PBGNT#
VCC2 PHITM# PRDY VSS VCC2 HOLD
PHIT# WB / WT# BOFF#
INIT IGNNE# VCC3 PEN# BF0 BF1 NC NC
VSS Y VCC3 X VSS W VCC3 V U
VCC2 BRDYC# NA# VSS BRDY#
VCC2 EWBE# KEN# V U T S VCC2 R VSS Q P N VCC2 M VSS L VCC2 K VSS J H G VCC2 F DP6 E D54 D D50 C B A 1 2 D48 D47 D45 D43 D44 DP4 VSS D41 4 5 6 D40 D38 D39 D36 D37 D34 VSS VCC2 D35 D32 VSS D33 D31 VSS DP3 D29 VSS D30 D27 VSS VCC3 20 21 VSS D28 D25 D26 D23 DP2 D24 VSS D19 D21 D20 VCC3 29 D22 DP1 D17 D16 D12 D52 D49 D46 D42 D51 DP5 D55 D53 VCC2 D57 D56 D58 D59 D61 D62 D60 D63 DP7 PM1BP1 BP2 BP3 VCC2 CACHE# INV VSS MI / O# VSS AHOLD
Pin Side View
STPCLK# VSS VCC3 VSS VCC3 T VCC3 NC NC NC VSS VCC3 VSS VCC3 Q P N TDO TCK VCC3 TDI VCC3 M VSS L PICD1 VCC3 K D0 PICD0 D2 VSS J VCC3 H PICCLK VSS D3 D5 D7 D8 D14 D13 D18 D15 D10 D11 A NC D6 D1 D4 VCC3 DP0 C D9 B E D VCC3 G F S R
VCC2 PM0BP0 FERR# VSS IERR#
TRST# CPUTYP
INC INC
VCC2 9
A6173-01
Datasheet
Pentium® Processor with MMX Technology
Table 1.
Pin Cross Reference
Pin Cross-Reference by Pin Name - Address and Data Pins
Pin Location Pin Location Pin Location Pin Location Pin Location
Address A3 A4 A5 A6 A7 A8 AL35 AM34 AK32 AN33 AL33 AM32 A9 A10 A11 A12 A13 A14 AK30 AN31 AL31 AL29 AK28 AL27 A15 A16 A17 A18 A19 A20 Data D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 K34 G35 J35 G33 F36 F34 E35 E33 D34 C37 C35 B36 D32 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 B34 C33 A35 B32 C31 A33 D28 B30 C29 A31 D26 C27 C23 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D24 C21 D22 C19 D20 C17 C15 D16 C13 D14 C11 D12 C09 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D10 D08 A05 E09 B04 D06 C05 E07 C03 D04 E05 D02 F04 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 E03 G05 E01 G03 H04 J03 J05 K04 L05 L03 M04 N03 AK26 AL25 AK24 AL23 AK22 AL21 A21 A22 A23 A24 A25 A26 AF34 AH36 AE33 AG35 AJ35 AH34 A27 A28 A29 A30 A31 AG33 AK36 AK34 AM36 AJ33
Datasheet
Pentium® Processor with MMX Technology
Table 2.
Pin Cross-Reference by Pin Name - Control Pins
Pin Location Pin Location Control A20M# ADS# ADSC# AHOLD AP APCHK# BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BP2 BP3 BRDY# BRDYC# AK08 AJ05 AM02 V04 AK02 AE05 AL09 AK10 AL11 AK12 AL13 AK14 AL15 AK16 Z04 S03 S05 X04 Y03 BREQ BUSCHK# CACHE# CPUTYP D / C# D / P# DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 EADS# EWBE# FERR# FLUSH# FRCMC# 1 AJ01 AL07 U03 Q35 AK04 AE35 D36 D30 C25 D18 C07 F06 F02 N05 AM04 W03 Q05 AN07 Y35 HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR / LINT 0 INV KEN# LOCK# M / IO# NA# NMI / LINT1 PCD PCHK# PEN# PM0 / BP0 PM1 / BP1 APIC PICCLK H342 PICD0 / DP EN# J33 PICD1 / API CEN L35 AK06 AL05 AJ03 AB04 P04 AA35 AA33 AD34 U05 W05 AH04 T04 Y05 AC33 AG05 AF04 Z34 Q03 R04 PRDY PWT R / S# RESET SCYC SMI# SMIACT# TCK TDI TDO TMS TRST# VCC2DET# W / R# WB / WT# AC05 AL03 AC35 AK20 AL17 AB34 AG03 M34 N35 N33 P34 Q33 AL01 AM06 AA05 Pin Location Pin Location
Clock Control CLK AK182 BF0 Y33 BF1 X34 STPCLK# V34
Dual Processor Private Interface PBGNT# AD04 PBREQ# AE03 PHIT# AA03 PHITM# AC03
Datasheet
Pentium® Processor with MMX Technology
Table 3.
Pin Cross-Reference by Pin Name - Power, Ground and No Connect Pins
VCC2 A17 A15 A13 A11 A09 A07 G01 J01 L01 N01 Q01 S01 U01 W01 Y01 VCC3 A19 A21 A23 A25 A27 A29 E37 G37 J37 L37 L33 N37 Q37 S37 T34 VSS B06 B08 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 H02 H36 K02 K36 M02 M36 NC A37 R34 S33 S35 W33 INC A03 B02 C01 AN01 AN03 AN05 W35 AL19 AN35 Y35 P02 P36 R02 R36 T02 T36 U35 V02 V36 X02 X36 Z02 Z36 AB02 AB36 AD02 AD36 AF02 AF36 AH02 AJ37 AL37 AM08 AM10 AM12 AM14 AM16 AM18 AM20 AM22 AM24 AM26 AM28 AM30 AN37 U33 U37 W37 Y37 AA37 AC37 AE37 AG37 AN29 AN27 AN25 AN23 AN21 AA01 AC01 AE01 AG01 AN09 AN11 AN13 AN15 AN17 AN19
Design Notes
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to GND. Note: No Connect (NC) pins must remain unconnected. Connection of NC or INC pins may result in component failure or incompatibility with future processor steppings.
Pin Quick Reference
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 1 of 7)
A20M#
ADS# ADSC#
AHOLD
APCHK#
APICEN PICD1
BE7#-BE4# BE3#-BE0#
BF1-BF0
BOFF#
BP3-BP2 PM1-PM0 / BP1-BP0
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 2 of 7)
BRDY#
BRDYC# BREQ
CACHE#
CPUTYP
D63-D0
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 3 of 7)
DP7-DP0
DPEN# PICD0
EADS#
EWBE#
FERR#
HITM#
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 4 of 7)
IERR#
IGNNE#
INTR / LINT0
LINT0 / INTR LINT1 / NMI
LOCK#
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 5 of 7)
NMI / LINT1
PBGNT#
PBREQ#
PCHK#
PHIT#
PHITM#
PICD0 / DPEN#- PICD1 / APICEN
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 6 of 7)
RESET
SMIACT#
STPCLK#
TMS TRST# VCC2 VCC3 VCC2DET#
Datasheet
Pentium® Processor with MMX Technology
Table 4.
Quick Pin Reference (Sheet 7 of 7)
Symbol VSS W / R# Type I O Name and Function The Pentium processor with MMX technology has 53 ground inputs. Write / read is one of the primary bus cycle definition pins. It is driven valid in the same clock as the ADS# signal is asserted. W / R# distinguishes between write and read cycles. The write back / write through input allows a data cache line to be defined as write back or write through on a line-by-line basis. As a result, it determines whether a cache line is initially in the S or E state in the data cache.
Core and bus frequencies can be set according to Table 5. Each Pentium processor with MMX technology is specified to operate within a single bus-to-core ratio and a specific minimum-tomaximum bus-frequency range (corresponding to a minimum-to-maximum core-frequency range). Operation in other bus-to-core ratios or outside the specified operating frequency range is not supported or advocated. For example, the 166 MHz Pentium processor with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2 / 5 bus-to-core ratio it does not support the 1 / 3, 1 / 2, or 2 / 3 bus-to-core ratios. Table 5. Bus Frequency Selections
Min Bus / Core Frequency (MHz) 33 / 100 N / A (2) N / A (2) 33 / 117
NOTES: 1. This is the default bus to core ratio for the Pentium® processor with MMX technology. If the BF pins are left floating, the processor will be configured for the 1 / 2 bus to core frequency ratio. 2. Currently, there are no embedded products that support these bus fractions.
Datasheet
Pentium® Processor with MMX Technology
Table 6.
Pin Reference Tables
Output Pins
Name ADS# (1) ADSC# APCHK# BE7#-BE4# BREQ CACHE#(1) D / P#
Active Level Low Low Low Low High Low N / A Low Low Low High Low Low
When Floated Bus Hold, BOFF# Bus Hold, BOFF#
Bus Hold, BOFF#
FERR# HIT# (1) HITM# HLDA
IERR# LOCK# (1) M / IO# , D / C# , W / R# PCHK# BP3-BP2, PM1 / BP1, PM0 / BP0 PRDY PWT, PCD SCYC
Bus Hold, BOFF# Bus Hold, BOFF#
N / A Low High High High High Low N / A Low
Bus Hold, BOFF# Bus Hold, BOFF#
SMIACT# TDO VCC2DET# NOTES:
All states except Shift-DR and Shift-IR
All output and input / output pins are floated during three-state test mode (except IERR#). 1. These are I / O signals when two Pentium® processors with MMX technology are operating in dual processing mode. 2. These signals are undefined when the processor is configured as a Dual processor. 3. M# pin has an internal pull-up resistor.
Datasheet
Pentium® Processor with MMX Technology
Table 7.
Input Pins
Name A20M# AHOLD APICEN BF0 BF1 BOFF# BRDY# BRDYC# BUSCHK# CLK CPUTYP EADS# EWBE# FLUSH# HOLD IGNNE# INIT INTR INV LINT1-LINT0 KEN# NA# NMI PEN# PICCLK R / S# RESET SMI# STPCLK# TCK TDI TMS TRST# WB / WT# Active Level Low High High N / A N / A Low Low Low Low N / A High Low Low Low High Low High High High High Low Low High Low High N / A High Low Low N / A N / A N / A Low N / A Synchronous / TCK Synchronous / TCK Asynchronous Synchronous Synchronous / RESET Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Synchronous Asynchronous Synchronous Synchronous Asynchronous Synchronous Asynchronous Asynchronous Asynchronous Asynchronous Asynchronous Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up First BRDY# / NA# TCK TCK Pull-up Pull-up BRDY# EADS# APICEN at RESET First BRDY# / NA# Bus State T2, TD, T2P BRDY# Pull-down Synchronous / Asynchronous Asynchronous Synchronous Synchronous / RESET Synchronous / RESET Synchronous / RESET Synchronous Synchronous Synchronous Synchronous Pull-up Pull-up Pull-up Bus State T2, T12, T2P Bus State T2, T12, T2P BRDY# Pull-up Pull-down Pull-up Internal Resistor Qualified
Undefined when the processor is configured as a Dual processor.
Datasheet
Pentium® Processor with MMX Technology
Table 8.
Input / Output Pins
Name(1) A31-A3 AP BE3#-BE0# D63-D0 DP7-DP0 DPEN# PICD0 PICD1 Active Level N / A N / A Low N / A N / A low N / A N / A When Floated Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Address Hold, Bus Hold, BOFF# Bus Hold, BOFF# Bus Hold, BOFF# Qualified (when an input) EADS# EADS# RESET BRDY# BRDY# RESET Pull-up Pull-up Pull-down Pull-down(2) Internal Resistor
NOTES: 1. All output and input / output pins are floated during three-state test mode (except TDO, IERR# and TDO). 2. BE3#-BE0# have Pull-downs during RESET only.
Table 9.
Inter-processor Input / Output Pins
Name PHIT# PHITM# PBGNT# PBREQ# Active Level Low Low Low Low Internal Resistor Pull-up Pull-up Pull-up Pull-up
NOTE: For proper inter-processor operation, the system cannot load these signals.
Datasheet
Pentium® Processor with MMX Technology
Pin Grouping According to Function
Table 10 organizes the pins with respect to their function.
Table 10. Pin Functional Grouping
Function Clock Initialization Address Bus Address Mask Data Bus Address Parity APIC Support Data Parity Internal Parity Error System Error Bus Cycle Definition Bus Control Page Cacheability Cache Control Cache Snooping / Consistency Cache Flush Write Ordering Bus Arbitration Dual Processing Private Bus Control Interrupts Floating-Point Error Reporting System Management Mode TAP Port Breakpoint / Performance Monitoring Power Management Miscellaneous Dual Processing Debugging Voltage Detection CLK RESET, INIT, BF1-BF0 A31-A3, BE7#-BE0# A20M# D63-D0 AP, APCHK# PICCLK, PICD1-PICD0 DP7-DP0, PCHK#, PEN# IERR# BUSCHK# M / IO#, D / C#, W / R#, CACHE#, SCYC, LOCK# ADS#, ADSC#, BRDY#, BRDYC#, NA# PCD, PWT KEN#, WB / WT# AHOLD, EADS#, HIT#, HITM#, INV FLUSH# EWBE# BOFF#, BREQ, HOLD, HLDA PBGNT#, PBREQ#, PHIT#, PHITM# INTR, NMI FERR#, IGNNE# SMI#, SMIACT# TCK, TMS, TDI, TDO, TRST# PM0 / BP0, PM1 / BP1, BP3-BP2 STPCLK# CPUTYP, D / P# R / S#, PRDY VCC2DET# Pins
Datasheet
Pentium® Processor with MMX Technology
Mechanical Specifications
Package summary information is provided in Table 11. The mechanical specifications for the Pentium processor with MMX technology are provided in Table 12 and Figure 4.
Table 11. PPGA Package Information
Package Type Plastic Staggered Pin Grid Array (PPGA) Total Pins 296 Pin Array 37 x 37 Package Size 1.95" x 1.95" 4.95 cm x 4.95 cm
Figure 4. PPGA Package Dimensions
Table 12. PPGA Package Dimensions
Millimeters Symbol Min A A1 A2 B D D1 D2 e1 F1 F2 L N S1 1.52 3.05 296 2.54 0.40 49.43 45.59 23.44 2.29 17.56 23.04 3.30 Lead Count 0.060 0.120 296 0.100 2.72 1.83 1.00 0.51 49.63 45.85 23.95 2.79 0.016 1.946 1.795 0.923 0.090 0.692 0.907 0.130 Lead Count Max 3.33 2.23 Notes Min 0.107 0.072 0.039 0.020 1.954 1.805 0.943 0.110 Max 0.131 0.088 Notes Inches
Datasheet
Pentium® Processor with MMX Technology
Thermal Specifications
The Pentium processor with MMX technology is specified for proper operation when case temperature, TCASE, (TC) is within the range of 0° C to 70° C. The power dissipation specification in Table 13 is provided for designing thermal solutions for operation at a sustained maximum level. This is the worst-case power the device would dissipate in a system for a sustained period of time. This number is provided to assist in the design of a thermal solution for the device.
Table 13. Power Dissipation Requirements for Thermal Design
Unit Watts Watts Watts Watts Watts
Notes 233 MHz 200 MHz 233 MHz, Note 5 200 MHz, Note 5 All frequencies, Note 6
Measuring Thermal Values
To verify that the proper TC is maintained, it should be measured at the center of the package top surface (opposite of the pins). The measurement is made in the same way with or without a heatsink attached. When a heatsink is attached, a hole (smaller than 0.150" diameter) should be drilled through the heatsink to allow probing the center of the package. See Figure 5 for an illustration of how to measure TC. To minimize the measurement errors, use the following approach:
· Use 36-gauge or finer diameter K, T, or J type thermocouples. The laboratory testing was done
using a thermocouple made by Omega (part number 5TC-TTK-36-36).
· Attach the thermocouple bead or junction to the center of the package top surface using high
thermal conductivity cements. The laboratory testing was done by using Omega Bond (part number OB-100).
· Attach the thermocouple at a 90-degree angle as shown in Figure 5.
Datasheet
Pentium® Processor with MMX Technology
· The hole size should be smaller than 0.150" in diameter. · Make sure there is no contact between thermocouple cement and heatsink base. The contact
will affect the thermocouple reading.
Thermal Equations
Table 14 lists the JC and CA values for the Pentium processor with MMX technology and a passive heatsink. JC is thermal resistance from die to package case. JC values shown in these tables are typical values. The actual JC values depend on actual thermal conductivity and process of die attach. CA is thermal resistance from package case to the ambient. CA values shown in these tables are typical values. The actual CA values depend on the heatsink design, the interface between the heatsink and the package, the air flow in the system, and thermal interactions between the processor and the surrounding components through the printed-circuit board and the ambient air. Figure 6 is a graph of the data from Table 14. Thermal data collection parameters:
Datasheet
Pentium® Processor with MMX Technology
Figure 5. Technique for Measuring TC on PPGA Packages
Table 14. Thermal Resistance for PPGA Packages
Heat Sink Height (inches) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 None JC (°C / Watt) 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 1.2 0 8.9 8.6 8.2 7.9 7.5 6.8 6.1 5.7 5.2 12.9 CA (°C / Watt) vs. Laminar Airflow (linear ft / min) 100 7.8 7.3 6.8 6.3 5.8 5.1 4.5 4.1 3.7 12.2 200 6.4 5.8 5.1 4.5 4.1 3.7 3.4 3.1 2.8 11.2 400 4.3 3.8 3.4 3.0 2.8 2.6 2.4 2.2 2.0 7.7 600 3.4 3.1 2.7 2.4 2.2 2.0 1.9 1.8 1.7 6.3 800 2.8 2.6 2.3 2.1 1.9 1.8 1.6 1.6 1.5 5.4
Figure 6. Thermal Resistance vs. Heatsink Height, PPGA Packages
Air Flow Rate (LFM)
Heatsink Height (inches)
Datasheet
Pentium® Processor with MMX Technology
Electrical Specifications
This section describes the electrical differences between the Pentium processor with MMX technology and the Pentium processor, and the AC and DC specifications of the Pentium processor with MMX technology.
Electrical Characteristics
When creating a Pentium processor with MMX technology design based on an existing Pentium processor design, there are a number of electrical differences that require attention. The following sections highlight key electrical issues pertaining to the Pentium processor with MMX technology power supplies, connection specifications and buffer models. Note that it is possible to design a single motherboard that supports more than one member of the Pentium processor family. Refer to Pentium® Processor Flexible Motherboard Design Guidelines (order number 243187) for more information and specific implementation examples.
Power Supplies
The main electrical difference between the Pentium processor with MMX technology and the Pentium processor is the operating voltage. The Pentium processor with MMX technology requires two separate voltage inputs, VCC2 and VCC3. The V CC2 pins supply power to the Pentium processor with MMX technology core, while the VCC3 pins supply power to the processor I / O pins. The Pentium processor, on the other hand, requires a single voltage supply for all VCC pins. This single supply powers both the core and I / O pins of the Pentium processor. By connecting all the VCC2 pins together and all the V CC3 pins together on separate power islands, Pentium processor designs can easily be converted to support the Pentium processor with MMX technology. In order to maintain compatibility with Pentium processor-based platforms, the Pentium processor with MMX technology supports the standard 3.3-V specification on its VCC3 pins.
Power Supply Sequencing
There is no specific power sequence required for powering up or powering down the separate V CC2 and VCC3 supplies of the Pentium processor with MMX technology. It is recommended that the VCC2 and VCC3 supplies be turned on or off within one second of each other.
Connection Specifications
Connection specifications for the power and ground inputs, 3.3-V inputs and outputs, and the NC / INC and unused inputs are discussed in the following sections.
Datasheet
Pentium® Processor with MMX Technology
Power and Ground
For clean on-chip power distribution, the embedded Pentium processor with MMX technology has 28 VCC3 (I / O power), 25 VCC2 (core power) and 53 VSS (ground) inputs. Power and ground connections must be made to all external V CC and VSS pins of the Pentium processor with MMX technology. On the circuit board, all V CC3 pins must be connected to a 3.3-V VCC plane. All VCC3 pins must be connected to a 2.8-V V CC plane. All VSS pins must be connected to a V SS plane.
VCC2 and VCC3 Measurement Specification
The values of VCC2 and VCC3 should be measured at the bottom side of the processor pins using an oscilloscope with a 3 dB bandwidth of at least 20 MHz (100 MS / s digital sampling rate). There should be a short isolation ground lead attached to a processor pin on the bottom side of the board. The measurement should be taken at the following VCC / VSS pairs: AN13 / AM10, AN21 / AM18, AN29 / AM26, AC37 / Z36, U37 / R36, L37 / H36, A25 / B28, A17 / B20, A7 / B10, G1 / K2, S1 / V2, AC1 / Z2. One-half of these pins are V CC2 while the others are VCC3 the operating ranges for the VCC2 and VCC3 pins are specified at different voltages. See Table 16 for the specification. The display should show continuous sampling of the voltage line, at 20 mV / div, and 500 ns / div with the trigger point set to the center point of the range. Slowly move the trigger to the high and low ends of the specification, and verify that excursions beyond these limits are not observed. There are no allowances for crossing the high and low limits of the voltage specification. For more information on measurement techniques, see Voltage Guidelines for Pentium® Processors with MMX Technology (order number 243186).
Decoupling Recommendations
Liberal decoupling capacitance should be placed near the Pentium processor with MMX technology. The Pentium processor with MMX technology, when driving its large address and data buses at high frequencies, can cause transient power surges, particularly when driving large capacitive loads. Low inductance capacitors and interconnects are recommended for best high-frequency electrical performance. Inductance can be reduced by shortening circuit board traces between the Pentium processor with MMX technology and decoupling capacitors as much as possible. These capacitors should be evenly distributed around each component on the power plane. Capacitor values should be chosen to ensure they eliminate both low and high frequency noise components. For the Pentium processor with MMX technology, the power consumption can transition from a low level of power to a much higher level (or high to low power) very rapidly. A typical example would be entering or exiting the Stop Grant State. Another example would be executing a HALT instruction, causing the Pentium processor with MMX technology to enter the AutoHALT Power Down State, or transitioning from HALT to the Normal State. All of these examples may cause abrupt changes in the power being consumed by the Pentium processor with MMX technology. Note that the AutoHALT Power Down feature is always enabled even when other power management features are not implemented. Bulk storage capacitors with a low Effective Series Resistance (ESR) in the 10- to 100- range are required to maintain a regulated supply voltage during the interval between the time the current load changes and the point that the regulated power supply output can react to the change in load. In order to reduce the ESR, it may be necessary to place several bulk storage capacitors in parallel.
Datasheet
Pentium® Processor with MMX Technology
These capacitors should be placed near the Pentium processor with MMX technology on both the VCC2 and V CC3 plane to ensure that the supply voltage stays within specified limits during changes in the supply current during operation. Detailed decoupling recommendations are provided in Flexible Motherboard Design Guidelines (order number 243187). Note: Reducing available bulk capacitance could degrade long term system reliability.
3.3-V Inputs and Outputs
The inputs and outputs of the Pentium processor with MMX technology comply with the 3.3-V JEDEC standard levels. Both inputs and outputs are also TTL-compatible, although the inputs cannot tolerate voltage swings above the VIN3 (max) specification. System support components which use TTL-compatible inputs will interface to the Pentium processor with MMX technology without extra logic. This is because the Pentium processor drives according to the 5-V TTL specification (but not beyond 3.3 V). For Pentium processor with MMX technology inputs, the voltage must not exceed the 3.3-V V IN3 (max) specification. System support components can consist of 3.3-V devices or open-collector devices. In an open-collector configuration, the external resistor should be biased to VCC3. All pins, including the CLK and PICCLK of the Pentium processor with MMX technology, are 3.3 V-tolerant-only. When an 8259A interrupt controller is used, for example, the system must provide level converters between the 8259A and the Pentium processor with MMX technology.
NC / INC and Unused Inputs
Important: All NC and INC pins must remain unconnected. For reliable operation, always connect unused inputs to an appropriate signal level. Unused active low inputs should be connected to VCC3. Unused active high inputs should be connected to VSS (ground).
Private Bus
When two Pentium processors with MMX technology are operating in dual processor mode, a "private bus" exists to arbitrate for the processor bus and maintain local cache coherency. The private bus consists of two pinout changes:
· Five pins are added: PBREQ#, PBGNT#, PHIT#, PHITM#, D / P#. · Ten output pins become I / O pins: ADS#, D / C#, W / R#, M / IO#, CACHE#, LOCK#, HIT#,
HITM#, HLDA, SCYC, BE4#. The new pins are given AC specifications of valid delays at 0 pF, setup times and hold times. Simulate with these parameters and their respective I / O buffer models to guarantee that proper timings are met. The AC specification gives input setup and hold times for the ten signals that become I / O pins. These setup and hold times must be met only when a dual processor is present in the system.
Datasheet
Pentium® Processor with MMX Technology
Buffer Models
The structure of the buffer models for the Pentium processor with MMX technology and the Pentium processor are identical. Some of the values of the components have changed to reflect the minor manufacturing process and package differences between the processors. The system should see insignificant differences between the AC behavior of the Pentium processor with MMX technology and the Pentium processor. Simulation of AC timings using the Pentium processor with MMX technology buffer models is recommended to ensure robust system designs. Pay specific attention to the signal quality restrictions imposed by 3.3-V buffers.
Absolute Maximum Ratings
Table 15 provides stress ratings only. Functional operation at the Absolute Maximum Ratings is not implied or guaranteed. Functional operating conditions are given in the AC and DC specification tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the Pentium processor with MMX technology contains protective circuitry to resist damage from electrostatic discharge, always take precautions to avoid high static voltages or electric fields.
Table 15. Absolute Maximum Ratings
Symbol Parameter Storage Temperature Case Temperature Under Bias VCC3 VCC2 VIN3 VCC3 Supply Voltage with respect to VSS VCC2 Supply Voltage with respect to VSS 3-V Only Buffer DC Input Voltage Min -65 -65 -0.5 -0.5 -0.5 Max 150 110 4.6 3.7 V CC3 +0.5 (not to exceed VCC3 max) Unit °C °C V V V
Warning:
Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the DC specifications is not recommended or guaranteed and extended exposure beyond the DC specifications may affect device reliability.
Datasheet
Pentium® Processor with MMX Technology
DC Specifications
Tables 16 through 19 list the DC specifications for the Pentium processor with MMX technology.
Table 16. VCC and TCASE Specifications
See "VCC2 and VCC3 Measurement Specification" on page 34.
Table 17. 3.3 V DC Specifications
Symbol VIL3 VIH3 VOL3 VOH3 Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 Min -0.3 2.0 Max 0.8 VCC3 +0.3 0.4 Unit V V V V Notes TTL Level TTL Level (1) TTL Level (2, 3) TTL Level(4)
NOTES: 1. Parameter measured at nominal VCC3 which is 3.3 V. 2. Parameter measured at -4 mA. 3. In dual processing systems, up to a 10 mA load from the second processor may be observed on the PCHK# signal. Based on silicon characterization data, VOL3 of PCHK# will remain less than 400 mV even with a 10 mA load. PCHK# VOL3 will increase to approximately 500 mV with a 14 mA load (worst case for a DP system with a 4 mA system load). 4. Parameter measured at 3 mA.
Table 18. ICC Specifications
This value should be used for power supply design. It was determined using a worst case instruction mix and maximum VCC . Power supply transient response and decoupling capacitors must be sufficient to handle the instantaneous current changes occurring during transitions from Stop Clock to full Active modes.
Datasheet
Pentium® Processor with MMX Technology
Table 19. Input and Output Characteristics
NOTES: 1. This parameter is for inputs / outputs without an internal pull-up or pull-down. 2. This parameter is for inputs with an internal pull-down. 3. This parameter is for inputs with an internal pull-up. 4. This specification applies to the HITM# pin when it is driven as an input (e.g., in JTAG mode).
AC Specifications
The AC specifications consist of output delays, input setup requirements and input hold requirements. All AC specifications (with the exception of those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input. All timings are referenced to 1.5 volts for both "0" and "1" logic levels unless otherwise specified. Within the sampling window, a synchronous input must be stable for correct Pentium processor with MMX technology operation. Each valid delay is specified for a 0 pF load. The system designer should use I / O buffer modeling to account for signal flight time delays. Each Pentium processor with MMX technology specified to operate within a single bus-to-core ratio and a specific minimum to maximum bus frequency range (corresponding to a minimum to maximum core frequency range). Operation in other bus-to-core ratios or outside the specified operating frequency range is not supported. For example, the 166 MHz Pentium processor with MMX technology does not operate beyond the 66 MHz bus frequency and only supports the 2 / 5 bus-to-core ratio it does not support the 1 / 3, 1 / 2, or 2 / 3 bus-to-core ratios. Table 5 summarizes these specifications.
Datasheet
Pentium® Processor with MMX Technology
Table 20. AC Specifications (Sheet 1 of 4)
t8a t8b t9a t9b t9c t10a t10b t11a t11b t12 t13 t14 t15 t16a t16b t17
NOTE: See Table 21 for notes.
Datasheet
Pentium® Processor with MMX Technology
Table 20. AC Specifications (Sheet 2 of 4)
NOTE: See Table 21 for notes.
Datasheet
Pentium® Processor with MMX Technology
Table 20. AC Specifications (Sheet 3 of 4)
NOTE: See Table 21 for notes.
Datasheet
Pentium® Processor with MMX Technology
Table 20. AC Specifications (Sheet 4 of 4)
NOTE: See Table 21 for notes.
Datasheet
Pentium® Processor with MMX Technology
Table 21. Notes for Table 20
Datasheet
Pentium® Processor with MMX Technology
Figure 7. Clock Waveform
P6CB761a
Figure 8. Valid Delay Timings
1.5V Tx max. Signal 1.5V VALID Tx min.
Figure 9. Float Delay Timings
Datasheet
Pentium® Processor with MMX Technology
Figure 10. Setup and Hold Timings
Figure 11. Reset and Configuration Timings
Datasheet
Pentium® Processor with MMX Technology
Figure 12. Test Timings
Figure 13. Test Reset Timings
Datasheet
Pentium® Processor with MMX Technology
Figure 14. 50 Percent VCC Measurement of Flight Time
Datasheet