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Pentium® Processor with On-Die Cache Low-Power Module
Processor core frequency Kbytes on-die level cache 66-MHz processor system speed Processor core voltage regulation supports input voltages from Above percent peak efficiency Integrated Active Thermal Feedback (ATF) system ACPI Specification Rev. compliant Internal digital signaling (SMBus) across module interface Programmable trip point interrupt poll mode temperature reading
Supports single 66-MHz, device Intel® 82443BX Host Bridge/Controller DRAM controller supports SDRAM Supports CLKRUN# protocol SDRAM clock support self-refresh SDRAM during Suspend mode only control, compliant Thermal transfer plate processor 82443BX Host Bridge/Controller heat dissipation
Order Number: 273257-002 February 2000
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Pentium® Processor with On-Die Cache Low-Power Module
Contents
Introduction Architecture Overview Connector Interface.
Signal Definitions. 3.1.1 Signal List.9 3.1.2 Memory (109 Signals) 3.1.3 Signals).11 3.1.4 Signals) 3.1.5 Processor/PIIX4E Sideband Signals).13 3.1.6 Power Management Signals) 3.1.7 Clock Signals) 3.1.8 Voltages Signals) 3.1.9 ITP/JTAG Signals) 3.1.10 Miscellaneous Signals) Connector Assignments Assignments Pentium® Processor With On-Die Cache Low-Power Module.21 Cache 82443BX Host Bridge/Controller 4.3.1 Memory Organization 4.3.2 Reset Strap Options 4.3.3 Interface 4.3.4 Interface.23 Power Management 4.4.1 Clock Control Architecture.23 4.4.2 Normal State 4.4.3 Auto Halt State 4.4.4 Stop Grant State.25 4.4.5 Quick Start State 4.4.6 HALT/Grant Snoop State 4.4.7 Sleep State.26 4.4.8 Deep Sleep State Typical POS/STR Power Electrical Requirements 4.6.1 Requirements.28 4.6.2 Requirements 4.6.2.1 Clock Signal Quality Specifications Measurement Guidelines Voltage Regulator.31 4.7.1 Voltage Regulator Efficiency 4.7.2 Control Voltage Regulator 4.7.2.1 Voltage Signal Definition Sequencing 4.7.3 Power Planes: Bulk Capacitance Requirements
Functional Description.21
Pentium® Processor with On-Die Cache Low-Power Module
4.7.3.1 V_DC Decoupling Surge Current Guidelines. 4.7.4.1 Slew-rate Control: Circuit Description 4.7.4.2 Undervoltage Lockout: Circuit Description (V_uv_lockout) 4.7.4.3 Overvoltage Lockout: Circuit Description (V_ov_lockout) 4.7.4.4 Overcurrent Protection: Circuit Description Active Thermal Feedback Thermal Sensor Configuration Register. 4.7.4 Module Dimensions. 5.1.1 Location 400-pin Connector 5.1.2 Printed Circuit Board Thickness 5.1.3 Height Restrictions Thermal Transfer Plate Module Physical Support 5.3.1 Module Mounting Requirements 5.3.2 Module Weight Thermal Design Power. Thermal Sensor Setpoint
Mechanical Specification
Thermal Specification
Labeling Information. Environmental Standards
Figures
Block Diagram Low-Power Module 400-Pin Connector Footprint Numbers Clock Control States BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins. Power-on Sequence Timing. V_DC Decoupling Circuit Example Instantaneous In-Rush Current Model Instantaneous In-Rush Current SPICE Simulation Overcurrent Protection Circuit. Spice Simulation Using In-rush Protection (Example ONLY)) Board Dimensions with 400-Pin Connector Orientation. Board Dimensions with 400-Pin Connector- Orientation Printed Circuit Board Thickness. Keep-Out Zone. Thermal Transfer Plate (A). Thermal Transfer Plate (B). Standoff Holes, Board Edge Clearance, Containment Ring Product Tracking Information
Pentium® Processor with On-Die Cache Low-Power Module
Tables
Connector Signal Summary Memory Signal Descriptions.10 Signal Descriptions Signal Descriptions.12 Processor/PIIX4E Sideband Signal Descriptions Power Management Signal Descriptions Clock Signal Descriptions.15 Voltage Descriptions ITP/JTAG Pins.16 Miscellaneous Pins.17 Connector Assignments Rows Through E.17 Connector Assignments Rows Through Connector Specifications.21 Configuration Straps 82443BX Host Bridge/Controller Clock State Characteristics POS/STR Power Power Supply Design Specifications.28 Specifications Processor Core Pins BCLK Signal Quality Specifications Processor Core.30 Typical Voltage Regulator Efficiency.31 Voltage Signal Definitions Sequences VR_ON In-rush Current.33 Capacitance Requirement Power Plane Thermal Sensor SMBus Address Table Thermal Sensor Configuration Register Thermal Design Power Specification Environmental Standards
Pentium® Processor with On-Die Cache Low-Power Module
Revision History
Revision Date February 2000 June 1999 Description Removed references Intel® SpeedStep(Geyserville) Technology. Added section decoupling capacitance (page 35). First release this document.
Pentium® Processor with On-Die Cache Low-Power Module
Introduction
This document provides technical information integrating Intel® Pentium® Processor with On-Die Cache Low-Power Module into latest applied computing systems. Building around this design gives system manufacturer these advantages:
Avoids complexities associated with designing high-speed processor core logic boards. Provides upgrade path from previous Intel modules using standard interface.
Architecture Overview
highly integrated assembly, Low-Power Module contains Pentium Processor with OnDie Cache Power core immediate system-level support. Low-Power Module offered with core speed MHz. processor speeds have 66-MHz processor system (PSB) speed. PIIX4E PCI/ISA Xcelerator bridge large-scale integrated devices Intel® 440BX AGPset. design's system electronics must include PIIX4E device connect Low-Power Module. PIIX4E provides extensive power management capabilities supports Intel® 82443BX Host Bridge/Controller, second integrated device. features 82443BX Host Bridge/Controller include DRAM controller, which supports with burst read 7-2-2-2 nanoseconds) SDRAM with burst read 8-1-1-1 MHz, CL=2). 82443BX Host Bridge/Controller also provides CLKRUN# signal request PIIX4E regulate clock bus. 82443BX clock enables Self Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management. E_SMRAM mode supports write-back cacheable SMRAM Mbyte. thermal transfer plate (TTP) 82443BX Host Bridge/Controller processor provides heat dissipation thermal attach point system manufacturer's thermal solution. on-board voltage regulator converts system voltage processor's core voltage. Isolating processor voltage requirements allows system manufacturer incorporate different processor variants into single system. Supporting input voltages from processor core voltage regulation enables above percent peak efficiency decouples processor voltage requirements from system. Low-Power Module also incorporates Active Thermal Feedback (ATF) sensing, compliant ACPI Specification 1.0. system management (SMBus) supports internal external temperature sensing with programmable trip points. Figure illustrates block diagram module.
Pentium® Processor with On-Die Cache Low-Power Module
Figure Block Diagram Low-Power Module
Processor Core Voltage
Pentium® Processor Power Core
Sense
V_CPUPU
V_DC V-21
V_CLK
443BX
Memory
GCLKO GCLKI
400-Pin Connector
Connector Interface
This section provides information signal groups corresponding information. signals defined compatibility with future modules.
Signal Definitions
Table provides list signals category corresponding number signals each category. proper signal termination, Pentium® Processor Power Module Design Guide (order number 273212).
PCLK1
SMBus
SMBus
DCLKRD DCLKWR DCLKO
PIIX4E Sidebands
Volt. Reg.
HCLK0
R_GTL
Pentium® Processor with On-Die Cache Low-Power Module
Table
Connector Signal Summary
Signal Group Memory Processor/PIIX4E Sideband Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: VCCAGP Voltage: V_CPUPU Voltage: V_CLK ITP/JTAG Module Ground Reserved Total Number Pins
3.1.1
Signal List
following notations used denote signal type: Input Output Open-drain output requiring pullup resistor Open-drain input requiring pullup resistor Input/Open-drain output requiring pullup resistor Bidirectional input/output
signal description also includes type buffer used particular signal: GTL+ CMOS Open-drain GTL+ interface signal interface signals interface signals CMOS buffers voltage compatible signals with 3.3-V outputs with 5.0-V tolerant inputs.
Pentium® Processor with On-Die Cache Low-Power Module
3.1.2
Memory (109 Signals)
Table lists memory interface signals.
Table
Memory Signal Descriptions
Name Type CMOS Voltage Description Memory Data: These signals carry Memory data during access DRAM. These pins implemented design tested module. Address Strobe (EDO): These pins select DRAM row. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low. Column Address Strobe (EDO): These pins select DRAM column. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle. Memory Address (EDO/SDRAM): This column address DRAM. 82443BX Host Bridge/Controller identical sets address lines (MAA MAB#). module supports only address lines. additional addressing features, please refer Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet. Memory Write Enable (EDO/SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. This signal also allows access pre-charge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock. This signal also allows Column access. SDRAM Clock Enable (SDRAM): SDRAM clock enable pin. When these signals deasserted, SDRAM enters power-down mode. Each individually controlled clock enable. Memory Data: These signals connected DRAM data bus. They terminated module.
MECC[7:0]
RASA[5:0]# CSA[5:0]#
CMOS
CASA[7:0]# DQMA[7:0]
CMOS
MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWEA# CMOS CMOS CMOS CMOS CMOS CMOS
SRASA#
SCASA#
CKE[5:0]
MD[63:0]
Pentium® Processor with On-Die Cache Low-Power Module
3.1.3
Signals)
Table lists interface signals.
Table
Signal Descriptions (Sheet
Name Type Voltage Description Address/Data: standard address data lines. This functions same AD[31:0] bus. address driven with FRAME# assertion data driven received following clocks. Command/Byte Enable: This carries command information during cycles when PIPE# used. During write, this contains byte enable information. command driven with FRAME# assertion byte enables corresponding supplied requested data driven following clocks. Frame: used during transactions. Remains deasserted internal pullup resistor. Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: Same function DEVSEL#. used during transactions. 82443BX Host Bridge/Controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Indicates compliant target ready provide write data current transaction. Asserted when initiator ready data transfer. Target Ready: Indicates compliant master ready provide write data current transaction. Asserted when target ready data transfer. Stop: Same function STOP#. used during transactions. Asserted target request master stop current transaction. Request: master requests AGP. Grant: Same function PCI. Additional information provided ST[2:0] bus. Grant: Permission given master PCI. Parity: single parity provided over GAD[31:0] GC/BE[3:0]. This signal used during transactions. Pipelined Request: Asserted current master indicate full width address that queued target. master queues request each rising clock edge while PIPE# asserted. Sideband Address: This provides additional conduit pass address commands 82443BX Host Bridge/Controller from master. Read Buffer Full: Indicates master ready accept previously requested, low-priority read data.
GAD[31:0]
GC/BE[3:0]#
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
GPAR
PIPE#
SBA[7:0]
RBF#
Pentium® Processor with On-Die Cache Low-Power Module
Table
Signal Descriptions (Sheet
Name ST[2:0] Type Voltage Description Status Bus: Provides information from arbiter Master what These bits only have meaning when GGNT asserted. Strobes: Provide timing double-clocked data bus. agent providing data drives these signals. These identical copies each other. Sideband Strobe: Provides timing sideband bus. SBA[7:0] (AGP master) drives sideband strobe.
ADSTB[B:A]
SBSTB
3.1.4
Signals)
Table lists interface signals.
Table
Signal Descriptions (Sheet
Name AD[31:0] Type Voltage Description Address/Data: standard address data lines. address driven with FRAME# assertion data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion byte enables corresponding supplied requested data driven following clocks. Frame: Assertion indicates address phase transfer. Negation indicates that cycle initiator desires more data transfer. Device Select: 82443BX Host Bridge/Controller drives this signal when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Asserted when initiator ready data transfer. Target Ready: Asserted when target ready data transfer. Stop: Asserted target request master stop current transaction. Lock: Indicates exclusive operation require multiple transactions complete. When LOCK# asserted, nonexclusive transactions proceed. 82443BX supports lock processor initiated cycles only. initiated locked cycles supported. Request: master requests PCI. Grant: Permission given master PCI.
C/BE[3:0]#
FRAME#
DEVSEL#
IRDY# TRDY# STOP#
PLOCK#
REQ[4:0]# GNT[4:0]#
Pentium® Processor with On-Die Cache Low-Power Module
Table
Signal Descriptions (Sheet
Name Type Voltage Description Hold: This signal comes from expansion bridge; bridge request PCI. 82443BX Host Bridge/Controller will drain DRAM write buffers, drain processor-to-PCI posting buffers, acquire host before granting request PHLDA#. This ensures that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: This signal driven 82443BX Host Bridge/Controller grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]#. System Error: 82443BX asserts this signal indicate error condition. Refer Intel® 440BX AGPset: Host Bridge/Controller datasheet further information. Clock Run: open-drain output input. 82443BX Host Bridge/Controller requests central resource (PIIX4E) start maintain clock asserting CLKRUN#. 82443BX Host Bridge/Controller three-states CLKRUN# upon deassertion Reset (since running upon deassertion Reset). Reset: When asserted, this signal asynchronously resets 82443BX Host Bridge. signals also three-state, compliant with Specifications.
PHOLD#
PHLDA#
SERR#
CLKRUN#
PCI_RST#
CMOS
3.1.5
Processor/PIIX4E Sideband Signals)
Table lists signals processor PIIX4E sideband signals. voltage level these signals determined V_CPUPU.
Table
Processor/PIIX4E Sideband Signal Descriptions (Sheet
Name Type CMOS CMOS CMOS CMOS Voltage Description Numeric Coprocessor Error: This functions FERR# signal supporting coprocessor errors. This signal tied coprocessor error signal processor driven processor PIIX4E. Ignore Error: This open-drain signal connected Ignore Error processor driven PIIX4E. Initialization: INIT# asserted PIIX4E processor system initialization. This signal open-drain. Processor Interrupt: INTR driven PIIX4E signal processor that interrupt request pending needs serviced. This signal open-drain. Non-maskable Interrupt: used force non-maskable interrupt processor. PIIX4E bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal open-drain.
FERR#
V_CPUPU
IGNNE# INIT#
V_CPUPU V_CPUPU
INTR
V_CPUPU
CMOS
V_CPUPU
Pentium® Processor with On-Die Cache Low-Power Module
Table
Processor/PIIX4E Sideband Signal Descriptions (Sheet
Name A20M# Type CMOS Voltage V_CPUPU Description Address Mask: When enabled, this open-drain signal causes processor emulate address wraparound which occurs Intel 8086 processor. System Management Interrupt: SMI# active synchronous output from PIIX4E that asserted response many enabled hardware software events. SMI# opendrain signal asynchronous input processor. However, this chip SMI# synchronous PCLK. Stop Clock: STPCLK# active synchronous open-drain output from PIIX4E that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted, responds entering power state (Quick Start). processor will only exit this mode when this signal deasserted.
SMI#
CMOS
V_CPUPU
STPCLK#
CMOS
V_CPUPU
3.1.6
Power Management Signals)
Table lists power management signals. SM_CLK SM_DATA signals refer two-wire serial SMBus interface. Although this interface currently used solely digital thermal sensor, SMBus contains reserved serial addresses future use. "Thermal Sensor Configuration Register" page more details.
Table
Power Management Signal Descriptions
Name SUS_STAT1# Type CMOS Voltage V_3ALWAY Description Suspend Status: This signal connects SUS_STAT1# output PIIX4E. provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This 3.3V tolerant) signal controls operation voltage regulator. VR_ON should generated function PIIX4E SUSB# signal which used controlling "Suspend State voltage planes. This signal should driven digital signal with rise/fall time less than equal Refer "Voltage Signal Definition Sequencing" page (VIL (max)=0.4V, (min)=3.0V). VR_PWRGD: This signal driven high module indicate that voltage regulator stable. signal pulled using resistor when inactive. used some combination generate system PWRGOOD signal. Power This signal must active after power rail stable, prior deassertion PCIRST#. Serial Clock: This clock signal used SMBus interface digital thermal sensor. Serial Data: Open-drain data signal SMBus interface digital thermal sensor. Interrupt: This signal open-drain output signal digital thermal sensor.
VR_ON
CMOS
VR_PWRGD
BXPWROK SM_CLK SM_DATA ATF_INT#
CMOS CMOS CMOS CMOS
V_3ALWAYS: supply. generated whenever V_DC available supplied PIIX4E resume well.
Pentium® Processor with On-Die Cache Low-Power Module
3.1.7
Clock Signals)
Table lists clock signals.
Table
Clock Signal Descriptions
Name Type Voltage Description Clock PCLK input module system's clocks. This clock used 82443BX Host Bridge/Controller logic clock domain. This clock stopped when PIIX4E PCI_STP# signal asserted and/or during suspend states. Host Clock These clocks inputs module from CK97-M clock source. processor 82443BX Host Bridge/Controller HCLK[0]. This clock stopped when PIIX4E CPU_STP# signal asserted and/or during suspend states. SDRAM Clock Out: 66-MHz SDRAM clock reference generated internally 82443BX Host Bridge/Controller onboard PLL. feeds external buffer that produces multiple copies SODIMMs. SDRAM Read Clock: Feedback reference from SDRAM clock buffer. 82443BX Host Bridge/Controller uses this clock when reading data from SDRAM array. This signal implemented module. SDRAM Write Clock: Feedback reference from SDRAM clock buffer. 82443BX Host Bridge/Controller uses this clock when writing data SDRAM array. Clock GCLKIN input feedback reference from GCLKO signal. Clock Out: This signal generated 82443BX Host Bridge/Controller onboard from HCLK0 host clock reference. frequency GCLKO MHz. GCLKO output used feed both reference input pins 82443BX Host Bridge/Controller device. board layout must maintain complete symmetry loading trace geometry minimize clock skew. Frequency Select: This output signal provides status host clock frequency system electronics. This signal static pulled either high V_CLK voltage supply through 10-K resistor. This module designed 66-MHz strapping option shown below. FQS=0 indicates FQS=1 indicates (for future modules)
PCLK
HCLK[1:0]
CMOS
V_CLK
DCLKO
CMOS
DCLKRD
CMOS CMOS CMOS
V_CLK
DCLKWR
V_CLK
GCLKIN
GCLKO
CMOS
CMOS
V_CLK
Pentium® Processor with On-Die Cache Low-Power Module
3.1.8
Voltages Signals)
Table lists voltage signal definitions.
Table
Voltage Descriptions
Name V_DC V_3S Type Number Pins Input: V-21 SUSB# controlled This rail used module. power managed supply. output voltage regulator system electronics. This rail during STR, STD, SOff. SUSC# controlled Power managed supply. output voltage regulator system electronics. This rail during SOff. SUSC# controlled Power managed supply. output voltage regulator system electronics. This rail during SOff. Voltage: This voltage rail implemented module. Intel recommends that this voltage rail connected system electronics. Processor Ring: Driven module power processor interface signals such PIIX4E open-drain pullups processor/PIIX4E sideband signals. Processor Clock Rail: Driven module power CK100-M VDDCPU rail. Description
VCCAGP
V_CPUPU V_CLK
3.1.9
ITP/JTAG Signals)
Table lists ITP/JTAG signals, which system manufacturer implement JTAG chain port desired.
Table
ITP/JTAG Pins
Name TCLK TRST# FS_RESET# FS_PREQ# FS_PRDY# Type Voltage V_CPUPU V_CPUPU V_CPUPU V_CPUPU V_CPUPU GTL+ V_CORE V_CPUPU GTL+ Description JTAG Test Data Out: Serial output port. instructions data shifted processor from this port. JTAG Test Data Serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: Controls controller change sequence. JTAG Test Clock: Testability clock clocking JTAG boundary scan sequence. JTAG Test Reset: Asynchronously resets controller processor. Processor Reset: Processor reset status ITP. GTL+ Termination Voltage: Used POWERON debug port determine when target system POWERON pulled using resistor VTT. Debug Mode Request: Driven makes request enter debug mode. Debug Mode Ready: Driven processor informs that processor debug mode.
NOTE: DBREST# (reset target system) debug port "logically ANDed" with VR_PWRGD PIIX4E's PWROK
Pentium® Processor with On-Die Cache Low-Power Module
3.1.10
Miscellaneous Signals)
Table lists miscellaneous signal pins.
Table Miscellaneous Pins
Name Module ID[3:0] Ground Reserved Type CMOS RSVD Number Description Module Revision These pins track revision level module. 100-K pullup resistor V_3S must placed system electronics these signals. "Labeling Information" page more information. Ground. Unallocated Reserved pins should connected.
Connector Assignments
Table Table list signals each connector system electronics. Refer "Pin Assignments" page assignments pads connector.
Table Connector Assignments Rows Through (Sheet
Number SBA5 GAD25 GAD30 RBF# BXPWROK MD36 MD41 MD43 MD14 MECC4 SCASA# CSA1# SRASA# Reserved Reserved Reserved ADSTBB GAD24 GAD29 VCCAGP GAD1 Reserved MD33 MD38 MD42 MD11 MD45 MECC0 MWEA# MID1 DQMA4 CSA2# CSA5# Reserved MAB4# Reserved SBA6 GAD26 GAD4 GAD3 GAD2 MD37 MD40 MD44 MD15 MECC5 DQMA0 MID0 CSA4# MAB0# MAB2# MAB5# GAD31 SBA4 GAD27 GAD6 GAD5 ADSTBA CLKRUN# MD32 MD35 MD39 MD10 MD13 MD47 Reserved DQMA1 DQMA5 CSA3# MAB1# Reserved Reserved Reserved SBA7 SBA0 GAD8 GC/BE0# GAD7 GAD0 MD34 MD12 MD46 Reserved CSA0# Reserved MAB3# MAB6# MAB7#
Pentium® Processor with On-Die Cache Low-Power Module
Table Connector Assignments Rows Through (Sheet
Number MAB8# Reserved MAB13 CKE1 CKE5 Reserved FS_RESET# FS_PRDY# Reserved Reserved Reserved Reserved V_CPUPU V_CLK Reserved V_DC V_DC Reserved MAB11# MID2 CKE2 Reserved SMCLK SMDAT Reserved V_DC V_DC Reserved MAB12# CKE3 MID3 DQMA2 Reserved MD26 MD58 Reserved V_3S V_3S V_3S Reserved V_DC V_DC MAB9# Reserved CKE0 CKE4 Reserved DCLKWR FS_PREQ# MD57 TCLK TRST# V_3S V_3S V_3S Reserved V_DC V_DC MAB10 DCLKO DCLKRD Reserved DQMA3 MD25 MD60 FERR# IGNNE# ATF_INT# V_3S V_3S V_3S Reserved V_DC V_DC
Table Connector Assignments Rows Through (Sheet
Number GREQ# GGNT# GAD13 GAD12 GAD10 GAD11 GAD9 VCCAGP MECC1 SERR# AD16 AD19 GSTOP# GPAR GAD15 GC/BE1# GAD14 VCCAGP C/BE0# AD10 AD13 TRDY# PIPE# SBA1 SBA2 GAD16 GAD18 GFRAME# GTRDY# GDEVSEL# AD15 STOP# AD17 SBA3 SBSTB GAD20 GAD17 GC/BE2# GIRDY# VCCAGP AD12 C/BE1# DEVSEL# GCLKI GCLKO GAD23 GC/BE3# GAD22 GAD21 GAD19 GAD28 AD11 AD14 PLOCK# AD18
Pentium® Processor with On-Die Cache Low-Power Module
Table Connector Assignments Rows Through (Sheet
Number AD23 AD27 PCI_RST# Reserved IRDY# GNT1# DQMA6 MECC2 DQMA7 MECC6 MECC3 MD27 SMI# A20M# Reserved V_DC V_DC AD30 AD22 PHOLD# FRAME# GNT2# GNT4# PHLDA# MECC7 MD48 MD16 MD17 MD49 MD28 MD29 INTR SUS_STAT1# STPCLK# Reserved V_DC V_DC AD24 C/BE3# AD20 AD31 REQ2# GNT0# MD50 MD18 MD19 MD21 MD20 MD61 VR_ON VR_PWRGD INIT# Reserved V_DC V_DC C/BE2# AD26 AD28 AD29 REQ1# REQ3# REQ4# MD51 MD52 MD53 MD22 MD62 MD30 Reserved V_DC V_DC AD21 PCLK AD25 REQ0# GNT3# MD59 MD54 MD24 MD23 MD55 MD56 MD63 MD31 HCLK0 HCLK1 Reserved V_DC V_DC
Pentium® Processor with On-Die Cache Low-Power Module
Assignments
module connector pins, 1.27-millimeter pitch, BGA-style surface mount. Refer "Height Restrictions" page connector size information. Figure shows assignments module connector.
Figure 400-Pin Connector Footprint Numbers
400-Pin Connector Assignments
(Viewed from Secondary Side)
Pentium® Processor with On-Die Cache Low-Power Module
Table summarizes some specifications connector. Table Connector Specifications
Parameter Contact Material Housing Current Voltage Electrical Insulation Resistance Termination Resistance Capacitance Mating Cycles Mechanical Connector Mating Force Contact Unmating Force Thermo Plastic Molded Compound: minimum maximum maximum contact cycles maximum contact minimum contact Condition Copper Alloy Specification
Functional Description
Pentium® Processor With On-Die Cache Low-Power Module
module offered core speed MHz, with 66-MHz processor system speed.
Cache
on-die cache Kbytes, four-way associative, runs speed processor core.
82443BX Host Bridge/Controller
Intel's 82443BX Host Bridge/Controller highly integrated device that combines controller, DRAM controller, controller into component. 82443BX Host Bridge/Controller multiple power management features designed specifically lowpower systems such
CLKRUN#, feature that enables controlling clock off. 82443BX Host Bridge/Controller suspend modes, which include Suspend-to-RAM
(STR), Suspend-to-Disk (STD), Power-On-Suspend (POS).
System Management (SMRAM) power management modes, which include Compatible
SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets. E_SMRAM feature that supports write-back cacheable SMRAM space Mbyte. minimize power
Pentium® Processor with On-Die Cache Low-Power Module
consumption while system idle, internal 82443BX Host Bridge/Controller clock turned (gated off) when there processor activity. This accomplished setting G_CLK enable power management register 82443BX through system BIOS.
4.3.1
Memory Organization
memory interface 82443BX Host Bridge/Controller available connector. This allows following:
memory control signals, sufficient support three SO-DIMM sockets
banks SDRAM MHz.
signal each bank.
Memory features supported 82443BX Host Bridge/Controller standard mode are:
Support eight banks memory. Second memory address lines (MAA[13:0]).
DRAM technologies supported 82443BX Host Bridge/Controller include SDRAM. These memory types mixed system, that DRAM rows (RAS[5:0]#) must same technology. 82443BX Host Bridge/Controller targets nanoseconds DRAMs 66-MHz SDRAMs. module's clocking architecture supports SDRAM. Tight timing requirements 66-MHz SDRAM clocks allow host SDRAM clocks generated from same clocking architecture. complete details about using SDRAM memory, trace length guidelines, Pentium® Processor Power Module SDRAM DIMM Routing Guidelines (order number 273230). Refer Intel® 440BX AGPset: 82443BX Host Bridge/Controller datasheet details memory device support, organization, size, addressing.
4.3.2
Reset Strap Options
Several strap options memory address define behavior module after reset. Other straps override default settings. Table shows straps their implementation.
Table Configuration Straps 82443BX Host Bridge/Controller
Signal MAB[12]# MAB[11]# MAB[10] MAB[9]# MAB[7]# MAB[6]# Function Host Frequency Select Order Queue Depth Quick Start Select disable Config Host Buffer Mode Select Module Default Setting strap-66 default. strap-maximum queue depth set, i.e., Strapped high module Quick Start mode. strap-AGP enabled. strap-standard mode. Strapped high module buffers. Optional Override System Electronics None None None Pull this signal disable interface. None None
Pentium® Processor with On-Die Cache Low-Power Module
4.3.3
Interface
interface 82443BX Host Bridge/Controller available connector. 82443BX Host Bridge/Controller supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. 82443BX Host Bridge/Controller responsible arbitrating bus. With module connector, 82443BX Host Bridge/Controller support five masters. There five Request/Grant pairs, REQ[4:0]# GNT[4:0]#, available connector manufacturer's system electronics. Note: interface module connector only. devices supported such devices that drive outputs nominal level. 82443BX Host Bridge/Controller compliant with Rev. specification, which improves worst case access latency from earlier specifications. 82443BX Host Bridge/Controller supports only Mechanism accessing configuration space, detailed specification. This implies that signals AD[31:11] available IDSEL signals. However, since 82443BX Host Bridge/Controller always device AD11 will never asserted during configuration cycles IDSEL. 82443BX reserves AD12 AGPbus. Thus, AD13 first available address line usable IDSEL. Intel recommends that AD18 used PIIX4E.
4.3.4
Interface
82443BX Host Bridge/Controller compliant with Interface Specification 1.0, which supports asynchronous interface coupling 82443BX core frequency. interface achieve real data throughput excess Mbytes/s using graphics device. Actual bandwidth vary depending specific hardware software implementations.
4.4.1
Power Management
Clock Control Architecture
clock control architecture optimal low-power designs. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep, Deep Sleep states. Auto Halt state provides low-power clock state that controlled through software execution instruction. Quick Start state provides very low-power, low-exit latency clock state that used hardware controlled "idle" states. Deep Sleep State provides extremely power state that used "Power-on Suspend" states, which alternative shutting processor's power. exit latency Deep Sleep State been reduced Stop Grant Sleep states available module since these states intended desktop server systems. Stop Grant state Quick Start clock state mutually exclusive. example, strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal enables Quick Start state ground Reset. Otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Stop Grant state useful platforms supported module. Quick Start state available module provides significantly lower power level.
Pentium® Processor with On-Die Cache Low-Power Module
Figure provides illustration clock control architecture. State transitions shown Figure neither recommended supported Figure Clock Control States
STPCLK#
Normal State
HS=false
(!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !STPCLK#
Quick Start
BCLK stopped BCLK
STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSE
Auto Halt
HS=true
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced Snoop occurs
Stop Grant
Snoop serviced
HALT/Grant Snoop
SLP# !SLP# RESET# BCLK stopped
BCLK !QSE
Sleep
Halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET# Intel Modules support shaded clock states
Pentium® Processor with On-Die Cache Low-Power Module
4.4.2
Normal State
This normal operating mode where processor's core clock running processor actively executing instructions.
4.4.3
Auto Halt State
This power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, SMI#). Asserting STPCLK# signal while Auto Halt state will cause processor transition Stop Grant state Quick Start state, where Stop Grant Acknowledge cycle will issued. Deasserting STPCLK# will cause processor return Auto Halt state without issuing Halt cycle. SMI# (System Management Interrupt) recognized Auto Halt state. return from handler either Normal state Auto Halt state. Intel® Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. Halt cycle issued when returning Auto Halt state from System Management Mode (SMM). FLUSH# signal serviced Auto Halt state. After flushing on-chip, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state.
4.4.4
Stop Grant State
Important: This state available module. processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made deassertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH#, RESET# assertion). processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion will cause processor immediately initialize itself. However, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal. While Stop Grant state, assertions SMI#, INIT#, INTR, LINT[1:0]) will latched processor. These latched events will serviced until processor returns Normal state. Only each event will recognized upon return Normal state.
Pentium® Processor with On-Die Cache Low-Power Module
4.4.5
Quick Start State
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated priority device. Because snooping behavior, Quick Start only used single processor configurations. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters, responding FLUSH# BINIT# assertions. Quick Start state, processor will respond properly input signal other than STPCLK#, RESET#, BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted.
4.4.6
HALT/Grant Snoop State
processor will respond snoop transactions while Auto Halt, Stop Grant, Quick Start state. When snoop transaction presented system bus, processor will enter HALT/Grant Snoop state. processor will remain this state until snoop been serviced quiet. After snoop been serviced, processor will return previous state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state (except those signal transitions that required perform snoop).
4.4.7
Sleep State
Important: This state available module. Sleep state very power state which processor maintains context phase locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state SLP# signal asserted, causing processor enter Sleep state. SLP# signal recognized Normal state Auto Halt state. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state, then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor Sleep state transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state processor enter lowest power state, Deep Sleep state. Removing processor's input clock puts processor Deep Sleep state. PICCLK removed Sleep state.
Pentium® Processor with On-Die Cache Low-Power Module
4.4.8
Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. Stopping BCLK input processor enters Deep Sleep state, while Sleep state Quick Start state. proper operation, BCLK input should stopped state. processor will return Sleep state Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there 30-ms delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior.
Table Clock State Characteristics
Clock State Normal Auto Halt Stop Grant1 Approximately clocks clocks Through snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks HALT/Grant Snoop Sleep1 clocks after snoop activity. Stop Grant state clocks specified Exit Latency Processor Power Varies Snooping System Uses Normal program execution. controlled entry idle mode. controlled entry/exit throttling.
Quick Start
controlled entry/exit throttling.
Supports snooping power states. controlled entry/exit desktop idle mode support. controlled entry/exit powered-on suspend support.
Deep Sleep
NOTES: module does support Sleep Stop Grant clock control states. 100% tested. Specified design/characterization.
Typical POS/STR Power
Table shows typical POS/STR power values.
Table POS/STR Power
State Typical Module Power 0.475 0.018
NOTE: These average values measurement guidelines only.
Pentium® Processor with On-Die Cache Low-Power Module
Electrical Requirements
following section provides information electrical requirements module.
4.6.1
Requirements
Table provides power supply design criteria.
Table Power Supply Design Specifications
Symbol IDC1,2 IDC-Surge IDC-Leakage I5-Surge I5-Leakage I3-Surge I3-Leakage VCPUPU ICPUPU4 VCLK ICLK
Parameter Input Voltage Input Current Maximum Surge Current Typical Leakage Current Power Managed Voltage Supply Power Managed Current Maximum Surge Current Typical Leakage Current Power Managed 3.3V Voltage Supply Power Managed 3.3V Current Maximum Surge Current Typical Leakage Current Processor Ring Voltage Processor Ring Current Processor Clock Rail Voltage Processor Clock Rail Current
12.0
21.0 17.3
Unit
Notes
4.75 5.25 3.135 3.465 2.375 2.375 24.0 35.0 2.625 2.625
0.125 0.125
NOTES: V_DC order determine typical V_DC current. V_DC order determine maximum V_DC current. Leakage current that expected when VR_ON deactivated V_DC still applied. These values system dependent.
Pentium® Processor with On-Die Cache Low-Power Module
4.6.2
Requirements
Table shows BCLK requirements.
Table Specifications Processor Core Pins
Parameter Frequency3 BCLK Period3,4 BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time7 BCLK Fall Time
5,6,7
66.67 15.0
Unit
Figure
Notes1,2 processor core frequencies
±250 0.175 0.175 0.875 0.875
>1.8 <0.7V (0.9 V-1.6 (1.6 V-0.9
NOTES: timings GTL+ signals referenced BCLK rising edge 1.25 processor core pin. GTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor core pins. timings CMOS signals referenced BCLK rising edge 1.25 processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25 processor core pins. internal core clock frequency derived from clock. clock core clock ratio determined during initialization described predetermined module. BCLK period allows +0.5 tolerance clock driver variation. CK97 Clock Synthesizer/Driver Specification further information. Measured rising edge adjacent BCLKs 1.25 jitter present must accounted component BCLK skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK97 Clock Synthesizer/Driver Specification further details. 100% tested. Specified design characterization clock driver requirement.
4.6.2.1
Clock Signal Quality Specifications Measurement Guidelines
Table describes signal quality specifications processor core processor system (PSB) clock (BCLK) signal. Figure describes signal quality waveform clock processor core pins.
Pentium® Processor with On-Die Cache Low-Power Module
Table BCLK Signal Quality Specifications Processor Core
Parameter1,5 BCLK
Unit
BCLK
-0.8
Absolute Voltage Range3 Rising Edge Ringback
Falling Edge Ringback
BCLK rising/falling slew rate
V/ns
NOTES: Unless otherwise noted, specifications this table apply modules. BCLK must rise/fall monotonically between VIL,BCLK VIH, BCLK. This processor clock overshoot undershoot specification 66-MHz operation. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. proper signal termination, refer Pentium® Processor Power Module Design Guide (order number 273212).
Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins
Pentium® Processor with On-Die Cache Low-Power Module
Voltage Regulator
voltage regulator (DC/DC converter) provides appropriate core voltage, ring voltage, sideband signal pullup voltage module. voltage range
4.7.1
Voltage Regulator Efficiency
Table lists voltage regulator efficiencies.
Table Typical Voltage Regulator Efficiency
Icore, V_DC, 12.0 12.0 12.0 12.0 12.0 12.0 12.0 21.0 21.0 21.0 21.0 21.0 21.0 21.0 I_DC, 0.370 0.702 1.044 1.404 1.762 2.144 2.528 0.159 0.295 0.438 0.584 0.736 0.890 1.043 0.091 0.170 0.253 0.340 0.429 0.519 0.617 Efficiency1 82.8% 88.8% 89.8% 89.7% 88.1% 86.4% 85.0% 79.7% 87.0% 87.8% 87.3% 86.1% 84.9% 83.8% 79.3% 86.0% 87.3% 85.3% 84.1% 82.9% 80.7%
NOTES: These efficiencies will change with future voltage regulators that accommodate wider ranges input voltages. With V_DC applied voltage regulator off, typical leakage with maximum Icore indicates core current being drawn during test measurement.
Pentium® Processor with On-Die Cache Low-Power Module
4.7.2
Control Voltage Regulator
VR_ON turns voltage regulator off. VR_ON should controlled function SUSB#, which controls system's power planes. VR_ON should switch high only when following conditions met: V_5(s) V_DC 4.75
Caution:
Turning VR_ON prior meeting these conditions will severely damage module. VR_PWRGD signal indicates that voltage regulator power operating stable voltage level. VR_PWRGD system electronics control power inputs gate PWROK PIIX4E. Table lists voltage signal definitions sequences, Figure shows signal sequencing voltage planes sequencing required normal operation module.
4.7.2.1
Voltage Signal Definition Sequencing
Table Voltage Signal Definitions Sequences
Signal Source Definitions Sequences V_DC required between driven system electronics' power supply. V_DC powers module's DC-to-DC converter processor core voltages. module cannot inserted removed while V_DC powered supplied system electronics 82443BX. supplied system electronics 82443BX's reference voltage module's voltage regulator. VR_ON tolerant) signal that enables module's voltage regulator circuit. When driven active high voltage regulator circuit activated. signal driving VR_ON should digital signal with rise/fall time less than equal (VIL (max)=0.4V, (min)=3.0V). result VR_ON being asserted, V_CORE output DC-DC regulator module driven core voltage processor. also used host GTL+ termination voltage, known VTT. Upon sampling voltage level V_CORE (minus tolerances ripple), VR_PWRGD driven active high. VR_PWRGD sampled active within second assertion VR_ON, then system electronics should deassert VR_ON. After V_CORE stabilized, VR_PWRGD will assert logic high (3.3V). This signal must pulled system electronics. VR_PWRGD should "ANDed" with V_3s generate PIIX4E input signal, PWROK. system electronics should monitor VR_PWRGD verify asserted high prior active high assertion PIIX4E PWROK. V_CPUPU system electronics this voltage power PIIX4E-to-processor interface circuitry. V_CLK system electronics this voltage power HCLK[0:1] drivers processor clock.
V_DC
System Electronics
System Electronics System Electronics
VR_ON
System Electronics
V_CORE (also host GTL+ termination voltage VTT)
Module
VR_PWRGD
Module
V_CPUPU V_CLK
Module Module
Pentium® Processor with On-Die Cache Low-Power Module
following list provides additional specifications clarifications power sequence timing Figure provides illustration.
VR_ON signal only asserted logical high digital signal after V_DC
volts, volts, volts. goes through VIH.
Rise Time Fall Time VR_ON must less than equal microsecond when VR_ON (max) +0.4 volts (min) +3.0 volts. VR_PWRGD will asserted logic high (3.3 volts) after V_CORE stabilized
V_DC reaches volts. This signal should pulled system electronics.
power-on process, Intel recommends raise higher voltage power plane first
(V_DC), followed lower power planes (V_5, V_3), finally assert VR_ON after above voltage levels rails. power-off process should reverse process, i.e., VR_ON gets deasserted, followed lower power planes, finally higher power planes.
VR_ON must monotonically rise through fall through points.
sign slope change between rising falling. values listed Table Table VR_ON In-rush Current
Instantaneous 41.0 Operating
VR_ON must provide instantaneous in-rush current module with following
NOTE: These values based 3.3V VR_ON signal.
VR_ON Valid-Low Time: This specifies long VR_ON needs valid
before VR_ON turned back again. going from valid then back following conditions must prevent damage system module:
VR_ON must millisecond. original voltage level requirements turn-on must before assertion VR_ON
(i.e., V_DC volts, volts, volts).
Pentium® Processor with On-Die Cache Low-Power Module
Figure Power-on Sequence Timing
V_DC V_3S VR_ON VR_PWRGD V_CPUPU/ V_CLK
POWER SEQUENCE TIMING
PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4E/M. V_DC 4.7V, V_5>=4.5V, V_3S>=3.0V. V_CPUPU V_CLK generated Intel Module. This power supplied processor module connector. This should first plane power VR_PWRGD specified associated high/active module regulator within less than equal max. after assertion VR_ON.
4.7.3
Power Planes: Bulk Capacitance Requirements
order provide adequate filtering in-rush current protection system design, bulk capacitance required. small amount bulk capacitance supplied module. However, order achieve proper filtering, additional capacitance should placed system electronics. Table details bulk capacitance requirements system electronics.
Table Capacitance Requirement Power Plane
Power Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK Capacitance Requirements 0.01 0.01
Ripple Current A-3.5
Rating tolerance tolerance tolerance tolerance tolerance tolerance tolerance
0.01 0.01 0.01 8200
8200
NOTES: Placement above capacitance requirements should located near connector. V_CLK filtering should located next system clock synthesizer. Ripple current specification depends V_DC input. V_DC, device required. V_DC higher, sufficient.
Pentium® Processor with On-Die Cache Low-Power Module
4.7.3.1
V_DC Decoupling
V_DC tied together, ensure that decoupling guidelines strictly followed avoid noise from V_DC rail coupling rail. Noise could trigger undervoltage lockout circuits module. example circuit shown Figure adheres decoupling guidelines.
Figure V_DC Decoupling Circuit Example
V5_0
200nH
0.1µF 0.1µF 0.1µF
Inductor
220µF
220µF
220µF
A7703-01
Exact component values system dependant. Intel recommends that specific component values determined through full simulation parasitic modeling.
4.7.4
Surge Current Guidelines
This section provides results worst case, surge current analysis. analysis determines maximum amount surge current that module manage. analysis, module with 0.15 each. module approximately 30.0 series resistance, total series resistance 0.18 powering system with adapter amount surge current module would approximately This information also used develop bulk capacitance requirements. Table more information. Note: Depending system electronics design, different impedances yield different results. thorough analysis should performed understand implications surge current their system. Figure shows electrical model used when analyzing instantaneous in-rush conditions, Figure illustrates results with SPICE simulation.
Pentium® Processor with On-Die Cache Low-Power Module
Figure Instantaneous In-Rush Current Model
Figure Instantaneous In-Rush Current SPICE Simulation
component height requirements millimeters) module, Polymerized Organic Semiconductor capacitors must used input bulk capacitance voltage regulator circuit. Because capacitor's susceptibility high in-rush current, special care must taken. soften in-rush current provide overvoltage overcurrent protection ramp V_DC slowly using circuit similar shown Figure
Pentium® Processor with On-Die Cache Low-Power Module
Figure Overcurrent Protection Circuit
NOTE: Values shown reference only.
4.7.4.1
Slew-rate Control: Circuit Description
Figure voltage generated applying Adaptor Battery. (on) P-Channel MOSFET such Siliconix* SI4435DY. When voltage applied increased over 4.75 UNDER_VOLTAGE_LOCKOUT circuit allows pull gate start turn-on sequence. pulls drain toward ground forcing current flow through will start source current until after t_delay with t_delay defined
t_delay Vpwr Vgs_max
Vgs_max
Vpwr
system manufacturer's Vgs_max specification must never exceeded. However, Vgs_max must high enough keep (on) device possible. After initial t_delay, will begin source current V_DC will start ramp ramp time, t_ramp, defined
t_ramp Vsat Vgs_max t_delay
Pentium® Processor with On-Die Cache Low-Power Module
Maximum current during voltage ramping
Vpwr Ctotal t_ramp
With circuit shown Figure t_delay 5.53 t_tran 14.0 I_max Figure shows SPICE simulation circuit Figure increase reliability tantalum capacitors, slew-rate control circuit described Figure voltage derate capacitor about percent. That maximum input voltage 18.0 35.0-V, capacitor with high ripple current capability. Place five, 22-µF/35-V capacitors baseboard, directly V_DC pins processor module connector. Finally, slew-rate control circuit should applied every input power source system V_DC provide most protection. potential problem still exists power sources "logically OR'ed" together node. example, system will immediately source current node V_DC Li-Ion battery pack powering system (12.0 PWR) Adaptor (18.0 plugged into system. This because slew-rate control already Therefore, slewrate control must applied every input power source provide most protection. Figure Spice Simulation Using In-rush Protection (Example ONLY))
Pentium® Processor with On-Die Cache Low-Power Module
4.7.4.2
Undervoltage Lockout: Circuit Description (V_uv_lockout)
circuit shown Figure provides undervoltage protection locks applied voltage module prevent accidental turn-on voltage. output this circuit, LM339 comparator, open collector output. when applied voltage less than 4.75 This voltage calculated with following equation with voltage across 2.5-V reference generator).
V_uv_lockout Vref. R18.
V_uv_lockout 4.757 volt
4.7.4.3
Overvoltage Lockout: Circuit Description (V_ov_lockout)
module operates with maximum input voltage This circuit locks input voltage exceeds maximum output this circuit, LM339 comparator, open-collector output. when applied voltage more than This voltage calculated with following equation:
V_ov_lockout Vref.
V_ov_lockout 20.998 volt
4.7.4.4
Overcurrent Protection: Circuit Description
Figure shows that circuit detects overcurrent condition cuts input voltage applied module. This circuit different current limit trip points, which accounts different maximum current drain module different input voltages. Assuming Adaptor 18.0 battery Li-Ion configuration with minimum voltage maximum current above circuit calculated using following expression: With Adaptor (I_wAdaptor):
I_wAdaptor Vref Vbe_Q1
I_wAdaptor 0.989 Without Adaptor (I_woAdaptor):
I_woAdaptor Vref Vbe_Q1. R14.
I_woAdaptor 2.375
Pentium® Processor with On-Die Cache Low-Power Module
Active Thermal Feedback
Table identifies address allocated SMBus thermal sensor used module.
Table Thermal Sensor SMBus Address Table
Function Thermal Sensor Reserved Reserved Fixed Address Bits (6:4) Selectable Address Bits (3:0) 1110 1010 1011
NOTE: thermal sensor used compliant with SMBus addressing. Please refer Pentium® processor Thermal Sensor Interface Specification.
Thermal Sensor Configuration Register
configuration register thermal sensor controls operating mode (Auto Convert Standby) device. Since processor temperature varies dynamically during normal operation, Auto Convert mode should used exclusively monitor processor temperature. Table shows format configuration register. RUN/STOP low, then thermal sensor enters auto-conversion mode. RUN/STOP high, then thermal sensor immediately stops converting enters Standby mode. thermal sensor will still perform temperature conversions Standby mode when receives one-shot command. However, result one-shot command during Auto Convert mode guaranteed. Intel does recommend using one-shot command monitor temperature when processor active, only Auto Convert mode should used.
Table Thermal Sensor Configuration Register
Name MASK Reset State Function Masks SMBALERT# when high. Standby mode control bit. low, device enters autoconvert mode. high, device immediately stops converting, enters standby mode where one-shot command performed. Reserved future use.
RUN/STOP
NOTE: bits should written read "don't care" programming purposes.
Pentium® Processor with On-Die Cache Low-Power Module
Mechanical Specification
This section provides physical dimensions module.
Module Dimensions
Figure shows board dimensions connector orientation.
Figure Board Dimensions with 400-Pin Connector Orientation
Pentium® Processor with On-Die Cache Low-Power Module
5.1.1
Location 400-pin Connector
Figure shows location 400-pin connector referenced adjacent mounting hole.
Figure Board Dimensions with 400-Pin Connector- Orientation
Pentium® Processor with On-Die Cache Low-Power Module
5.1.2
Printed Circuit Board Thickness
Figure shows minimum maximum thickness printed circuit board (PCB). range thickness allows different technologies used with current future modules. Note: system manufacturer must ensure that mechanical restraining method and/or system-level contacts able support this range compatibility with future modules.
Figure Printed Circuit Board Thickness
min: 0.90mm max: 1.10mm Processor Module printed circuit board
5.1.3
Height Restrictions
Figure shows mechanical stack-up associated component clearance requirements. This module keep-out zone should entered. system manufacturer establishes board-to-board clearance between module system electronics selecting three mating connectors. connector sizes available millimeters, millimeters, millimeters. three sizes provide flexibility choosing system electronics components between boards. Information these connectors obtained from Berg Electronics (part number 74291-002).
Pentium® Processor with On-Die Cache Low-Power Module
Figure Keep-Out Zone
NOTE: topside component clearance independent thickness.
Thermal Transfer Plate
processor 82443BX provides heat dissipation thermal attach point where system manufacturer attach heat pipe, heat spreader plate, thermal solution transfer heat through system. Figure Figure attachment dimensions from thermal interface block TTP. When attaching mating block TTP, thermal elastomer thermal grease should used. This material reduces thermal resistance. thermal interface block should secured with 2.0-mm screws using maximum torque Kg*cm Kg*cm (equivalent 0.147 0.197 N*m). thread length 2.00-mm screws should 2.25-mm gaugeable thread (2.25-mm minimum 2.80-mm maximum). system manufacturer should exact dimensions maximum contact area ensure that warpage occurs. warpage occurs, thermal resistance module could adversely affected. thermal resistance between processor core system interface (top TTP) less than C/W.
Pentium® Processor with On-Die Cache Low-Power Module
Figure Thermal Transfer Plate
Figure Thermal Transfer Plate
Pentium® Processor with On-Die Cache Low-Power Module
5.3.1
Module Physical Support
Module Mounting Requirements
Three mounting holes available securing module system base. Figure mounting hole locations. These hole locations board edge clearances will remain fixed modules. three mounting holes should used ensure long term mechanical reliability integrity system. board edge clearance includes 0.762-mm (0.030 inches) wide containment ring around perimeter module. This ring each layer module grounded. surface module, metal exposed shielding purposes. hole patterns also have plated surrounding ring metal standoff shielding purposes. Standoffs should used provide support installed module. distance from bottom module system electronics board with connectors mated millimeters 0.16 -0.13 However, warpage baseboard vary should calculated into final dimensions standoffs used. Figure shows standoff support hole patterns, board edge clearance, dimensions containment ring. components placed board keep-out area.
Figure Standoff Holes, Board Edge Clearance, Containment Ring
Hole detail, places
3.81+/-0.19
2.413
0.050 0.025 hole diameter
4.45 diameter grounded ring
1.27+/- 0.19 board edge ring
0.762 width containment ring
2.54+/-0.19 keep-out area
3.81+/-0.19 board edge hole centerline
5.3.2
Module Weight
module weighs approximately
Pentium® Processor with On-Die Cache Low-Power Module
Thermal Specification
Thermal Design Power
power handling capability system thermal solution reduced less than recommended typical thermal design power (TDP) with implementation firmware/software control "throttling," which reduces processor power consumption dissipation. typical typical power dissipation under normal operating conditions nominal V_CORE (CPU power supply) while executing worst case power instruction mix. This includes power dissipated relevant components. During operating environments, processor junction temperature, must within specified range 100°
Thermal Sensor Setpoint
thermal sensor implements SMBALERT# signal described SMBus specification. SMBALERT# always asserted when temperature processor core thermal diode thermal sensor internal temperature exceeds either upper lower temperature thresholds. SMBALERT# also asserted measured temperature equals either upper lower threshold.
Table Thermal Design Power Specification
Symbol TDPmodule Parameter Module Thermal Design Power Typical 11.5 Notes Module core, 82443BX, voltage regulator
NOTES: During operating environments, processor temperature, must within specified range 100° TDPmodule thermal solution design reference point thermal solution readiness total module power.
Pentium® Processor with On-Die Cache Low-Power Module
Labeling Information
modules tracked ways. first Product Tracking Code (PTC). Intel uses label determine assembly level module. contains characters shown below. AABCCCDDEEEFF where Code Description (Low-Power Module markings) Processor Module (PM) Low-Power Module Speed Identity (333) Cache Size 256Kbyte) Notifiable Design Revision (Start 001) Notifiable Processor Revision (Start
Figure Product Tracking Information
second tracking method generated software utility. Four strapping resistors located module determine production level. connected terminated properly, module-revision levels determined. generated software utility then read these bits with stepping provide complete module manufacturing revision level.
Pentium® Processor with On-Die Cache Low-Power Module
Environmental Standards
environmental standards defined Table
Table Environmental Standards
Parameter Temperature Cycle Humidity Voltage Condition Non-operating Operating Unbiased Shock Non-operating Unpackaged Packaged Packaged Vibration Unpackaged Packaged Packaged Specification -40° relative humidity Half Sine, Trapezoidal, Inclined Impact ft/s Half Sine, Simulated Free Fall gRMS random gRMS 11,800 impacts (low frequency) Non-powered test module only non-catastrophic failure. module tested then inserted system functional test.
Damage
Human Body Model
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