The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

Pentium® Processor Power running Second-level cache pipeline burst SRA


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



Pentium® Processor Low-Power Module
Pentium® Processor Power running Second-level cache pipeline burst SRAM Dedicated 64-bit wide high speed data transfer Kbyte cache data array Clock BSRAM turns when processor low-power states Processor core voltage regulation supports input voltages from Above percent peak efficiency Active Thermal Feedback (ATF) sensing Internal digital signaling (SMBUS) across module interface Programmable trip point interrupt poll mode temperature reading
Thermal transfer plate heat dissipation Intel 443BX Host Bridge/Controller DRAM controller supports SDRAM Supports CLKRUN# protocol SDRAM clock enable support self refresh SDRAM during Suspend mode Compatible SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management; E_SMRAM mode supports write-back cacheable SMRAM Mbyte control, compliant Support single AGP-66 device
Low-Power Module small, highly integrated assembly containing Intel Pentium® Processor Low-Power immediate system-level support. processor module contains power supply processor's unique voltage requirements, system Level cache memory, core logic required bridge processor standard system buses. module interfaces electrically host system 3.3-V bus, 3.3-V memory some control signals Intel 443BX Host Bridge/Controller.
Order Number: 273256-002 February 2000
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. MPEG international standard video compression/decompression promoted ISO. Implementations MPEG CODECs, MPEG enabled platforms require licenses from various entities, including Intel Corporation. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 *Third-party brands names property their respective owners.
Pentium® Processor Low-Power Module
Contents
Introduction
Module Terminology.
Architecture Overview Module Connector Interface
Signal Definitions.10 3.1.1 Signal List.10 3.1.2 Memory (109 Signals) 3.1.3 SIGNALS).12 3.1.4 SIGNALS) 3.1.5 Processor/PIIX4E Sideband Signals).14 3.1.6 Power Management Signals) 3.1.7 Clock Signals) 3.1.8 Voltages Signals) 3.1.9 ITP/JTAG Signals) 3.1.10 Miscellaneous Signals) Connector Assignments Assignments Low-Power Module.22 Cache 443BX Host Bridge/Controller 4.3.1 Memory Organization 4.3.2 Reset Strap Options 4.3.3 Interface 4.3.4 Interface.24 Electrical Requirements 4.4.1 Requirements.25 4.4.2 Requirements 4.4.2.1 System Clock (BCLK) Signal Quality Specifications Measurement Guidelines Module Signal Termination.28 Processor Core Voltage Regulation 4.6.1 Voltage Regulator Efficiency 4.6.2 Voltage Regulator Control 4.6.2.1 Voltage Signal Definition Sequencing 4.6.3 Power Planes: Bulk Capacitance Requirements 4.6.3.1 V_DC Decoupling 4.6.4 Surge Current Study.32 4.6.4.1 Slew-Rate Control: Circuit Description 4.6.4.2 Under-Voltage Lockout: Circuit Description 4.6.4.3 Over Voltage Lockout: Circuit Description.36 4.6.4.4 Over Current Protection: Circuit Description Active Thermal Feedback.37 Power Management
Functional Description.22
Pentium® Processor Low-Power Module
Clock Control Architecture. Normal State Auto Halt State Stop Grant State 4.8.4.1 Quick Start State 4.8.5 HALT/GRANT Snoop State. 4.8.6 Sleep State. 4.8.7 Deep Sleep State 4.8.8 Currently Supported Clock States 4.8.9 Operating System Implications Quick Start Sleep States Typical POS/STR Power. Module Dimensions. 5.1.1 Board Area 5.1.2 Module Location. 5.1.3 Printed Circuit Board Thickness 5.1.4 Height Restrictions Thermal Transfer Plate Module Physical Support 5.3.1 Module Mounting Requirements 5.3.1.1 Module Weight
4.8.1 4.8.2 4.8.3 4.8.4
Mechanical Requirements
Thermal Specifications Labeling Information.
Product Tracking Code 7.1.1 Module Identification Bits
Environmental Standards
Figures
Block Diagram Pentium Processor Low-Power Module. 400-Pin Connector Footprint Numbers, Module Secondary Side. BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins. Power Sequence Timing V_DC Decoupling Circuit Example Instantaneous In-Rush Current Model Instantaneous In-Rush Current Over Current Protection Circuit Spice Simulation Using Rush Protection. Pentium® Processor Power Clock Control States Low-Power Module Board Dimensions Low-Power Module Board Dimensions- Connector Orientation Board Thickness Module Mechanical Drawing Thermal Transfer Plate Thermal Transfer Plate Standoff Holes, Board Edge Clearance Containment Ring Module Product Tracking Information
Pentium® Processor Low-Power Module
Tables
Module Connector Signal Summary.10 Memory Signal Descriptions.11 Signal Descriptions Signal Descriptions.13 Processor/PIIX4E Sideband Signal Descriptions Power Management Signal Descriptions Clock Signal Descriptions.16 Voltage Descriptions ITP/JTAG Pins.17 Miscellaneous Pins.18 Connector Assignments, Through Connector Assignments, Through K.19 Connector Specifications.21 Configuration Straps 443BX Host Bridge/Controller Power Supply Design Specifications.25 Module Specifications (BCLK) Processor Core Pins.26 BCLK Signal Quality Specifications Simulation Processor Core.27 Typical Voltage Regulator Efficiency.28 Voltage Signal Definitions Sequences Capacitance Requirement Power Plane.31 Thermal Sensor SMBUS Address.37 Processor Clock State Characteristics Low-Power Clock States Supported Processor.42 Low-Power Module Power Specifications Environmental Standards
Pentium® Processor Low-Power Module
Revision History
Revision Date 2/00 5/99 Description Removed references Intel® SpeedstepTechnology (Geyserville). Added section decoupling. First publication this document.
Pentium® Processor Low-Power Module
Introduction
Pentium® Processor Low-Power Module fundamental building block system manufacturer incorporate into system. Pentium Processor Low-Power Module incorporates Pentium processor -Low Power core, second-level cache with RAM, Intel 443BX Host Bridge/Controller (Northbridge), voltage regulator, SMBus thermal sensor single printed circuit board. Intel's host bridge architecture allows physical partitioning PCI, DRAM interfaces; therefore electrical interconnect defined module includes bus, bus, DRAM memory some host bridge sideband signals. onboard voltage regulator provides conversion from system manufacturer's system voltage processor's core voltage. This isolation processor voltage requirements allows system manufacturer incorporate Low-Power Modules with different processor variants into single system. Building around this modular design gives system manufacturer these advantages:
Avoids complexities associated with designing high-speed processor core logic boards Provides upgrade path from previous modules designs using standard interface
This document provides technical information required assist developing latest systems applied computing market segment.
Module Terminology
following terms used often this document explained here clarification: Pentium processor Power-The central processing unit including cache components. Processor core-The processor's execution engine. Thermal Transfer Plate (TTP)-The surface used attach system level thermal solution Pentium Processor Low-Power Module. Thermal Design Power (TDP)-The typical power consumed while executing standard application.
Architecture Overview
Pentium Processor Low-Power Module small, highly integrated assembly containing Pentium processor -Low Power core with internal/bus frequencies 266/66 immediate system-level support. module interfaces electrically host system bus, bus, memory Intel 443BX Host Bridge/Controller. module includes second-level cache pipeline burst SRAM supporting Kbytes. "snooze" mode power management featured previous modules supported. Instead supports "Stop Clock" mode power management SRAMs. this mode, clock signals SRAMs stopped "parked" power state processor.
Pentium® Processor Low-Power Module
module contains features Intel 443BX Host Bridge/Controller. DRAM controller supports with burst read 7-2-2-2 SDRAM with burst read 8-1-1-1 MHz, CL=2). system controller provides CLKRUN# signal request PIIX4E start maintain clock bus. 82443BX clock enable support enables Self Refresh mode SDRAM during Suspend mode compatible with SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM) modes power management; E_SMRAM mode supports write-back cacheable SMRAM Mbyte. Intel 443BX Host Bridge/Controller control which compliant with specifications. 443BX Host Bridge/Controller physical VLSI devices that constitute Intel 440BX AGPset. second device (Southbridge) known PIIX4E PCI/ISA bridge. system manufacturer's system electronics, which connect module, must include PIIX4E device. PIIX4E provides extensive power management capabilities designed support 82443BX module. processor core voltage regulation supports input voltages from enabling above percent peak efficiency. regulator decouples processor voltage requirements from system. module incorporates Active Thermal Feedback (ATF) sensing compliant ACPI specification. This accomplished including SMBus compliant thermal sensor capable supporting internal external temperature sensing with programmable trip points. thermal transfer plate heat dissipation from processor 443BX provides standard thermal attach point which system manufacturer connects system thermal solution. Figure illustrates block diagram Pentium Processor Low-Power Module.
Pentium® Processor Low-Power Module
Figure Block Diagram Pentium Processor Low-Power Module
SRAM V_3S
V_3S
SRAM V_3S
Backside Voltage Processor Core Voltage
Pentium® Processor Power Core
V_DC 5V-21V
V_CPUPU 2.5V
2.5V
Memory
GCLKO GCLKI
Board-to-Board Connector
PCLK1
SMBUS
SMBUS
443BX "Northbridge"
DCLKRD DCLKWR DCLKO
PIIX4 Sidebands
Volt. Reg.
R_GTL
Sense
HCLK0
Pentium® Processor Low-Power Module
Module Connector Interface
Signal Definitions
Table provides list signals category corresponding number signals each category. proper signal termination, Pentium® Processor Power Module Design Guide (order number 273212).
Table
Module Connector Signal Summary
Signal Group Memory Processor/PIIX4E Sideband Power Management Clocks Voltage: V_DC Voltage: V_3S Voltage: Voltage: Voltage: VCCAGP Voltage: V_CPUPU Voltage: V_CLK ITP/JTAG Module Ground Reserved TOTAL PINS Number
3.1.1
Signal List
following notations used denote signal type:
Input Output Open Drain Output pin. This requires pull-up resistor. Open Drain Input pin. This requires pull-up resistor. Input Open Drain Output pin. This requires pull-up resistor. Bidirectional Input/Output
Pentium® Processor Low-Power Module
signal description also includes type buffer used particular signal:
GTL+ CMOS
Open Drain GTL+ interface signal interface signals interface signals Pentium Processor Low-Power Module Voltage compatible (LVTTL) interfacing.
3.1.2
Memory (109 Signals)
Table lists Pentium Processor Low-Power Module memory interface signals.
Table
Memory Signal Descriptions
Name MECC[7:0] Type CMOS CMOS Voltage Description Memory Data: These signals carry Memory data during access DRAM. These pins implemented design tested module. Address Strobe (EDO): These pins select DRAM row. Chip Select (SDRAM): These pins activate SDRAMs. SDRAM accepts command when active low. Column Address Strobe (EDO): These pins select DRAM column. Input/Output Data Mask (SDRAM): These pins synchronized output enables during read cycle byte mask during write cycle.1 Memory Address (EDO/SDRAM): This column address DRAM. 443BX Host Bridge/Controller identical sets address lines (MAA MAB#). module supports only address lines. additional addressing features, please refer Intel 440BX AGPset datasheet (Order Number 290633).2 Memory Write Enable (EDO/SDRAM): MWEA# should used write enable memory data bus. SDRAM Address Strobe (SDRAM): When active low, this signal latches Address positive edge clock. This signal also allows access pre-charge. SDRAM Column Address Strobe (SDRAM): When active low, this signal latches Column Address positive edge clock. This signal also allows Column access. SDRAM Clock Enable (SDRAM): SDRAM clock enable pin. When these signals de-asserted, SDRAM enters power-down mode. Each individually controlled clock enable. MD[63:0] CMOS Memory Data: These signals connected DRAM data bus. They terminated module.
RASA[5:0]# CSA[5:0]#
CASA[7:0]# DQMA[7:0]
CMOS
MAB[9:0]# MAB[10] MAB[12:11]# MAB[13] MWEA# CMOS CMOS CMOS CMOS CMOS
SRASA#
SCASA#
CKE[5:0]
NOTES: DQMA signals non-inverted now. Please refer 82443BX Spec Update. MAB[13] non-inverted address signal now. Please refer 82443BX Spec Update.
Pentium® Processor Low-Power Module
3.1.3
SIGNALS)
Table lists Pentium Processor Low-Power Module's interface signals.
Table
Signal Descriptions (Sheet
Name Type Voltag Description Address/Data: standard address data lines. This functions same AD[31:0] bus. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: This carries command information during cycles when PIPE# being used. During write, this contains byte enable information. command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: used during transactions. Remains deasserted internal pullup resistor. Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. Device Select: Same function DEVSEL#. used during transactions. This signal driven 443BX Host Bridge/Controller when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Indicates compliant target ready provide write data current transaction. Asserted when initiator ready data transfer. Target Ready: Indicates compliant master ready provide write data current transaction. Asserted when target ready data transfer. Stop: Same function STOP#. used during transactions. Asserted target request master stop current transaction. Request: master requests AGP. Grant: Same function PCI. Additional information provided ST[2:0] bus. Grant: Permission given master PCI. Parity: single parity provided over GAD[31:0] GC/BE[3:0]. This signal used during transactions. Pipelined Request: Asserted current master indicate full width address queued target. master queues request each rising clock edge while PIPE# asserted. Sideband Address: This provides additional conduit pass address commands 443BX Host Bridge/Controller from master. Read Buffer Full: Indicates master ready accept previously requested priority read data.
GAD[31:0]
GC/BE[3:0]#
GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GREQ#
GGNT#
GPAR
PIPE#
SBA[7:0]
RBF#
Pentium® Processor Low-Power Module
Table
Signal Descriptions (Sheet
Name Type Voltag Description Status Bus: Provides information from arbiter Master what These bits only have meaning when GGNT asserted. Strobes: Provide timing double clocked data bus. agent that providing data drives these signals. These identical copies each other. Sideband Strobe: Provides timing side-band bus. always driven agent driving SBA[7:0], i.e., master.
ST[2:0]
ADSTB[B:A]
SBSTB
3.1.4
SIGNALS)
Table lists Pentium Processor Low-Power Module's interface signals.
Table
Signal Descriptions (Sheet
Name AD[31:0] Type Voltage Description Address/Data: standard address data lines. address driven with FRAME# assertion, data driven received following clocks. Command/Byte Enable: command driven with FRAME# assertion, byte enables corresponding supplied requested data driven following clocks. Frame: Assertion indicates address phase transfer. Negation indicates that more data transfers desired cycle initiator. Device Select: This signal driven 443BX Host Bridge/Controller when initiator attempting access DRAM. DEVSEL# asserted medium decode time. Initiator Ready: Asserted when initiator ready data transfer. Target Ready: Asserted when target ready data transfer. Stop: Asserted target request master stop current transaction. Lock: Indicates exclusive operation require multiple transactions complete. When LOCK# asserted, nonexclusive transactions proceed. 443BX supports lock processor initiated cycles only. initiated locked cycles supported Request: master requests PCI. Grant: Permission given master PCI.
C/BE[3:0]#
FRAME#
DEVSEL#
IRDY# TRDY# STOP#
PLOCK#
REQ[4:0]# GNT[4:0]#
Pentium® Processor Low-Power Module
Table
Signal Descriptions (Sheet
Name Type Voltage Description Hold: This signal comes from expansion bridge; bridge request PCI. 443BX Host Bridge drains DRAM write buffers, drains processor-to-PCI posting buffers, acquires host before granting request PHLDA#. This ensures that timing masters. PHOLD# protocol been modified include support passive release. Hold Acknowledge: This signal driven 443BX Host Bridge grant expansion bridge. PHLDA# protocol been modified include support passive release. Parity: single parity provided over AD[31:0] C/BE[3:0]# System Error: 443BX asserts this signal indicate error condition. Please refer Intel 440BX AGPset datasheet (order number 290633) further information. Clock Run: open-drain output also input. 443BX Host Bridge requests central resource (PIIX4E) start maintain clock asserting CLKRUN#. 443BX Host Bridge three-states CLKRUN# upon deassertion Reset (since running upon deassertion Reset). Reset: When asserted, this signal asynchronously resets 443BX Host Bridge. signals also three-state, compliant with specifications.
PHOLD#
PHLDA#
SERR#
CLKRUN#
PCI_RST#
CMOS
3.1.5
Processor/PIIX4E Sideband Signals)
Table lists module's processor PIIX4E sideband signals connector interface. voltage level these signals determined V_CPUPU, which supplied module.
Table
Processor/PIIX4E Sideband Signal Descriptions (Sheet
Name Type CMOS CMOS CMOS CMOS Voltage Description Numeric Coprocessor Error: This functions FERR# signal supporting coprocessor errors. This signal tied coprocessor error signal processor driven processor PIIX4E. Ignore Error: This open drain signal connected ignore error processor driven PIIX4E. Initialization: INIT# asserted PIIX4E processor system initialization. This signal open drain. Processor Interrupt: INTR driven PIIX4E signal processor that interrupt request pending needs serviced. This signal open drain. Non-Maskable Interrupt: used force non-maskable interrupt processor. PIIX4E bridge generates when either SERR# IOCHK# asserted, depending Status Control Register programmed. This signal open drain.
FERR#
V_CPUPU
IGNNE# INIT#
V_CPUPU V_CPUPU
INTR
V_CPUPU
CMOS
V_CPUPU
Pentium® Processor Low-Power Module
Table
Processor/PIIX4E Sideband Signal Descriptions (Sheet
Name A20M# Type CMOS Voltage V_CPUPU Description Address Mask: When enabled, this open drain signal causes processor emulate address wraparound Mbyte which occurs Intel 8086 processor. System Management Interrupt: SMI# active synchronous output from PIIX4E that asserted response many enabled hardware software events. SMI# open drain signal asynchronous input processor. However, this chip SMI# synchronous PCLK. Stop Clock: STPCLK# active synchronous open drain output from PIIX4E that asserted response many hardware software events. STPCLK# connects directly processor synchronous PCICLK. When processor samples STPCLK# asserted responds entering power state (Quick Start). processor will only exit this mode when this signal de-asserted.
SMI#
CMOS
V_CPUPU
STPCLK#
CMOS
V_CPUPU
3.1.6
Power Management Signals)
Table lists module's Power Management signals. SM_CLK SM_DATA signals refer two-wire serial SMBus interface. Although this interface currently used solely digital thermal sensor thermal sensor, there reserved serial addresses future use. "Active Thermal Feedback" page more details.
Table
Power Management Signal Descriptions
Name Type CMOS Voltage Description Suspend Status: This signal connects SUS_STAT1# output PIIX4E. provides information host clock status asserted during suspend states. VR_ON: Voltage regulator This tolerant) signal controls operation module's voltage regulator. VR_ON should generated function PIIX4E SUSB# signal which used controlling "Suspend State voltage planes. VR_PWRGD: This signal driven high indicate voltage regulator stable pulled using 131.6K resistor when inactive. used some combination generate system PWRGOOD signal. Power This signal must active after power rail stable. Serial Clock: This clock signal used SMBUS interface digital thermal sensor. Serial Data: Open-drain data signal SMBUS interface digital thermal sensor. Interrupt: This signal open-drain output signal digital thermal sensor.
SUS_STAT1#
V_3ALWAYS
VR_ON
CMOS
V_3S
VR_PWRGD
V_3S
BXPWROK SM_CLK SM_DATA ATF_INT#
CMOS CMOS CMOS CMOS
V_3ALWAYS: voltage supply. generated whenever V_DC available supplied PIIX4E resume well.
Pentium® Processor Low-Power Module
3.1.7
Clock Signals)
Table lists module's clock signals.
Table
Clock Signal Descriptions
Name Type Voltage Description Clock PCLK input module system's clocks. This clock used 443BX Host Bridge logic clock domain. This clock stopped when PIIX4E PCI_STP# signal asserted and/or during suspend states. Host Clock Only HCLK0 input module from CK100-M clock source used processor 443BX Host Bridge/Controller. HCLK0 only clock input supplied module. This clock stopped when PIIX4E CPU_STP# signal asserted and/or during suspend states. SDRAM Clock Out: SDRAM clock reference generated internally 443BX Host Bridge/Controller onboard PLL. feeds external buffer that produces multiple copies SODIMMs. SDRAM Read Clock: Feedback reference from SDRAM clock buffer. This clock used 443BX Host Bridge/Controller when reading data from SDRAM array. SDRAM Write Clock: Feedback reference from SDRAM clock buffer. This clock used 443BX Host Bridge/Controller when writing data SDRAM array. Clock GCLKIN input feedback reference from GCLKO signal. Clock Out: This signal generated 443BX Host Bridge/Controller onboard from HCLK0 host clock reference. frequency GCLKO MHz. GCLKO output used feed both reference input 443BX Host Bridge/Controller device. board layout must maintain complete symmetry loading trace geometry minimize clock skew. Frequency Select: This output signal provides status host clock frequency system electronics. This signal static pulled either high V_CLK voltage supply through 10-K resistor. This module designed 66-MHz strapping option shown below. FQS=0 indicates FQS=1 indicates (for future modules)
PCLK
V_3S
HCLK[1:0]
CMOS
V_CLK
DCLKO
CMOS CMOS CMOS CMOS
DCLKRD
DCLKWR
GCLKIN
GCLKO
CMOS
CMOS
V_3S
Pentium® Processor Low-Power Module
3.1.8
Voltages Signals)
Table lists module's voltage signal definitions.
Table
Voltage Descriptions
Name V_DC V_3S Type Number Input: SUSB# controlled Power-managed voltage supply. output voltage regulator system electronics. This rail during STR, STD, SOff. SUSC# controlled Power-managed voltage supply. output voltage regulator system electronics. This rail during SOff. SUSC# controlled Power-managed voltage supply. output voltage regulator system electronics. This rail during SOff. Voltage: this revision module, this rail must connected V_3. Processor Ring: Driven module power processor interface signals such PIIX4E open-drain pullups processor/PIIX4E sideband signals. Processor Clock Rail: Driven module power CK100-M VDDCPU rail. Description
VCCAGP
V_CPUPU
V_CLK
3.1.9
ITP/JTAG Signals)
Table lists module's ITP/JTAG signals, which system electronics implement JTAG chain port, desired.
Table
ITP/JTAG Pins
Name TCLK TRST# FS_RESET# Type Voltage V_CPUPU V_CPUPU V_CPUPU V_CPUPU V_CPUPU GTL+ V_Core Description JTAG Test Data Out: Serial output port. instructions data shifted processor from this port. JTAG Test Data Serial input port. instructions data shifted into processor from this port. JTAG Test Mode Select: Controls controller change sequence. JTAG Test Clock: Testability clock clocking JTAG boundary scan sequence. JTAG Test Reset: Asynchronously resets controller processor. Processor Reset: Processor reset status ITP. GTL+ Termination Voltage: Used POWERON debug port determine when target system POWERON pulled using resistor VTT. Debug Mode Request: Driven makes request enter debug mode. Debug Mode Ready: Driven processor informs that processor debug mode.
FS_PREQ# FS_PRDY#
V_CPUPU GTL+
NOTE: Recommendation: DBREST# (reset target system) debug port "logically AND'ed" with signal VR_PWRGD connected PIIX4E input PWROK.
Pentium® Processor Low-Power Module
3.1.10
Miscellaneous Signals)
Table lists module's miscellaneous signal pins.
Table Miscellaneous Pins
Name Type CMOS RSVD Number Description Module Revision These pins track revision level processor module. pull resistor V_3S required these signals placed system electronics these signals. Ground Unallocated Reserved pins should connected.
Module ID[3:0]
Ground Reserved
Connector Assignments
Table Table list signals each connector from module system electronics. Refer "Pin Assignments" page assignments pads connector.
Table Connector Assignments, Through (Sheet
Pin# SBA5 GAD25 GAD30 RBF# BXPWROK MD36 MD41 MD43 MD14 MECC4 SCASA# CSA1# SRASA# Reserved Reserved ADSTBB GAD24 GAD29 VCCAGP GAD1 Reserved MD33 MD38 MD42 MD11 MD45 MECC0 WEA# MID1 DQMA4 CSA2# CSA5# Reserved MAB4# SBA6 GAD26 GAD4 GAD3 GAD2 MD37 MD40 MD44 MD15 MECC5 DQMA0 MID0 CSA4# MAB0# MAB2# GAD31 SBA4 GAD27 GAD6 GAD5 ADSTBA CLKRUN# MD32 MD35 MD39 MD10 MD13 MD47 Reserved DQMA1 DQMA5 CSA3# MAB1# Reserved Reserved SBA7 SBA0 GAD8 GC/BE0# GAD7 GAD0 MD34 MD12 MD46 Reserved CSA0# Reserved MAB3# MAB6#
Pentium® Processor Low-Power Module
Table Connector Assignments, Through (Sheet
Pin# Reserved MAB8# Reserved MAB13 CKE1 CKE5 Reserved FS_RESET# FS_PRDY# Reserved Reserved Reserved Reserved V_CPUPU V_CLK Reserved V_DC V_DC Reserved Reserved MAB11# MID2 CKE2 Reserved SMCLK SMDAT Reserved V_DC V_DC MAB5# Reserved MAB12# CKE3 MID3 DQMA2 Reserved MD26 MD58 Reserved V_3S V_3S V_3S Reserved V_DC V_DC Reserved MAB9# Reserved CKE0 CKE4 Reserved DCLKWR FS_PREQ# MD57 TCLK TRST# V_3S V_3S V_3S Reserved V_DC V_DC MAB7# MAB10 DCLKO DCLKRD Reserved DQMA3 MD25 MD60 FERR# IGNNE# ATF_INT# V_3S V_3S V_3S Reserved V_DC V_DC
Table Connector Assignments, Through (Sheet
Pin# GREQ# GGNT# GAD13 GAD12 GAD10 GAD11 GAD9 VCCAGP MECC1 SERR# AD16 GSTOP# GPAR GAD15 GC/BE1# GAD14 VCCAGP C/BE0# AD10 AD13 TRDY# PIPE# SBA1 SBA2 GAD16 GAD18 GFRAME# GTRDY# GDEVSEL# AD15 STOP# SBA3 SBSTB GAD20 GAD17 GC/BE2# GIRDY# VCCAGP AD12 C/BE1# DEVSEL# GCLKI GCLKO GAD23 GC/BE3# GAD22 GAD21 GAD19 GAD28 AD11 AD14 PLOCK#
Pentium® Processor Low-Power Module
Table Connector Assignments, Through (Sheet
Pin# AD19 AD23 AD27 PCI_RST# Reserved IRDY# GNT1# DQMA6 MECC2 DQMA7 MECC6 MECC3 MD27 SMI# A20M# Reserved V_DC V_DC AD30 AD22 PHOLD# FRAME# GNT2# GNT4# PHLDA# MECC7 MD48 MD16 MD17 MD49 MD28 MD29 INTR SUS_STAT1# STPCLK# Reserved V_DC V_DC AD17 AD24 C/BE3# AD20 AD31 REQ2# GNT0# MD50 MD18 MD19 MD21 MD20 MD61 VR_ON VR_PWRGD INIT# Reserved V_DC V_DC C/BE2# AD26 AD28 AD29 REQ1# REQ3# REQ4# MD51 MD52 MD53 MD22 MD62 MD30 Reserved V_DC V_DC AD18 AD21 PCLK AD25 REQ0# GNT3# MD59 MD54 MD24 MD23 MD55 MD56 MD63 MD31 HCLK0 HCLK1 Reserved V_DC V_DC
Assignments
module connector surface mount, 1.27 pitch style, 400-pin connector. There currently three unique mating connector receptacles that available module from Berg Electronics (part number 74219-002). Figure shows connector assignments manufacturer's system electronics. This footprint viewed from secondary side processor module (the side printed circuit board which 400-pin connector soldered).
Pentium® Processor Low-Power Module
Figure 400-Pin Connector Footprint Numbers, Module Secondary Side
400-Pin Connector Assignments
(Viewed from Secondary Side)
Table summarizes some more critical specifications connector. Table Connector Specifications
Parameter Contact Material Housing Current Voltage Electrical Insulation Resistance Termination Resistance Capacitance Mating Cycles Mechanical Connector Mating Force Contact Un-mating Force Thermo Plastic Molded Compound: min. max. 20mV open circuit with 10mA max. contact cycles max. contact min. contact Condition Copper Alloy Specification
Pentium® Processor Low-Power Module
Functional Description
Low-Power Module
Pentium Processor Low-Power Module supports Pentium Processor Power core running 266/66 with Kbyte code data cache sizes.
Cache
processor core's internal cache complimented with second-level cache using highperformance pipeline burst SRAM which uses dedicated high speed into processor core. cache support Mbytes system memory, while maximum amount cacheable system memory supported 443BX Host Bridge/Controller Mbytes with Mbit DRAMs. (The system controller support Gbytes system memory using 64-Mbit technology.) module 100-pin TQFP footprints Kbyte direct-mapped writeback cache. module supports "Stop Clock" mode power management SRAMs. this mode, clock signals synchronous SRAMs stopped "parked" low-power state.
443BX Host Bridge/Controller
Intel's 443BX Host Bridge/Controller highly integrated device that combines controller, DRAM controller, controller into component. 443BX Host Bridge multiple power management features low-power systems:
CLKRUN# feature that enables controlling clock 443BX Host Bridge suspend modes include Suspend-to-RAM (STR), Suspend-to-Disk (STD)
Powered-On-Suspend (POS)
System Management (SMRAM) power management modes include Compatible
SMRAM (C_SMRAM) Extended SMRAM (E_SMRAM). C_SMRAM traditional SMRAM feature implemented Intel chipsets. E_SMRAM feature that supports write-back cacheable SMRAM space Mbyte. minimize power consumption while system idle, internal 443BX Host Bridge clock turned (gated off) when there processor activity. module supports only 443BX Host Bridge/Controller features "mobile compatible" legacy mode. Refer Intel 440BX AGPset: 82443BX Host Bridge/Controller datasheet (order number 290633) complete details.
Pentium® Processor Low-Power Module
4.3.1
Memory Organization
complete memory interface 443BX Host Bridge/Controller available module's connector; 443BX standard Mode memory configurations modes operation supported signaling interface. This allows memory interface support following:
memory control signals, sufficient support three SO_DIMM sockets
banks SDRAM
signal each banks
memory features supported 443BX Host Bridge/Controller standard Mode are:
Support eight banks memory Second memory address lines (MAA[13:0]) SDRAM (and Front Side Bus)
DRAM technologies supported 443BX Host Bridge/Controller include Extended Data (EDO) SDRAM. These memory types mixed system. other words, DRAM rows (RAS[5:0]#) must same technology. 443BX Host Bridge/Controller targets DRAMs. SDRAMs. module's clocking architecture supports SDRAM. tight timing requirements 66-MHz SDRAM clocks, clocking mode SDRAM system manufacturer custom memory configurations allows host SDRAM clocks generated from same clocking architecture OEM's system electronics. complete details about using SDRAM memory, trace length guidelines, Pentium® Processor Power Module SDRAM DIMM Routing Guidelines (order number 273230). details memory device support, organization, size addressing, refer Intel 440BX AGPset: 82443BX Host Bridge/Controller datasheet (order number 290633).
4.3.2
Reset Strap Options
443BX Host Bridge/Controller several strap options memory address which define behavior device after reset. module, several these strap options implemented module. Other straps allowed override default settings. Table shows various straps they handled module.
Table Configuration Straps 443BX Host Bridge/Controller
Signal MAB[12]# MA[11]# MA[10] MA[9]# MA[7]# MA[6]# Function Host Frequency Select Order Queue Depth Quick Start Select disable Config Host Buffer Mode Select Module Default Setting strap. default) strap. (Maximum Queue Depth (i.e., Strapped high module Quick Start mode. strap. enabled strap. Standard mode. Strapped high module buffers. Optional Override System Electronics None None None Pull this signal disable interface. None None
Pentium® Processor Low-Power Module
4.3.3
Interface
443BX Host Bridge/Controller compliant with specification, which improves worst-case access latency from earlier specifications. complete interface 443BX Host Bridge/Controller available connector. 443BX Host Bridge/Controller supports Clockrun protocol power management. this protocol, devices assert CLKRUN# open-drain signal when they require interface. 443BX Host Bridge/Controller responsible arbitrating bus. Since module configured "mobile compatible" legacy mode, 443BX Host Bridge/Controller support only five masters. There five Request/Grant pairs, REQ[4:0]# GNT[4:0]#, available connector manufacturer's system electronics. interface module only. devices supported, specifically devices which drive outputs nominal level. 443BX Host Bridge/Controller supports only Mechanism accessing configuration space, detailed specification. This implies that signals AD[31:11] available IDSEL signals. However, since 443BX Host Bridge always device AD11 will never asserted during configuration cycles IDSEL. AD12 reserved 443BX bus. Thus, AD13 first available address line usable IDSEL. AD18 recommended used PIIX4E Southbridge.
4.3.4
Interface
443BX Host Bridge/Controller compliant with Rev. specification, which supports only asynchronous interface coupling 443BX core frequency. interface reach theoretical ~500 Mbytes/s transfer rate (i.e., using 2X/133 devices). actual bandwidth will limited capability 443BX memory subsystem.
Pentium® Processor Low-Power Module
Electrical Requirements
following section provides information requirements module.
4.4.1
Requirements
Refer Table power supply design criteria ensure compliance with module's power requirements.
Table Power Supply Design Specifications
Symbol
Parameter Input Voltage Input Current Maximum Surge Current
12.0
21.0 17.3
Unit
Notes1
IDC-Surge
IDC-Leakage
Typical Leakage Current Power Managed Voltage Supply Power Managed Current Maximum Surge Current Typical Leakage Current Power Managed 3.3V Voltage Supply Power Managed 3.3V Current Maximum Surge Current Typical Leakage Current Processor Ring Voltage Processor Ring Current Processor Clock Rail Voltage Processor Clock Rail Current 2.375 2.375 24.0 3.135 4.75
5.25 3.465 35.0 2.625 2.625
I5-Surge I5-Leakage I3-Surge I3-Leakage VCPUPU ICPUPU VCLK ICLK
0.125 0.125
NOTES: V_DC order determine typical V_DC current. V_DC order determine maximum V_DC current. Leakage current that expected when VR_ON deactivated V_DC still applied. These values system dependent.
Pentium® Processor Low-Power Module
4.4.2
Requirements
Please refer Table module timing requirements BCLK. BCLK system timing specified terms signal quality. waveform Figure describes typical system clock seen processor core pin.
Table Module Specifications (BCLK) Processor Core Pins
Parameter 66.67 ±250 0.175 0.175 0.875 0.875 Unit Figure Notes1,2,3 processor core frequencies @>1.765 @<0.5 (0.9 V-1.6 (1.6 V-0.9
System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time
NOTES: Unless otherwise noted, specifications this table apply modules. timings GTL+ signals referenced BCLK rising edge 1.25 processor core pin. GTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor core pins. timings CMOS signals referenced BCLK rising edge 1.25 processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25 processor core pins. internal core clock frequency derived from system clock. system clock core clock ratio determined during initialization described predetermined module. BCLK period allows +0.5 tolerance clock driver variation. CK97 Clock Synthesizer/Driver Specification further information. This specification applies Pentium processor system frequency MHz. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25 processor core pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CKDM66-M Clock Synthesizer/Driver Specification further details. 100% tested. Specified design characterization clock driver requirement.
Pentium® Processor Low-Power Module
4.4.2.1
System Clock (BCLK) Signal Quality Specifications Measurement Guidelines
Table describes signal quality specifications processor core module system clock (BCLK) signal. Figure describes signal quality waveform system clock processor core pins.
Table BCLK Signal Quality Specifications Simulation Processor Core
Parameter BCLK BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback 1.765 -0.8 1.765 Unit Figure Notes1
NOTES: Unless otherwise noted, specifications this table apply modules. This Pentium processor system clock overshoot undershoot specification 66-MHz system operation. Clock signal must monotonic from +0.5 +1.765 rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins
Pentium® Processor Low-Power Module
Module Signal Termination
System design requirements signal termination module have been split between processor module system electronics. system designer responsible ensuring proper termination signals.
Processor Core Voltage Regulation
module's voltage regulator (DC/DC converter) designed support core voltage ring voltage current future processors. voltage regulator provides appropriate processor core voltage, processor sideband signal pull-up voltage, voltage components processor core backside bus. these voltages, only processor sideband pull-up voltage (V_CPUPU) delivered system electronics. module supports input voltage range from system battery, power supply.
4.6.1
Voltage Regulator Efficiency
There three voltage regulators module. These voltage regulators generate core voltage used CPU, voltage backside bus, voltage ring voltage. core voltage regulator provides required current from V_DC (battery voltage adapter) supply. relative efficiencies shown Table backside ring voltage regulators plane about percent efficient typical loads.
Table Typical Voltage Regulator Efficiency
Icore, V_DC, 5.00 5.00 5.00 5.00 5.00 5.00 5.00 12.00 12.00 12.00 12.00 12.00 12.00 12.00 I_DC, 0.394 0.752 1.212 1.506 1.921 2.290 2.683 0.186 0.335 0.491 0.652 0.816 0.980 1.149 Efficiency1 V_DC, 18.00 18.00 18.00 18.00 18.00 18.00 18.00 21.00 21.00 21.00 21.00 21.00 21.00 21.00 I_DC2 0.135 0.233 0.340 0.451 0.561 0.674 0.790 0.129 0.215 0.304 0.396 0.493 0.592 0.692 Efficiency1
NOTES: These efficiencies will change with future voltage regulators that accommodate wider ranges input voltages. With V_DC applied voltage regulator off, typical leakage with maximum Icore indicates processor core current being drawn during test measurement.
Pentium® Processor Low-Power Module
4.6.2
Voltage Regulator Control
VR_ON connector allows digital signal (3.3 safe) control voltage regulator. system manufacturer this signal turn module's voltage regulator off. VR_ON should controlled function same digital control signal (SUSB#) used control system's switched V/3.3 power planes. PIIX4E Southbridge defines Suspend power management state which power physically removed from processor, cache, 443BX Host Bridge/Controller, voltage regulator. this state, SUSB# PIIX4E controls these power planes.
Caution:
VR_ON should switch high only when following conditions met; V_5(s) V_DC Turning VR_ON prior meeting these conditions will severely damage module. Figure page proper timing sequencing.
4.6.2.1
Voltage Signal Definition Sequencing
Table Voltage Signal Definitions Sequences
Signal Source Definitions Sequences voltage driven from power supply required between V_DC powers module's DC-to-DC converter processor core voltages. module cannot inserted removed while V_DC powered supplied system electronics 443BX. supplied system electronics 443BX's reference voltage module's voltage regulator. V_3S supplied system electronics cache devices. Each must powered during system states. Enables module's voltage regulator circuit. When driven active high (3.3V) voltage regulator circuit module activated. signal driving VR_ON should digital signal with rise/fall time less than equal result VR_ON being asserted, V_CORE output DC-DC regulator module driven core voltage processor. also used host GTL+ termination voltage, known VTT. V_BSB_IO 1.8V. system electronics uses this voltage power cache-to-processor interface circuitry. Upon sampling voltage level V_CORE processor, minus tolerances ripple, VR_PWRGD driven active high (3.3 system electronics sample prior providing PWROK PIIX4E. VR_PWRGD sampled active within second assertion VR_ON system electronics should deassert VR_ON. V_CPUPU system electronics uses this voltage power PIIX4E-to-processor interface circuitry. V_CLK system electronics uses this voltage power HCLK_(0:1) drivers processor clock.
V_DC
System Electronics
System Electronics System Electronics
V_3S
System Electronics
VR_ON
System Electronics
V_CORE (also used host GTL+ termination voltage VTT) V_BSB_IO
Module Only; module interface.
Module Only; module interface.
VR_PWRGD
Module
V_CPUPU
Module
V_CLK
Module
Pentium® Processor Low-Power Module
Figure details sequencing Signals Voltage planes required normal operation module. module provides VR_PWRGD signal, which indicates that voltage regulator power operating stable voltage level. system manufacturer should this signal system electronics control power inputs gate PWROK PIIX4E Southbridge. Note: VR_ON signal should driven digital signal with rise/fall time less than equal signaling voltage levels that meet requirement Vil(max)=0.4V Vih(min)=3.0
Figure Power Sequence Timing
V_DC V_3S VR_ON VR_PWRGD V_CPUPU/ V_CLK NOTE NOTE
POWER SEQUENCE TIMING
PWROK board should active when VR_PWRGD active V_3S good. CPU_RST from board should active minimum after PWROK active PLL_STP# CPU_STP# inactive. Note that PLL_STP# condition RSMRST# SUSB# PIIX4. V_DC 4.7V, V_5>=4.5V, V_3S>=3.0V. V_CPUPU V_CLK generated Intel Mobile Module. This power supplied thep rocessor module connector. This should first plane power
Pentium® Processor Low-Power Module
4.6.3
Power Planes: Bulk Capacitance Requirements
order provide adequate filtering in-rush current protection system design, bulk capacitance required. small amount bulk capacitance supplied Module, however, order achieve proper filtering additional capacitance should placed system electronics. Table details bulk capacitance requirements system electronics when using Module.
Table Capacitance Requirement Power Plane
Power Plane V_DC V_3S VCC_AGP V_CPUPU V_CLK Capacitance Requirements 0.01 0.01
Ripple Current 1-3.5 Amp3
Rating tolerance tolerance tolerance tolerance tolerance tolerance tolerance
0.01 0.01
0.01 8200 8200
NOTES: Placement above capacitance requirements should located near module connector. V_CLK filtering should located next system clock synthesizer. Ripple current specification depends V_DC input. V_DC, device required. V_DC higher, sufficient.
Pentium® Processor Low-Power Module
4.6.3.1
V_DC Decoupling
V_DC tied together, ensure that decoupling guidelines strictly followed avoid noise from V_DC rail coupling rail. Noise could trigger undervoltage lockout circuits module. example circuit shown Figure adheres decoupling guidelines.
Figure V_DC Decoupling Circuit Example
V5_0
200nH
0.1µF 0.1µF 0.1µF
Inductor
220µF
220µF
220µF
A7703-01
Exact component values system dependant. Intel recommends that specific component values determined through full simulation parasitic modeling.
4.6.4
Surge Current Study
Surge current analysis performed typical system power supply determine maximum amount surge current that module capable handling. This information then used develop module system bulk capacitance requirements (Table 20). This section provides results this study. Figure shows electrical model used when analyzing instantaneous power-on conditions. following analysis provided worst case analysis. Depending system electronics design, different impedances seen yielding different results. should perform thorough analysis understand implications surge current their system. previously stated, following study performed "worst-case" situation with bulk capacitance V_DC line system electronics. Given that, module with each. module connector approximately series resistance total series resistance 0.33 user powers system with adapter amount surge current seen capacitors module would greater than Amps! Figure illustrates results this situation with SPICE simulation.
Pentium® Processor Low-Power Module
Figure Instantaneous In-Rush Current Model
Figure Instantaneous In-Rush Current
stringent component height requirements 4mm) module, tantalum capacitors must used input bulk capacitance voltage regulator circuit. Because tantalum capacitor's susceptibility high in-rush current, special care must taken soften initial rush current applied these capacitors. soften in-rush current provide over voltage/over current protection ramp V_DC slowly using circuit similar shown Figure
Pentium® Processor Low-Power Module
Figure Over Current Protection Circuit
4.6.4.1
Slew-Rate Control: Circuit Description
Figure voltage generated applying Adaptor Battery. RDS(on) P-Channel MOSFET such Siliconix SI4435DY. When voltage applied increased over 4.75 UNDER_VOLTAGE_LOCKOUT Circuit allows pull gate start turn-on sequence. pulls drain toward ground forcing current flow through will start source current until after t_delay with t_delay defined
t_delay Vpwr Vgs_max
Vgs_max
Vpwr
manufacturer's Vgs_max specification must never exceeded. However, Vgs_max must high enough keep (on) device possible. After initial t_delay, will begin source current V_DC will start ramp ramp time, t_ramp, defined
t_ramp Vsat Vgs_max t_delay
Maximum current during voltage ramping
Vpwr Ctotal t_ramp
With circuit shown Figure t_delay 5.53 t_tran 14.0 I_max
Pentium® Processor Low-Power Module
Figure shows SPICE simulation circuit Figure increase reliability Tantalum capacitors, slew rate control circuit described Figure voltage-derate capacitor about percent. That maximum input voltage capacitor with with high ripple current capability. base board, place five µF/35 capacitors directly V_DC pins processor module connector. acceptable capacitor this application would component from AVX: TPSE226K035R0300. more issue that must raised here that Slew Rate Control circuit should applied every input power source system V_DC provide most protection. power sources (i.e., battery batteries, Adaptor, etc.) OR'ed together node, there still potential problem. example, Li-Ion battery pack powering system PWR), Adaptor plugged into system, will immediately source current node V_DC rapidly. This because Slew Rate Control already Therefore, slew rate control must applied every input power source provide most protection. Also shown Figure under over voltage over-current protection circuits that used increase protection level module. Figure Spice Simulation Using Rush Protection
Pentium® Processor Low-Power Module
4.6.4.2
Under-Voltage Lockout: Circuit Description
circuit shown Figure provides under-voltage protection locks applied voltage module prevent accidental turn-on voltage. output this circuit, LM339 comparator, open-collector output. when applied voltage less than 4.75 This voltage calculated with following equation with voltage across 2.5-V reference generator.)
V_uv_lockout Vref. R18.
V_uv_lockout 4.757 volt
4.6.4.3
Over Voltage Lockout: Circuit Description
module specified operate with maximum input voltage This circuit locks input voltage exceeds maximum output this circuit, LM339 comparator, open-collector output. when applied voltage more than This voltage calculated with following equation:
V_ov_lockout Vref.
V_ov_lockout 20.998 volt
4.6.4.4
Over Current Protection: Circuit Description
Figure shows that circuit detects over-current condition cuts input voltage applied module. This circuit different current limit trip points. This takes into account different maximum current drain module different input voltages (i.e., whether Adaptor plugged not.) Assuming adapter voltage battery Li-Ion configuration with minimum voltage maximum current above circuit calculated using following equation: With Adaptor:
I_wAdaptor Vref Vbe_Q1
I_wAdaptor 0.989
I_woAdaptor Vref Vbe_Q1. R14.
I_woAdaptor 2.375
Pentium® Processor Low-Power Module
Active Thermal Feedback
Table identifies address allocated System Management (SMBus) thermal sensor used module.
Table Thermal Sensor SMBUS Address
Function Thermal Sensor Reserved Reserved Fixed Address Bits (6:4) Selectable Address Bits (3:0) 1110 1010 1011
NOTE: thermal sensor used compliant with SMBus addressing. Please refer Pentium® processor Thermal Sensor Interface Specification.
4.8.1
Power Management
Clock Control Architecture
processor clock control architecture (Figure been optimized leading edge deep green system designs. Auto Halt state provides power clock state that controlled through software execution instruction. Quick Start state provides very power, exit latency clock state that used hardware controlled "idle" computer states. Deep Sleep state provides extremely power state that used "Power-on Suspend" computer states, which alternative shutting processor's power. Compared Pentium processor exit latency exit latency Deep Sleep state been reduced Pentium processor Power. Stop Grant Sleep states shown Figure intended "Deep Green" desktop server systems-not applied computing systems. Performing state transitions shown Figure neither recommended supported. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep Deep Sleep states. Stop Grant Quick Start clock states mutually exclusive, i.e., strapping option A15# chooses which state entered when STPCLK# signal asserted. Quick Start state enabled strapping A15# ground Reset; otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Stop Grant state higher power level than Quick Start state designed platforms. Quick Start state much lower power level, only used uniprocessor platforms. Table provides clock state characteristics (power numbers based estimates Pentium Processor Power running MHz), which described detail following sections.
Pentium® Processor Low-Power Module
Figure Pentium® Processor Power Clock Control States
STPCLK# stop grant cycle (!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !QSS stop grant cycle (!STPCLK# !HS) stop break !STPCLK# STPCLK# !QSS stop grant cycle Snoop occurs Snoop serviced SLP# !SLP# RESET# BCLK stopped STPCLK# stop grant cycle !STPCLK#
Normal State
HS=false
Quick Start
BCLK stopped BCLK
Auto Halt
HS=true
Snoop Snoop serviced occurs
Deep Sleep
Snoop occurs Snoop serviced
Stop Grant
HALT/Grant Snoop
BCLK !QSS
Sleep
halt break BINIT#, FLUSH#, SMI#, NMI, INTR, INIT#, RESET#, A20M# stop break BINIT#, FLUSH#, RESET# Quick Start Strapping option Processor Halt State instruction executed
NOTE: shaded states features Pentium® Processor Power implemented module. module never enters shaded states.
Pentium® Processor Low-Power Module
Table Processor Clock State Characteristics
Clock State Normal Auto Halt Stop Grant Approximately clocks clocks Through snoop, HALT/Grant Snoop state: immediate Through STPCLK#, Normal state: clocks clocks after snoop activity. Stop Grant state clocks Exit Latency Power Varies Snooping? System Uses Normal program execution controlled entry idle mode controlled entry/exit throttling controlled entry/exit throttling Supports snooping power states controlled entry/exit desktop idle mode support controlled entry/exit powered-on suspend support
Quick Start
HALT/ Grant Snoop Sleep
specified
Deep Sleep
4.8.2
Normal State
Normal state processor normal operating mode where processor's internal clock running processor actively executing instructions.
4.8.3
Auto Halt State
This power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH# SMI#). Asserting STPCLK# signal while Auto Halt state causes processor transition Stop Grant Quick Start state, where Stop Grant Acknowledge cycle issued. deasserting STPCLK#, system logic return processor Auto Halt state without issuing Halt cycle. SMI# interrupt recognized Auto Halt state. return from System Management Interrupt (SMI) handler either Normal state Auto Halt state. Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide, more information. Halt cycle issued when returning Auto Halt state from SMM. FLUSH# signal serviced Auto Halt state. After on-chip off-chip caches have been flushed, processor will return Auto Halt state without issuing Halt cycle. Transitions A20M# recognized while Auto Halt state.
Pentium® Processor Low-Power Module
4.8.4
Stop Grant State
processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made de-assertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH# RESET# assertion). While Stop Grant state, SMI#, INIT# LINT[1:0] will latched processor, only serviced when processor returns normal state. Only occurrence each event will recognized upon return normal state. processor will return Stop Grant state after completion BINIT# initialization unless STPCLK# been deasserted. RESET# assertion will cause processor immediately initialize itself, processor will stay Stop Grant state after initialization until STPCLK# deasserted. FLUSH# signal asserted, processor will flush on-chip off-chip caches return Stop Grant state. transition Sleep state made assertion SLP# signal.
4.8.4.1
Quick Start State
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated system priority device. Because snooping behavior, Quick Start only used Uniprocessor (UP) configuration. transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupt, servicing snoop transactions from symmetric masters responding FLUSH# BINIT# assertions. While processor Quick Start state, will respond properly input signal other than STPCLK#, RESET# BPRI#. other input signal changes, then behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. thermal sensor will respond normally SMBus transactions when processor Quick Start state. RESET# assertion will cause processor immediately initialize itself, processor will stay Quick Start state after initialization until STPCLK# deasserted. Asserting SLP# signal when processor configured Quick Start will result unpredictable behavior recommended.
Pentium® Processor Low-Power Module
4.8.5
HALT/GRANT Snoop State
processor will respond snoop transactions system while Auto Halt, Stop Grant Quick Start state. When snoop transaction presented system processor will enter HALT/GRANT Snoop state. processor will remain this state until snoop system been serviced system quiet. After snoop been serviced, processor will return previous Auto Halt, Stop Grant Quick Start state. HALT/Grant Snoop state entered from Quick Start state, then input signal restrictions Quick Start state still apply HALT/Grant Snoop state, except those signal transitions that required perform snoop.
4.8.6
Sleep State
Sleep state very power state which processor maintains context phase-locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state, SLP# signal asserted, causing processor enter Sleep state. SLP# recognized Normal Auto Halt states. processor reset RESET# while Sleep state. RESET# driven active while processor Sleep state then SLP# STPCLK# must immediately driven inactive ensure that processor correctly executes Reset sequence. Input signals (other than RESET#) change while processor Sleep state transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. thermal sensor will respond normally SMBus transactions when processor Sleep state. While Sleep state, processor capable entering lowest power state, Deep Sleep state, removing processor's input clock. PICCLK removed Sleep state.
4.8.7
Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. Deep Sleep state entered stopping BCLK input processor, while Sleep Quick Start state. proper operation, BCLK input should stopped state. re-enter either Sleep Quick Start state from Deep Sleep state, BCLK input must restarted. processor will return Sleep Quick Start state, appropriate, after PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior. thermal sensor will respond normally SMBus transactions when processor Deep Sleep state.
Pentium® Processor Low-Power Module
4.8.8
Currently Supported Clock States
Table shows low-power clock states supported Pentium processor family product line.
Table Low-Power Clock States Supported Processor
Clock State Processor Stop Grant Pentium® Processor Pentium Processor Pentium Processor Power Pentium Processor Low-Power Module Auto Halt Quick Start Sleep Deep Sleep
4.8.9
Operating System Implications Quick Start Sleep States
There number architectural features Pentium Processor Power that available when Quick Start state enabled function Quick Start Sleep state they Stop Grant state. These features part APIC, time-stamp counter performance monitor counters. local APIC timer does behave properly when processor Quick Start Sleep state. There guarantee that local APIC timer will count down Quick Start Sleep state. timer counts down zero when processor about enter Quick Start Sleep state, processor's behavior will unpredictable. Inter-Processor Interrupts (IPIs) should used Pentium processor Power systems. software generates just before processor enters Quick Start Sleep state, then message APIC will generated. This would violate requirement that input signals toggle Quick Start Sleep state. software-generated Pentium Processor Power system (uniprocessor system) will always result error. time-stamp counter performance monitor counters guaranteed count Quick Start Sleep states. software sets APIC interrupt enable either performance counters, then resulting behavior will unpredictable.
Typical POS/STR Power
Module supports both power suspend (POS) suspend (STR) features. Typical power during these states are:
State Module Power 910mW
These average values measurement several typical modules guidelines only.
Pentium® Processor Low-Power Module
Mechanical Requirements
Module Dimensions
This section provides physical dimensions module.
5.1.1
Board Area
Figure shows board dimensions connector orientation module.
Figure Low-Power Module Board Dimensions
Pentium® Processor Low-Power Module
5.1.2
Module Location
Figure shows location 400-pin connector referenced adjacent mounting hole.
Figure Low-Power Module Board Dimensions- Connector Orientation
Figure Board Thickness
min: 0.90mm max: 1.10mm Processor Module printed circuit board
Pentium® Processor Low-Power Module
5.1.3
Printed Circuit Board Thickness
Figure shows module profile associated minimum maximum thickness printed circuit board (PCB). range thickness allows different technologies used with current future modules. Note: system manufacturer must ensure that mechanical restraining method and/or system-level contacts able support this range thickness, ensure compatibility with future modules.
5.1.4
Height Restrictions
Figure shows module mechanical stackup associated component clearance requirements. system manufacturer establishes board-to-board clearance between module system electronics selecting three possible mating connectors. mating connectors provide board-to-board clearances (distance underneath module) With these three options, system manufacturer reasonable flexibility choosing components system electronics that between boards. connector receptacles available from Berg Electronics (part number 74219-002).
Figure Module Mechanical Drawing
Note:
module side component clearance referenced from bottom PCB, independent thickness.
Pentium® Processor Low-Power Module
Thermal Transfer Plate
module provides thermal transfer plate, TTP, connected processor standard position called thermal attach point (see Figure Figure exact dimensions). thermal attach point fixed location relative mounting holes other physical datum module. system manufacturer both heat pipe heat spreader plate contact with thermal attach point transfer heat through system thermal solution their choice. thermal resistance measured between processor core less than Watt. thermal transfer plate physically mounted module, different from generation module next. following figures detail mechanical dimensions thermal transfer plate used module, conceptual relationship between circuit board thermal transfer plate, thermal attach point.
Figure Thermal Transfer Plate
Pentium® Processor Low-Power Module
Figure Thermal Transfer Plate
Module Physical Support
Figure shows module standoff support hole patterns board edge clearance around perimeter module. These hole locations board edge clearances will remain fixed modules. hole patterns board edge clearance lets system manufacturer develop several methods mechanically supporting module within system.
5.3.1
Module Mounting Requirements
Three mounting holes available System securing module system base system electronics. Figure mounting hole locations. strongly recommended that designer mounting screws through three mounting holes ensure long term reliability mechanical integrity system. interface module's thermal transfer plate (TTP), recommended that exact dimensions shown Figure thermal interface block used. These dimensions provide maximum contact area while ensuring that warpage occurs. warpage occurs improperly-designed interface, over-tightening assembly screws, thermal resistance module could adversely affected.
Pentium® Processor Low-Power Module
When attaching mating block module TTP, material such thermal elastomer thermal grease should used. This material designed reduce thermal resistance should placed between mating block. This will improve overall system thermal efficiency. After placed mating thermal transfer plate, should secured with screws using maximum torque Kg*cm (equivalent 0.147 0.197 N*m). thread length 2.00 screws should 2.25 gaugeable thread (2.25 minimum 2.80 maximum). board edge clearance includes 0.762 (0.030 width containment ring around perimeter module. This ring each layer module grounded. surface module, metal exposed shielding purposes. hole patterns placed module also have plated surrounding ring metal standoff contact ring shielding purposes. Figure shows dimensions containment ring keepout area. components placed board keepout area. Figure Standoff Holes, Board Edge Clearance Containment Ring
Standoffs should used provide support installed module. distance from bottom module system electronics board with connectors mated +0.16 -0.13 however warpage baseboard vary should calculated into final dimensions standoffs used.
5.3.1.1
Module Weight
weight module
Pentium® Processor Low-Power Module
Thermal Specifications
Table Low-Power Module Power Specifications
Symbol Parameter Thermal Design Power Max1 13.9 Unit Notes Module (core, Northbridge, voltage regulator, cache)
NOTES: TDPMAX specification total power dissipation worst-case processor, worst-case Northbridge, worst-case cache, worst-case voltage regulator while executing worst-case instruction under normal operating conditions nominal voltages. 100% tested. Specified design/characterization.
Labeling Information
module means being tracked. first means labeling information Intel Product Tracking Code (PTC) other generated software utility.
Product Tracking Code
Product Tracking Code label provides module information that used Intel determine assembly level module. label exists secondary side module provides following information:
Figure Module Product Tracking Information
Pentium® Processor Low-Power Module
Thirteen letters make Product Tracking Code. example definition each element tracking code shown below. Example: PME26605001AA format AABCCCDDEEEFF.
Tracking Code Definition processor module Pentium® Processor Power Processor speed Cache size, Kbyte Design Revision (starts 001) Processor Revision (starts
7.1.1
Module Identification Bits
Located module four strapping resistors used determine production level module. connected terminated properly, unique module revision levels determined. Using software utility generated OEM, these bits read along with processor Northbridge stepping provide complete module manufacturing revision level.
Environmental Standards
environmental standards module defined Table
Table Environmental Standards
Parameter Temperature Cycle Humidity Voltage Condition Non-Operating Operating Unbiased V_3S Shock Non-Operating Unpackaged Packaged Packaged Vibration Unpackaged Packaged Packaged Human Body Model Specification -40° relative humidity Half Sine, Trapezoidal, Inclined Impact ft/s Half Sine, Simulated Free Fall gRMS random gRMS 11,800 impacts (low frequency) detectable err)

Other recent searches


V4070 - V4070   V4070 Datasheet
TDA7389 - TDA7389   TDA7389 Datasheet
PD77630A - PD77630A   PD77630A Datasheet
M3D116 - M3D116   M3D116 Datasheet
LTC1514-3 - LTC1514-3   LTC1514-3 Datasheet
CXT3150 - CXT3150   CXT3150 Datasheet
CS22210 - CS22210   CS22210 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive