SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER Fully inte
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ICS8752I
SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fully integrated LVCMOS outputs, typical output impedance Selectable LVCMOS CLK0 CLK1 inputs redundant clock applications Input/Output frequency range: 18.33MHz 240MHz 3.3V range: 220MHz 480MHz External feedback "zero delay" clock regeneration Cycle-to-cycle jitter: 75ps (maximum), (all outputs same frequency) Output skew: 100ps (maximum) Bank skew: 55ps (maximum) 3.3V 2.5V supply voltage -40°C 85°C ambient operating temperature Functionally compatible with MPC952 some applications
GENERAL DESCRIPTION
ICS8752I voltage, skew LVCMOS clock generator member HiPerClockSthe HiPerClockSfamily High Performance Clock Solutions from ICS. With output frequencies 240MHz, ICS8752I targeted high performance clock applications. Along with fully integrated PLL, ICS8752I contains frequency configurable outputs external feedback input regenerating clocks with "zero delay".
Dual clock inputs, CLK0 CLK1, support redundant clock applications. CLK_SEL input determines which reference clock used. output divider values Bank controlled DIV_SELA0:1, DIV_SELB0:1, respectively. test system debug purposes, PLL_SEL input allows bypassed. When HIGH, MR/nOE input resets internal dividers forces outputs high impedance state. impedance LVCMOS outputs ICS8752I designed drive terminated transmission lines. effective fanout each output doubled utilizing ability each output drive series terminated transmission lines.
BLOCK DIAGRAM
PLL_SEL FB_IN CLK0 CLK1 CLK_SEL DIV_SELA1 DIV_SELA0
PHASE DETECTOR
ASSIGNMENT
PLL_SEL VDDO
DIV_SELB0 DIV_SELB1 DIV_SELA0 DIV_SELA1 MR/nOE CLK0
CLK_SEL VDDA CLK1 VDDO
VDDO VDDO
ICS8752I
FB_IN
DIV_SELB1 DIV_SELB0
MR/nOE
32-Lead LQFP 1.4mm package body package View
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Description
TABLE DESCRIPTIONS
Number Name DIV_SELB0, DIV_SELB1 DIV_SELA0, DIV_SELA1 MR/nOE CLK0 FB_IN CLK_SEL VDDA CLK1 QA0, QA1, QA2, VDDO QB0, QB1, QB2, PLL_SEL Input Input Input Input Power Input Input Power Power Input Output Power Output Unused Input Pullup Pulldown Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Master reset output enable. Resets outputs tristate. Pulldown Enables disables outputs. LVCMOS LVTTL interface levels. Pulldown Clock input. LVCMOS LVTTL interface levels. Power supply ground. Feedback input phase detector generating clocks with "zero delay". LVCMOS LVTTL interface levels. Clock select input. Selects between CLK0 CLK1 phase detector Pulldown reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS LVTTL interface levels. Analog supply pin. Positive supply pins. Pulldown Clock input. LVCMOS LVTTL interface levels. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. Output supply pins. Bank clock outputs. typical output impedance. LVCMOS LVTTL interface levels. connect. Selects between CLK0 CLK1 input dividers. When HIGH selects PLL. When selects CLK0 CLK1. LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDDA, VDD, VDDO 3.465V Test Conditions Minimum Typical Maximum Units
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Inputs DIV_ SELA1 Outputs DIV_ SELA0 DIV_ SELB1 DIV_ SELB0 Hi-Z fVCO/2 fVCO/4 fVCO/6 fVCO/8 fCLK0/2 fCLK0/4 fCLK0/6 fCLK0/8 fCLK1/2 fCLK1/4 fCLK1/6 fCLK1/8 Hi-Z fVCO/4 fVCO/6 fVCO/8 fVCO/12 fCLK0/4 fCLK0/6 fCLK0/8 fCLK0/12 fCLK1/4 fCLK1/6 fCLK1/8 fCLK1/12
TABLE CONTROL INPUT FUNCTION TABLE
MR/nOE
PLL_SEL
CLK_SEL
NOTE: normal operation, MR/nOE LOW. When MR/nOE HIGH, ouputs disabled.
TABLE OUTPUT FREQUENCY W/FB_IN
Inputs FB_IN DIV_ DIV_ SELB1 SELB0 Output Divider Mode (NOTE CLK0, CLK1 (MHz) (NOTE Minimum Maximum DIV_ SELA1 36.66 27.5 18.33 NOTE frequency range 220MHz 480MHz. NOTE output frequency equal CLKx frequency times multiplier output frequency equal CLKx.
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Outputs DIV_ SELA0 Output Divider Mode Multiplier (NOTE 0.667 0.75 1.33
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Inputs CLK0, CLK1 (MHz) (NOTE Minimum Maximum Outputs DIV_ SELB1 DIV_ SELB0 Output Divider Mode Multiplier (NOTE 0.333 0.25 0.167 0.667 0.333 0.75 1.333 0.667
TABLE OUTPUT FREQUENCY W/FB_IN
Output Divider Mode (NOTE
FB_IN
DIV_ SELA1
DIV_ SELA0
(NOTE
36.66
27.5
NOTE frequency range 220MHz 480MHz. NOTE output frequency equal CLKx frequency times multiplier output frequency equal CLKx. NOTE Maximum frequency 240MHz valid 3.3V only.
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
4.6V -0.5V 0.5V -0.5V VDDO 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Positive Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage CLK0, CLK1, FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL CLK0, CLK1, FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL Output High Voltage; NOTE Test Conditions Minimum -0.3 Typical Maximum Units
Input High Current
3.465V
3.465V 3.465V, 3.465V,
Input Current
-150
Output Voltage; NOTE NOTE Outputs terminated with VDDO/2. Parameter Measurement Information Section, "3.3V Output Load Test Circuit".
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum Typical Maximum Units
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Reference Frequency NOTE: Input reference frequency limited fREF divider selection lock range.
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Test Conditions fOUT Output Frequency (PLL Mode) fVCO Lock Range Static Phase Offset; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Time Output Rise Time Output Fall Time Different Frequencies Different Banks Outputs Same Frequency fVCO 400MHz, Feedback Measured rising edge VDDO/2 Measured rising edge VDDO/2 Minimum 36.67 27.5 18.33 Typical Maximum Units
tsk(b) tsk(o)
tjit(cc)
Output Duty Cycle parameters measured fMAX unless noted otherwise. NOTE Defined time difference between input clock average feedback input signal, when locked input reference frequency stable. NOTE Defined skew within bank outputs same supply voltages with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE This parameter defined accordance with JEDEC Standard
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum 2.375 2.375 2.375 Typical Maximum 2.625 2.625 2.625 Units
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Positive Supply Current Analog Supply Current Output Supply Current
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage CLK0, CLK1, FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL CLK0, CLK1, FB_IN, CLK_SEL, DIV_SELA1, DIV_SELA0, DIV_SELB1, DIV_SELB0, MR/nOE PLL_SEL Output High Voltage; NOTE Test Conditions Minimum -0.3 Typical Maximum Units
Input High Current
2.625V
2.625V 2.625V, 2.625V,
Input Current
-150
Output Voltage; NOTE NOTE Outputs terminated with VDDO/2. Parameter Measurement Information Section, "2.5 Output Load Test Circuit".
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol Parameter Input Reference Frequency NOTE: Input reference frequency limited fREF divider selection lock range. Test Conditions Minimum Typical Maximum Units
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum 36.67 27.5 18.33 fVCO 400MHz Feedback Measured rising edge VDDO/2 Measured rising edge VDDO/2 Typical Maximum Units
TABLE CHARACTERISTICS, VDDA VDDO 2.5V±5%, -40°C 85°C
Symbol Parameter
fOUT
Output Frequency (PLL Mode)
fVCO
Lock Range Static Phase Offset; NOTE Bank Skew; NOTE Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Time Output Rise Time Output Fall Time Different Frequencies Different Banks Outputs Same Frequency
tsk(b) tsk(o)
tjit(cc)
Output Duty Cycle parameters measured fMAX unless noted otherwise. NOTE Defined time difference between input clock average feedback input signal, when locked input reference frequency stable. NOTE Defined skew within bank outputs same supply voltages with equal load conditions. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE This parameter defined accordance with JEDEC Standard
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDD, VDDA, VDDO
SCOPE
LVCMOS
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
1.25V±5%
VDD, VDDA, VDDO
SCOPE
LVCMOS
-1.25V±5%
2.5V OUTPUT LOAD TEST CIRCUIT
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
VDDO
VDDO
tsk(o)
OUTPUT SKEW
QAx,
jit(cc) tcycle -tcycle
1000 Cycles
Cycle-to-Cycle Jitter
CLK0, CLK1
FB_IN
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STATIC PHASE OFFSET
tcycle
tcycle
VDD/2
VDD/2
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Clock Inputs Outputs
INPUT
OUTPUT RISE
FALL TIME
QAx,
Pulse Width
PERIOD
tPERIOD
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8752I 1546
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SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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ICS8752I
SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
Marking ICS8752CYI ICS8752CYI Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8752CYI ICS8752CYIT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8752CYI
REV. JUNE 2002
ICS8752I
SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
REVISION HISTORY SHEET
Table
Page
Description Change Characterisitics tables, Static Phase Offset/Test Conditions changed Feedback Feedback Bank Skew should read 55ps Max. from 40ps Max.
Date 6/17/02
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REV. JUNE 2002
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