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HIGH-SPEED 2.5V PRELIMINARY 512/256/128K IDT70T3339/19/99S SYNCHRONOUS DUAL-PORT STATIC WITH 3.3V 2.5V INTERFACE
True Dual-Port memory cells which allow simultaneous access same memory location High-speed data access Commercial: (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz)(max.) Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined Flow-Through output mode Counter enable repeat features Dual chip enables allow depth expansion without additional logic Interrupt Collision Detection Flags Full synchronous operation both ports cycle time, 200MHz operation (14Gbps bandwidth) Fast 3.4ns clock data 1.5ns setup clock 0.5ns hold control, data, address inputs 200MHz
Data input, address, byte enable control registers Self-timed write allows fast cycle time Separate byte controls multiplexed matching compatibility Dual Cycle Deselect (DCD) Pipelined Output Mode 2.5V (±100mV) power supply core LVTTL compatible, selectable 3.3V (±150mV) 2.5V (±100mV) power supply I/Os control signals each port Industrial temperature range (-40°C +85°C) available 166MHz 133MHz Available 256-pin Ball Grid Array (BGA), 144-pin Thin Quad Flatpack (TQFP) 208-pin fine pitch Ball Grid Array (fpBGA) Supports JTAG features compliant with IEEE 1149.1 limited count JTAG, Collision Detection Interrupt supported 144-pin TQFP package
Functional Block Diagram
FT/PIPEL
FT/PIPE
R/WL
R/WR
CE0R CE1R
Dout0-8_L Dout9-17_L
Dout0-8_R Dout9-17_R
FT/PIPE
FT/PIPER
512/256/128K MEMORY ARRAY
I/O0L I/O17L
Din_L
Din_R
I/O17R
18L(1) REPEATL ADSL CNTENL 18R(1)
Counter/ Address Reg.
ADDR_L
ADDR_R
Counter/ Address Reg.
REPEATR ADSR CNTENR
TRST
CE1L
INTERRUPT COLLISION DETECTION LOGIC
JTAG
INTL
COLR INTR
CONTROL LOGIC
5652
NOTES: Address IDT70T3319. Also, Addresses NC's IDT70T3399. sleep mode shuts dynamic inputs, except JTAG inputs, when asserted. static inputs, i.e., PL/FTx OPTx sleep mode pins themselves (ZZx) affected during sleep mode.
NOVEMBER 2003
DSC-5652/3
©2003 Integrated Device Technology, Inc.
IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Description:
IDT70T3339/19/99 high-speed 512/256/128k synchronous Dual-Port RAM. memory array utilizes Dual-Port memory cells allow simultaneous access address from both ports. Registers control, data, address inputs provide minimal setup hold times. timing latitude provided this approach allows systems designed with very short cycle times. With input data register, IDT70T3339/19/99 been optimized applications having unidirectional bidirectional data flow bursts. automatic power down feature, controlled CE1, permits on-chip circuitry each port enter very standby power mode. IDT70T3339/19/99 support operating voltage either 3.3V 2.5V both ports, controllable pins. power supply core device (VDD) 2.5V.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Configuration (3,4,5,6,9)
70T3339/19/99BC BC-256(8)
01/13/03
256-Pin View(9)
17L(2) A14L
A11L
CE1L
CNTENL
INTL
A18L(1) A15L
CE0L R/WL REPEATL
COLL I/O9L
A13L
CLKL ADSL
OPTL
I/O8L
I/O9R
PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR
I/O8R
I/O10R I/O10L
VDDQL
VDDQR
I/O7L I/O7R
I/O11L
I/O11R VDDQL
VDDQR I/O6R
I/O6L
I/O12L VDDQR
VDDQL I/O5L
I/O12R
DDQR
VDDQL
I/O5R
I/O13L I/O14R I/O13R VDDQL
VDDQR I/O4R I/O3R I/O4L
I/O14L VDDQL
VDDQR
I/O3L
I/O15L
I/O15R VDDQR
VDDQL I/O2L
I/O2R
I/O16R I/O16L
VDDQR
VDDQL I/O1R
I/O1L
I/O17R
PIPE/ VDDQR VDDQR DDQL VDDQL VDDQR VDDQR VDDQL VDDQL
I/O0R
COLR I/O17L
A16R
A13R
CLKR ADSR
I/O0L
TRST A18R(1) A15R
A12R
CE0R R/WR REPEATR
OPTR
A17R(2) A14R
A11R
CE1R
CNTENR
5652
NOTES: IDT70T3319 IDT70T3399. IDT70T3399. pins must connected 2.5V power supply. VDDQ pins must connected appropriate power supply: 3.3V that port (2.5V), 2.5V that port (0V). pins must connected ground supply. Package body approximately 17mm 17mm 1.4mm, with 1.0mm ball-pitch. This package code used reference package diagram. This text does indicate orientation actual part-marking. Pins will REFL VREFR respectively future HSTL device.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
PL/FTL A18L(1) A17L(2) A16L A15L A14L A13L A12L A11L A10L CE1L CE0L CLKL R/WL ADSL CNTENL REPEATL
01/07/03
VDDQR I/O9L I/O9R I/O10L I/O10R I/O11L I/O11R VDDQL I/O12L I/O12R VDDQR VDDQL I/O13R I/O13L I/O14R I/O14L VDDQR I/O15R I/O15L I/O16R I/O16L I/O17R I/O17L VDDQL
70T3339/19/99DD DD-144(7) 144-Pin TQFP View(8)
OPTL VDDQR I/O8L I/O8R I/O7L I/O7R I/O6L I/O6R VDDQL I/O5L I/O5R VDDQR VDDQL I/O4R I/O4L I/O3R I/O3L VDDQR I/O2R I/O2L I/O1R I/O1L I/O0R I/O0L VDDQL OPTR
5652
NOTES: IDT70T3319 IDT70T3399. IDT70T3399. pins must connected 2.5V power supply. VDDQ pins must connected appropriate power supply: 3.3V that port (2.5V), 2.5V that port (0V). pins must connected ground supply. Package body approximately 20mm 20mm 1.4mm. This package code used reference package diagram. This text does indicate orientation actual part-marking. limited count, JTAG, Collison Detection Interrupt supported DD-144 package. Pins will VREFL VREFR respectively future HSTL device.
PL/FTR A18R(1) A17R(2) A16R A15R A14R A13R A12R A11R A10R CE1R CE0R CLKR R/WR ADSR CNTENR REPEATR
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
01/13/03
I/O9L
INTL
A16L
A12L
CLKL
CNTEN
COLL
A17L(2)
A13L
CE0L
ADSL
VDDQR
I/O8L
VDDQL
I/O9R
VDDQR PIPE/FTL A18L(1)
A14L
A10L
CE1L
R/WL
I/O8R
I/O10L
A15L
A11L
REPEAT
VDDQL
I/O7L
I/O7R
I/O11L
VDDQR I/O10R
I/O6L
VDDQL I/O11R
I/O6R
VDDQR
I/O12L
VDDQL
I/O5L
VDDQR I/O12R
70T3339/19/99BF BF-208(7) 208-Pin fpBGA View(8)
I/O5R
VDDQL
VDDQR
I/O14R
I/O13R
I/O3R
VDDQL
I/O4R
I/O14L
VDDQR
I/O13L
I/O3L
I/O4L
VDDQL
I/O15R
I/O2R
VDDQR
I/O15L
I/O1R
VDDQL
I/O2L
I/O16R
I/O16L
VDDQR COLR
TRST
A16R
A12R
CLKR CNTEN
I/O1L
I/O17R
A17R(2)
A13R
CE0R
ADSR
VDDQL
I/O0R
VDDQR
I/O17L
VDDQL
A18R(1)
A14R
A10R
CE1R
R/WR
INTR
PIPE/FTR
A15R
A11R
REPEAT
I/O0L
5652
NOTES: IDT70T3319 IDT70T3399. IDT70T3399. pins must connected 2.5V power supply. VDDQ pins must connected appropriate power supply: 3.3V that port (2.5V), 2.5V that port (0V). pins must connected ground supply. Package body approximately 15mm 15mm 1.4mm with 0.8mm ball pitch. This package code used reference package diagram. This text does indicate orientation actual part-marking. Pins will VREFL VREFR respectively future HSTL device.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Names
Left Port CE0L, CE1L R/WL A18L
Right Port CE0R, CE1R R/WR A18R
Names Chip Enables (Input)(7) Read/Write Enable (Input) Output Enable (Input) Address (Input) Data Input/Output Clock (Input) Pipeline/Flow-Through (Input) Address Strobe Enable (Input) Counter Enable (Input) Counter Repeat(3) Upper Byte Enable (I/O9 I/O17)(7) Lower Byte Enable (I/O0 I/O8)(7)
I/O0L I/O17L CLKL PL/FTL ADSL CNTENL REPEATL VDDQL OPTL
I/O0R I/O17R CLKR PL/FTR ADSR CNTENR REPEATR VDDQR OPTR
Power (I/O Bus) (3.3V 2.5V)(1) (Input) Option selecting DDQX(1,2) (Input) Sleep Mode pin(4) (Input) Power (2.5V)(1) (Input) Ground (0V) (Input) Test Data Input Test Data Output Test Logic Clock (10MHz) (Input) Test Mode Select (Input) Reset (Initialize Controller) (Input)
TDO(5)
TRST(5) INTL(5) COLL(5) INTR(5) COLR(5)
Interrupt Flag (Output) Collision Alert (Output)
5652
NOTES: VDD, OPTX, VDDQX must appropriate operating levels prior applying inputs I/Os controls that port. OPTX selects operating voltage levels I/Os controls that port. OPTX (2.5V), then that port's I/Os controls will operate 3.3V levels VDDQX must supplied 3.3V. (0V), then that port's I/Os address controls will operate 2.5V levels VDDQX must supplied 2.5V. pins independent another-both ports operate 3.3V levels, both operate 2.5V levels, either operate 3.3V with other 2.5V. When REPEATX asserted, counter will reset last valid address loaded sleep mode shuts dynamic inputs, except JTAG inputs, when asserted. static inputs, i.e., PL/FTx OPTx sleep mode pins themselves (ZZx) affected during sleep mode. limited count, JTAG, Collision Detection Interrupt supported DD-144 package. Address A18x IDT70T3319. Also, Addresses A18x A17x NC's IDT70T3399. Chip Enables Byte Enables double buffered when PL/FT VIH, i.e., signals take cycles deselect.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Truth Table I-Read/Write Enable Control
Upper Byte I/O9-17 High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z High-Z
(1,2,3,4)
Lower Byte I/O0-8 High-Z High-Z High-Z High-Z DOUT High-Z DOUT High-Z High-Z
MODE Deselected-Power Down Deselected-Power Down Both Bytes Deselected Write Lower Byte Only Write Upper Byte Only Write Both Bytes Read Lower Byte Only Read Upper Byte Only Read Both Bytes Outputs Disabled Sleep Mode
5652
NOTES: VIL, Don't Care. ADS, CNTEN, REPEAT VIH. asynchronous input signals. possible read write combination bytes during given access. representative samples have been illustrated here.
Truth Table II-Address Counter Control
Address Previous Internal Address Internal Address Used L(4) CNTEN
(1,2)
REPEAT(6)
I/O(3) DI/O DI/O(n+1) DI/O(n+1) DI/O(n) External Address Used
MODE
Counter Enabled-Internal Address generation External Address Blocked-Counter disabled reused) Counter last valid load
5652
NOTES: VIH, VIL, Don't Care. Read write operations controlled appropriate setting R/W, CE0, Outputs configured flow-through output mode: outputs pipelined mode data will delayed cycle. REPEAT independent other memory control signals including CE0, CE1, address counter advances CNTEN rising edge CLK, regardless other memory control signals including CE1, When REPEAT asserted, counter will reset last valid address loaded ADS. This value power-up: known location should loaded during initialization desired. subsequent access during operations will update REPEAT address location.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Maximum Operating Temperature Supply Voltage(1)
Grade Commercial Industrial Ambient Temperature +70OC -40OC +85OC 2.5V 100mV 2.5V 100mV
5652
NOTES: This parameter This "instant case temperature.
Recommended Operating Conditions with VDDQ 2.5V
Symbol VDDQ Parameter Core Supply Voltage Supply Voltage Ground Input High Volltage (Address, Control Data Inputs)(3) Input High Voltage JTAG
Min.
Typ.
Max. VDDQ 100mV
Unit
0.2V -0.3
100mV 100mV
5652
Input High Voltage OPT, PIPE/FT Input Voltage Input Voltage OPT, PIPE/FT
-0.3(1)
NOTES: (min.) -1.0V pulse width less than tCYC/2 5ns, whichever less. (max.) VDDQ 1.0V pulse width less than tCYC 5ns, whichever less. select operation 2.5V levels I/Os controls given port, that port must Vss(0V), VDDQX that port must supplied indicated above.
Recommended Operating Conditions with VDDQ 3.3V
Symbol Parameter Core Supply Voltage Supply Voltage Ground Input High Voltage (Address, Control &Data Inputs)(3) Input High Voltage JTAG
Min. 3.15
Typ.
Max. 3.45 VDDQ 150mV(2)
Unit
0.2V -0.3(1) -0.3(1)
100mV(2) 100mV(2)
Input High Voltage OPT, PIPE/FT Input Voltage Input Voltage OPT, PIPE/FT
5652 NOTES: (min.) -1.0V pulse width less than tCYC/2, 5ns, whichever less. (max.) VDDQ 1.0V pulse width less than tCYC/2 5ns, whichever less. select operation 3.3V levels I/Os controls given port, that port must (2.5V), VDDQX that port must supplied indicated above.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM (VDD) VTERM(2) (VDDQ) VTERM(2) (INPUTS I/O's) TBIAS(3) TSTG Rating Terminal Voltage with Respect Terminal Voltage with Respect Input Terminal Voltage with Respect Temperature Under Bias Storage Temperature Junction Temperature Commercial Industrial -0.5 -0.3 VDDQ -0.3 VDDQ +125 +150 +150 Unit
IOUT(For 3.3V) Output Current IOUT(For 2.5V) Output Current
5652
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. This steady-state parameter that applies after power supply reached nominal operating value. Power sequencing necessary; however, voltage Input cannot exceed VDDQ during power supply ramp Ambient Temperature under Bias. Conditions. Chip Deselected.
Capacitance(1)
+25°C, 1.0MHz) PQFP ONLY
Symbol COUT
Parameter Input Capacitance Output Capacitance
Conditions(2) VOUT
Max. 10.5
Unit
5652
NOTES: These parameters determined device characterization, production tested. references interpolated capacitance when input output switch from from COUT also references CI/O.
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VDD 2.5V 100mV)
70T3339/19/99S Symbol |ILI| |ILI| |ILO| (3.3V) (3.3V) (2.5V) (2.5V) Parameter Input Leakage Current(1) JTAG Input Leakage Current Output Leakage Current Output Voltage
(1,3) (1,2)
Test Conditions VDDQ Max., VDDQ Max., VIL, VOUT VDDQ +4mA, VDDQ Min. -4mA, VDDQ Min. +2mA, VDDQ Min. -2mA, VDDQ Min.
Min.
Max.
Unit
5652
Output High Voltage Output Voltage
Output High Voltage
NOTES: VDDQ selectable (3.3V/2.5V) pins. Refer details. Applicable only TMS, TRST inputs. Outputs tested tri-state mode.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range (3)(VDD 2.5V 100mV)
70T3339/19/99 S200 Com'l Only(8) Symbol Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports Level Inputs) Standby Current (One Port Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Sleep Mode Current (Both Ports Level Inputs) CER= VIL, Outputs Disabled, fMAX(1) fMAX(1) CE"A" CE"B" VIH(5) Active Port Outputs Disabled, f=fMAX(1) Both Ports VDDQ 0.2V, VDDQ 0.2V 0.2V, 0(2) CE"A" 0.2V CE"B" VDDQ 0.2V(5) VDDQ 0.2V 0.2V Active Port, Outputs Disabled, fMAX(1) f=fMAX(1) Test Condition Version COM'L COM'L COM'L COM'L COM'L COM'L Typ.(4)
70T3339/19/99 S166 Com'l Ind(7) Typ.(4) Max.
70T3339/19/99 S133 Com'l Typ.(4) Max.
5652
Max.
Unit
ISB1(6)
ISB2(6)
ISB3
ISB4(6)
NOTES: fMAX, address control lines (except Output Enable) cycling maximum frequency clock cycle 1/tCYC, using TEST CONDITIONS". means address, clock, control lines change. Applies only input CMOS level standby. Port either left right port. Port opposite from port "A". 2.5V, 25°C Typ, production tested. DC(f=0) 15mA (Typ). means CE1X means CE0X CE1X 0.2V means CE0X 0.2V CE1X 0.2V 0.2V means CE0X 0.2V CE1X 0.2V represents left port right port. ISB1, ISB2 ISB4 will reach full standby levels (ISB3) appropriate port(s) and/or VIH. 166MHz I-Temp available BF-208 package. 200Mhz available BF-208 DD-144 packages.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Test Conditions (VDDQ 3.3V/2.5V)
Input Pulse Levels (Address Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V/GND 2.4V 3.0V/GND 2.4V 1.5V/1.25V 1.5V/1.25V Figures
5652
DATAOUT
1.5V/1.25 10pF (Tester)
5652
Figure Output Test load.
(Typical,
Capacitance (pF) from Test Load
5652
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Range (Read Write Cycle Timing) (2,3) (VDD 2.5V 100mV, +70°C)
70T3339/19/99 S200 Com'l Only(5) Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tSAD tHAD tSCN tHCN tSRPT tHRPT tOLZ(6) tOHZ tCD1 tCD2 tCKHZ(6) tCKLZ(6) tINS tINR tCOLS tCOLR tZZSC tZZRC
70T3339/19/99 S166 Com'l Ind(4) Min.
70T3339/19/99 S133 Com'l Min.
Parameter Clock Cycle Time (Flow-Through)(1) Clock Cycle Time (Pipelined)(1) Clock High Time (Flow-Through)
Min.
Max.
Max.
Max.
Unit cycles cycles
Clock Time (Flow-Through)(1) Clock High Time (Pipelined)(2) Clock Time (Pipelined)(1) Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Byte Enable Setup Time Byte Enable Hold Time Setup Time Hold Time Input Data Setup Time Input Data Hold Time Setup Time Hold Time CNTEN Setup Time CNTEN Hold Time REPEAT Setup Time REPEAT Hold Time Output Enable Data Valid Output Enable Output Low-Z Output Enable Output High-Z Clock Data Valid (Flow-Through)(1) Clock Data Valid (Pipelined)(1) Data Output Hold After Clock High Clock High Output High-Z Clock High Output Low-Z Interrupt Flag Time Interrupt Flag Reset Time Collision Flag Time Collision Flag Reset Time Sleep Mode Cycles Sleep Mode Recovery Cycles
Port-to-Port Delay tOFS Clock-to-Clock Offset Clock-to-Clock Offset Collision Detection
Please refer Collision Detection Timing Table Page
5652
NOTES: Pipelined output parameters (tCYC2, tCD2) apply either both left right ports when FT/PIPEX (2.5V). Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE (0V) that port. input signals synchronous with respect clock except asynchronous Output Enable (OE), FT/PIPE OPT. FT/PIPE should treated signals, i.e. steady state during operation. These values valid either level VDDQ (3.3V/2.5V). page details selecting desired operating voltage levels each port. 166MHz I-Temp available BF-208 package. 200Mhz available BF-208 DD-144 packages. Guaranteed design (not production tested).
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Read Cycle Pipelined Operation (FT/PIPE'X' VIH)(2)
tCYC2 tCH2
tCL2
Latency) tCD2 tCKLZ
ADDRESS
DATAOUT
tOLZ
tOHZ
5652
Timing Waveform Read Cycle Flow-through Output (FT/PIPE"X" VIL)(2,6)
tCYC1 tCH1
tCL1
tCD1 tCKLZ
ADDRESS
tCKHZ
DATAOUT
tOHZ tOLZ
2(5)
5652
NOTES: asynchronously controlled; other inputs depicted above waveforms synchronous rising clock edge. VIL, CNTEN REPEAT VIH. output disabled (High-Impedance state) VIH, VIL, following next rising edge clock. Refer Truth Table Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. HIGH, then appropriate Byte DATAOUT would disabled (High-Impedance state). denotes Left Right port. diagram with respect that port.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Multi-Device Pipelined Read(1,2)
tCYC2 tCH2 ADDRESS(B1)
CE0(B1)
tCL2
tCD2 tCD2 tCKLZ tCKHZ tCD2 tCKHZ
DATAOUT(B1) ADDRESS(B2)
CE0(B2)
tCD2 tCKHZ tCKLZ tCKLZ
5652
tCD2
DATAOUT(B2)
Timing Waveform Multi-Device Flow-Through Read(1,2)
tCH1 ADDRESS(B1)
tCYC1 tCL1
CE0(B1)
tCD1 tCD1 tCKHZ
tCD1 tCKLZ
tCD1 tCKHZ(1) tCKLZ
DATAOUT(B1)
ADDRESS(B2)
CE0(B2) tCD1 DATAOUT(B2) tCKLZ
tCKHZ
tCD1 tCKLZ
tCKHZ
5652
NOTES: Represents Device Represents Device Each Device consists IDT70T3339/19/99 this waveform, setup depth expansion this example. ADDRESS(B1) ADDRESS(B2) this situation. VIL; CE1(B1), 1(B2), R/W, CNTEN, REPEAT VIH.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Left Port Write Pipelined Right Port Read(1,2,4)
CLK"A" R/W"A
ADDRESS"A"
MATC
MATC
DATAIN"A"
VALID
tCO(3) CLK"B" tCD2 R/W"B" ADDRESS"B"
MATCH
MATC
DATAOUT"B"
VALID
5652 NOTES: VIL; CE1, CNTEN, REPEAT Port "B", which being read from. Port "A", which being written minimum specified, then data from Port read valid until following Port clock cycle (ie, time from write valid read opposite port will tCYC2 tCD2 minimum, then data from Port read available first Port clock cycle (ie, time from write valid read opposite port will CYC2 CD2). timing same Left Right ports. Port either Left Right port. Port opposite Port
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
ADDRESS
MATCH
MATCH
DATAIN
VALID
tCD1 ADDRESS
MATCH
MATCH
tCD1 DATAOUT
VALID VALID
5652
NOTES: VIL; CE1, CNTEN, REPEAT Right Port, which being read from. Left Port, which being written minimum specified, then data from Port read valid until following Port clock cycle (i.e., time from write valid read opposite port will tCYC tCD1). minimum, then data from Port read available first Port clock cycle (i.e., time from write valid read opposite port will CD1). timing same both left right ports. Port either left right port. Port opposite Port "A".
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Pipelined Read-to-Write-to-Read tCYC2 VIL)(2) tCH2 tCL2
ADDRESS
DATAIN
tCD2
tCKHZ
tCKLZ
tCD2
DATAOUT READ
WRITE
READ
5652 NOTES: Output state (High, Low, High-impedance) determined previous cycle control signals. CE0, CE1, CNTEN, REPEAT VIH. "NOP" Operation". Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. "NOP" Operation." Data memory selected address corrupted should re-written guarantee data integrity.
Timing Waveform Pipelined Read-to-Write-to-Read Controlled)(2)
tCH2
tCYC2 tCL2
ADDRESS
DATAIN
tCD2 tOHZ
tCKLZ
tCD2
DATAOUT
NOTES: 5652 Output state (High, Low, High-impedance) determined previous cycle control signals. CE0, VIL; CE1, CNTEN, REPEAT Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. This timing does meet requirements fastest speed grade. This waveform indicates logically could done timing allows.
READ
WRITE
READ
6.42
IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Flow-Through Read-to-Write-to-Read VIL)(2)
tCH1 tCYC1 tCL1
ADDRESS
DATAIN
tCD1 READ
tCD1 tCKHZ
tCD1
tCD1 READ
5652
DATAOUT
tCKLZ WRITE
Timing Waveform Flow-Through Read-to-Write-to-Read Controlled)(2)
tCYC1 tCH1 tCL1
ADDRESS
DATAIN tCD1 tOHZ
tCD1 tCKLZ
tCD1
DATAOUT
READ
WRITE
READ
5652
NOTES: Output state (High, Low, High-impedance) determined previous cycle control signals. CE0, VIL; CE1, CNTEN, REPEAT Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. "NOP" Operation." Data memory selected address corrupted should re-written guarantee data integrity.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Pipelined Read with Address Counter Advance(1)
tCH2 ADDRESS tSAD tHAD
tCYC2 tCL2
tSAD tHAD
CNTEN
tSCN tHCN tCD2
DATAOUT
1(2)
2(2)
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ WITH COUNTER
5652
Timing Waveform Flow-Through Read with Address Counter Advance(1)
tCYC1 tCH1 tCL1 ADDRESS
tSAD tHAD
tSAD tHAD tSCN tHCN
CNTEN
tCD1 DATAOUT Qx(2) READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
5652
3(2)
NOTES: CE0, VIL; CE1, R/W, REPEAT VIH. there address change (loading address) CNTEN (advancing address), i.e. CNTEN VIH, then data output remains constant subsequent clocks.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Timing Waveform Write with Address Counter Advance (Flow-through Pipelined Inputs)(1)
tCH2 ADDRESS tCYC2 tCL2
INTERNAL(3) ADDRESS tSAD tHAD
An(7)
tSCN
CNTEN
DATAIN WRITE EXTERNAL ADDRESS
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5652
Timing Waveform Counter Repeat(2)
tCH2
tCYC2 tCL2
ADDRESS INTERNAL(3) ADDRESS LAST LOAD
CNTEN
LAST
tSAD tHAD tSCN tHCN tSRPT tHRPT
REPEAT
DATAIN
DATAOUT EXECUTE REPEAT
QLAST WRITE LAST ADDRESS READ LAST ADDRESS READ LAST ADDRESS
QLAST+1 READ ADDRESS
READ ADDRESS
NOTES: 5652 REPEAT VIH. VIL; VIH. "Internal Address" equal "External Address" when equals counter output when VIH. Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. Output state (High, Low, High-impedance) determined previous cycle control signals. dead cycle exists during REPEAT operation. READ WRITE cycle coincidental with counter REPEAT cycle: Address loaded last valid load will accessed. Extra cycles shown here simply clarification. more information REPEAT function refer Truth Table CNTEN advances Internal Address from `An' +1'. transition shown indicates time required counter advance. +1'Address written during this cycle.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Waveform Interrupt Timing
CLKL R/WL ADDRESS
L(3)
7FFFF
L(1)
tINS INTR tINR CER(1)
CLKR
R/WR ADDRESSR(3)
7FFFF
5652
NOTES: timing same Left Right ports. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
Truth Table Interrupt Flag
Left Port CLKL R/WL
Right Port A18L-A0L
(3,4,5)
INTL
CLKR
R/WR
CER(2)
A18R-A0R(3,4,5) 7FFFF 7FFFE
INTR
Function Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
5652
7FFFF 7FFFE
NOTES: INTR must initialized power-up Resetting flags. VIH. synchronous with respect clock need valid set-up hold times. A18X IDT70T3319, therefore Interrupt Addresses 3FFFF 3FFFE. A18X A17X NC's IDT70T3399, therefore Interrupt Addresses 1FFFF 1FFFE. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Waveform Collision Timing (1,2) Both Ports Writing with Left Port Clock Leading
CLKL tOFS ADDRESSL
tCOLS COLL
tCOLR
tOFS CLKR
ADDRESSR
tCOLS COLR
tCOLR
5652
NOTES: VIL, VIH. reading port, Don't care Collision Detection Logic. Please refer Truth Table specific cases. Leading Port Output flag might output 3tCYC tCOLS after Address match. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
Collision Detection Timing(3,4)
Cycle Time Region (ns) 7.5ns
tOFS (ns)
Region (ns) 2.81 3.81 5.31
5652
NOTES: Region Both ports show collision after cycle Addresses etc. Region Leading port shows collision after cycle addresses etc. while trailing port shows collision after cycle addresses etc. production units tested midpoint each region. These ranges based characterization typical device.
Truth Table Collision Detection Flag
Left Port CLKL R/WL(1) CEL(1) A18L-A0L(2) MATCH MATCH MATCH MATCH COLL CLKR R/WR(1) Right Port R(1) A18R-A0R(2) MATCH MATCH MATCH MATCH COLR Function Both ports reading. valid collision. flag output either port. Left port reading, Right port writing. Valid collision, flag output Left port. Right port reading, Left port writing. Valid collision, flag output Right port. Both ports writing. Valid collision. Flag output both ports.
5652
NOTES: VIH. synchronous with respect clock need valid set-up hold times. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
Timing Waveform Sleep Mode (1,2)
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PRELIMINARY Industrial Commercial Temperature Ranges
NOTES: timing same Left Right ports. deactivated (CE0 VIH) three cycles prior asserting (ZZx VIH) held cycles after asserting (ZZx VIH). deactivated (CE0 VIH) cycles prior de-asserting (ZZx VIL) held three cycles after de-asserting (ZZx VIL).
IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Functional Description
IDT70T3339/19/99 provides true synchronous Dual-Port Static interface. Registered inputs provide minimal set-up hold times address, data, critical control inputs. internal registers clocked rising edge clock signal, however, self-timed internal write pulse width independent cycle time. asynchronous output enable provided ease asynchronous interfacing. Counter enable inputs also provided stall operation address counters fast interleaved memory applications. HIGH clock cycle will power down internal circuitry reduce static power consumption. Multiple chip enables allow easier banking multiple IDT70T3339/19/99s depth expansion configurations. cycles required with HIGH re-activate outputs.
Interrupts
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) asserted when right port writes memory location 7FFFE (HEX), where write defined R/WR Truth Table. left port clears interrupt through access address location 7FFFE when R/WL VIH. Likewise, right port interrupt flag (INT asserted when left port writes memory location 7FFFF (HEX) clear interrupt flag (INTR), right port must read memory location 7FFFF (3FFFF 3FFFE IDT70T3319 1FFFF 1FFFE IDT70T3399). message bits) 7FFFE 7FFFF (3FFFF 3FFFE IDT70T3319 1FFFF 1FFFE IDT70T3399) user-defined since addressable SRAM location. interrupt function used, address locations 7FFFE 7FFFF (3FFFF 3FFFE IDT70T3319 1FFFF 1FFFE IDT70T3399) used mail boxes, part random access memory. Refer Truth Table interrupt operation.
flag. third collision will generate alert flag appropriate. event that user initiates burst access both ports with same starting address both ports both ports writing during each access (i.e., imposes long string collisions contiguous clock cycles), alert flag will asserted cleared every other cycle. Please refer Collision Detection timing waveform page Collision detection IDT70T3339/19/99 represents significant advance functionality over current sync multi-ports, which have such capability. addition this functionality IDT70T3339/19/99 sustains features bandwidth flexibility. collision detection function very useful case bursting data, string accesses made sequential addresses, that indicates problem within burst, giving user option either repeating burst continuing watch alert flag whether number collisions increases above acceptable threshold value. Offering this function chip also allows users reduce their need arbitration circuits, typically done CPLD's FPGA's. This reduces board space design complexity, gives user more flexibility developing solution.
Sleep Mode
IDT70T3339/19/99 equipped with optional sleep power mode both ports. sleep mode both ports asynchronous active high. During normal operation, pulled low. When pulled high, port will enter sleep mode where will meet lowest possible power conditions. sleep mode timing diagram shows modes operation: Normal Operation, Read/Write Allowed Sleep Mode. normal operation inputs must meet setup hold times prior sleep after recovering from sleep. Clocks must also meet cycle high times during these periods. Three cycles prior asserting (ZZx VIH) three cycles after de-asserting (ZZx VIL), reads writes allowed. write read operation occurs during these periods, memory array corrupted. Validity data from cannot guaranteed immediately after asserted (prior being sleep). During sleep mode automatically deselects itself. disconnects internal clock buffer. external clock continue without impacting RAMs sleep current (IZZ). outputs will remain high-Z state while sleep mode. inputs allowed toggle. will selected will perform reads writes.
Collision Detection
Collision defined overlap access between ports resulting potential either reading writing incorrect data specific address. specific cases: Both ports reading data corrupted, lost, incorrectly output, collision flag output either port. port writing, other port reading result write will still valid. However, reading port might capture data that state transition hence reading port's collision flag output. Both ports writing there risk that ports will interfere with each other, data stored memory will valid write from either port essentially random combination two). Therefore, collision flag output both ports. Please refer Truth Table above cases. alert flag (COLX) asserted rising clock edge affected port following collision, remains cycle. Please refer Collision DetectionTiming table Page During that next cycle, internal arbitration engaged resetting alert flag (this avoids specific requirement part user reset alert flag). collisions occur subsequent clock cycles, second collision generate appropriate alert
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Depth Width Expansion
IDT70T3339/19/99 features dual chip enables (refer Truth Table order facilitate rapid simple depth expansion with requirements external logic. Figure illustrates control various chip enables order expand devices depth. IDT70T3339/19/99 also used applications requiring expanded width, indicated Figure Through combining control signals, devices grouped necessary accommodate applications needing 36-bits wider.
A19/A18/A17(1)
IDT70T3339/19/99
IDT70T3339/19/99
Control Inputs
Control Inputs
IDT70T3339/19/99
IDT70T3339/19/99
R/W, CLK, ADS, REPEAT, CNTEN
Control Inputs
Control Inputs
Figure Depth Width Expansion with IDT70T3339/19/99
5652
NOTE: IDT70T3339, IDT70T3319, IDT70T3399.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
JTAG Timing Specifications
tJCYC
tJCL
tJCH
Device Inputs(1)/ TDI/TMS Device Outputs(2)/ TRST
5652
tJDC
tJRSR
tJCD
tJRST
NOTES: Device inputs device inputs except TDI, TMS, TRST. Device outputs device outputs except TDO.
JTAG Electrical Characteristics (1,2,3,4)
70T3339/19/99 Symbol tJCYC tJCH tJCL tJRST tJRSR tJCD tJDC Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min.
Max.
Units
5652
NOTES: Guaranteed design. 30pF loading external output signals. Refer Electrical Test Conditions stated earlier this document. JTAG operations occur speed (10MHz). base device speed specified this datasheet.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Identification Register Definitions
Instruction Field Revision Number (31:28) Device (27:12) JEDEC (11:1) Register Indicator (Bit Value 0x333(1) 0x33 Reserved version number Defines part number Allows unique identification device vendor Indicates presence register
5652
Description
NOTE: Device IDT70T3319 0x334. Device IDT70T3399 0x335.
Scan Register Sizes
Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Size Note
5652
System Interface Parameters
Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0100 Description Forces contents boundary scan cells onto device outputs (1). Places boundary scan register (BSR) between TDO. Places bypass register (BYR) between TDO. Loads register (IDR) with vendor code places register between TDO. Places bypass register (BYR) between TDO. Forces device output drivers High-Z state except COLx INTx outputs. Uses BYR. Forces contents boundary scan cells onto device outputs. Places bypass register (BYR) between TDO. Places boundary scan register (BSR) between TDO. SAMPLE allows data from device inputs captured boundary scan cells shifted serially through TDO. PRELOAD allows data input serially into boundary scan cells TDI. Several combinations reserved. codes other than those identified above. internal only.
5652
HIGHZ CLAMP SAMPLE/PRELOAD
0011 0001
RESERVED PRIVATE
0101, 0111, 1000, 1001, 1010, 1011, 1100 0110,1110,1101
NOTES: Device outputs device outputs except TDO. Device inputs device inputs except TDI, TMS, TRST. Boundary Scan Descriptive Language (BSDL) file this device available website (www.idt.com), contacting your local sales representative.
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IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Ordering Information
XXXXX Device Type Power Speed Package Process/ Temperature Range
Blank
Commercial (0°C +70°C) Industrial (-40°C +85°C) 256-pin (BC-256) 144-pin TQFP (DD-144) 208-pin fpBGA (BF-208)
Commercial Only(2) Commercial Industrial(1) Commercial Industrial
Speed Megahertz
Standard Power
70T3339 9Mbit (512K 18-Bit) Synchronous Dual-Port 70T3319 4Mbit (256K 18-Bit) Synchronous Dual-Port 70T3399 2Mbit (128K 18-Bit) Synchronous Dual-Port
NOTES: 166MHz I-Temp available BF-208 package. 200Mhz available BF-208 DD-144 packages.
5652
Clock Solution IDT70T3339/19/99 Dual-Port
Dual-Port Specitications Dual-Port Part Number Voltage Input Capacitance Clock Specifications Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance Clock Device Non-PLL Clock Device 5T9010 5T905, 5T9050 5T907, 5T9070
5652
70T3339/19/99
LVTTL
75ps
5T2010
Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions products that early release.
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-5166 fax: 408-492-8674 www.idt.com
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Tech Support: 831-754-4613 DualPortHelp@idt.com
logo registered trademark Integrated Device Technology, Inc.
IDT70T3339/19/99S High-Speed 2.5V 512/256/128K Dual-Port Static
PRELIMINARY Industrial Commercial Temperature Ranges
Datasheet Document History:
01/20/03: 04/25/03: 11/11/03: Initial Datasheet Page Added Capacitance Derating drawing Page Changed tINS tINR specs Electrical Characteristics table Page Updated power numbers Electrical Characteristics table Page Added tOFS symbol parameter Electrical Characteristics table Page Updated Collision Timing waveform Page Added Collision Detection Timing table footnotes Page Updated HIGHZ function System Interface Parameters table Page Added Clock Solution table
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