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Pentium® Processor Power
Available Supports Intel architecture with dynamic execution Integrated primary 16-Kbyte instruction cache 16-Kbyte write back data cache Integrated 256-Kbyte second-level cache packaging technology Supports thin form factor designs Exposed enables more efficient heat dissipation
Fully compatible with previous Intel microprocessors Binary compatible with applications Support MMXtechnology Power Management Features Quick Start Deep Sleep modes provide extremely power dissipation Low-Power GTL+ processor system interface Integrated math co-processor Integrated thermal diode
Intel® Pentium® Processor Power introduces higher level performance today's applied computing environment, including multimedia enhancements improved Internet communications capabilities. built-in power management capabilities, Pentium Processor Power takes advantage software designed Intel's MMXtechnology unleash enhanced color, smoother graphics other multimedia communications enhancements.
Order Number: 273268-001 September, 1999
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Processor Power contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product rder. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 1999 *Third-party brands names property their respective owners.
Pentium® Processor Power
Contents
Introduction
Overview Terminology. References Features Pentium® Processor Power.10 2.1.1 Integrated Cache.10 2.1.2 Signal Differences from Mini-Cartridge Processors Power Management 2.2.1 Clock Control Architecture.11 2.2.2 Normal State 2.2.3 Auto Halt State 2.2.4 Stop Grant State.13 2.2.5 Quick Start State 2.2.6 Halt/Grant Snoop State 2.2.7 Sleep State.14 2.2.8 Deep Sleep State 2.2.9 Operating System Implications Quick Start Sleep States Power GTL+ 2.3.1 GTL+ Signals.16 Pentium® Processor Power CPUID.16 Processor System Signals 3.1.1 Power Sequencing Requirements.18 3.1.2 Test Access Port (TAP) Connection.18 3.1.3 Catastrophic Thermal Protection.19 3.1.4 Unused Signals 3.1.5 Signal State Power States 3.1.5.1 System Signals 3.1.5.2 CMOS Open-Drain Signals 3.1.5.3 Other Signals.19 Power Supply Requirements.20 3.2.1 Decoupling Recommendations 3.2.2 Voltage Planes System Clock Processor Clocking Maximum Ratings.21 Specifications Specifications 3.6.1 System Bus, Clock, APIC, TAP, CMOS Open-Drain Specifications System Clock (BCLK) Signal Quality Specifications Power GTL+ Signal Quality Specifications Non-Low Power GTL+ Signal Quality Specifications
Pentium® Processor Power Features
Electrical Specifications
System Signal Simulations
Pentium® Processor Power
4.3.1 4.3.2 4.3.3
Overshoot Undershoot Guidelines Ringback Specification. Settling Limit Guideline
Mechanical Specifications
Dimensions Signal Listings Thermal Diode. Case Temperature Description 7.1.1 Quick Start Enable 7.1.2 System Frequency 7.1.3 APIC Disable Clock Frequencies Ratios Alphabetical Signal Reference 8.1.1 A[35:3]# (I/O Power GTL+). 8.1.2 A20M# 2.5V Tolerant). 8.1.3 ADS# (I/O Power GTL+). 8.1.4 AERR# (I/O Power GTL+) 8.1.5 AP[1:0]# (I/O Power GTL+) 8.1.6 BCLK 2.5V Tolerant). 8.1.7 BERR# (I/O Power GTL+) 8.1.8 BINIT# (I/O Power GTL+). 8.1.9 BNR# (I/O Power GTL+) 8.1.10 BP[3:2]# (I/O Power GTL+) 8.1.11 BPM[1:0]# (I/O Power GTL+) 8.1.12 BPRI# Power GTL+) 8.1.13 BREQ0# (I/O Power GTL+). 8.1.14 BSEL Tolerant) 8.1.15 D[63:0]# (I/O Power GTL+) 8.1.16 DBSY# (I/O Power GTL+) 8.1.17 DEFER# Power GTL+). 8.1.18 DEP[7:0]# (I/O Power GTL+). 8.1.19 DRDY# (I/O Power GTL+). 8.1.20 EDGCTRLN (Analog) 8.1.21 FERR# Tolerant Open-drain). 8.1.22 FLUSH# Tolerant) 8.1.23 HIT# (I/O Power GTL+), HITM# (I/O Power GTL+) 8.1.24 IERR# Tolerant Open-drain). 8.1.25 IGNNE# Tolerant). 8.1.26 INIT# Tolerant) 8.1.27 INTR Tolerant). 8.1.28 LOCK# (I/O Power GTL+) 8.1.29 Tolerant) 8.1.30 PICCLK Tolerant)
Thermal Specifications
Processor Initialization Configuration.
Processor Interface
Pentium® Processor Power
8.1.31 PICD[1:0] (I/O Tolerant Open-drain) 8.1.32 PRDY# Power GTL+) 8.1.33 PREQ# Tolerant) 8.1.34 PWRGOOD Tolerant) 8.1.35 REQ[4:0]# (I/O Power GTL+) 8.1.36 RESET# Power GTL+) 8.1.37 (I/O Power GTL+) 8.1.38 RS[2:0]# Power GTL+) 8.1.39 RSP# Power GTL+).59 8.1.40 SLP# 2.5V Tolerant) 8.1.41 SMI# Tolerant).60 8.1.42 STPCLK# Tolerant) 8.1.43 Tolerant) 8.1.44 Tolerant) 8.1.45 Tolerant Open-drain).60 8.1.46 THERMDA, THERMDC (Analog) 8.1.47 Tolerant).60 8.1.48 TRDY# Power GTL+) 8.1.49 TRST# Tolerant).61 Signal Summaries
Figures
Components Pentium® Processor Power-based System Clock Control States.11 Ramp Rate Requirement.18 Filter Generic Clock Waveform Valid Delay Timings.28 Setup Hold Timings Cold/Warm Reset Configuration Timings Power-On Reset Timings Test Timings (Boundary Scan).30 Test Reset Timings Quick Start/Deep Sleep Timing Stop Grant/Sleep/Deep Sleep Timing BCLK Generic Clock Waveform High, Power GTL+ Receiver Ringback Tolerance Non-GTL+ Overshoot/Undershoot Ringback Surface-Mount BGA1 Package-Top Side View.38 Surface-Mount BGA1 Package-Bottom View.38 Ball View Technique Measuring Case Temperature.50 PWRGOOD Relationship Power-On
Pentium® Processor Power
Tables
Pentium® Processor Power Signals. Removed Mini-Cartridge Processor Signals Clock State Characteristics Pentium® Processor Power CPUID Pentium® Processor Power CPUID Cache Descriptors System Signal Groups Recommended Resistors Open Drain Signals Filter Specifications Core Frequency System Ratio Configuration Pentium® Processor Power Absolute Maximum Ratings. Pentium® Processor Power Specifications Power GTL+ Signal Group Specifications Power GTL+ Specifications. Clock, APIC, TAP, CMOS Open-Drain Signal Group Specifications System Clock Specifications1. Valid Pentium® Processor Power Frequencies. Power GTL+ Signal Groups Specifications CMOS Open-Drain Signal Groups Specifications Reset Configuration Specifications Signal Specifications Quick Start/Deep Sleep Specifications Stop Grant/Sleep/Deep Sleep Specifications. BCLK Signal Quality Specifications Power GTL+ Signal Group Ringback Specification Signal Ringback Specifications Non-GTL+ Signals Surface-Mount BGA1 Package Specifications. Signal Listing Order Ball Number Signal Listing Order Signal Name Voltage No-Connect Ball Locations Pentium® Processor Power Specifications Thermal Diode Interface. Thermal Diode Specifications Input Signals Output Signals. Input/Output Signals (Single Driver). Input/Output Signals (Multiple Driver)
Pentium® Processor Power
Introduction
Pentium® Processor Power offered MHz, with system speed MHz. Pentium Processor Power integrated cache 64-bit high performance system bus. integrated cache designed help improve performance; complements system providing critical data faster reducing total system power consumption. Pentium Processor Power's 64-bit wide Power Gunning Transceiver Logic (GTL+) system compatible with 440BX AGPset provides glueless, point-to-point interface bridge/memory controller. Figure shows components Pentium Processor Power-based system components connect processor.
Figure Components Pentium® Processor Power-based System
Thermal Sensor
Pentium® Processor
System CMOS/Open Drain
SMBus
443BX North Bridge
DRAM
System Controller
PIIX4E South Bridge
ISA/EIO
Pentium® Processor Power
Overview
Performance Applied Computing applications
Supports Intel Architecture with Dynamic Execution Supports Intel Architecture MMXtechnology Integrated Intel Floating-Point Unit compatible with IEEE
Integrated primary (L1) instruction data caches
4-way associative, 32-byte line size, line sector 16-Kbyte instruction cache 16-Kbyte writeback data cache Cacheable range programmable processor programmable registers
Integrated second level (L2) cache
4-way set-associative, 32-byte line size, line sector Operates full core speed 256-Kbyte, protected cache data array Gbyte cacheable range
Power GTL+ system interface
64-bit data bus, 66-MHz operation Uni-processor, loads only (processor bridge/memory controller) Short trace length capacitance allows single-ended termination
Voltage reduction technology Pentium processor clock control
Quick Start power, exit latency clock "throttling" Deep Sleep mode extremely power dissipation
Thermal diode measuring processor temperature
Terminology
this document symbol following signal name indicates that signal active low. This means that when signal asserted (based name signal) electrical state. Otherwise, signals driven electrical high state when they asserted. state machine diagrams, signal name condition indicates condition that signal being asserted. signal name preceded symbol, then indicates condition that signal being asserted. example, condition `!STPCLK# equivalent `the active signal STPCLK# unasserted (i.e., condition true.' symbols refer respectively electrical electrical high signal levels. symbols refer respectively logical logical high signal levels. example, BD[3:0] `1010' `HLHL' refers hexadecimal `A', D[3:0]# `1010' `LHLH' also refers hexadecimal `A'.
Pentium® Processor Power
References
Document Order Number 243335 243502 243190 243191 243192 243672 243671
Pentium Processor MHz, MHz, datasheet Pentium Processor Developer's Manual Intel Architecture Software Developer's Manual Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide Mobile Pentium® Processor System Layout Guideline Mobile Pentium Processor Mechanical Thermal User's Guide
Pentium® Processor Power
Pentium® Processor Power Features
Features Pentium® Processor Power
features include integrated cache, various signal differences from minicartridge processors.
2.1.1
Integrated Cache
Pentium Processor Power 256-Kbyte cache integrated onto processor die. cache 4-way associative runs speed processor core. cache cache Gbytes memory.
2.1.2
Table
Signal Differences from Mini-Cartridge Processors
Pentium® Processor Power Signals
Signals EDGCTRLN BSEL TESTHI, TESTHI3 TESTHI2 TESTLO THERMDA, THERMDC PLL1, PLL2 VREF Purpose GTL+ output buffer edge rate control signals Connect (same RSVD signals mini-cartridge) speed select Testability signals. Pull-up VCC. Testability signals. Pull-up VCCP. Testability signals. Connect VSS. Thermal diode analog power supply GTL+ reference voltage
Table
Removed Mini-Cartridge Processor Signals
Signals SMBALERT#, SMBCLK, SMBDATA VCC_S, VCCP_S, VSS_S VCC3 VID[3:0] Purpose SMBus interface thermal sensor Voltage sense signals supply external cache components Voltage identification
Pentium® Processor Power
2.2.1
Power Management
Clock Control Architecture
Pentium Processor Power clock control architecture (Figure been optimized leading edge "Deep Green" designs.
Figure Clock Control States
STPCLK# Normal HS=false (!STPCLK# !HS) RESET# halt cycle halt break STPCLK# !QSE (!STPCLK# !HS) stop break !STPCLK# Auto Halt HS=true STPCLK# !STPCLK# BCLK stopped BCLK Quick Start
Snoop serviced
Snoop occurs
Deep Sleep
Snoop occurs Snoop serviced
STPCLK# !QSE Snoop occurs Stop Grant Snoop serviced SLP# !SLP# RESET#
HALT/Grant Snoop
BCLK stopped
BCLK !QSE
Sleep
V0001-00
NOTES: halt break A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI# instruction executed Processor Halt State Quick Start State Enabled Stop Grant Acknowledge cycle issued Stop break BINIT#, FLUSH#, RESET#
Pentium® Processor Power
Auto Halt state provides power clock state that controlled through software execution instruction. Quick Start state provides very power, exit latency clock state that used hardware controlled "idle" computer states. Deep Sleep state provides extremely power state that used "Power-on Suspend" computer states, which alternative shutting processor's power. Compared Pentium processor exit latency exit latency Deep Sleep state been reduced Pentium Processor Power. Performing state transitions shown Figure neither recommended supported. clock control architecture consists seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start, HALT/Grant Snoop, Sleep Deep Sleep states. Stop Grant Quick Start clock states mutually exclusive; strapping option signal A15# chooses which state entered when STPCLK# signal asserted. Strapping A15# signal ground Reset enables Quick Start state; otherwise, asserting STPCLK# signal puts processor into Stop Grant state. Stop Grant state higher power level than Quick Start state designed platforms. Quick Start state much lower power level, only used uniprocessor platforms. Table provides clock state characteristics (power numbers based estimates Pentium Processor Power running MHz), which described detail following sections.
2.2.2
Normal State
Normal state processor normal operating mode which processor's internal clock running processor actively executing instructions.
2.2.3
Auto Halt State
This power mode entered processor through execution instruction. power level this mode similar Stop Grant state. transition Normal state made halt break event (one following signals going active: NMI, INTR, BINIT#, INIT#, RESET#, FLUSH# SMI#). Asserting STPCLK# signal while Auto Halt state causes processor transition Stop Grant Quick Start state, where Stop Grant Acknowledge cycle issued. Deasserting STPCLK# causes processor return Auto Halt state without issuing Halt cycle. SMI# interrupt recognized Auto Halt state. return from System Management Interrupt (SMI) handler either Normal state Auto Halt state. Intel® Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. Halt cycle issued when returning Auto Halt state from System Management Mode (SMM). FLUSH# signal serviced Auto Halt state. After on-chip off-chip caches have been flushed, processor returns Auto Halt state without issuing Halt cycle. Transitions A20M# PREQ# signals recognized while Auto Halt state.
Pentium® Processor Power
Table
Clock State Characteristics
Clock State Normal Auto Halt Stop Grant Approximately clocks Approximately clocks Through snoop, HALT/ Grant Snoop state: immediate through STPCLK#, Normal state: clocks clocks after snoop activity. Stop Grant state clocks Exit Latency Power Varies 1.25 1.25 Snooping? System Uses Normal program execution controlled entry idle mode controlled entry/exit power throttling controlled entry/exit power throttling Supports snooping power states controlled entry/exit desktop idle mode support controlled entry/exit powered-on suspend support
Quick Start
HALT/Grant Snoop Sleep Deep Sleep NOTE:
specified
100% tested. Specified design/characterization.
2.2.4
Stop Grant State
processor enters this mode with assertion STPCLK# signal when configured Stop Grant state (via A15# strapping option). processor still able respond snoop requests latch interrupts. Latched interrupts will serviced when processor returns Normal state. Only occurrence each interrupt event will latched. transition back Normal state made deassertion STPCLK# signal, occurrence stop break event BINIT#, FLUSH# RESET# assertion). processor returns Stop Grant state after completion BINIT# initialization unless STPCLK# been de-asserted. RESET# assertion causes processor immediately initialize itself, processor stays Stop Grant state after initialization until STPCLK# deasserted. When FLUSH# signal asserted, processor flushes on-chip caches returns Stop Grant state. transition Sleep state made assertion SLP# signal. While Stop Grant state, assertions SMI#, INIT#, INTR latched processor. These latched events serviced until processor returns Normal state. Only each event recognized upon return Normal state.
2.2.5
Quick Start State
This mode entered processor with assertion STPCLK# signal when configured Quick Start state (via A15# strapping option). Quick Start state processor only capable acting snoop transactions generated system priority device. Because snooping behavior, Quick Start only used Uniprocessor (UP) configuration.
Pentium® Processor Power
transition Deep Sleep state made stopping clock input processor. transition back Normal state (from Quick Start state) made only STPCLK# signal deasserted. While this state processor limited ability respond input. incapable latching interrupts, servicing snoop transactions from symmetric masters responding FLUSH# BINIT# assertions. While processor Quick Start state, will respond properly input signal other than STPCLK#, RESET# BPRI#. other input signal changes, behavior processor will unpredictable. serial interrupt messages begin progress while processor Quick Start state. RESET# assertion causes processor immediately initialize itself, processor stays Quick Start state after initialization until STPCLK# deasserted.
2.2.6
Halt/Grant Snoop State
processor responds snoop transactions system while Auto Halt, Stop Grant Quick Start state. When snoop transaction presented system processor enters HALT/Grant Snoop state. processor remains this state until snoop been serviced system quiet. After snoop been serviced, processor returns previous state. When HALT/Grant Snoop state entered from Quick Start state, input signal restrictions Quick Start state still apply HALT/Grant Snoop state, except those signal transitions that required perform snoop.
2.2.7
Sleep State
Sleep state very power state which processor maintains context phase-locked loop (PLL) maintains phase lock. Sleep state only entered from Stop Grant state. After entering Stop Grant state, SLP# signal asserted, causing processor enter Sleep state. SLP# signal recognized Normal Auto Halt states. processor reset RESET# signal while Sleep state. RESET# driven active while processor Sleep state then SLP# STPCLK# must immediately driven inactive ensure that processor correctly initializes itself. Input signals (other than RESET#) change while processor Sleep state transitioning into Sleep state. Input signal changes these times will cause unpredictable behavior. Thus, processor incapable snooping latching events Sleep state. While Sleep state, processor enter lowest power state, Deep Sleep state. Removing processor's input clock puts processor Deep Sleep state. PICCLK removed Sleep state.
2.2.8
Deep Sleep State
Deep Sleep state lowest power mode processor enter while maintaining context. Deep Sleep state entered stopping BCLK input processor, while Sleep Quick Start state. proper operation, BCLK input should stopped state.
Pentium® Processor Power
processor returns Sleep Quick Start state from Deep Sleep state when BCLK input restarted. lock latency, there delay after clocks have started before this state transition happens. PICCLK removed Deep Sleep state. PICCLK should designed turn when BCLK turns when transitioning Deep Sleep state. input signal restrictions Deep Sleep state same Sleep state, except that RESET# assertion will result unpredictable behavior.
2.2.9
Operating System Implications Quick Start Sleep States
There number architectural features Pentium Processor Power that available when Quick Start state enabled function Quick Start Sleep state they Stop Grant state. These features part time-stamp counter performance monitor counters. time-stamp counter performance monitor counters guaranteed count Quick Start Sleep states.
Power GTL+
Pentium Processor Power system signals variation voltage swing signaling technology. Pentium Processor Power system specification similar Pentium processor system specification, which itself version with enhanced noise margins less ringing. Pentium Processor Power system specification reduces system cost power consumption raising termination voltage termination resistance changing termination from dual ended single ended. Because specification different from standard specification from Pentium processor GTL+ specification, referred Power GTL+. Pentium processor GTL+ system depends incident wave switching uses flight time timing calculations GTL+ signals. Power GTL+ system short lightly loaded. With Power GTL+ signals, timing calculations based capacitive derating. Analog signal simulation system including trace lengths highly recommended ensure that there significant transmission line effects. Contact your field sales representative receive IBIS models Pentium Processor Power. GTL+ system Pentium processor designed support high-speed data transfers with multiple loads long that behaves like transmission line. However, mobile system, system only loads (the processor chipset) traces short enough that transmission line effects significant. possible change layout termination system take advantage mobile environment using same GTL+ buffers. benefit that reduces number terminating resistors half substantially reduces power dissipation system bus. Power GTL+ uses GTL+ buffers only loads allowed. trace length limited terminated only. Since system small lightly loaded, behaves like capacitor, GTL+ buffers behave like high-speed open-drain buffers. With 66-MHz frequency, pull-up would been increased from processor eliminate need power plane. termination resistors used rather than then more power will dissipated termination resistors. termination recommended conserve power. Refer Pentium® Processor Power System Layout Guideline (order number 243672) details laying Power GTL+ system bus.
Pentium® Processor Power
2.3.1
GTL+ Signals
signals system potentially meet Power GTL+ layout requirements: PRDY# RESET#. These signals connect debug port might meet maximum length requirements. PRDY# RESET# meet layout requirements Power GTL+, then they must terminated using dual-ended termination Higher resistor values used simulations show that signal quality specifications "System Signal Simulations" page met.
Pentium® Processor Power CPUID
Pentium Processor Power same CPUID family model number some Celeronprocessors. Pentium Processor Power distinguished from these Celeron processors looking stepping number CPUID cache descriptor information. Pentium Processor Power stepping number range cache descriptor 042H (256-Kbyte cache). stepping number less than cache descriptor 042H processor Celeron processor. cache must properly initialized cache descriptor information correct. After power-on RESET, when CPUID instruction executed, register contains values shown Table After cache initialized, CPUID cache/TLB descriptors will values shown Table
Table
Pentium® Processor Power CPUID
Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0]
Table
Pentium® Processor Power CPUID Cache Descriptors
Cache Descriptors 01H, 02H, 03H, 04H, 08H, 0CH,
Pentium® Processor Power
Electrical Specifications
Processor System Signals
Table lists processor system signals type. Power GTL+ signals synchronous with BCLK signal. signals synchronous with signal except TRST#. CMOS input signals applied asynchronously.
Table
System Signal Groups
Group Name Power GTL+ Input Power GTL+ Output Power GTL+ CMOS Input Open Drain Output Clock APIC Clock APIC
Signals BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, BSEL, A20M#, FLUSH#, IGNNE#, INIT#, INTR, NMI, PREQ#, PWRGOOD, SLP#, SMI#, STPCLK# FERR#, IERR# BCLK PICCLK PICD[1:0] THERMDA, THERMDC TCK, TDI, TMS, TRST# EDGECTRLN, PLL1, PLL2, TESTHI, TESTHI2, TESTHI3, TESTLO, VCC, VCCP, VREF,
Thermal Diode Input Output Power/Other
NOTE: "Alphabetical Signal Reference" page information PWRGOOD signal. These signals tolerant only. Table recommended pull-up resistor. power supply core logic. PLL1 PLL2 power supply analog section. VCCP power supply CMOS voltage references. VREF voltage reference Power GTL+ input buffers. system ground.
CMOS, Clock, APIC inputs driven from ground outputs open drain should pulled using resistors with values shown Table open drain drivers used input signals, then they should also pulled using resistors with values shown Table
Pentium® Processor Power
Table
Recommended Resistors Open Drain Signals
Recommended Resistor Value pull-up pull-up pull-up pull-down 4.7K pull-up TDI, STPCLK# INIT#, TCK, TESTHI, TESTHI2, TESTHI3, TRST# A20M#, FERR#, FLUSH#, IERR#, IGNNE#, INTR, NMI, PREQ#, PWRGOOD, SLP#, SMI# Open Drain Signal
NOTE: Refer "Unused Signals" page required pull-up pull-down resistors signals that being used.
3.1.1
Power Sequencing Requirements
Pentium Processor Power power sequencing requirements. recommended that processor power planes rise their specified values within second each other.
Figure Ramp Rate Requirement
(nominal) Volts (nominal)
Time
power plane must rise fast. least (TR) must pass from time that nominal value until time that nominal value (see Figure
3.1.2
Test Access Port (TAP) Connection
interface implementation IEEE 1149.1 (JTAG) standard. voltage levels supported interface, recommended that Pentium Processor Power other JTAG specification compliant devices last JTAG chain after devices with JTAG interfaces within system. translation buffer should used reduce output voltage last 3.3/5 device down range that Pentium Processor Power tolerate. Multiple copies TCK, TMS, TRST# must provided, each voltage level. Debug Port connector placed start JTAG chain containing processor, with first component coming from Debug Port from last component going Debug Port. There requirements placement Pentium Processor Power JTAG chain, except those that dictated voltage requirements signals.
Pentium® Processor Power
3.1.3
Catastrophic Thermal Protection
Pentium Processor Power does support catastrophic thermal protection THERMTRIP# signal. external thermal sensor should thermal diode protect processor system against excessive temperatures.
3.1.4
Unused Signals
signals named must unconnected. signals named TESTLO must pulled down VSS, tied directly VSS. signals named TESTHI TESTHI3 must pulled with resistor. signals named TESTHI2 must pulled VCCP with resistor. Each TESTHI TESTHI2 signal must have individual, pull-up resistor. TESTHI3 signals share single pull-up resistor. Unused Power GTL+ inputs, outputs bidirectional signals should individually connected with pull-up resistors. Unused CMOS active inputs should connected unused active high inputs should connected VSS. Unused open-drain outputs should unconnected. processor configured enter Quick Start state rather than Stop Grant state, then SLP# signal should connected When tying signal power ground, resistor will allow system testability. unused signals, suggested that resistors used pull-ups resistors used pull-downs. PICCLK PICD[1:0] must tied with resistor. BSEL must connected VSS.
3.1.5
3.1.5.1
Signal State Power States
System Signals
system signals have Power GTL+ input, output input/output drivers. Except when servicing snoops, system signals three-stated pulled termination resistors. Snoops permitted Sleep Deep Sleep states.
3.1.5.2
CMOS Open-Drain Signals
CMOS input signals allowed either logic high state when processor low-power state. Auto Halt Stop Grant states these signals allowed toggle. These input buffers have internal pull-up pull-down resistors system logic CMOS open-drain drivers drive them. open-drain output signals have open drain drivers external pull-up resistors required. output signals (IERR#) catastrophic error indicator three-stated (and pulled-up) when processor functioning normally. FERR# output either threestated driven when processor power state depending condition floating point unit. Since this signal current path when driven VSS, recommended that software clear mask floating point error condition before putting processor into Deep Sleep state.
3.1.5.3
Other Signals
system clock (BCLK) must driven power states except Deep Sleep state.
Pentium® Processor Power
3.2.1
Power Supply Requirements
Decoupling Recommendations
amount bulk decoupling required meet processor voltage tolerance requirements strong function power supply design. Contact your Intel Field Sales Representative tools help determine much decoupling required. processor core power plane (VCC) should have least twenty-six high frequency decoupling capacitors. CMOS voltage reference power plane (VCCP) requires bulk decoupling least eight high frequency decoupling capacitors. Power GTL+ pull-up resistors, high frequency decoupling capacitor recommended resistor pack. There should more than eight pull-up resistors resistor pack. Power GTL+ voltage reference power plane (VREF) should have least three high frequency decoupling capacitors.
3.2.2
Voltage Planes
balls must connected appropriate voltage plane. VCCP VREF balls must connected appropriate traces system electronics. addition main VCC, VCCP power supply signals, PLL1 PLL2 provide isolated power section. PLL1 PLL2 should connected according Figure connect PLL2 directly VSS. Table contains requirements
Figure Filter
PLL1 VCCP
PLL2
V0027-00
Table
Filter Specifications
Symbol Parameter Filter Capacitance Unit Notes tolerance, series resistance, series inductance low-Q type choke, tolerance, series resistance, current, self-resonant frequency
Filter Inductance
Pentium® Processor Power
System Clock Processor Clocking
BCLK clock input directly controls operating speed system interface. system timing parameters specified with respect rising edge BCLK input. Pentium Processor Power core frequency multiple BCLK frequency. processor core frequency must configured during Reset using A20M#, IGNNE#, NMI, INTR pins (see Table value these pins during Reset determines multiplier that will internal core clock. Pentium® Processor Developer's Manual (order number 243502) definition these pins during Reset operation pins after Reset.
Table
Core Frequency System Ratio Configuration
Processor Core Frequency System Frequency Ratio (266 MHz) (333 MHz) INTR IGNNE# A20M# Powerup Configuration [25:22] 0010 0000
multiplexer required between system electronics processor drive ratio configuration signals during Reset. Figure Figure describe timing requirements this operation. 443BX CRESET# signal suitable timing control multiplexer. After RESET# PWRGOOD asserted, multiplexer logic must guarantee that ratio configuration signals encode ratios Table that ratio corresponds core frequency below marked core frequency processor. selected ratio visible software Power-On configuration register, "Clock Frequencies Ratios" page details. Multiplying clock frequency necessary increase performance while allowing easier distribution signals within system. Clock multiplication within processor provided internal Phase Lock Loop (PLL), which requires constant frequency BCLK input. During Reset, exit from Deep Sleep state, requires some amount time acquire phase BCLK. This time called lock latency, which specified Specifications" page (T18 T47). system frequency ratio changed when RESET# active, assuming that Reset specifications met. BCLK frequency should changed during Deep Sleep state (see "Deep Sleep State" page 14).
Maximum Ratings
Table contains Pentium Processor Power stress ratings. Functional operation absolute maximum minimum neither implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions provided tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Pentium® Processor Power
Table Pentium® Processor Power Absolute Maximum Ratings
Symbol TStorage VCC(Abs) VCCP VIN25 Parameter Storage Temperature Supply Voltage with respect CMOS Reference Voltage with respect GTL+ Buffer Input Voltage with respect Buffer Input Voltage with respect -0.5 -0.3 -0.3 -0.3 Unit Note Note Notes Note1
NOTES: shipping container only rated Parameter applies Power GTL+ signal groups only. Parameter applies CMOS, Open-Drain, APIC signal groups only.
Specifications
Table through Table list specifications Pentium Processor Power. Specifications valid only while meeting specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter.
Table Pentium® Processor Power Specifications (Sheet
TCASE TCASE,max; ±135 VCCP Symbol VCC,LP VCCP ICCP ICC,SG Parameter core logic regular voltage processors when CMOS voltage references core frequency: Current VCCP Processor Stop Grant Auto Halt current 7.95 6.63 1190 Note Notes Note 1.465 1.465 1.71 1.735 1.805 1.89 Unit Notes1 ±135 +205/-135
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. higher VCC,MAX allowed when processor power state enable high efficiency, current modes power regulator. ICCP current supply CMOS voltage references. 100% tested. Specified design/characterization. ICCx,max specifications specified VCC,max, VCCP,max 100° under maximum signal loading conditions. Based simulations averaged over duration change current. compute maximum inductance reaction time voltage regulator. This parameter tested. Maximum values specified design/characterization nominal VCCP.
Pentium® Processor Power
Table Pentium® Processor Power Specifications (Sheet
TCASE TCASE,max; ±135 VCCP Symbol ICC,QS ICC,DSLP dICC/dt Parameter Processor Quick Start Sleep current Processor Deep Sleep leakage current power supply current slew rate Unit A/µs Notes1 Note Note Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. higher VCC,MAX allowed when processor power state enable high efficiency, current modes power regulator. ICCP current supply CMOS voltage references. 100% tested. Specified design/characterization. ICCx,max specifications specified VCC,max, VCCP,max 100° under maximum signal loading conditions. Based simulations averaged over duration change current. compute maximum inductance reaction time voltage regulator. This parameter tested. Maximum values specified design/characterization nominal VCCP.
signals Pentium Processor Power system included Power GTL+ signal group. These signals specified terminated VCC. specifications these signals listed Table termination reference voltage specifications these signals listed Table Pentium Processor Power requires external termination VREF. Refer Mobile Pentium® Processor System Layout Guideline (order number 243672) full details system VREF requirements. Clock, CMOS, Open-Drain signals designed interface CMOS levels allow connection other devices. specifications these tolerant signals listed Table Table Power GTL+ Signal Group Specifications
TCASE TCASE,max; VCCP Symbol Parameter Input Voltage Input High Voltage Output High Voltage Output Drive Strength Leakage Current Output Leakage Current
-0.3 /9VTT
/9VTT ±100
Unit ohms Note Note
Notes Table Note Table
NOTES: VREF worst case, nominal. Noise VREF should accounted for. VCC). VOUT VCC).
Pentium® Processor Power
Table Power GTL+ Specifications
TCASE TCASE,max; ±135 VCCP Symbol VREF Parameter Termination Voltage Input Reference Voltage
VCC,MIN /9VTT
/9VTT
VCC,MAX /9VTT
Unit
Notes Note
NOTES: intent same power supply VTT. VREF system logic should created from voltage divider.
Table Clock, APIC, TAP, CMOS Open-Drain Signal Group Specifications
TCASE TCASE,max; ±135 VCCP Symbol VIL,BCLK VIH,BCLK Parameter Input Voltage Input Voltage, BCLK Input High Voltage Input High Voltage, BCLK Output Voltage Output High Voltage Output Current Input Leakage Current Output Leakage Current -0.3 -0.3 2.625 2.625 2.625 ±100 Unit Note Note Note outputs open-drain Notes
NOTES: Parameter measured 2.625
3.6.1
Specifications
System Bus, Clock, APIC, TAP, CMOS Open-Drain Specifications
Table through Table provide specifications associated with Pentium Processor Power. specifications divided into following categories: Table contains system clock specifications; Table contains processor core frequencies; Table contains Power GTL+ specifications; Table contains CMOS Open-Drain signal groups specifications; Table contains timings reset conditions; Table contains APIC specifications; Table contains specifications; Table Table contain power management timing specifications. system specifications Power GTL+ signal group relative rising edge BCLK input 1.25 Power GTL+ timings referenced both logic levels unless otherwise specified.
Pentium® Processor Power
Table System Clock Specifications1
TCASE TCASE,max; ±135 VCCP Symbol Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 0.175 0.175 0.875 0.875 66.67 ±250 Unit Note Notes @>1.8 @<0.7 (0.9 Note (1.6 Note Figure Notes
NOTES: timings Power GTL+ CMOS signals referenced BCLK rising edge 1.25 CMOS signals referenced 1.25 BCLK period allows +0.5 tolerance clock driver variation. 100% tested. Specified design/characterization. Measured rising edge adjacent BCLKs 1.25 jitter present must accounted component BCLK skew between devices.
Table Valid Pentium® Processor Power Frequencies
TCASE TCASE,max; ±135 VCCP BCLK Frequency (MHz) 66.67 66.67 Frequency Multiplier Core Frequency (MHz) 266.67 333.33
Table Power GTL+ Signal Groups Specifications
terminated VCC; VREF VCC; load TCASE TCASE,max; ±135 VCCP Symbol Parameter Power GTL+ Output Valid Delay Power GTL+ Input Setup Time Power GTL+ Input Hold Time RESET# Pulse Width 0.00 2.98 0.90 7.78 Unit Figure Notes Note Notes Notes Notes
NOTES: timings Power GTL+ signals referenced BCLK rising edge 1.25 Power GTL+ signals referenced VREF. RESET# asserted (active) asynchronously, must deasserted synchronously. Specification minimum 0.40 swing. Specification maximum swing. After VCC, VCCP BCLK become stable PWRGOOD asserted.
Pentium® Processor Power
Table CMOS Open-Drain Signal Groups Specifications
TCASE TCASE,max; ±135 VCCP Symbol Parameter Input Pulse Width, except PWRGOOD PWRGOOD Inactive Pulse Width Unit BCLKs BCLKs Figure Notes Active Inactive states; Notes Notes 1,2,
NOTES: timings CMOS Open-Drain signals referenced BCLK rising edge 1.25 CMOS Open-Drain signals referenced 1.25 Minimum output pulse width CMOS outputs BCLKs. When driven inactive, after VCC, VCCP BCLK become stable. PWRGOOD must remain below VIL,max from Table until voltage planes meet voltage tolerance specifications Table BCLK BCLK specifications Table least clock cycles. PWRGOOD must rise glitch-free monotonically BCLK signal meets specification within turning then PWRGOOD Inactive Pulse Width specification (T15) waived BCLK start after PWRGOOD asserted. PWRGOOD must still remain below VIL,max until voltage planes meet voltage tolerance specifications.
Table Reset Configuration Specifications
TCASE TCASE,max; ±135 VCCP Symbol Parameter Reset Configuration Signals (A[15:5]#, BR0#, FLUSH#, INIT#, PICD0) Setup Time Reset Configuration Signals (A[15:5]#, BR0#, FLUSH#, INIT#, PICD0) Hold Time Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Setup Time Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Delay Time Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time Unit BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET# Before deassertion RESET# After assertion RESET# After clock that deasserts RESET#
BCLKs
BCLKs
BCLKs
NOTES: least must pass after PWRGOOD rises above VIH,min from Table BCLK meets timing specification, until RESET# deasserted. Reset, clock ratio defined these signals must safe value (their final value lower multiplier) within this delay after RESET# asserted unless PWRGOOD inactive (below VIL,max).
Pentium® Processor Power
Table Signal Specifications
TCASE TCASE,max; ±135 VCCP Symbol Parameter Frequency Period High Time Time Rise Time Fall Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Outputs Float Delay Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 40.0 14.0 10.0 25.0 25.0 25.0 25.0 25.0 16.67 Unit Figure Note Note Notes Notes (0.7 V-1.7 Notes (1.7 V-0.7 Notes Asynchronous; Notes Notes Notes Notes Notes Notes Notes Notes Notes Notes
NOTES: timings signals referenced rising edge 1.25 CMOS signals referenced 1.25 100% tested. Specified design/characterization. added maximum rise fall times every below MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified into terminated Non-Test Outputs Inputs normal output input signals (except TCK, TRST#, TDI, TMS). These timings correspond response these signals boundary scan operations. During Debug Port operation normal specified timings rather than signal timings.
Table Quick Start/Deep Sleep Specifications
TCASE TCASE,max; ±135 VCCP Symbol Parameter Stop Grant Cycle Completion Clock Stop Stop Grant Cycle Completion Input Signals Stable Deep Sleep Lock Latency STPCLK# Hold Time from Lock Input Signal Hold Time from STPCLK# Deassertion Unit BCLKs BCLKs Figure
NOTE: Input signals other than RESET# BPRI# must held constant Quick Start state.
Pentium® Processor Power
Table Stop Grant/Sleep/Deep Sleep Specifications
TCASE TCASE,max; ±135 VCCP Symbol Parameter SLP# Signal Hold Time from Stop Grant Cycle Completion SLP# Assertion Input Signals Stable SLP# Assertion Clock Stop SLP# Hold Time from Lock STPCLK# Hold Time from SLP# Deassertion Input Signal Hold Time from SLP# Deassertion Unit BCLKs BCLKs BCLKs BCLKs Figure
NOTE: Input signals other than RESET# must held constant Sleep state.
Figure through Figure used conjunction with Table through Table Figure Generic Clock Waveform
NOTES: Tr=T5, (Rise Time) Tf=T6, (Fall Time) Th=T3, (High Time) Tl=T4, (Low Time) Tp=T1, (Period)
D0003-00
1.25V
Figure Valid Delay Timings
Signal Valid
NOTES: Tx=T7, (Valid Delay) Tpw=T14 (Pulse Width) V=VREF Power GTL+ signal group; 1.25 CMOS, Open-Drain, signal groups
Valid
D0004-00
Pentium® Processor Power
Figure Setup Hold Timings
Signal
Valid
D0005-00
NOTES: Ts=T8, (Setup Time) Th=T9, (Hold Time) V=VREF Power GTL+ signals; 1.25 CMOS signals
Figure Cold/Warm Reset Configuration Timings
BCLK
RESET#
Configuration (A20M#, IGNNE#, INTR, NMI) Configuration (A[15:5], BREQ0#, FLUSH#, INIT#, PICD0)
Safe Valid Valid
D0006-01
NOTES: Tt=T9 (Low Power GTL+ Input Hold Time) Tu=T8 (Low Power GTL+ Input Setup Time) Tv=T10 (RESET# Pulse Width) Tw=T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time) Tx=T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time) Ty=T19 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Delay Time) Tz=T18 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Setup Time)
Pentium® Processor Power
Figure Power-On Reset Timings
BCLK
VCCP, VCC, VREF
PWRGOOD
VIL,max
VIH,min
RESET#
Configuration (A20M#, IGNNE#, INTR, NMI)
Valid Ratio
D0007-01
NOTES: Ta=T15 (PWRGOOD Inactive Pulse Width) Tb=T10 (RESET# Pulse Width) Tc=T20 (Reset Configuration Signals (A20M#, IGNNE#, INTR, NMI) Hold Time)
Figure Test Timings (Boundary Scan)
TDI,
1.25V
Input Signals
Output Signals
D0008-00
NOTES: Tr=T43 (All Non-Test Inputs Setup Time) Ts=T44 (All Non-Test Inputs Hold Time) Tu=T40 (TDO Float Delay) Tv=T37 (TDI, Setup Time) Tw=T38 (TDI, Hold Time) Tx=T39 (TDO Valid Delay) Ty=T41 (All Non-Test Outputs Valid Delay) Tz=T42 (All Non-Test Outputs Float Delay)
Pentium® Processor Power
Figure Test Reset Timings
TRST# 1.25V
D0009-00
NOTES: Tq=T36 (TRST# Pulse Width)
Figure Quick Start/Deep Sleep Timing
Normal BCLK
Quick Start Running
Deep Sleep
Quick Start Running
Normal
STPCLK#
stpgnt
SLP# Compatibility Signals Changing Frozen
V0010-00
NOTES: Tv=T45 (Stop Grant Acknowledge Cycle Completion Clock Shut Delay) Tw=T46 (Setup Time Input Signal Hold Requirement) Tx=T47 (Deep Sleep Lock Latency) Ty=T48 (PLL lock STPCLK# Hold Time) Tz=T49 (Input Signal Hold Time)
Pentium® Processor Power
Figure Stop Grant/Sleep/Deep Sleep Timing
Stop Grant Stop Grant
Normal BCLK Running
Sleep
Deep Sleep
Sleep Running
Normal
STPCLK# stpgnt SLP# Compatibility Signals Changing Frozen Changing
V0011-00
NOTES: Tt=T50 (Stop Grant Acknowledge Cycle Completion SLP# Assertion Delay) Tu=T51 (Setup Time Input Signal Hold Requirement) Tv=T52 (SLP# assertion clock shut delay) Tw=T47 (Deep Sleep lock latency) Tx=T54 (SLP# Hold Time) Ty=T55 (STPCLK# Hold Time) Tz=T56 (Input Signal Hold Time)
Pentium® Processor Power
System Signal Simulations
Many scenarios have been simulated generate Power GTL+ processor system layout guidelines which available Mobile Pentium® Processor System Layout Guideline (order number 243672). Systems must simulated using IBIS model determine they compliant with this specification.
System Clock (BCLK) Signal Quality Specifications
Table Figure show signal quality system clock (BCLK) signal measured processor. timings illustrated Figure taken from Table page BCLK clock.
Table BCLK Signal Quality Specifications
Symbol VIL,BCLK VIH,BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback BCLK rising/falling slew rate -0.7 Parameter Unit V/ns Figure Note Note Undershoot, Overshoot Absolute Value Absolute Value Notes
NOTE: BCLK must rise/fall monotonically between VIL,BCLK VIH,BCLK. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing VIH,BCLK (rising) VIL,BCLK (falling) voltage limits.
Figure BCLK Generic Clock Waveform
V0012-00
Pentium® Processor Power
Power GTL+ Signal Quality Specifications
Table Figure illustrate Power GTL+ signal quality specifications Pentium Processor Power. Refer Pentium® Processor Developer's Manual GTL+ buffer specification.
Table Power GTL+ Signal Group Ringback Specification
Symbol Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Sequential Ringback Parameter -100 Unit Figure Notes Notes Notes Notes Notes Notes
NOTE: Specified edge rate V/ns. Figure generic waveform. values determined design/characterization. Ringback below VREF +100 authorized during high transitions. Ringback above VREF authorized during high transitions.
Figure High, Power GTL+ Receiver Ringback Tolerance
VIH,BCLK VREF+0.2V VREF Vstart VIL,BCLK Clock
VREF-0.2V
Time
V0014-00
NOTE: High-to-low case analogous.
Pentium® Processor Power
Non-Low Power GTL+ Signal Quality Specifications
Signals driven Pentium Processor Power should meet signal quality specifications ensure that processor reads data properly that incoming signals affect longterm reliability processor. There three signal quality parameters defined: overshoot/ undershoot, ringback settling limit. three signal quality parameters shown Figure non-GTL+ signal groups.
4.3.1
Overshoot Undershoot Guidelines
Overshoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot/undershoot guideline limits transitions beyond fast signal edge rates. processor damaged repeated overshoot events tolerant buffers charge large enough (i.e., overshoot great enough). However, excessive ringback dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating overshoot/undershoot guideline will make difficult satisfy ringback specification). overshoot/undershoot guideline assumes absence diodes input. These guidelines should verified simulations without onchip protection diodes present because diodes will begin clamping tolerant signals beginning approximately 1.25 above below VSS. signals reach clamping voltage, this will issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
Figure Non-GTL+ Overshoot/Undershoot Ringback
Settling Limit Overshoot VHI=2.5V Rising-Edge Ringback
Falling-Edge Ringback Settling Limit
Time Undershoot
V0015-00
Pentium® Processor Power
4.3.2
Ringback Specification
Ringback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input signal each receiving agent. Violations signal Ringback specification allowed under circumstances non-GTL+ signals. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications non-GTL+ signals.
4.3.3
Settling Limit Guideline
Settling limit defines maximum amount ringing receiving signal that signal reach before next transition. amount allowed total signal swing (VHI VLO) above below final value. signal should within settling limits final value, when either high state state, before next transition. Signals that within their settling limit before transitioning risk unwanted oscillations that could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Table Signal Ringback Specifications Non-GTL+ Signals
Input Signal Group Non-GTL+ Signals Non-GTL+ Signals Transition Maximum Ringback (with Input Diodes Present) Figure
Pentium® Processor Power
Mechanical Specifications
Dimensions
Pentium® Processor Power packaged PBGA-B615 package (also known BGA1) with back processor exposed top. mechanical specifications surface-mount package provided Table Figure shows side views surface-mount package, Figure shows bottom view surface-mount package. component handling, substrate only contacted within shaded region between keepout outline edge substrate.
Table Surface-Mount BGA1 Package Specifications
Symbol PDIE Parameter Overall Height, delivered Ball Height, delivered Height Ball Diameter Package Width Width Package Length Ball Pitch Length Keepout Outline Edge Substrate Keepout Outline Edge Substrate Corner Ball Count Outer Ball Center Short Edge Substrate Outer Ball Center Long Edge Substrate Allowable Pressure Thermal Solution Package Weight 1.625 0.895 3.71 4.52 2.29 0.76 1.23 2.79 1.10 1.38 Unit 35.150 each grams
0.78 30.850 10.36 34.850 1.270 17.36 31.150
Pentium® Processor Power
Figure Surface-Mount BGA1 Package-Top Side View
0.650)
swatch swatch
2.032)
1.500)
0.570) 1.150) 1.800) substrate keepout outline V0026-00
NOTES: Dimensions parentheses reference only. dimensions millimeters.
Figure Surface-Mount BGA1 Package-Bottom View
V0025-01
Pentium® Processor Power
Signal Listings
Figure topside view ball Pentium Processor Power with voltage balls called out. Table lists signals ball number order. Table Table list signals signal name order.
Figure Ball View
A29# A26# A34# D18# D16#
A35# CTRLN A19# A22# A30# A24# TESTHI D15# D17# D13# D26# D31#
A25# A17# A31# A33# RESET# BERR# D10# D14# D19# D21# D24# D27# D29# D35#
A28# TESTLO TESTLO A23# A20# A27# VREF VREF D20# D22# D32# D28# D33#
A16# A12# A13# TESTLO A21# VREF A18# A32# D12# D11# D30# D23# D25# VREF D34# D39#
A11# A15# A10# D36# D43# VCCP
A14# D44#
AP0# D45# D42# D51# D49#
TESTHI3 BNR# RSP# AP1# VREF D48# D47# D41# D52# D40#
TESTHI3 TESTHI3 D59# D57#
REQ1# BPRI# REQ4# REQ0# TESTHI D54# VREF D55# D46# D53#
DEFER# REQ2# TESTHI3 LOCK# TRDY# D61# D56# D50# D58# D60#
REQ3# HITM# VREF DEP7# D63# D62#
DBSY# DRDY# HIT# DEP0# DEP3# DEP5# DEP6#
BREQ0# RS0# RS2# RS1# PWRGOOD BPM1# VREF DEP1# DEP2# DEP4#
ADS# THERMDA SLP# BP3# PRDY# BINIT#
AERR# VCCP THERMDC PICD1 PICCLK TESTHI3 BP2# BPM0#
BSEL VCCP INTR PREQ# TESTHI
TRST# VCCP PICD0
SMI# FERR# TESTLO VCCP VCCP
STPCLK# A20M# INIT# IERR#
IGNNE# VCCP
FLUSH# TESTHI2 TESTLO
VCCP TESTHI2
BCLK PLL2 PLL1
V0024-01
VCCP
Other Analog Decoupling
Pentium® Processor Power
Table Signal Listing Order Ball Number (Sheet
Ball Signal Name A29# A26# A34# D18# D16# EDGCTRLN A35# A19# A22# A30# A24# A15# A10# Ball Signal Name TESTHI D15# D17# D13# D26# D31# A25# A17# A31# A33# RESET# BERR# Ball Signal Name D10# D14# D19# D21# D24# D27# D29# D35# A28# TESTLO TESTLO A23# A20# A27# VREF VREF D20# D22# D45# Ball Signal Name D32# D28# D33# A16# A12# A13# TESTLO A21# VREF A18# A32# D12# D11# D30# D23# D25# VREF D34# D39# A11# D47# D41# D52# D40# TESTHI3
Pentium® Processor Power
Table Signal Listing Order Ball Number (Sheet
Ball Signal Name D37# D36# D43# VCCP A14# BPRI# REQ4# REQ0# TESTHI Ball Signal Name D38# D44# AP0# D61# D56# Ball Signal Name D42# D51# D49# TESTHI3 BNR# RSP# AP1# VREF D48# DEP7# D63# D62# DBSY# Ball Signal Name TESTHI3 D59# D57# REQ1# DEP0# DEP3# DEP5# DEP6# BREQ0# RS0# RS2# RS1# PWRGOOD
Pentium® Processor Power
Table Signal Listing Order Ball Number (Sheet
Ball Signal Name D54# VREF D55# D46# D53# DEFER# REQ2# TESTHI3 LOCK# TRDY# ADS# THERMDA SLP# BP3# PRDY# Ball Signal Name D50# D58# D60# REQ3# HITM# VREF PICD1 PICCLK TESTHI3 BP2# BPM0# BSEL VCCP Ball Signal Name DRDY# HIT# INTR PREQ# TESTHI TRST# VCCP Ball Signal Name BPM1# VREF DEP1# DEP2# DEP4# PICD0 SMI# FERR# TESTLO
Pentium® Processor Power
Table Signal Listing Order Ball Number (Sheet
Ball AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 Signal Name BINIT# AERR# VCCP THERMDC IGNNE# VCCP Ball AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AC10 AC11 AC12 AC13 AC14 AC15 Signal Name FLUSH# TESTHI2 TESTLO Ball AC18 AC19 AC20 AC21 AC22 AC23 AC24 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 Signal Name VCCP TESTHI2 Ball AD24 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 Signal Name VCCP VCCP STPCLK# A20M# INIT# IERR# BCLK
Pentium® Processor Power
Table Signal Listing Order Ball Number (Sheet
Ball AB10 AB11 AF10 Signal Name PLL1 Ball AC16 AC17 AF11 AF12 AF13 AF14 AF15 Signal Name Ball AD22 AD23 AF16 AF17 AF18 AF19 AF20 Signal Name Ball AF21 AF22 AF23 AF24 Signal Name PLL2
Table Signal Listing Order Signal Name (Sheet
Ball Signal Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# Signal Buffer Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Ball Signal Name A33# A34# A35# A20M# ADS# AERR# AP0# AP1# BCLK BERR# BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BREQ0# BSEL Signal Buffer Type Power GTL+ Power GTL+ Power GTL+ CMOS Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Processor Clock Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ CMOS Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+
Pentium® Processor Power
Table Signal Listing Order Signal Name (Sheet
Ball Signal Name A29# A30# A31# A32# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# DEP5# DEP6# DEP7# Signal Buffer Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Ball Signal Name D10# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# DEP1# DEP2# DEP3# DEP4# RS0# RS1# RS2# Signal Buffer Type Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ Input Power GTL+ Input
Pentium® Processor Power
Table Signal Listing Order Signal Name (Sheet
Ball AA24 Signal Name DRDY# EDGCTRLN FERR# FLUSH# HIT# HITM# IERR# IGNNE# INIT# INTR LOCK# PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# RESET# VREF VREF VREF VREF Signal Buffer Type Power GTL+ Power GTL+ Control Open Drain Output CMOS Input Power GTL+ Power GTL+ Open Drain Output CMOS Input CMOS Input CMOS Input Power GTL+ CMOS Input APIC Clock Input Open Drain Open Drain Analog Voltage Analog Voltage Power GTL+ Output CMOS Input CMOS Input Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Power GTL+ Input Power GTL+ GTL+ Reference Voltage GTL+ Reference Voltage GTL+ Reference Voltage GTL+ Reference Voltage Ball Signal Name RSP# SLP# SMI# STPCLK# TESTHI TESTHI TESTHI TESTHI2 TESTHI2 TESTHI3 TESTHI3 TESTHI3 TESTHI3 TESTHI3 TESTLO TESTLO TESTLO TESTLO TESTLO THERMDA THERMDC TRDY# TRST# VREF VREF VREF VREF Signal Buffer Type Power GTL+ Input CMOS Input CMOS Input CMOS Input JTAG Clock Input JTAG Input JTAG Output GTL+ Test Input GTL+ Test Input GTL+ Test Input CMOS Test Input CMOS Test Input GTL+ Test Input GTL+ Test Input GTL+ Test Input GTL+ Test Input GTL+ Test Input Test Input Test Input Test Input Test Input Test Input Thermal Diode Anode Thermal Diode Cathode JTAG Input Power GTL+ Input JTAG Input GTL+ Reference Voltage GTL+ Reference Voltage GTL+ Reference Voltage GTL+ Reference Voltage
Pentium® Processor Power
Table Voltage No-Connect Ball Locations
Signal Name Ball Numbers A10, A12, A13, A24, B10, B11, B12, B13, B14, C10, C11, C12, C13, C14, D12, D13, E11, E12, E13, E24, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F23, G17, G18, G19, G23, H17, H18, H19, J17, J18, J19, K17, K18, K19, L17, L18, L19, M17, M18, M19, N17, N18, N19, P17, P18, P19, R17, R18, R19, T17, T18, T19, U17, U18, U19, V17, V18, V19, V20, W17, W18, W19, W20, Y17, Y18, Y19, Y20, Y21, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, AA17, AA18, AA19, AA20, AA21, AA22, AA23, AB3, AB5, AB6, AB7, AB8, AB9, AB10, AB11, AB12, AB13, AB14, AB15, AB16, AB17, AB18, AB19, AB20, AB21, AB22, AB23, AB24, AC3, AC6, AC7, AC8, AC9, AC10, AC11, AC12, AC13, AC14, AC15, AC16, AC17, AC18, AC19, AC20, AC21, AC22, AD5, AD6, AD7, AD8, AD9, AD10, AD11, AD12, AD13, AD14, AD15, AD16, AD17, AD18, AD19, AD20, AD21, AD22, AD23, AD24, AE8, AE9, AE10, AE11, AE12, AE13, AE14, AE15, AE16, AE17, AE18, AE19, AE20, AE21, AE22, AE23, AE24, AF1, AF8, AF9, AF10, AF11, AF12, AF13, AF14, AF15, AF16, AF17, AF18, AF19, AF20, AF21, AF22, AF23, AF24 G10, G12, G14, G16, H11, H13, H15, J10, J12, J14, J16, K11, K13, K15, L10, L12, L14, L16, M11, M13, M15, N10, N12, N14, N16, P11, P13, P15, R10, R12, R14, R16, T11, T13, T15, U10, U12, U14, U16, V11, V13, V15, W10, W12, W14, W16, Y11, Y13, Y15, F24, Y22, Y23, AB4, A11, A14, A16, A17, A20, A23, B23, B24, D11, D14, D17, D20, D23, E20, G11, G13, G15, G21, H10, H12, H14, H16, J11, J13, J15, K10, K12, K14, K16, K21, K22, K24, L11, L13, L15, M10, M12, M14, M16, N11, N13, N15, N21, N24, P10, P12, P14, P16, P24, R11, R13, R15, T10, T12, T14, T16, T21, T24, U11, U13, U15, V10, V12, V14, V16, W11, W13, W15, W21, W22, Y10, Y12, Y14, Y16, Y24, AC4, AC23, AC24, AD1, AE1, AE2, AE3, AE4, AE5, AE6, AE7, AF2, AF4,
VCCP
Pentium® Processor Power
Thermal Specifications
order achieve proper cooling processor, thermal solution (e.g., heat spreader, heat pipe, other heat transfer system) must make firm contact exposed processor die. processor must clean before thermal solution attached processor damaged. During operating environments, processor case temperature, TCASE, must within specified range 100° converter attached thermal diode used measure processor core temperature ensure compliance with this specification. designer responsible insuring that thermal diode converter accurately track processor temperature. designer should verify this correlating "sensor" output temperature with thermocouple placed directly surface. Refer "Case Temperature" page more details.
Table Pentium® Processor Power Specifications
Symbol PSGNT PDSLP TCASE Parameter Thermal Design Power Stop Grant Auto Halt power Quick Start Sleep power Deep Sleep power Case Temperature Typ1 Max2 11.8 1.25 Unit Notes Note Note Note Note
NOTE: TDPTYP recommendation based power dissipation processor while executing publicly available software under normal operating conditions nominal voltages. Contact your Intel Field Sales Representative further information. TDPMAX specification total power dissipation processor while executing worst-case instruction under normal operating conditions nominal voltages. includes power dissipated components within processor. Specified design/characterization. 100% tested guaranteed. power specifications composed current processor various voltage planes. These currents measured specified high temperature Specifications" page These power specifications determined characterization processor currents higher temperatures.
Pentium® Processor Power
Thermal Diode
Pentium Processor Power on-die diode that used monitor temperature. thermal sensor located system electronics diode monitor temperature Pentium Processor Power thermal management purposes. Table Table provide diode interface specifications.
Table Thermal Diode Interface
Signal Name THERMDA THERMDC Ball Number Signal Description Thermal diode anode Thermal diode cathode
Table Thermal Diode Specifications
Symbol Parameter Forward Bias Current Diode Ideality Factor 1.0000 1.0065 1.0173 Unit Notes Note Notes
NOTE: Intel does support recommend operation thermal diode under reverse bias. Intel does support recommend operation thermal diode when processor power supplies within their specified tolerance range. with forward bias 100% tested. Specified design/characterization. ideality factor, represents deviation from ideal diode behavior exemplified diode equation:
Pentium® Processor Power
Case Temperature
verify that proper TCASE (case temperature) maintained Pentium Processor Power, should measured center package surface. minimize measurement errors, following techniques recommended:
gauge finer diameter type thermocouples. Intel's laboratory testing
done using thermocouple made Omega Engineering, Inc. (part number: 5TC-TTK-3636).
Attach thermocouple bead junction center package surface
using highly thermally conductive cements. Intel's laboratory testing done using OMEGABOND* cement (part number: OB100). Thermal grease provides equivalent temperature measurement results when used correctly mechanically resilient cement.
thermocouple should attached angle shown Figure horizontal
thermocouple mount acceptable. Figure Technique Measuring Case Temperature
V0028-00
Pentium® Processor Power
Processor Initialization Configuration
Description
Pentium® Processor Power some configuration options that determined hardware some that determined software. processor samples hardware configuration reset, active-to-inactive transition RESET#. Most configuration options Pentium Processor Power identical those Pentium processor. Pentium® Processor Developer's Manual (order number 243502) describes these configuration options. configuration options Pentium Processor Power described remainder this section.
7.1.1
Quick Start Enable
processor normally enters Stop Grant state when STPCLK# signal asserted, will enter Quick Start state instead A15# sampled active RESET# signal's active-toinactive transition. Quick Start state supports snoops from priority device like Stop Grant state, does support symmetric master snoops, latching interrupts supported. position Power-On Configuration register indicates that Quick Start state been enabled.
7.1.2
System Frequency
Pentium Processor Power will only function with system frequency MHz. position Power-On Configuration register indicates which speed processor will run. indicates 66-MHz frequency indicates 100-MHz frequency.
7.1.3
APIC Disable
APIC been removed feature Pentium Processor Power. PICCLK PICD[1:0] signals must tied with resistor disable APIC. Driving PICD0 reset effect clearing APIC Global Enable APIC Base MSR. This normally when processor reset, when cleared APIC completely disabled until next reset.
Clock Frequencies Ratios
Pentium Processor Power uses clock design which clock multiplied ratio produce processor's internal "core") clock. ratio used programmed into processor during Reset. "System Clock Processor Clocking" page describes this done. ratio programmed into processor visible positions Power-On Configuration register. Table page shows 4-bit codes Power-On Configuration register their corresponding ratios.
Pentium® Processor Power
8.1.1
Processor Interface
Alphabetical Signal Reference
A[35:3]# (I/O Power GTL+)
A[35:3]# (Address) signals define 36-byte physical memory address space. When ADS# active, these signals transmit address transaction; when ADS# inactive, these signals transmit transaction information. These signals must connected appropriate balls both agents system bus. A[35:24]# signals protected with AP1# parity signal, A[23:3]# signals protected with AP0# parity signal. active-to-inactive transition RESET#, each processor agent samples A[35:3]# signals determine power-on configuration. "Processor Initialization Configuration" page Pentium® Processor Developer's Manual details.
8.1.2
A20M# 2.5V Tolerant)
A20M# (Address-20 Mask) input signal asserted, processor masks physical address (A20#) before looking line internal cache before driving read/write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around 1-Mbyte boundary. Assertion A20M# only supported real mode. During active RESET#, processor begins sampling A20M#, IGNNE#, INTR values determine ratio core-clock frequency bus-clock frequency (see Table page 21). active-to-inactive transition RESET#, processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation.
8.1.3
ADS# (I/O Power GTL+)
ADS# (Address Strobe) signal asserted indicate validity transaction address A[35:3]# signals. Both agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop deferred reply match operations associated with transaction. This signal must connected appropriate balls both agents system bus.
8.1.4
AERR# (I/O Power GTL+)
AERR# (Address Parity Error) signal observed driven both system agents, used, must connected appropriate balls both agents system bus. AERR# observation optionally enabled during power-on configuration; enabled, valid assertion AERR# aborts current transaction. AERR# observation disabled during power-on configuration, central agent handle assertion AERR# appropriate error handling architecture system.
Pentium® Processor Power
8.1.5
AP[1:0]# (I/O Power GTL+)
AP[1:0]# (Address Parity) signals driven request initiator along with ADS#, A[35:3]#, REQ[4:0]# RP#. AP1# covers A[35:24]#. AP0# covers A[23:3]#. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connected appropriate balls both agents system bus.
8.1.6
BCLK 2.5V Tolerant)
BCLK (Bus Clock) signal determines system frequency. Both system agents must receive this signal drive their outputs latch their inputs BCLK rising edge. external timing parameters specified with respect BCLK signal.
8.1.7
BERR# (I/O Power GTL+)
BERR# (Bus Error) signal asserted indicate unrecoverable error without protocol violation. driven either system agent, must connected appropriate balls both agents, used. However, Pentium Processor Power does observe assertions BERR# signal. BERR# assertion conditions defined system configuration. Configuration options enable BERR# driver follows:
8.1.8
Enabled disabled Asserted optionally internal errors along with IERR# Asserted optionally request initiator transaction after observes error Asserted agent when observes error transaction
BINIT# (I/O Power GTL+)
BINIT# (Bus Initialization) signal observed driven both system agents, must connected appropriate balls both agents, used. BINIT# driver enabled during power-on configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# enabled during power-on configuration, BINIT# sampled asserted, state machines reset data which transit lost. agents reset their rotating arbitration state after reset, internal count information lost. caches affected. BINIT# disabled during power-on configuration, central agent handle assertion BINIT# appropriate Machine Check Architecture (MCA) system.
8.1.9
BNR# (I/O Power GTL+)
BNR# (Block Next Request) signal used assert stall agent that unable accept transactions. During stall, current owner cannot issue transactions.
Pentium® Processor Power
Since multiple agents need request stall simultaneously, BNR# wired-OR signal which must connected appropriate balls both agents system bus. order avoid wire-OR glitches associated with simultaneous edge transitions driven multiple drivers, BNR# activated specific clock edges sampled specific clock edges.
8.1.10
BP[3:2]# (I/O Power GTL+)
BP[3:2]# (Breakpoint) signals System Support group Breakpoint signals. They outputs from processor that indicate status breakpoints.
8.1.11
BPM[1:0]# (I/O Power GTL+)
BPM[1:0]# (Breakpoint Monitor) signals breakpoint performance monitor signals. They outputs from processor that indicate status breakpoints programmable counters used monitoring processor performance.
8.1.12
BPRI# Power GTL+)
BPRI# (Bus Priority Request) signal used arbitrate ownership system bus. must connected appropriate balls both agents system bus. Observing BPRI# active asserted priority agent) causes processor stop issuing requests, unless such requests part ongoing locked operation. priority agent keeps BPRI# asserted until requests completed, then releases deasserting BPRI#.
8.1.13
BREQ0# (I/O Power GTL+)
BREQ0# (Bus Request) signal processor Arbitration signal. processor indicates that wants ownership system asserting BREQ0# signal. During power-up configuration, central agent must assert BREQ0# signal. processor samples BREQ0# active-to-inactive transition RESET#.
8.1.14
BSEL Tolerant)
BSEL (System Speed Select) signal used configure processor system frequency. this signal configures processor operation configures operation. This signal must connected
8.1.15
D[63:0]# (I/O Power GTL+)
D[63:0]# (Data) signals data signals. These signals provide 64-bit data path between both system agents, must connected appropriate balls both agents. data driver asserts DRDY# indicate valid data transfer.
Pentium® Processor Power
8.1.16
DBSY# (I/O Power GTL+)
DBSY# (Data Busy) signal asserted agent responsible driving data system indicate that data use. data released after DBSY# deasserted. This signal must connected appropriate balls both agents system bus.
8.1.17
DEFER# Power GTL+)
DEFER# (Defer) signal asserted agent indicate that transaction cannot guaranteed in-order completion. Assertion DEFER# normally responsibility addressed memory agent agent. This signal must connected appropriate balls both agents system bus.
8.1.18
DEP[7:0]# (I/O Power GTL+)
DEP[7:0]# (Data Protection) signals provide optional protection data bus. They driven agent responsible driving D[63:0]#, must connected appropriate balls both agents system they used. During power-on configuration, DEP[7:0]# signals enabled checking disabled checking.
8.1.19
DRDY# (I/O Power GTL+)
DRDY# (Data Ready) signal asserted data driver each data transfer, indicating valid data data bus. multi-cycle data transfer, DRDY# deasserted insert idle clocks. This signal must connected appropriate balls both agents system bus.
8.1.20
EDGCTRLN (Analog)
This signal used configure edge rate Power GTL+ output buffers. Connect EDGCTRLN (Edge Rate Control N-FET) signal with resistor.
8.1.21
FERR# Tolerant Open-drain)
FERR# (Floating-point Error) signal asserted when processor detects unmasked floating-point error. FERR# similar ERROR# signal Intel387 coprocessor, included compatibility with systems using DOS-type floating-point error reporting.
8.1.22
FLUSH# Tolerant)
When FLUSH# (Flush) input signal asserted, processor writes back internal cache lines Modified state invalidates internal cache lines. completion flush operation, processor issues Flush Acknowledge transaction. processor stops caching data while FLUSH# signal remains asserted. active-to-inactive transition RESET#, each processor agent samples FLUSH# determine power-on configuration.
Pentium® Processor Power
8.1.23
HIT# (I/O Power GTL+), HITM# (I/O Power GTL+)
HIT# (Snoop Hit) HITM# (Hit Modified) signals convey transaction snoop operation results, must connected appropriate balls both agents system bus. Either agent assert both HIT# HITM# together indicate that requires snoop stall, which continued reasserting HIT# HITM# together.
8.1.24
IERR# Tolerant Open-drain)
IERR# (Internal Error) signal asserted processor result internal error. Assertion IERR# usually accompanied SHUTDOWN transaction system bus. This transaction optionally converted external error signal (e.g., NMI) system logic. processor will keep IERR# asserted until handled software with assertion RESET#, BINIT INIT#.
8.1.25
IGNNE# Tolerant)
IGNNE# (Ignore Numeric Error) signal asserted force processor ignore numeric error continue execute non-control floating-point instructions. IGNNE# deasserted, processor freezes non-control floating-point instruction previous instruction caused error. IGNNE# effect when control register (CR0) set. During active RESET#, processor begins sampling A20M#, IGNNE#, INTR values determine ratio core-clock frequency bus-clock frequency (see Table page 21). active-to-inactive transition RESET#, processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation.
8.1.26
INIT# Tolerant)
INIT# (Initialization) signal asserted reset integer registers inside processor without affecting internal caches floating-point registers. processor begins execution power-on reset vector configured during power-on configuration. processor continues handle snoop requests during INIT# assertion. INIT# asynchronous input. INIT# sampled active RESET#'s active-to-inactive transition, then processor executes built-in self test (BIST).
8.1.27
INTR Tolerant)
INTR (Interrupt) signal indicates that external interrupt been generated. interrupt maskable using EFLAGS register. set, processor vectors interrupt handler after completing current instruction execution. Upon recognizing interrupt request, processor issues single Interrupt Acknowledge (INTA) transaction. INTR must remain active until INTA transaction guarantee recognition. INTR must deasserted minimum clocks guarantee inactive recognition.
Pentium® Processor Power
During active RESET#, processor begins sampling A20M#, IGNNE#, INTR values determine ratio core-clock frequency bus-clock frequency (see Table page 21). active-to-inactive transition RESET#, processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation.
8.1.28
LOCK# (I/O Power GTL+)
LOCK# (Lock) signal indicates system that sequence transactions must occur atomically. This signal must connected appropriate balls both agents system bus. locked sequence transactions, LOCK# asserted from beginning first transaction through last transaction. When priority agent asserts BPRI# arbitrate ownership, waits until observes LOCK# deasserted. This enables processor retain ownership throughout locked operation guarantee atomicity lock.
8.1.29
Tolerant)
(Non-Maskable Interrupt) indicates that external interrupt been generated. Asserting causes interrupt with internally supplied vector value external interrupt-acknowledge transaction generated. asserted during execution service routine, remains pending recognized after IRET executed service routine. most, assertion held pending. rising-edge sensitive. Active inactive pulse widths must minimum clocks. During active RESET#, processor begins sampling A20M#, IGNNE#, INTR values determine ratio core-clock frequency bus-clock frequency (see Table page 21). active-to-inactive transition RESET#, processor latches these signals freezes frequency ratio internally. System logic must then release these signals normal operation.
8.1.30
PICCLK Tolerant)
PICCLK (APIC Clock) signal input clock processor system logic APIC that required operation processor, system logic APIC components APIC bus.
8.1.31
PICD[1:0] (I/O Tolerant Open-drain)
PICD[1:0] (APIC Data) signals used bidirectional serial message passing APIC bus. They must connected appropriate balls APIC agents, including processor system logic APIC components. PICD0 signal sampled active-to-inactive transition RESET# signal, then APIC hardware disabled.
8.1.32
PRDY# Power GTL+)
PRDY# (Probe Ready) signal processor output used debug tools determine processor debug readiness.
Pentium® Processor Power
8.1.33
PREQ# Tolerant)
PREQ# (Probe Request) signal used debug tools request debug operation processor.
8.1.34
PWRGOOD Tolerant)
PWRGOOD (Power Good) tolerant input. processor requires this signal clean indication that clocks power supplies (VCC, VCCP, etc.) stable within their specifications. Clean implies that signal will remain low, (capable sinking leakage current) without glitches, from time that power supplies turned until they come within specification. signal will then transition monotonically high (2.5 state. Figure illustrates relationship PWRGOOD other system signals. PWRGOOD driven inactive time, clocks power must again stable before rising edge PWRGOOD. must also meet minimum pulse width specified Table page followed RESET# pulse.
Figure PWRGOOD Relationship Power-On
BCLK VCC, VCCP, VREF PWRGOOD
VIH,min msec
RESET#
D0026-00
PWRGOOD signal, which must supplied processor, used protect internal circuits against voltage sequencing issues. PWRGOOD signal should driven high throughout boundary scan operation.
8.1.35
REQ[4:0]# (I/O Power GTL+)
REQ[4:0]# (Request Command) signals must connected appropriate balls both agents system bus. They asserted current owner when drives A[35:3]# define currently active transaction type.
8.1.36
RESET# Power GTL+)
Asserting RESET# signal resets processor known state invalidates caches without writing back Modified state) lines. RESET# must remain active microsecond "warm" reset. power-on type reset, RESET# must stay active least after BCLK have reached their proper specifications after PWRGOOD been asserted. When observing active RESET#, agents will deassert their outputs within clocks.
Pentium® Processor Power
number signals sampled active-to-inactive transition RESET# poweron configuration. configuration options described "Processor Initialization Configuration" page Pentium® Processor Developer's Manual. Unless outputs three-stated during power-on configuration, after active-to-inactive transition RESET#, processor optionally executes built-in self-test (BIST) begins program execution reset-vector 000FFFF0H FFFFFFF0H. RESET# must connected appropriate balls both agents system bus.
8.1.37
(I/O Power GTL+)
(Request Parity) signal driven request initiator, provides parity protection ADS# REQ[4:0]#. should connected appropriate balls both agents system bus. correct parity signal high even number covered signals number covered signals low. This definition allows parity high when covered signals high.
8.1.38
RS[2:0]# Power GTL+)
RS[2:0]# (Response Status) signals driven response agent (the agent responsible completion current transaction), must connected appropriate balls both agents system bus.
8.1.39
RSP# Power GTL+)
RSP# (Response Parity) signal driven response agent (the agent responsible completion current transaction) during assertion RS[2:0]#. RSP# provides parity protection RS[2:0]#. RSP# should connected appropriate balls both agents system bus. correct parity signal high even number covered signals number covered signals low. During Idle state RS[2:0]# (RS[2:0]#=000), RSP# also high since driven agent guaranteeing correct parity.
8.1.40
SLP# 2.5V Tolerant)
SLP# (Sleep) signal, when asserted Stop Grant state, causes processor enter Sleep state. During Sleep state, processor stops providing internal clock signals units, leaving only Phase-Locked Loop (PLL) still running. processor will recognize snoop interrupts Sleep state. processor will only recognize changes SLP#, STPCLK# RESET# signals while Sleep state. SLP# deasserted, processor exits Sleep state returns Stop Grant state which restarts internal clock APIC processor units.
Pentium® Processor Power
8.1.41
SMI# Tolerant)
SMI# (System Management Interrupt) asserted asynchronously system logic. accepting System Management Interrupt, processor saves current state enters System Management Mode (SMM). Acknowledge transaction issued, processor begins program execution from handler.
8.1.42
STPCLK# Tolerant)
STPCLK# (Stop Clock) signal, when asserted, causes processor enter low-power Stop Grant state. processor issues Stop Grant Acknowledge special transaction, stops providing internal clock signals units except APIC units. processor continues snoop transactions service interrupts while Stop Grant state. When STPCLK# deasserted, processor restarts internal clock units resumes execution. assertion STPCLK# effect clock.
8.1.43
Tolerant)
(Test Clock) signal provides clock input test (also known test access port).
8.1.44
Tolerant)
(Test Data signal transfers serial test data processor. provides serial input needed JTAG support.
8.1.45
Tolerant Open-drain)
(Test Data Out) signal transfers serial test data from processor. provides serial output needed JTAG support.
8.1.46
THERMDA, THERMDC (Analog)
THERMDA (Thermal Diode Anode) THERMDC (Thermal Diode Cathode) signals connect anode cathode on-die thermal diode.
8.1.47
Tolerant)
(Test Mode Select) signal JTAG support signal used debug tools.
8.1.48
TRDY# Power GTL+)
TRDY# (Target Ready) signal asserted target indicate that target ready receive write implicit writeback data transfer. TRDY# must connected appropriate balls both agents system bus.
Pentium® Processor Power
8.1.49
TRST# Tolerant)
TRST# (Test Reset) signal resets Test Access Port (TAP) logic. Pentium Processor Power does self- reset during power-on; therefore, necessary drive this signal during power-on reset.
Signal Summaries
Table through Table list attributes processor input, output, signals.
Table Input Signals
Name A20M# BCLK BPRI# BSEL DEFER# FLUSH# IGNNE# INIT# INTR PICCLK PREQ# PWRGOOD RESET# RS[2:0]# RSP# SLP# SMI# STPCLK# TRDY# TRST# Active Level High High High High High High High Clock Asynch BCLK Asynch BCLK Asynch Asynch Asynch Asynch Asynch Asynch Asynch BCLK BCLK BCLK Asynch Asynch Asynch BCLK Asynch Signal Group CMOS System System Implementation System CMOS CMOS System CMOS CMOS APIC Implementation Implementation System System System Implementation CMOS Implementation JTAG JTAG JTAG System JTAG Response phase Qualified Always Always Always Always Always Always Always Always APIC disabled mode APIC disabled mode Always Always Always Always Always Always Stop Grant state Always Always
Pentium® Processor Power
Table Output Signals
Name FERR# IERR# PRDY# High Active Level Asynch Asynch BCLK Clock Signal Group Open-Drain Open-Drain Implementation JTAG
Table Input/Output Signals (Single Driver)
Name A[35:3]# ADS# AP[1:0]# BREQ0# BP[3:2]# BPM[1:0]# D[63:0]# DBSY# DEP[7:0]# DRDY# LOCK# REQ[4:0]# Active Level BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK BCLK Clock Signal Group System System System System System System System System System System System System System Qualified ADS#, ADS#+1 Always ADS#, ADS#+1 Always Always Always DRDY# Always DRDY# Always Always ADS#, ADS#+1 ADS#, ADS#+1
Table Input/Output Signals (Multiple Driver)
Name AERR# BERR# BINIT# BNR# HIT# HITM# PICD[1:0] Active Level High Clock BCLK BCLK BCLK BCLK BCLK BCLK PICCLK Signal Group System System System System System System APIC Qualified ADS#+3 Always Always Always Always Always Always
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