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Pentium® XeonProcessor
Binary compatible with applications running previous members Intel microprocessor family Optimized 32-bit applications running advanced 32-bit operating systems Dynamic Execution micro architecture Dual Independent architecture: Separate dedicated external 100MHz System dedicated internal cache operating full processor core speed Power Management capabilities System Management mode Multiple low-power states SMBus interface advanced manageability features Intel® processor serial number
Single Edge Contact (S.E.C.) cartridge packaging technology; S.E.C. cartridge delivers high performance processing technology mid-range high-end servers workstations system speeds data transfer between processor system Integrated high performance16K instruction data, nonblocking, level-one cache Available 512K, unified, nonblocking level-two cache Enables systems which scaleable four processors physical memory Streaming SIMD Extensions enhanced video, sound performance
Intel® Pentium® Xeonprocessor designed mid-range high-end servers workstations, binary compatible with previous Intel Architecture processors. Pentium Xeon processor provides best performance available applications running advanced operating systems such Windows* Windows UNIX*. Pentium Xeon processor scalable four processors multiprocessor system extends power Pentium® processor with features designed make this processor right choice powerful workstation, advanced server management, mission-critical applications. Pentium Xeon processor-based workstations offer memory architecture required most demanding workstation applications workloads. Specific features Pentium Xeon processor address platform manageability meet needs robust environment, maximize system time ensure optimal configuration operation servers. Pentium Xeon processor enhances ability server platforms monitor, protect, service processor environment.
Order Number: 245094-002 February 2000
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2000 *Third-party brands names property their respective owners.
Pentium® XeonProcessor
Contents
Introduction.9 Terminology.9 1.1.1 S.E.C. Cartridge Terminology References Pentium® XeonProcessor System VREF Power Ground Pins Decoupling Guidelines 2.3.1 Pentium® XeonProcessor VCCCORE 2.3.2 Level Cache Decoupling 2.3.3 System AGTL+ Decoupling.13 System Clock Processor Clocking 2.4.1 Mixing Processors Voltage Identification System Unused Pins Test Pins.17 System Signal Groups 2.7.1 Asynchronous Synchronous System Signals.19 Test Access Port (TAP) Connection.19 Maximum Ratings.20 Processor Specifications.20 AGTL+ System Specifications System Specifications System Clock Signal Quality Specifications.33 AGTL+ Signal Quality Specifications 3.2.1 AGTL+ Ringback Tolerance Specifications.34 3.2.2 AGTL+ Overshoot/Undershoot Guidelines.34 Non-AGTL+ Signal Quality Specifications.35 3.3.1 Tolerant Buffer Overshoot/Undershoot Guidelines 3.3.2 Tolerant Buffer Ringback Specification.35 3.3.3 Tolerant Buffer Settling Limit Guideline Functional Redundancy Checking Mode.36 Power States Clock Control.37 4.2.1 Normal State- State 4.2.2 Auto Halt Power Down State State 4.2.3 Stop-Grant State State 4.2.4 Halt/Grant Snoop State State 4.2.5 Sleep State State 5.39 4.2.6 Clock Control.39 System Management (SMBus) Interface 4.3.1 Processor Information ROM.41 4.3.2 Scratch EEPROM.42
Electrical Specifications.11
2.10 2.11 2.12
Signal Quality
Processor Features
Pentium® XeonProcessor
4.3.3 4.3.4 4.3.5 4.3.6
4.3.7
Processor Information Scratch EEPROM Supported SMBus Transactions Thermal Sensor.43 Thermal Sensor Supported SMBus Transactions.44 Thermal Sensor Registers.46 4.3.6.1 Thermal Reference Registers 4.3.6.2 Thermal Limit Registers 4.3.6.3 Status Register.46 4.3.6.4 Configuration Register.47 4.3.6.5 Conversion Rate Register SMBus Device Addressing.48
Thermal Specifications Design Considerations.49 Thermal Specifications.50 5.1.1 Power Dissipation 5.1.2 Plate Flatness Specification Processor Thermal Analysis 5.2.1 Thermal Solution Performance.51 5.2.2 Thermal Plate Heat Sink Interface Management Guide. 5.2.3 Measurements Thermal Specifications. 5.2.3.1 Thermal Plate Temperature Measurement 5.2.3.2 Cover Temperature Measurement Guideline Weight Cartridge Connector Mating Details Pentium® XeonProcessor Substrate Edge Finger Signal Listing Introduction Mechanical Specifications.71 7.2.1 Boxed Processor Heatsink Dimensions 7.2.2 Boxed Processor Heatsink Weight.73 7.2.3 Boxed Processor Retention Mechanism Thermal Specifications.74 7.3.1 Boxed Processor Cooling Requirements 7.3.2 Optional Auxiliary Attachment 7.3.2.1 Clearance Recommendations Auxiliary 7.3.2.2 Power Recommendations Auxiliary 7.3.2.3 Thermal Evaluation Auxiliary In-Target Probe (ITP) Pentium® XeonProcessors. 8.1.1 Primary Function 8.1.2 Debug Port Connector Description.79 8.1.3 Debug Port Signal Descriptions 8.1.4 Debug Port Signal Notes.82 8.1.4.1 General Signal Quality Notes 8.1.4.2 Signal Note: DBRESET#.83 8.1.4.3 Signal Note: 8.1.4.4 Signal Note: TCK.83 8.1.5 Using Boundary Scan Communicate Processor
Mechanical Specifications.55
Boxed Processor Specifications.71
Integration Tools
Pentium® XeonProcessor
Integration Tool (Logic Analyzer) Considerations Alphabetical Signals Reference 9.1.1 A[35:03]# (I/O).86 9.1.2 A20M# (I).86 9.1.3 ADS# (I/O).87 9.1.4 AERR# (I/O) 9.1.5 AP[1:0]# (I/O) 9.1.6 BCLK (I).87 9.1.7 BERR# (I/O) 9.1.8 BINIT# (I/O) 9.1.9 BNR# (I/O).88 9.1.10 BP[3:2]# (I/O) 9.1.11 BPM[1:0]# (I/O) 9.1.12 BPRI# (I).88 9.1.13 BR0# (I/O), BR[3:1]# 9.1.14 CPU_SENSE.89 9.1.15 D[63:00]# (I/O).89 9.1.16 DBSY# (I/O) 9.1.17 DEFER# (I).90 9.1.18 DEP[7:0]# (I/O).90 9.1.19 DRDY# (I/O) 9.1.20 9.1.21 FERR# 9.1.22 FLUSH# 9.1.23 FRCERR (I/O) 9.1.24 HIT# (I/O), HITM# (I/O) 9.1.25 IERR# (O).91 9.1.26 IGNNE# (I).91 9.1.27 INIT# 9.1.28 INTR LINT0 9.1.29 LINT[1:0] 9.1.30 LOCK# (I/O) 9.1.31 L2_SENSE 9.1.32 LINT1 9.1.33 PICCLK 9.1.34 PICD[1:0] (I/O).93 9.1.35 PM[1:0]# 9.1.36 PRDY# 9.1.37 PREQ# (I).93 9.1.38 PWREN[1:0] (I).93 9.1.39 PWRGOOD (I).93 9.1.40 REQ[4:0]# (I/O) 9.1.41 RESET# 9.1.42 (I/O) 9.1.43 RS[2:0]# 9.1.44 RSP# (I).95 9.1.45 SA[2:0] 9.1.46 SELFSB[1:0] (I/O)
Appendix
Pentium® XeonProcessor
9.1.47 SLP# 9.1.48 SMBALERT# (O).96 9.1.49 SMBCLK 9.1.50 SMBDAT (I/O) 9.1.51 SMI# 9.1.52 STPCLK# (I).97 9.1.53 (I).97 9.1.54 9.1.55 9.1.56 TEST_25_A62 9.1.57 TEST_VCC_CORE_XXX (I).97 9.1.58 THERMTRIP# 9.1.59 9.1.60 TRDY# 9.1.61 TRST# 9.1.62 VID_L2[4:0], VID_CORE[4:0](O).98 9.1.63 Signal Summaries
Figures
Timing Diagram Clock Ratio Signals.15 Logical Schematic Clock Ratio Sharing. Curve nMOS Device.23 BCLK, PICCLK, Generic Clock Waveform. SMBCLK Clock Waveform Valid Delay Timings Setup Hold Timings.30 Mode BCLK PICCLK Timing.30 System Reset Configuration Timings. Power-On Reset Configuration Timings.31 Test Timings (Boundary Scan).32 Test Reset Timings BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins. High AGTL+ Receiver Ringback Tolerance. Non-AGTL+ Overshoot/Undershoot, Settling Limit, Ringback Stop Clock State Machine.38 Logical Schematic SMBus Circuitry Thermal Plate View Plate Flatness Reference.51 Interface Agent Dispensing Areas Thermal Plate Temperature Measurement Points Technique Measuring TPLATE with Angle Attachment Technique Measuring TPLATE with Angle Attachment Guideline Locations Cover Temperature (TCOVER) Thermocouple Placement Isometric View Pentium® XeonProcessor S.E.C. Cartridge S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure S.E.C. Cartridge Retention Enabling Details (Notes follow Figure S.E.C. Cartridge Retention Enabling Details.59 Side View Connector Mating Details.60
Pentium® XeonProcessor
View Cartridge Insertion Pressure Points Front View Connector Mating Details.61 Boxed Pentium® XeonProcessor.71 Side View Space Requirements Boxed Processor Front View Space Requirements Boxed Processor Front Views Boxed Processor with Attached Auxiliary (Not Included with Boxed Processor) Front View Boxed Processor Heatsink with Attach Features (Fan Included).75 Cross-sectional View Grommet Attach Features Heatsink (Grommet Shown) Side View Space Recommendation Auxiliary Front View Space Recommendations Auxiliary Boxed Processor Fan/Heatsink Power Cable Connector Description.77 Hardware Components ITP.79 AGTL+ Signal Termination with Individual Buffering Scheme System Preferred Debug Port Layout PWRGOOD Relationship Power-On
Tables
Core Frequency System Multiplier Configuration.14 Core Voltage Identification Definition Pentium® XeonProcessor System Groups.18 Pentium® XeonProcessor Absolute Maximum Ratings Voltage Specifications Current Specifications AGTL+ Signal Groups, Specifications Processor Core.23 CMOS, TAP, Clock APIC Signal Groups, Specifications Processor Core SMBus Signal Group, Specifications Processor Core Pentium® XeonProcessor Internal Parameters AGTL+ Bus.25 System Specifications (Clock) Processor Core.25 AGTL+ Signal Groups, System Specifications Processor Core.26 CMOS, TAP, Clock APIC Signal Groups, Specifications Processor Core System Specifications (Reset Conditions) System Specifications (APIC Clock APIC I/O) Processor Core.27 System Specifications (TAP Connection) Processor Core SMBus Signal Group, Specifications Edge Fingers BCLK Signal Quality Specifications Simulation Processor Core.33 AGTL+ Signal Groups Ringback Tolerance Specifications Processor Core.34 AGTL+ Overshoot/Undershoot Guidelines Processor Core.35 Tolerant Signal Overshoot/Undershoot Guidelines Processor Core35 Signal Ringback Specifications 2.5V Tolerant Signal Simulation Processor Core Processor Information Format Current Address Read SMBus Packet Random Address Read SMBus Packet
Pentium® XeonProcessor
Byte Write SMBus Packet Write Byte SMBus Packet Read Byte SMBus Packet.45 Send Byte SMBus Packet Receive Byte SMBus Packet SMBus Packet Command Byte Assignments.45 Thermal Sensor Status Register Thermal Sensor Configuration Register.47 Thermal Sensor Conversion Rate Register Thermal Sensor SMBus Addressing Pentium® XeonProcessor. Memory Device SMBus Addressing Pentium® XeonProcessor Thermal Design Power Example Thermal Solution Performance Thermal Plate Power Watts. Signal Listing Order Number Signal Listing Order Name Boxed Processor Heatsink Dimensions Fan/Heatsink Power Signal Specifications. Debug Port Pinout Description Requirements BR[3:0]# Signals Rotating Interconnect, 4-Way System. BR[3:0]# Signals Rotating Interconnect, 2-Way System. Agent Configuration.89 Output Signals Input Signals1 Signals (Single Driver).100 Signals (Multiple Driver) .100
Pentium® XeonProcessor
IntroductioThe Pentium Xeon processor follow-on Pentium Pentium® Xeon processors. Pentium Xeon processor, like Pentium Pentium Xeon processors, implements Dynamic Execution micro-architecture unique combination multiple branch prediction, data flow analysis, speculative execution. This enables Pentium Xeon processors deliver higher performance than Pentium® processor, while maintaining binary compatibility with previous Intel Architecture processors. Pentium Xeon processor available 512K, 1MB, cache options. Pentium Xeon processor, like Pentium Xeon processor, executes technology instructions enhanced media communication performance. addition, Pentium® processor executes Streaming SIMD Extensions enhanced floating point application performance.The Pentium Xeon processor also utilizes Single Edge Contact Cartridge (S.E.C.C.) package technology first introduced Pentium® processor. This packaging technology allows Pentium Xeon processors implement Dual Independent Architecture have 2-MBytes level cache. Like Pentium Pentium Xeon processors, level cache communication occurs full speed processor core. Pentium Xeon processor extends concept processor identification with addition processor serial number. Refer Intel® Processor Serial Number more detailed information implementation Intel processor serial number. significant feature Pentium Xeon processor, from system perspective, built-in direct multiprocessing support. systems with four processors, important consider additional power burdens signal integrity issues supporting multiple loads high-speed bus. Pentium Xeon processor supports both uniprocessor multiprocessor implementations with four processor each local processor bus, system bus. Pentium Xeon processor system operates using GTL+ signaling levels with type buffer utilizing active negation multiple terminations. This logic called Assisted Gunning Transistor Logic, AGTL+. Pentium Xeon processors also deviate from Pentium processor implementing S.E.C. cartridge package supported 330-Contact Slot Connector (SC330). (See Section processor mechanical specifications.) This document provides information allow user design system using Pentium Xeon processors.
Terminology
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. case lines where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', [3:0] `LHLH' also refers High logic level, logic level). term `system bus' refers interface between processor, system core logic other agents. system multiprocessing interface processors, memory I/O. term `cache bus' refers interface between processor cache. cache does connect system bus, accessible other agents system bus. Cache coherency maintained with other agents system through MESI cache protocol supported HIT# HITM# signals.
Pentium® XeonProcessor
term "Pentium Xeon processor" refers cartridge package which interfaces host system board through SC330 Connector. Pentium Xeon processors include processor core, level cache, system termination various system management features. Pentium Xeon processor includes thermal plate cooling solution attachment protective cover.
1.1.1
S.E.C. Cartridge Terminology
following terms used often this document explained here clarification:
Cover processor casing opposite side thermal plate. Pentium® Xeonprocessor SC330 product including internal
components, substrate, thermal plate cover.
cache Integrated static used maintain recently used information. code
locality, maintaining recently used information significantly improve system performance many applications. cache integrated directly processor core.
cache -The cache increases total cache size significantly through
multiple components.
Processor substrate structure which components mounted inside S.E.C.
cartridge (with without components attached).
Processor core processor's execution engine. S.E.C. cartridge processor packaging technology used Pentium Xeoprocessor. S.E.C. short "Single Edge Contact" cartridge.
Thermal plate surface used connect heatsink other thermal solution
processor. Additional terms referred this other related documentation:
Slot Former nomenclature connector that S.E.C. cartridge plugs into, just Retention mechanism mechanical component designed hold processor
SC330 connector.
Pentium® processor uses Socket called 330-Contact Slot Connector (SC330).
SC330 Abbreviation 330-Contact Slot Connector that S.E.C. cartridge plugs
into, just Pentium processor uses Socket
References
reader this specification should also familiar with material concepts presented following documents:
AP-586, Pentium® Processor Thermal Design Guidelines (Order Number 243331) CPU-ID Instruction application note (Order Number 241618) Pentium® XeonProcessor Buffer Models, Viewlogic* XTK* (formally Quad) Format
(Electronic Form)
Pentium® XeonProcessor Power Distribution Guidelines (Order Number 245095) Pentium® XeonProcessor Specification Update (Order Number 244460)
Pentium® XeonProcessor
Pentium® XeonProcessor Support Component Vendor List (http://developer.intel.com/
Intel Architecture Software Developer's Manual (Order Number 243193)
Volume Basic Architecture (Order Number 243190) Volume Instruction Reference (Order Number 243191) Volume III: System Programming Guide (Order Number 243192)
330-Contact Slot Connector (SC330) Design Guidelines (Order Number 244428) DC-DC Converter Design Guidelines (www.developer.intel.com) DC-DC Converter Design Guidelines, (Order Number 243870) Intel® Pentium® Processor Terminator Design Guidelines (Order Number 245099) Pentium® XeonProcessor/Intel 450NX PCIset AGTL+ Layout Guidelines (Order Number 245097) Guidelines (Order Number 245096)
2-Way Pentium XeonProcessor/Intel 440GX AGPset AGTL+ Layout Family Processors Hardware Developer's Manual (Order Number 244001) Pentium® Processor Developer's Manual (Order Number 243502) Pentium® XeonProcessor SMBus Thermal Reference Guidelines (Order Number
245098)
Intel® Processor Serial Number (Order Number 245119)
Most this documentation found Intel's developer's world wide site: www.developer.intel.com.
Electrical Specifications
Pentium® XeonProcessor System
Most Pentium Xeon processor signals variation Pentium processor GTL+ signaling technology. Pentium Xeon processor differs from Pentium processor output buffer implementation. buffers that drive most system signals Pentium Xeon processor actively driven CCCORE clock cycle after high transition improve rise-times reduce noise. These signals should still considered opendrain require termination supply that provides high signal level. Because this specification different from GTL+ specification, referred Assisted Gunning Transistor Logic (AGTL+) this document. AGTL+ logic GTL+ logic compatible with each other both used same system bus. Also refer Pentium® Processor Developer's Manual GTL+ buffer specification. AGTL+ inputs differential receivers which require reference signal (VREF). VREF used receivers determine signal logical logical Pentium Xeon processor generates version VREF. VREF must generated baseboard other devices AGTL+ system bus. Termination used pull high voltage level control signal integrity transmission line. processor contains termination resistors that
Pentium® XeonProcessor
provide termination each Pentium Xeon processor. These specifications assume equivalent AGTL+ loads termination resistors ensure proper timings rising falling edges. test conditions described with each specification. existence termination each processors Pentium Xeon processor system, AGTL+ typically daisy chain topology previous family processor systems. Also Pentium Xeon processors, timing specifications defined points internal processor packaging. Analog signal simulation system required when developing Pentium Xeon processor based systems ensure proper operation over conditions. Pentium® XeonProcessor Buffer Models available simulation. 2-Way Pentium® XeonProcessor/Intel® 440GX AGPset AGTL+ Layout Guidelines Pentium® XeonProcessor/Intel® 450NX PCIset AGTL+ Layout Guidelines contain information possible layout topologies other information analog simulation.
Power Ground Pins
operating voltage processor core cache differ from each other. There groups power inputs Pentium Xeon processor package support this voltage difference between components package. There also five pins defined package core voltage identification (VID_CORE), five pins defined package cache voltage identification (VID_L2). These pins specify voltage required processor core cache respectively. These have been added cleanly support voltage specification variations current future Pentium Xeon processors. signal integrity improvement clean power distribution within S.E.C. package, Pentium Xeon processors have (power) (ground) inputs. pins further divided provide different voltage levels components. VCCCORE inputs processor core account pins, while inputs (1.5 used provide AGTL+ termination voltage processor VCCL2 inputs cache. VCCSMBUS provided SMBus VCCTAP test access port. VCCSMBUS, VCCL2, VCCCORE must remain electrically separated from each other. circuit board, VCCCORE pins must connected voltage island VCCL2 pins must connected separate voltage island island portion power plane that been divided, entire plane). Similarly, pins must connected system ground plane.
Decoupling Guidelines
large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. This causes voltages power planes below their nominal values bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations reduced lifetime component.
2.3.1
Pentium® XeonProcessor VCCCORE
Regulator solutions must provide bulk capacitance with Effective Series Resistance (ESR) system designer must also control interconnect resistance from regulator pins) SC330 connector. Simulation required. Bulk decoupling large current swings
Pentium® XeonProcessor
when part powering entering/exiting power states, provided voltage regulation module (VRM) defined DC-DC Converter Design Guidelines DC-DC Converter Design Guidelines. input VCCCORE should capable delivering recommended minimum dICCCORE/dt defined Table while maintaining required tolerances defined Table Pentium® XeonProcessor Power Distribution Guidelines.
2.3.2
Level Cache Decoupling
Regulator solutions need provide bulk capacitance with Effective Series Resistance (ESR) order meet tolerance requirements VCCL2. similar design practices those recommended VCCCORE. Pentium® XeonProcessor Power Distribution Guidelines.
2.3.3
System AGTL+ Decoupling
Pentium Xeon processor contains high frequency decoupling capacitance processor substrate; bulk decoupling must provided system baseboard proper AGTL+ operation. High frequency decoupling necessary SC330 connector further improve signal integrity noise picked connector interface. Pentium® XeonProcessor Power Distribution Guidelines.
System Clock Processor Clocking
BCLK input directly controls operating speed system interface. system timing parameters specified with respect rising edge BCLK input, measured processor core. Pentium Xeon processor core frequency must configured during Reset using A20M#, IGNNE#, LINT[1]/NMI, LINT[0]/INTR pins (see Table value these pins during Reset determines multiplier that Phase Lock Loop (PLL) will internal core clock. Family Processors Hardware Developer's Manual definition these pins during reset operation pins after reset. Note: frequency multipliers supported shown Table other combinations will validated supported Intel. Also, each multiplier only valid product frequency indicated Table Clock multiplying within processor provided internal PLL, requiring constant frequency BCLK input. BCLK frequency ratio cannot changed dynamically during normal operation power modes. BCLK frequency ratio changed when RESET# active, assuming that Reset specifications met.
Table
Core Frequency System Multiplier ConfiguratioMultiplication Processor Core Frequency System Frequency Product Supported Reset only Supported Supported 500, LINT[1] LINT[0] A20M# IGNNE#
Pentium® XeonProcessor
Table
Core Frequency System Multiplier ConfiguratioMultiplication Processor Core Frequency System Frequency 2/11 Reserved 2/13 2/15 Product Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Reset Only LINT[1] LINT[0] A20M# IGNNE#
Figure timing relationship between system multiplier signals, RESET#, normal processor operation. Using CRESET# (CMOS Reset) timing shown Figure circuit Figure used share these configuration signals. component used multiplexer must have outputs that drive higher 2.5V order meet processor's tolerant buffer specifications. multiplexer output current should limited 200mA maximum, case VCCCORE supply processor ever fails. shown Figure pull-up resistors between multiplexer processor force "safe" ratio into processor event that processor powers before multiplexer and/or core logic. This prevents processor from ever seeing ratio higher than final ratio. multiplexer were powered CC2.5, pull-down resistor could used CRESET# instead four pull-up resistors between multiplexer Pentium Xeon processors. this case, multiplexer must designed such that compatibility inputs truly ignored, their state unknown. case, compatibility inputs multiplexer must meet input specifications multiplexer. This require level translation before multiplexer inputs unless inputs signals driving them already compatible. mode operation, these inputs processor must synchronized using BCLK meet setup hold times processors. This require high-speed programmable logic.
Pentium® XeonProcessor
Figure Timing Diagram Clock Ratio Signals
BCLK
RESET#
CRESET#
Ratio Pins#
Final Ratio
Final Ratio
Compatibility
Figure Logical Schematic Clock Ratio Sharing
A20M# IGNNE# LINT1/NMI LINT0/INTR
Processors
Ratio:
CRESET#
Note:
Signal Integrity issues require this circuit modified.
2.4.1
Mixing Processors
Mixing components different internal clock frequencies supported been validated Intel. Operating system support with mixed frequency components should also considered. Also, Intel does support validate operation processors with different cache sizes. Intel only supports validates multi-processor configurations where processors operate with same system core frequencies have same cache sizes. Pentium Xeon processors with different cache components, same cache size validated supported. Similarly, Intel does support validate mixing Pentium Xeon processors Pentium Xeon processors same system bus, regardless frequency cache sizes.
Pentium® XeonProcessor
Voltage IdentificatioThe Pentium Xeon processor contains five voltage identification pins core voltage selection five voltage identification pins cache voltage selection. These pins used support automatic selection both power supply voltages. VID_CORE[4:0] controls voltage supply processor core VID_L2[4:0] controls voltage supply cache. Both same encoding shown Table They driven signals, either open circuit short circuit VSS. combination opens shorts defines voltage required processor core cache. pins support variations processor core voltage specifications cache implementations among processors Pentium Xeon processor family. Table shows recommended range values support both processor core cache. this table refers open refers short ground. definition provided below superset definition previously defined Pentium processor (VID4 used Pentium processor) common Pentium Pentium Xeon processor, Pentium Xeon processors. power supply must supply voltage that requested must disable itself. ensure system ready Pentium Xeon processors, system should support those voltages indicated with bold Table Supporting smaller range will risk ability system migrate possible higher performance processors future. Support wider range provides more flexibility acceptable.
Table
Core Voltage Identification Definition (Sheet
Processor Pins VID4 VID3 VID2 VID1 VID0 Reserved 1.80 1.85 1.90 1.95 2.00 2.05 Core3
00110b 01111b
Pentium® XeonProcessor
Table
Core Voltage Identification Definitio
(Sheet
Processor Pins VID4 VID3 VID2 VID1 VID0 core Core3
NOTES Processor connected VSS, Open processor; pulled baseboard. DC-DC Converter Design Guidelines and/or DC-DC Converter Design Guidelines. output should disabled CCCORE values less than 1.80V. Required
Note:
`11111' (all opens) used detect absence processor core given slot long power supply used does affect these lines. Detection logic pull-ups should affect inputs power source. (See Section 9.0.) pins should pulled TTL-compatible level with external resistors power source regulator only required regulator external logic monitoring VID[4:0] signals. power source chosen must guaranteed stable whenever supply voltage regulator stable. This will prevent possibility processor supply going above VCCCORE event failure supply lines. case DC-to-DC converter, this accomplished using input voltage converter line pull-ups. resistor greater than equal used connect signals converter input. DC-DC Converter Design Guidelines and/or DC-DC Converter Design Guidelines further information.
System Unused Pins Test Pins
RESERVED_XXX pins must remain unconnected. Connection RESERVED_XXX pins VCCCORE, VCCL2, VSS, VTT, each other, other signal result component malfunction incompatibility with future members Pentium Xeon processor family. Section listing processor edge connector location each reserved pin. TEST_25_A62 must connected 2.5V pull-up resistor between TEST_VCC_CORE must each connected individually VCCCORE through (approximately) resistor. TEST_VTT pins must each connected individually with ~150 resistor. TEST_VSS pins must each connected individually with resistor. PICCLK must always driven with valid clock input, PICD[1:0] lines must pulled-up even when APIC will used. separate pull-up resistor (keep trace short) required each PICD line. reliable operation, always connect unused inputs appropriate signal level. Unused AGTL+ inputs should left connects; AGTL+ termination processor provides high level. Unused active CMOS inputs should connected 2.5V with resistor. Unused active high CMOS inputs should connected ground (VSS). Unused outputs left unconnected. resistor must used when tying bi-directional signals power ground.
Pentium® XeonProcessor
When tying signal power ground, resistor will also allow system testability. correct operation when using logic analyzer interface, refer Section design considerations.
System Signal Groups
order simplify following discussion, system signals have been combined into groups buffer type. system outputs should treated open drain require high level source provided externally termination pull-up resistor. AGTL+ input signals have differential input buffers, which reference level. AGTL+ output signals require termination 1.5V. nthis document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. AGTL+ buffers employ active negation clock cycle after assertion improve rise times. CMOS, Clock, APIC, inputs each driven from ground 2.5V. CMOS, APIC, outputs open drain should pulled high 2.5V.This ensures only correct operation current Pentium Xeon processors, compatibility future Pentium Xeon processor products well. There active negation CMOS outputs. ~150 resistors expected PICD[1:0] lines. Timings specified into load resistance defined timing tables. Section design considerations debug equipment. SMBus signals should driven using standard CMOS logic levels.
Table
Pentium® XeonProcessor System Groups
Group Name AGTL+ Input AGTL+ Output AGTL+ CMOS Input CMOS Output System Clock APIC Clock APIC
Signals BPRI#, BR[3:1]#1, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:03]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1, D[63:00]#, DBSY#, DEP[7:0]#, DRDY#, FRCERR, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#, SLP#2, STPCLK# FERR#, IERR#, THERMTRIP#2 bclk picclk picd[1:0] tck, tdi, tms, trst#
Input Output
SMBDAT, SMBCLK, SMBALERT#, VCCCORE, VCCL2, VCCTAP CCSMBUS, VID_L2[4:0], VID_CORE[4:0], VSS, TEST_25_A62, TEST_VCC_CORE, TEST_VSS, PWR_EN[1:0] RESERVED_XXX, SA[2:0], SELFSB[1:0]
SMBus Interface Power/Other
Pentium® XeonProcessor
NOTES BR0# only BREQ# signal that bi-directional. internal BREQ# signals mapped onto pins based processor's agent Section more information. information these signals, Section 9.0. These signals specified 2.5V operation. VCCCORE power supply Pentium® Xeonprocessor core. VCCL2 power supply cache memory. VID_CORE[4:0], VID_L2[4:0] pins described Table used AGTL+ termination. system ground. VCCTAP theTAP supply. VCCSMBUS supply. Reserved pins must left unconnected. connect each other. Test Pins described Section 2.6. Other signals described Section 9.0.
2.7.1
Asynchronous Synchronous System Signals
AGTL+ signals synchronous BCLK. CMOS, Clock, APIC, signals applied asynchronously BCLK, except when running processors pair. Synchronization logic required signals going both processors order mode. logic used while processor running pair, signals should therefore appropriate inactive levels operation. Also note timing requirements mode operation. With enabled, PICCLK must frequency BCLK, synchronized with respect BCLK, must always BCLK specified Table Figure APIC signals synchronous PICCLK. signals synchronous TCK. SMBus signals synchronous SMBCLK. SMBCLK always asynchronous other clocks.
Test Access Port (TAP) ConnectioDepending voltage levels supported other components Test Access Port (TAP) logic, recommended that Pentium Xeon processors first chain followed other components within system. voltage translation buffer should used drive next device chain unless component used that capable accepting 2.5V input. Similar considerations must made TCK, TMS, TRST#. Multiple copies each signal required multiple voltage levels needed within system. Note: pulled CCTAP with ~150 Pentium Xeon processor cartridge. open drain signal driving this must able deliver sufficient current drive signal low. Also, resistor should exist system design this would parallel with this resistor Debug Port described Section 8.0. Debug Port must placed start chain with first component coming from Debug Port from last component going Debug Port. system, cautious when including empty SC330 connector scan chain. connectors scan chain must have processor termination card installed complete chain between system must support method bypass empty connectors; SC330 terminator substrates should directly TDO. (See Section more details.)
Pentium® XeonProcessor
Maximum Rating
Table contains Pentium Xeon processor stress ratings. Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table
Pentium® XeonProcessor Absolute Maximum Ratings
Symbol TSTORAGE VCCCORE VCCL2 VSMBUS VCCTAP VCCL2 VCCCORE VinGTL VinCMOS VinSMBus IPWR_EN IVID Parameter Processor storage temperature Processor core supply voltage with respect processor supply voltage with respect processor supply voltage with respect processor supply voltage with respect supply voltage with respect core voltage. AGTL+ buffer input voltage with respect CMOS APIC buffer input voltage with respect SMBus buffer input voltage with respect PWR_EN[1:0] current current -0.5 -0.5 -0.3 -0.3 -(Core Operating Voltage -0.3 -0.3 -0.1 Operating voltage Operating voltage Operating voltage Operating Voltage VCCCORE Unit Notes
NOTES: Operating voltage voltage which component designed operate. Table This parameter specifies that processor will immediately damaged either supply being disabled.
2.10
Processor Specifications
voltage current specifications provided Table Table defined processor edge fingers. processor signal specifications Table Table Table defined Pentium Xeon processor core. Each signal trace between processor edge finger processor core carries small amount current finite resistance. current produces voltage drop between processor edge finger core. Simulations should therefore versus these specifications processor core. Section processor edge finger signal definitions Table signal grouping.
Pentium® XeonProcessor
Most signals Pentium Xeon processor system AGTL+ signal group. These signals specified terminated VTT. specifications these signals listed Table ease connection with other devices, Clock, CMOS, APIC, SMBus signals designed interface non-AGTL+ levels. specifications these pins listed Table Table Note: Unless otherwise noted, each specification applies Pentium Xeon processors. Where differences exist between Pentium Xeon processors, look table entries identified "FMB" order design Flexible Mother Board (FMB) capable accepting types Pentium Xeon processors. Specifications only valid while meeting specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter Table Voltage Specifications
Symbol VCCCORE VCCCORE Tolerance, Static VCCCORE Tolerance, Transient VCCL2 Parameter processor core products Processor core voltage static tolerance edge fingers Processor core voltage transient tolerance edge fingers second level cache 0MHz 12KB 0MHz 0MHz 0MHz 12KB 0MHz 0MHz VCCL2 Tolerance, Static VCCL2 Tolerance, Transient VCCSMBUS VCCTAP Static tolerance edge fingers second level cache supply Transient tolerance edge fingers second level cache supply AGTL+ termination voltage SMBus supply voltage supply voltage -0.085 -0.085 1.8-2.1 2.00 0.085 Unit Notes
-0.130
0.130
1.8-2.8 0.085
-0.125
0.125
1.365 3.135 2.375
1.50 2.50
1.635 3.465 2.625
V±5% V±5%
NOTES Unless otherwise noted, specifications this table apply processor frequencies cache sizes. "FMB" suggested design guideline flexible baseboard design. VCCCORE supplies processor core. refers range possible points expect future Pentium® Xeonprocessors. These voltages targets only. variable voltage source should exist systems event that different voltage required. Section more information. Typical Voltage specification along with Tolerance specifications provide correct voltage regulation processor. VCCL2 supplies cache. This parameter measured processor edge fingers. must held 1.5V ±9%. recommended that held 1.5V while Pentium Xeon processor system idle. This parameter measured processor edge fingers. SC330
Pentium® XeonProcessor
connector specified have self-inductance maximum, pin-to-pin capacitance (maximum MHz), average contact resistance over pins maximum. These tolerance requirements, ross 20MHz bandwidth, processor edge fingers. requirements processor edge fingers account voltage drops (and impedance discontinuities) processor edge fingers processor core. Voltage must return within static voltage specification within after transient event. SC330 connector specified have selfinductance maximum, pin-to-pin capacitance (maximum MHz), average contact resistance maximum order function with Intel specified voltage regulator module (VRM 8.3). Contact Intel testing details these parameters. 100% tested. Specified design characterization.
Table
Current Specifications
Symbol ICCCORE Parameter processor core 0MHz 0MHz ICCL2 second level cache FMB1 0MHz, 12KB 0MHz, 0MHz, 0MHz 12KB 0MHz 0MHz IVTT ISGnt ICCSLP dlccCORE/dt dlccL2/dt Termination voltage supply current Stop Grant processor core Sleep processor core Core slew rate SC330 connector pins Second level cache slew rate SC330 connector pins 0MHz 0MHz dlCCVTT/dt ICCTAP ICCSMBUS Termination current slew rate SC330 connector pins power supply SMBus power supply A/µs
16.0 14.0 15.4
Unit
Notes
A/µs A/µs
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. "FMB" suggested design guideline flexible baseboard design. ICCCORE supplies processor core. theTypical Voltage specification with Tolerance specifications provide correct voltage regulation processor. must held 1.5V ±9%. recommended that held 1.5V while Pentium Xeonprocessor system idle. This measured processor edge fingers. typical ICCCORE measurements average current draw during execution Winstone* under Windows* operating system. These numbers meant guideline only, guaranteed specification. Actual measurements will vary based upon system environmental conditions configuration. measurements measured nominal voltage under maximum signal loading conditions. Voltage regulators designed with minimum equivalent internal resistance ensure that output voltage, maximum current output, greater than nominal (i.e., typical) voltage level CCCORE (VCCCORE_TYP). this case, maximum current level regulator, CCCOR_REG, reduced from specified maximum current CCCORE_MAX calculated equation: ICCCORE_REG ICCCORE_MAX VCCCORE_TYP (VCCCORE_TYP+ VCCCORE static tolerance) This current required single Pentium Xeon processor. similar current drawn through termination resistors each load AGTL+ bus. decoupled S.E.C. cartridge such that
Pentium® XeonProcessor
negative current flow active pull-up VCCCORE Pentium Xeon processor will seen processor fingers. current specified also AutoHALT state. 10.Maximum values specified design/characterization nominal SC330 connector pins. 11.Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested.
Table
AGTL+ Signal Groups, Specifications Processor Core
Symbol RONN RONP VOHTS Parameter Input Voltage Input High Voltage nMOS Resistance pMOS Resistance Output High Voltage Tri-state Leakage Current Output Leakage Current -0.3 +0.1 -0.1 VCCCORE 12.5 ±100 Unit Notes
NOTES Processor core parameter correlated into resistor Excursions above VCCCORE allowed. VCCCORE 5%). VOUT VCCCORE 5%). processor core drives high only clock cycle. then drives tri-states outputs. specified Table 100% tested. Specified design characterization. This specification corresponds OL_MAX 0.49 when taken into effective load
Figure Curve nMOS Device
0.12
0.08
0.06
0.04
0.02
Vout
Pentium® XeonProcessor
Table
CMOS, TAP, Clock APIC Signal Groups, Specifications Processor Core
Symbol Parameter Input Voltage Input High Voltage Output Voltag Output High Voltage Output Current Input Leakage Current Output Leakage Current -0.3 2.625 2.625 ±100 Unit maximum Measured 24mA outputs open-drai 2.5V Notes
NOTES: 2.62 5V). VOUT 2.62 5V).
Table
SMBus Signal Group, Specifications Processor Core
Symbol IOL2 Parameter Input Voltage Input High Voltage Output Voltage Output Current Output Current Input Leakage Current Output Leakage Current -0.3 VCCSMBUS VCCSMBUS 3.465 Unit Except SMBALERT# SMBALERT#
Notes
maximum
SMBALERT# open drain signal.
2.11
AGTL+ System Specifications
Table below lists parameters controlled within Pentium Xeon processor taken into consideration during simulation. valid high levels determined input buffers using reference voltage (VREF) which generated internally processor cartridge from VTT. VREF should same level other AGTL+ logic using voltage divider baseboard. important that baseboard impedance specified held ±10% tolerance, that intrinsic trace capacitance AGTL+ signal group traces known wellcontrolled. more details AGTL+, 2-Way Pentium XeonProcessor/Intel® 440GX AGPset AGTL+ Layout Guidelines Pentium® XeonProcessor/ Intel® 450NX PCIset AGTL+ Layout Guidelines. Also refer Pentium® Processor Developer's Manual GTL+ buffer specification.
Pentium® XeonProcessor
Table Pentium® XeonProcessor Internal Parameters AGTL+
Symbol VREF Parameter Termination Resistor Reference Voltage Units Notes
NOTES Pentium Xeonprocessor contains AGTL+ termination resistors signal trace processor substrate. VREF generated processor substrate.
2.12
System Specifications
system timings specified this section defined Pentium Xeon processor core pins unless otherwise noted. Timings tested processor core during manufacturing. Timings processor edge fingers specified design characterization. Information regarding signal characteristics between processor core pins processor edge fingers found Pentium® XeonProcessor Buffer Models, Viewlogic* XTK* Format. Section Pentium Xeon processor edge connector signal definitions. Note: Timing specifications T45-T49 reserved future use. system specifications AGTL+ signal group relative rising edge BCLK input. AGTL+ timings referenced both logic levels unless otherwise specified.
Table System Specifications (Clock) Processor Core
Parameter 90.00 90.00 9.98 10.00 10.0 100.0 100.20 100.00 11.11 11.11 Unit Figure Notes @>2.0 @<0.5 (0.5 V-2.0 (2.0 V-0.5
System Frequency System Frequency BCLK Period BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time
NOTES Table shows supported ratios each processor. Minimum System Frequency 100% tested. Specified design characterization allow lowe speed system operation load systems. Applies 500MHz products. Applies 550MHz product. BCLK period allows +0.3 tolerance clock driver routing variation. BCLK must within specification whenever PWRGOOD asserted. recommended that clock driver used that designed meet period stability specification into test load Cycle-to-cycle jitter should measured adjacent rising edges BCLK crossing 1.25 processor core. This cycle-to-cycle jitter present must accounted component flight time between processor(s) and/or core logic components. Positive negative jitter
Pentium® XeonProcessor
allowed between adjacent cycles. Positive negative jitter tolerated, will result AGTL+ CMOS timing degradation (i.e., timing parameters T7-9 T11-13 will increase ps). Thus system with jitter would need flight times that (100 additional jitter timing degradation both source receiver) better than system with jitter clock driver's closed loop jitter bandwidth should less than -20dB). bandwidth must allow cascade connected PLL-based devices track clock drivers with specified jitter. Therefore bandwidth clock driver's output frequency-attenuation plot should less than measured attenuation point. test load should 2-Way Pentium® XeonProcessor/Intel® 440GX AGPset AGTL+ Layout Guidelines Pentium® XeonProcessor/Intel 450NX PCIset AGTL+ Layout Guidelines additional recommendations. 100% tested. Specified design characterization clock driver requirement.
Table AGTL+ Signal Groups, System Specifications Processor Core
Terminated T10: Parameter AGTL+ Output Valid Delay AGTL+ Input Setup Time AGTL+ Input Hold Time RESET# Pulse Width -0.07 1.75 0.62 1.00 Unit Figure Notes
NOTES: These specifications tested during manufacturing. Valid delay timings these signals processor core correlated into mination 1.5V with .5V. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. signal processor core must transition monotonically through overdrive region (2/3 200mV). After ratio A20M#, IGNNE# LINT[1:0] stable, CCCORE, VCCL2 BCLK within specification, PWRGOOD asserted. Figure
Table CMOS, TAP, Clock APIC Signal Groups, Specifications Processor Core
T11: T12: T13: T14: Parameter CMOS Output Valid Delay CMOS Input Setup Time CMOS Input Hold CMOS Input Pulse Width, except PWRGOOD LINT[1:0] Unit BCLKs BCLKs BCLKs Figure Active Inactive states Notes
T14B: LINT[1:0] Input Pulse Width T15: PWRGOOD Inactive Pulse Width
NOTES: These specifications tested during manufacturing. These signals driven asynchronously must driven synchronously mode Valid delay timings these signals specified o100W 2.5V. ensure recognition specific clock, setup hold times with respect BCLK must met. INTR only valid when local APIC disabled. LINT[1:0] only valid when local APIC enabled. This specification only applies when APIC enabled LINT1 LINT0 configured edge triggered interrupt with fixed delivery, otherwise specification applies. When driven inactive after CCCORE, VCCL2 BCLK become stable. PWRGOOD must remain below VIL_MAX from Table until voltage planes meet voltage tolerance specifications Table
Pentium® XeonProcessor
BCLK BCLK specifications Table least clock cycles. PWRGOOD must rise glitch-free monotonica 2.5V. BCLK signal meets specification withi 150ns turning then PWRGOOD Inactive Pulse Width specification waived BCLK start after PWRGOOD asserted. PWRGOOD must still remain below VIL_MAX until voltage planes meet voltage tolerance specifications.
Table System Specifications (Reset Conditions)
T16: T17: T18: T19: T20: Parameter Reset Configuration Signals (A[14:05]#, BR0#, FLUSH#, INIT#) Setup Time Reset Configuration Signals (A[14:05]#, BR0#, FLUSH#, INIT#) Hold Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time Unit BCLKs BCLKs BCLKs BCLKs Figure Notes Before deassertion RESET After clock that deasserts RESET# Before deassertion RESET# After assertion RESET# After clock that deasserts RESET#
Reset, clock ratio defined these signals must safe value (their final lower multiplier) within this delay unless PWRGOOD being driven inactive.
Table System Specifications (APIC Clock APIC I/O) Processor Core
T21: Parameter PICCLK Frequency 30.0 12.0 12.0 0.25 0.25 10.0 33.3 500.0 Unit Figure Notes
T21B: Mode BCLK PICCLK Offset T22: T23: T24: T25: T26: T27: T28: T29: PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time PICD[1:0] Valid Delay
NOTE: These specifications tested during manufacturing. With enabled PICCLK must BCLK synchronized with respect BCLK. Referenced PICCLK rising edge. open drain signals, valid delay synonymous with float delay. Valid delay timings these signals specif 2.5V.
Pentium® XeonProcessor
Table System Specifications (TAP Connection) Processor Core
T30: T31: T32: T33: T34: T35: T36: T37: T38: T39: T40: T41: T42: T43: T44: Parameter Frequency Period High Time Time Rise Time Fall Time TRST# Pulse Width TDI, Setup Time TDI, Hold Valid Delay Float Dela Non-Test Outputs Valid Delay Non-Test Inputs Setup Time Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 60.0 25.0 25.0 40.0 14.0 10.0 25.0 25.0 25.0 16.667 Unit Figure
Notes
@1.7 @0.7 (0.7 V-1. (1.7 V-0. Asynchronous
NOTES: Unless otherwise noted, these specifications tested during manufacturing. 100% tested. Specified design characterization. added maximum rise fall times every 1MHz below 16.667MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal spec ified 2.5V. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals operations. During Debug Port operation, normal specified timings rather than signal timings.
Table SMBus Signal Group, Specifications Edge Fingers
T50: T51: T52: T53: T54: T55: T56: T57: T58: T59:
Parameter SMBCLK Frequency SMBCLK Period SMBCLK High Time SMBCLK Time SMBCLK Rise Time SMBCLK Fall Time SMBus Output Valid Delay SMBus Input Setup Time SMBus Input Hold Time Free Time
Unit
Figure
Notes
Minimum time allowed between request cycles.
Pentium® XeonProcessor
Figure through Figure used conjunction with specification timings tables. Figure BCLK, PICCLK, Generic Clock Waveform
Clock
T25, (Rise Time) T26, (Fall Time) T23, (High Time) T24, (Low Time) T22, (BCLK, PICCLK, TCK, Period)
1.25
Figure SMBCLK Clock Waveform
SCLK 2.46V 0.84V
2.97V 0.84V
Figure Valid Delay Timings
Clock Signal Valid Valid
T11, (Valid Delay) T14, (Pulse Wdith)
GTL+ signal group; 1.25V CMOS, APIC signal groups
Pentium® XeonProcessor
Figure Setup Hold Timings
Clock
Vclk
Signal
Valid
T12, (Setup Time) T13, (Hold Time) AGTL+ signal group; 1.25V CMOS, APIC signal groups Vclk 1.25V BCLK, PICCLK
Figure Mode BCLK PICCLK Timing
BCLK
1.25
PICCLK
1.25
T21B (FRC Mode BCLK PICCLK offset)
Pentium® XeonProcessor
Figure System Reset Configuration Timings
BCLK
RESET#
Configuration (A20M#, IGNNE#, LINT[1:0]) Configuration (A[14:5]#, BR0#, FLUSH#, INIT#)
Safe
Valid Valid
(GTL+ Input Hold Time) (GTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
Figure Power-On Reset Configuration Timings
BCLK
CORE
PWRGOOD
RESET# Configuration (A20M#, IGNNE#, LINT[1:0])
Valid Ratio (PWRGOOD Inactive Pulse Width) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Pentium® XeonProcessor
Figure Test Timings (Boundary Scan)
1.25V
TDI, Non-Test Input Signals
1.25V
Non-Test Output Signals
(All Non-Test Inputs Setup Time) (All Non-Test Inputs Hold Time) (TDO Float Delay) (TDI, Setup Time) (TDI, Hold Time) (TDO Valid Delay) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Delay)
Figure Test Reset Timings
TRST# 1.25V (TRST# Pulse Width)
Signal Quality
Signals driven Pentium Xeon processor system should meet signal quality specifications ensure that components read data properly ensure that incoming signals affect long term reliability component. Specifications provided simulation processor core. Meeting specifications processor core Table through Table ensures that signal quality effects will adversely affect processor operation.
Pentium® XeonProcessor
System Clock Signal Quality Specifications
Table describes signal quality specifications processor core Pentium Xeon processor system clock (BCLK) signal. Figure shows signal quality waveform system clock processor core pads. Please Table definition numbers Table definition numbers.
Table BCLK Signal Quality Specifications Simulation Processor Core
Parameter BCLK BCLK Absolute Voltage Range Rising Edge Ringback Falling Edge Ringback -0.7 Unit Figure
Notes
NOTES Unless otherwise noted, specifications this table apply Pentium® Xeonprocessor frequencies cache sizes. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Figure BCLK, TCK, PICCLK Generic Clock Waveform Processor Core Pins
AGTL+ Signal Quality Specifications
Many scenarios have been simulated generate AGTL+ layout guidelines which available 2-Way Pentium® XeonProcessor/Intel 440GX AGPset AGTL+ Layout Guidelines Pentium® XeonProcessor/Intel 450NX PCIset AGTL+ Layout Guidelines. Also refer Pentium® Processor Developer's Manual specification GTL+ buffer specification.
Pentium® XeonProcessor
3.2.1
AGTL+ Ringback Tolerance Specifications
Table provides AGTL+ signal quality specifications Pentium Xeon processors simulating signal quality processor core pads. Figure describes signal quality waveform AGTL+ signals processor core pads. more information AGTL+ interface, Pentiu Processor Developer's Manual.
Table AGTL+ Signal Groups Ringback Tolerance Specifications Processor Core
Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Squarewave Ringback
0.50
Unit
Figure
Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium® Xeonprocessor frequencies cache sizes. Specifications edge rate V/ns. values specified design characterization. Ringback below supported. Intel recommends performing simulations using (rho) -100 allow margin other sources system noise.
Figure High AGTL+ Receiver Ringback Tolerance
2/3V +0.2 2/3V
2/3V -0.2
1.25V
Vstart Clock
Time Note: High case analogous.
3.2.2
AGTL+ Overshoot/Undershoot Guidelines
overshoot/undershoot guideline limits transitions beyond fast signal edge rates. (Overshoot shown Figure non-AGTL+ signals also applied AGTL+ signals.) processor damaged repeated overshoot undershoot events great enough. overshoot/undershoot guideline shown Table
Pentium® XeonProcessor
Table AGTL+ Overshoot/Undershoot Guidelines Processor Core
Guideline Overshoot Undershoot Transition Signal Must Maintain -0.7 Unit Figure
Non-AGTL+ Signal Quality Specifications
There three signal quality parameters defined non-AGTL+ signals: overshoot/undershoot, ringback, settling limit. three signal quality parameters shown Figure nonAGTL+ signal group processor core pads.
Figure Non-AGTL+ Overshoot/Undershoot, Settling Limit, Ringback
Overshoot Settli
ng-Edge ngback
oltage
ing-Edge ngback
Settli
ndershoot
3.3.1
Tolerant Buffer Overshoot/Undershoot Guidelines
overshoot/undershoot guideline limits transitions beyond fast signal edge rates. (See Figure non-AGTL+ signals.) processor damaged repeated overshoot undershoot events tolerant buffers great enough. overshoot/undershoot guideline shown Table
Table Tolerant Signal Overshoot/Undershoot Guidelines Processor Core
Guideline Overshoot Undershoot Transition Signal Must Maintain -0.3 Unit Figure
3.3.2
Tolerant Buffer Ringback SpecificatioThe ringback specification voltage receiving that signal rings back after achieving maximum absolute value. (See Figure illustration ringback.) Excessive ringback cause false signal detection extend propagation delay. Violations signal ringback specification allowed tolerant signals. Table shows signal ringback specifications tolerant signals used simulations processor core.
Pentium® XeonProcessor
Table Signal Ringback Specifications 2.5V Tolerant Signal Simulation Processor Core
Input Signal Group Non-AGTL+ Signals Non-AGTL+ Signals Transition Maximum Ringback (with Input Diodes Present) Unit Figure
3.3.3
Tolerant Buffer Settling Limit Guideline
Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed total signal swing (VHI VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Processor Feature
Functional Redundancy Checking Mode
Pentium Xeon processor agents configured (functional redundanc checking) pair. this configuration, processor acts master other acts checker, pair operates single processor. checker agent detects mismatch between internally sampled outputs master processor's outputs, checker asserts FRCERR. FRCERR observation enabled master processor with software. master enters machine check FRCERR provided that Machine Check Execution enabled. proper synchronization signals when operating mode, Section 9.1.23. operation supported mode. Systems configured implement mode must write processors' internal MSRs deterministic values before performing either read read-modify-write operation using these registers. following list MSRs that initialized processors' reset sequences. fixed variable MTRRs, Machine Check Architecture (MCA) status registers, Microcode Update signature register, Cache initialization MSRs.
Pentium® XeonProcessor
Power States Clock Control
Pentium Xeon processor allows Auto HALT, Stop-Grant, Sleep states reduce power consumption stopping clock specific internal sections processor, depending each particular state. There Deep Sleep state Pentium Xeon processor. Refer following sections power states Pentium Xeon processor. processor fully realize current consumption Stop Grant, Sleep states, must set. 02AH (Hex), must (power default `0') processor stop internal clocks during these modes. more information, Intel Architecture Software Developer's Manual, Volume III: System Programming Guide. being able recognize transactions during Sleep state, systems allowed have more processors Sleep state other processors Normal Stop Grant states simultaneously.
4.2.1
Normal State- State
This normal operating state processor
4.2.2
Auto Halt Power Down State State
Auto HALT power state entered when Pentium Xeon processor executes HALT instruction. processor will issue normal HALT cycle BE[7:0]# REQ[4:0]# when entering this state. processor will transition Normal state upon occurrence SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR). RESET# will cause processor immediately initialize itself. SMI# will cause processor execute handler. return from handler either Normal Mode Auto HALT Power Down state. Chapter Intel Architecture Software Developer's Manual, Volume III: System Programming Guide. FLUSH# will serviced during Auto HALT state. on-chip first level caches external second level cache will flushed processor will return Auto HALT state. A20M# will serviced during Auto HALT state; processor will mask physical address (A20#) before look-up either on-chip first level caches external second level cache, before read/write transaction driven bus. system generate STPCLK# while processor Auto HALT Power Down state. processor will generate Stop Grant cycle when enters Stop Grant state from HALT state. processor enters Stop Grant state from Auto HALT state, STPCLK# signal must deasserted before interrupts serviced (see below). When system deasserts STPCLK# interrupt signal, processor will return execution HALT state. processor will generate HALT cycle when re-enters HALT state from Stop Grant state.
Pentium® XeonProcessor
Figure Stop Clock State Machine
HALT Instruction HALT Cycle Generated Auto HALT Power Down State BCLK running. Snoops interrupts allowed. INIT#, BINIT#, INTR, NMI, SMI#, RESET# Normal State Normal execution.
STPC
Snoop Event Occurs Snoop Event Serviced
STPC
rted
De-a ssert
STPCLK# Asserted
STPCLK# De-asserted
HALT/Grant Snoop State BCLK running. Service snoops caches.
Snoop Event Occurs Snoop Event Serviced
Stop Grant State BCLK running. Snoops interrupts allowed.
SLP# Asserted
SLP# De-asserted
Sleep State BCLK running. snoops interrupts allowed.
4.2.3
Stop-Grant State State
Stop-Grant state Pentium Xeon processor entered when STPCLK# signal asserted. Pentium Xeon processor will issue Stop-Grant Transaction Cycle. Exit latency from this mode BLCK periods after STPCLK# signal deasserted. Since AGTL+ signal pins receive power from system bus, these pins should driven (allowing level return VTT) minimum power drawn termination resistors this state. addition, other input pins system should driven inactive state. BINIT# will serviced while processor Stop-Grant state. event will latched serviced software upon exit from Stop-Grant state. FLUSH# will serviced during Stop Grant state. RESET# will cause processor immediately initialize itself; processor will stay Stop Grant state. transition back Normal state will occur with deassertion STPCLK# signal. transition HALT/Grant Snoop state will occur when processor detects snoop phase system bus. transition Sleep state will occur with assertion SLP# signal. While Stop Grant State, other interrupts will latched Pentium Xeon processor, only serviced when processor returns Normal State.
Pentium® XeonProcessor
4.2.4
Halt/Grant Snoop State State
Pentium Xeon processor will respond snoop phase transactions (initiated ADS#) system while Stop-Grant state Auto HALT Power Down state. When snoop transaction presented upon system bus, processor will enter HALT/Grant Snoop state. processor will stay this state until snoop system been serviced (whether processor another agent system bus). After snoop serviced, processor will return Stop-Grant state Auto HALT Power Down state, appropriate.
4.2.5
Sleep State State
Sleep state very power state which processor maintains context, maintains PLL, stopped internal clocks. Sleep state only entered from Stop-Grant state. Once Stop-Grant state (verified termination Stop-Grant transaction cycle), SLP# asserted, causing Pentium Xeon processor enter Sleep state. system must wait BCLK cycles after completion Stop-Grant cycle before SLP# asserted. system, processors must complete Stop Grant cycle before subsequent BCLK wait assertion SLP# occur. processor Sleep state BCLKs after assertion SLP# pin. latency exit Sleep state BCLK cycles. SLP# recognized Normal, Auto HALT States. Snoop events that occur during transition into Sleep state will cause unpredictable behavior. Therefore, transactions should blocked system logic during these transitions. Sleep state, processor incapable responding snoop transactions latching interrupt signals immediately after assertion SLP# (one exception RESET# which causes processor re-initialize itself). system core logic must detect these events deassert SLP# signal (and subsequently deassert STPCLK# signal interrupts) processor correctly interpret transaction signal transition. Once Sleep state, SLP# deasserted another asynchronous event occurs. transitions assertions signals allowed system while Pentium Xeon processor Sleep state. transition input signal (with exception SLP# RESET#) before processor returned Stop Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop Grant State. RESET# driven active while processor Sleep State normal operation desired, SLP# STPCLK# should deasserted immediately after RESET# asserted.
4.2.6
Clock Control
Pentium Xeon processor provides clock signal Cache. processor does stop this clock second level cache during Auto HALT Power Down Stop-Grant states. During Auto HALT Power Down Stop-Grant states, processor will continue process snoop phase system cycle. PICCLK signal should removed during Auto HALT Power Down Stop-Grant states. When processor Sleep state, will respond interrupts snoop transactions. PICCLK removed during Sleep state.
Pentium® XeonProcessor
processor will enter power states until internal queues second level cache empty. When re-entering Normal state, processor will resume processing external cache requests soon requests encountered.
System Management (SMBus) Interface
Pentium Xeon processor includes SMBus interface which allows access several processor features, including memory components (referred Processor Information Scratch EEPROM) thermal sensor Pentium Xeon processor substrate. These devices their features described below. Pentium Xeon processor SMBus implementation uses clock data signals SMBus specification. does implement SMBSUS# signals.
Figure Logical Schematic SMBus Circuitry
VCC_SMB
Core TDIODEA TDIODEC
Processor Information
STBY#
Thermal Sensing Device
ALERT#
Scratch EEPROM
A159 A162 A163
B148 SMBDATA B161 SMBCLK B160 SMBALERT# A151
NOTE:
Actual implementation vary. general understanding architecture.
Pentium® XeonProcessor
4.3.1
Processor Information
electrically programmed read-only memory with information about Pentium Xeon processor provided processor substrate. This information permanently write-protected. Table shows data fields formats provided memory.
Table Processor Information Format (Sheet
Offset/Section HEADER: PROCESSOR: Bits CORE: CACHE: Function Data Format Revision EEPROM Size Processor Data Address Processor Core Data Address Cache Data Address Cartridge Data Address Part Number Data Address Thermal Reference Data Addres Feature Data Address Other Data Address Reserved Checksum S-spec/QDF Number Sample/Production Reserved Checksum Processor Core Type Processor Core Family Processor Core Model Processor Core Steppin Reserved Maximum Core Frequency Core Voltage Core Voltage Tolerance, Core Voltage Tolerance, Reserved Checksum Reserved Cache Size Number SRAM Components Reserved Cache Voltage Notes 4-bit digits Size bytes (MSB first) Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Reserved future byte checksum 8-bit ASCII characters Sample only Reserved future byte checksum From CPUID From CPUID From CPUID From CPUID Reserved future 16-bit binary number MHz) Voltage Edge finger tolerancein Edge finger tolerancein Reserved future byte checksum Reserved future 16-bit binary number Kbytes 4-bit digit Reserved future Voltage
Pentium® XeonProcessor
Table Processor Information Format (Sheet
Offset/Section CARTRIDGE: PART NUMBERS: THERMAL REF.: FEATURES: Function Cache Voltage Tolerance, High Cache Voltage Tolerance, Cache/Tag Stepping Reserved Checksu Cartridge Revision Substrate Rev. Software Reserved Checksu Processor Part Number Processor Processor Electronic Signature Reserved Checksu Thermal Reference Byte Reserved Checksu Processor Core Feature Flags Notes Edge finger tolerancein Edge finger tolerancein 4-bit digit Reserved future byte checksu Four 8-bit ASCII characters 2-bit revision number Reserved future byte checksu Seven 8-bit ASCII characters Fourteen 8-bit ASCII characters 64-bit processor number Reserved future byte checksu below Reserved future byte checksu From CPUID Serial Signature Electronic Signature Present Thermal Sense Device Present Thermal Reference Byte Present EEPROM Present Core Present Cache Present
Cartridge Feature Flags
OTHER:
Number Devices inTAP Chain Reserved Checksu Reserved
4-bit digit Reserved future byte checksu Reserved future
4.3.2
Scratch EEPROM
Also available SMBus EEPROM which used other data system processor vendor's discretion. data this EEPROM, once programmed, writeprotected asserting active-high signal. This signal weak pull-down allow EEPROM programmed systems with implementation this signal. Scratch EEPROM 1024 part.
Pentium® XeonProcessor
4.3.3
Processor Information Scratch EEPROM Supported SMBus Transactions
Processor Information responds three SMBus packet types: current address read, random address read, sequential read. Scratch EEPROM responds additional packet types: byte write page write. Table diagrams current address read. internal address counter keeps track address accessed during last read write operation, incremented one. Address "roll over" during reads from last byte last eight byte page first byte first page. "Roll over" during writes from last byte current eight byte page first byte same page. Table diagrams random read. write with data loads address desired read. Sequential reads begin with current address read random address read. After SMBus host controller receives data word responds with acknowledge. This will continue until SMBus host controller responds with negative acknowledge stop. Table diagrams byte write. page write operates same byte write except that SMBus host controller does send stop after first data byte acknowledge. Scratch EEPROM internally increments address. SMBus host controller continues transmit data bytes until terminates sequence with stop. data bytes will result acknowledge from Scratch EEPROM. more than eight bytes written internal address will "roll over" previous data will overwritten. tables, represents SMBus start bit, represents stop bit, represents read bit, represents write bit, represents acknowledge, represents negative acknowledge. shaded bits transmitted Processor Information Scratch EEPROM, bits that aren't shaded transmitted SMBus host controller. tables data addresses indicate bits. SMBus host controller should transmit bits, there only addresses, most significant don't care.
Table Current Address Read SMBus Packet
Device Address bits Data bits
Table Random Address Read SMBus Packet
Device Address bits Data Address bits Device Address bits Data bits
Table Byte Write SMBus Packet
Device Addres bits Data Addres bits Data bits
4.3.4
Thermal Sensor
Pentium Xeon processor's thermal sensor provides means acquiring thermal data from processor with exceptional degree precision. thermal sensor composed control logic, SMBus interface logic, precision analog-to-digital converter, precision current source. thermal sensor drives small current through junction thermal diode located same silicon processor core. forward bias voltage generated across
Pentium® XeonProcessor
thermal diode sensed precision converter derives single byte thermal reference data, "thermal byte reading." System management software running processor microcontroller acquire data from thermal sensor thermally manage system. Upper lower thermal reference thresholds individually programmed thermal diode. Comparator circuits sample register where single byte thermal data (thermal byte reading) stored. These circuits compare single byte result against programmable threshold bytes. alert signal Pentium Xeon processor SMBus (SMBALERT#) will assert when either threshold crossed. increase usefulness thermal diode thermal sensor, Intel added procedure manufacturing test flow Pentium Xeon processor. This procedure determines Thermal Reference Byte programs into Processor Information ROM. Thermal Reference Byte uniquely determined each unit. procedure causes each unit dissipate maximum power (which vary from unit unit) while same time maintaining thermal plate maximum specified operating temperature. Correctly used, this feature permits efficient thermal solution while preserving data integrity. thermal byte reading used conjunction with Thermal Reference Byte Processor Information ROM. Byte Processor Information contains address this byte, described more detail Section 4.3.1. thermal byte reading from thermal sensor compared this Thermal Reference Byte provide indication difference between temperature processor core instant thermal byte reading temperature processor core under steady state conditions high power maximum TPLATE specifications. nominal precision least significant thermal byte 1°C. Reading thermal sensor explained Section 4.3.5. Pentium® XeonProcessor SMBus Thermal Reference Guidelines more details further recommendations this feature Pentium Xeon processor-based systems. thermal sensor feature processor cannot used measure TPLATE. TPLATE specification Section must regardless reading processor's thermal sensor order ensure adequate cooling entire Pentium Xeon processor. thermal sensor feature only available while VCCCORE VCCSMBUS valid levels processor low-power state.
4.3.5
Thermal Sensor Supported SMBus Transactions
thermal sensor responds five SMBus packet types: write byte, read byte, send byte, receive byte, Alert Response Address (ARA). send byte packet used sending oneshot commands only. receive byte packet accesses register commanded last read byte packet. receive byte packet preceded write byte send byte packet more recently than read byte packet, then behavior undefined. Table through Table diagram five packet types. these figures, represents SMBus start bit, represents stop bit, `Ack' represents acknowledge, `///' represents negative acknowledge. shaded bits transmitted thermal sensor, bits that aren't shaded transmitted SMBus host controller. Table shows encoding command byte.
Pentium® XeonProcessor
Table Write Byte SMBus Packet
Address bits Write Command bits Data bits
Table Read Byte SMBus Packet
Addres bits Write Command bits Addres bits Read Data bits
Table Send Byte SMBus Packet
Addres bits Write Command bits
Table Receive Byte SMBus Packet
Address bits Read Data bits
Table SMBus Packet
0001 Read Address Device Address
This 8-bit field. device which sent alert will respond Packet with address seven most significant bits. least significant undefined return `0'. Section 4.3.7 details Thermal Sensor Device addressing.
Table Command Byte Assignments (Sheet
Register RESERVED RESERVED RESERVED RRHL RRLL RESERVED Command Reset State 0000 0000 0000 0010 0111 1111 1100 1001 0111 1111 1100 1001 Function Reserved future Read processor core thermal data Read status byte (flags, busy signal) Read configuration byte Read conversion rate byte Reserved future Reserved future Read processor core thermal diode HIGH limit Read processor core thermal diode limit Write configuration byte Write conversion rate byte Reserved future
Pentium® XeonProcessor
Table Command Byte Assignments (Sheet
Register RESERVED WRHL WRLL OSHT RESERVED Command Reset State Function Reserved future Write processor core thermal diode THIGH limit Write processor core thermal diode TLOW shot command (use send byte packet) Reserved future
commands reading writing registers thermal sensor except one-shot command (OSHT). one-shot command forces immediate start conversion cycle. conversion progress when one-shot command received, then command ignored. thermal sensor standby mode when one-shot command received, conversion performed sensor returns standby mode. one-shot command supported when thermal sensor auto-convert mode. default command after reset reserved value (00h). After reset, receive byte packets will return invalid data until another command sent thermal sensor.
4.3.6
4.3.6.1
Thermal Sensor Register
Thermal Reference Registers
processor core thermal sensor internal thermal reference registers contain thermal reference value thermal sensor processor core thermal diodes. This value ranges from +127 -128 decimal expressed two's complement, eight-bit number. These registers saturating, i.e., values above represented decimal, values below -128 represented -128 decimal.
4.3.6.2
Thermal Limit Registers
thermal sensor thermal limit registers; they define high limits processor core thermal diode. encoding these registers same thermal reference registers. diode thermal value equals exceeds limits, then alarm Status Register triggered.
4.3.6.3
Status Register
status register shown Table indicates which any) thermal value thresholds have been exceeded. also indicates conversion progress open circuit been detected processor core thermal diode connection. Once set, alarm bits stay until they cleared status register read. successful read status register will clear alarm bits that have been set, unless alarm condition persists.
Pentium® XeonProcessor
Table Thermal Sensor Status Register
(MSB) (LSB) Name BUSY RESERVED RESERVED RHIGH RLOW RESERVED RESERVED Function indicates that device's analog digital converter busy converting. Reserved future Reserved future indicates that processor core thermal diode high temperature alarm activated. indicates that processor core thermal diode temperature alarm activated. indicates open fault connection processor core diode. Reserved future use. Reserved future use.
4.3.6.4
Configuration Register
configuration register controls operating mode (standby auto-convert) thermal sensor. Table shows format configuration register. RUN/STOP (high) then thermal sensor immediately stops converting enters standby mode. thermal sensor will still perform analog digital conversions standby mode when receives one-shot command. RUN/STOP clear (low) then thermal sensor enters auto-conversion mode.
Table Thermal Sensor Configuration Register
(MSB) Name RESERVED RUN/STOP RESERVED Reset State Reserved future use. Standby mode control bit. high, device immediately stops converting, enters standby mode. low, device converts either one-shot mode automatically updates timed basis. Reserved future use. Functio
4.3.6.5
Conversion Rate Register
contents conversion rate register determine nominal rate which analog digital conversions happen when thermal sensor auto-convert mode. Table shows mapping between conversion rate register values conversion rate. indicated Table conversion rate register default state (0.2 nominally) when thermal sensor powered There ±25% error tolerance between conversion rate indicated conversion rate register actual conversion rate.
Pentium® XeonProcessor
Table Thermal Sensor Conversion Rate Register
Register Contents Conversion Rate (Hz) 0.0625 0.125 0.25 Reserved future
4.3.7
SMBus Device Addressing
addresses broadcast across SMBus, memory components claim those form "1010XXYZb". "XX" bits used enable devices cartridge adjacent addresses. hard-wired cartridge (`0') Scratch EEPROM pulled VCCSMBUS (`1') Processor Information ROM. "XX" bits defined processor slot pins SC330 connector. These address pins pulled down weakly ensure that memory components known state systems which support SMBus, only support partial implementation. read/write serial transaction. thermal sensor internally decodes upper address patterns from form "0011XXXZb", "1001XXXZb" "0101XXXZb". device's addressing, implemented, uses includes Hi-Z state address pin. Therefore thermal sensor supports unique resulting addresses. Hi-Z state SA2, must left floating. system should drive SA0, will pulled driven) pulldown resistor processor substrate. Attempting drive either these signals Hi-Z state would cause ambiguity memory device address decode, possibly resulting devices responding, thus timing hanging SMBus. before, read/write serial transaction. Note: Addresses form "0000XXXXb" Reserved should generated SMBus master. thermal sensor latches signals power System designers should ensure that these signals valid input levels (see Table before thermal sensor powers This should done pulling pins VCCSMBUS smaller resistor. Additionally, left unconnected achieve tri-state state. designer desires drive with logic designer must ensure that pins valid input levels (see Table before VCCSMBUS begins ramp. system designer must also ensure that their particular system implementation does excessive capacitance (>50 address inputs. Excess capacitance address inputs cause address recognition problems. Figure shows logical diagram connections. Table Table describe address connections they affect addressing devices.
Pentium® XeonProcessor
Table Thermal Sensor SMBus Addressing Pentium XeonProcessor
Address (Hex) Upper Address1 0011 0011 0101 0101 1001 1001 Slot Selec
8-bit Address Word Serial b[7:0] 0011000Xb 0011010Xb 0101001Xb 0101011Xb 1001100Xb 1001110Xb
NOTES Upper address bits decoded conjunction with select pins. tri-state state this achieved leaving this unconnected.
Note:
System management software must aware slot number-dependent changes address thermal sensor.
Table Memory Device SMBus Addressing Pentium® XeonProcessor
Address (Hex) Upper Address bits A0h/A1h A2h/A3h A4h/A5h A6h/A7h A8h/A9h Aah/Abh Ach/Adh Aeh/Afh 1010 1010 1010 1010 1010 1010 1010 1010 Slot Select (SA1) (SA0) Memory Device Selec Device Addressed
Scratch EEPROM Processor Information Scratch EEPROM Processor Information Scratch EEPROM Processor Information Scratch EEPROM Processor Information
Though this addressing scheme targeted 4-way systems, more processors supported using multiplexed separate) SMBus implementation.
Thermal Specifications Design ConsideratioThe Pentium Xeon processor will thermal plate heatsink attachment. thermal plate interface intended provide multiple types thermal solutions. This chapter will provide necessary data thermal solution developed. Figure thermal plate location.
Pentium® XeonProcessor
Figure Thermal Plate View
Thermal Specifications
This section provides power dissipation specifications each variation Pentium Xeon processor. thermal plate flatness also specified S.E.C. cartridge.
5.1.1
Power DissipatioTable provides thermal design power dissipation Pentium Xeon processors. While processor core dissipates majority thermal power, system designer should also aware thermal power dissipated second level cache. Systems should design highest possible thermal power, even processor with lower frequency smaller second level cache planned. thermal plate attach location thermal solutions. maximum temperature entire thermal plate surface shown Table processor power dissipated through thermal plate other paths. power dissipation combination power from processor core, second level cache AGTL+ termination resistors. overall system thermal design must comprehend total processor power. combined power from processor core second level cache that dissipates through thermal plate thermal plate power. heatsink should designed dissipate thermal plate power. thermal sensor feature processor cannot used measure TPLATE. TPLATE specification must regardless reading processor's thermal sensor order ensure adequate cooling entire Pentium Xeon processor.
Pentium® XeonProcessor
Table Thermal Design Power
Processor Core Frequency (MHz) FMB5 Cache Size 512K 512K Core Power 35.2 28.0 28.0 28.0 30.8 30.8 30.8 Power 21.0 12.0 19.0 11.6 12.4
AGTL+ Power4
Processor Power2 50.0 36.0 44.0 36.2 34.0 34.0 39.5
Thermal Plate Power3 50.0 37.0 45.0 37.1 35.0 35.0 40.5
TPLATE (°C)
TPLATE (°C)
TCOVER (°C)
TCOVER (°C)
NOTES These values specified nominal CCCORE processor core nominal CCL2 cache. Processor power indicates worst case power that dissipated entire processor. This value will determined after product been characterized. possible AGTL+ bus, cache processor core full power simultaneously. combined power that dissipates through thermal plate thermal plate power. This value will determined after product been characterized. value shown follows expectation that virtually power will dissipate through thermal plate. AGTL+ power worst case power dissipated termination resistors AGTL+ bus. "FMB" suggested design guideline flexible baseboard design. Notice that worst case power worst case processor power occur same processor.
5.1.2
Plate Flatness SpecificatioThe thermal plate flatness Pentium Xeon processor specified 0.010" across entire thermal plate surface, with more than 0.003" step anywhere surface plate, shown Figure
Figure Plate Flatness Reference
.003/1.00x1.00
Pentium® XeonProcessor
5.2.1
Processor Thermal Analysis
Thermal Solution Performance
Processor cooling solutions should attach thermal plate. processor cover designed thermal solution attachment. complete thermal solution must adequately control thermal plate cover temperatures below maximum above minimum specified Table performance thermal solution defined thermal resistance between thermal plate ambient around processor (thermal plate ambient). lower thermal resistance between thermal plate ambient air, more efficient thermal solution required thermal plate ambient dependent upon maximum allowed thermal plate temperature (TPLATE), local ambient temperature (TLA) thermal plate power (PPLATE). thermal plate ambient (TPLATE TLA)/PPLATE maximum TPLATE thermal plate power listed Table function system design. Table provides resultant thermal solution performance Pentium Xeon processor maximum power dissipation allowable under constraints different ambient temperatures around processor
Table Example Thermal Solution Performance Thermal Plate Power Watts
Thermal Solution Performance thermal plate ambient (°C/watt) Local Ambient Temperature
thermal plate ambient value made primary components: thermal resistance between thermal plate heatsink (thermal plate heatsink) thermal resistance between heatsink ambient around processor (heatsink air). critical, controllable factor decrease resultant value thermal plate heatsink management thermal interface between thermal plate heatsink. other controllable factor (heatsink air) determined design heatsink airflow around heatsink. General Information thermal interfaces heatsink design constraints found AP-586, Pentium® Processor Thermal Design Guidelines.
5.2.2
Thermal Plate Heat Sink Interface Management Guide
Figure shows suggested interface agent dispensing areas when using Intel suggested interface agent. Actual user area interface agent selections will determined system issues meeting TPLATE requirements.
Pentium® XeonProcessor
Figure Interface Agent Dispensing Areas Thermal Plate Temperature Measurement Points
1.960 .980
NOTES Interface agent suggestions: ShinEtsu* G749 Thermoset* TC330; Dispense volume adequate ensure required minimum area coverage when cooling solution attached. Areas suggested 512-Kbyte cache product areas 1-Mbyte 2-Mbyte cache products. Recommended cooling solution mating surface flatness greater than 0.007" flatter. Temperature entire thermal plate surface exceed specification. combination interface agent, cooling solution, flatness condition, etc., ensure this condition met. Thermocouple measurement locations expected high temperature locations without external heat source influence. Ensure that external heat sources cause violation PLATE requirements
5.2.3
5.2.3.1
Measurements Thermal Specifications
Thermal Plate Temperature Measurement
ensure functional reliable processor operation, processor's thermal plate temperature (TPLATE) must maintained below maximum TPLATE above minimum TPLATE specified Table Power from processor core cache transferred thermal plate locations 512-Kbyte cache product locations 1-Mbyte
Pentium® XeonProcessor
2-Mbyte cache products. Figure shows locations TPLATE measurement directly above these transfer locations. Figure shows locations TCOVER measurement, directly above component locations back side processor substrate. Thermocouples used measure TPLATE special care required ensure accurate temperature measurement. Before taking temperature measurements, thermocouples must calibrated. When measuring temperature surface, errors introduced measurement handled properly. Such measurement errors poor thermal contact between thermocouple junction measured surface, conduction through thermocouple leads, heat loss radiation convection, contact between thermocouple cement heatsink base. minimize these errors, following approach recommended:
gauge finer diameter type thermocouples. Intel's laboratory testing
done using thermocouple made Omega* (part number: 5TC-TTK-36-36).
Attach each thermocouple bead junction surface thermal plate
locations specified Figure using high thermal conductivity cements.
thermocouple should attached angle heatsink attached thermal plate.
heatsink attached thermal plate heatsink does cover location specified TPLATE measurement, thermocouple should attached angle (refer Figure 21).
thermocouple should attached angle heatsink attached thermal
plate heatsink covers location specified PLATE measurement (refer Figure 22).
hole size through heatsink base route thermocouple wires should smaller
than 0.150" diameter
Make sure there contact between thermocouple cement heatsink base. This
contact will affect thermocouple reading. Figure Technique Measuring TPLATE with Angle Attachment
Figure Technique Measuring TPLATE with Angle Attachment
5.2.3.2
Cover Temperature Measurement Guideline
maximum minimum S.E.C. cartridge cover temperature (TCOVER) Pentium Xeon processors specified Table Meeting this temperature specification required ensure correct reliable operation processor. design system, other sources heat convection, conduction radiation should evaluated possible effect cartridge cover temperature. system free from such external sources heat, higher temperature
Pentium® XeonProcessor
areas cover have been characterized illustrated Figure external heat sources present, TCOVER thermal measurements should made these points. cover designed thermal solution attachment. Figure Guideline Locations Cover Temperature (TCOVER) Thermocouple Placement
NOTE: Four thermocouple attach locations ±0.015". Thermocouple measurement locations expected high temperature locations, without external heat source influence. Temperature entire cover surface exceed Ensure that external heat sources cause violation COVER requirements.
Mechanical SpecificatioPentium Xeon processors S.E.C. cartridge package technology. S.E.C. cartridge contains processor core, cache other components. S.E.C. cartridge package connects baseboard through edge connector. Mechanical specifications processor given this section. Section 1.1.1 complete terminology listing. Figure shows thermal plate side view cover side view Pentium Xeon processor. Figure shows Pentium Xeon S.E.C. cartridge cooling solution attachment feature details thermal plate depict package form factor dimensions retention enabling features S.E.C. cartridge. processor edge connector defined this document referred SC330. SC330 connector specifications further details edge connector.
Pentium® XeonProcessor
Table Table provide edge finger SC330 connector signal definitions Pentium Xeon processors. signal locations SC330 edge connector used signal routing, simulation component placement baseboard. Figure Isometric View Pentium® XeonProcessor S.E.C. Cartridge
NOTES: retention holes retention indents optional. 11.For SC330 connector specifications, 330-Contact Slot Connector (SC330) Design Guidelines.
Pentium® XeonProcessor
Figure S.E.C. Cartridge Cooling Solution Attach Details (Notes follow Figure
3.000 .017
2.658 ±.035
Pentium® XeonProcessor
Figure S.E.C. Cartridge Retention Enabling Details (Notes follow Figure
.325 .004 5.350 .008
.125 .002
.280 .009
6.000
+.015 .008
Pentium® XeonProcessor
Figure S.E.C. Cartridge Retention Enabling Details
.277 .174
.919 .010
.189 4.840 .032 (FRONTSIDE HEIGHT)
4.777 .036 4.836 .008 (BACKSIDE HEIGHT)
.287 .016
.150 .010 SECTION
.733 .013 SECTION
NOTES Maximum protrusion mechanical heatsink attach media into cartridge during assembly installed condition exceed 0.160" from external face thermal plate. Specified cover retention indent dimension external indent. Indent walls have degree draft, with wider section external end. Clip extension internal surface retention slots should little possible exceed 0.040". 12.Tapped holes cooling solution attach. torque recommendation screw tapped hole inch-lb.
Pentium® XeonProcessor
Weight
maximum weight Pentium Xeon processor approximately grams.
Cartridge Connector Mating Details
staggered edge connector layout Pentium Xeon processor makes processor susceptible damage from socketing (inserting cartridge while power applied connector). Extra care should taken ensure socketing does occur. electrical mechanical integrity processor edge fingers specified insertion/extraction cycles.
Figure Side View Connector Mating Details
4.995 .036
FULLY INSTALLED
.049 .028 (.144)
NOTES: Dimensional variation when cartridge fully installed substrate bottomed connector. Actual system installed height tolerance subject user's manufacturing tolerance SC330 connector baseboard. Retention devices this cartridge must accommodate this cartridge "Float" relative connector, without preload edge contacts axes. 10.Fully installed dimensions must maintained user's retention device. Cartridge backout from fully installed position exceed 0.020.
Pentium® XeonProcessor
Figure View Cartridge Insertion Pressure Points
Figure Front View Connector Mating Details
.168 .021
NOTE: Retention devices this cartridge must accommodate this cartridge "Float" relative connector, without preload edge contacts axes.
Pentium® XeonProcessor
Pentium® XeonProcessor Substrate Edge Finger Signal Listing
Table Pentium Xeon processor substrate edge finger listing order number Table Pentium Xeon processor substrate edge connector listing order name.
Table Signal Listing Order Number (Sheet
VCC_TAP SELFSB1 SELFSB0 TEST_VSS_A11 IERR# A20M# FERR# IGNNE# PWRGOOD
Name
Signal Buffer Type
Connect Supply Connect Ground AGTL+ Supply AGTL+ Supply CMOS Ground CMOS Ground Pull down CMOS Output Ground CMOS Input CMOS Output Ground CMOS Input Input Ground Output CMOS Input Ground
Name
PWR_EN[1] VCC_CORE RESERVED_B3 TEST_VSS_B4 VCC_CORE VCC_CORE RESERVED_B9 FLUSH# VCC_CORE SMI# INIT# VCC_CORE STPCLK# VCC_CORE SLP# VCC_CORE TRST# RESERVED_B22 VCC_CORE RESERVED_B24 RESERVED_B25 VCC_CORE TEST_VCC_CORE_B27 LINT[1] VCC_CORE PICCLK PICD[1] VCC_CORE BP#[2] RESERVED_B34 VCC_CORE PRDY# BPM#[1]
Signal Buffer Type
Short PWR_EN[0] Core CONNECT Pull down Core AGTL+ Supply AGTL+ Supply Core CONNECT CMOS Input Core CMOS Input CMOS Input Core CMOS Input Clock Core CMOS Input Input Core Input CONNECT Core CONNECT CONNECT Core Pull VCC_CORE CMOS Input Core APIC Clock Input CMOS Core AGTL+ CONNECT Core AGTL+ Output AGTL+
TEST_VCC_CORE_A23 Pull VCC_CORE THERMTRIP# RESERVED_A26 LINT[0] PICD[0] PREQ# BP#[3] BPM#[0] BINIT# DEP#[0] CMOS Output Ground CONNECT CMOS Input Ground CMOS CMOS Input Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground
Pentium® XeonProcessor
Table Signal Listing Order Number (Sheet
Name
DEP#[1] DEP#[3] DEP#[5] DEP#[6] D#[61] D#[55] D#[60] D#[53] D#[57] D#[46] D#[49] D#[51] CPU_SENSE D#[42] D#[45] D#[39] TEST_25_A62 D#[43] D#[37] D#[33] D#[35] D#[31] D#[30] D#[27] D#[24] D#[23] D#[21] D#[16] D#[13]
Signal Buffer Type
AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground Voltage Sense Ground AGTL+ AGTL+ Ground AGTL+ Pull Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+
Name
VCC_CORE DEP#[2] DEP#[4] VCC_CORE DEP#[7] D#[62] VCC_CORE D#[58] D#[63] VCC_CORE D#[56] D#[50] VCC_CORE D#[54] D#[59] VCC_CORE D#[48] D#[52] VCC_CORE L2_SENSE VCC_CORE D#[41] D#[47] VCC_CORE D#[44] D#[36] VCC_CORE D#[40] D#[34] VCC_CORE D#[38] D#[32] VCC_CORE D#[28] D#[29] VCC_CORE D#[26] D#[25] VCC_CORE D#[22] D#[19] VCC_CORE D#[18]
Signal Buffer Type
Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core Voltage Sense Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+
Pentium® XeonProcessor
Table Signal Listing Order Number (Sheet
A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 A115 A116 A117 A118 A119 A120 A121 A122 A123 TEST_VTT_A82 RESERVED_A83 D#[11] D#[10] D#[14] D#[09] D#[08] D#[05] D#[03] D#[01] BCLK TEST_ _A98 BERR# A#[33] A#[34] A#[30] A#[31] A#[27] A#[22] A#[23] A#[19] A#[18] A#[16] A#[13] A#[14] A#[10] A#[05] A#[09]
Name
Signal Buffer Type
Ground Pull CONNECT Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground System Clock Pull down Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ Ground AGTL+ AGTL+ Ground AGTL+
B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 B117 B118 B119 B120 B121 B122 B123 D#[20]
Name
Signal Buffer Type
AGTL+ Core CONNECT CONNECT Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Core AGTL+ Input AGTL+ Core AGTL+ AGTL+ Core AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ Cache AGTL+ AGTL+ Cache
VCC_CORE RESERVED_B83 RESERVED_B84 VCC_CORE D#[17] D#[15] VCC_CORE D#[12] D#[07] VCC_CORE D#[06] D#[04] VCC_CORE D#[02] D#[00] VCC_CORE RESET# FRCERR VCC_CORE A#[35] A#[32] VCC_CORE A#[29] A#[26] VCC_L2 A#[24] A#[28] VCC_L2 A#[20] A#[21] VCC_L2 A#[25] A#[15] VCC_L2 A#[17] A#[11] VCC_L2 A#[12] VCC_L2 A#[08] A#[07] VCC_L2
Pentium® XeonProcessor
Table Signal Listing Order Number (Sheet
A124 A125 A126 A127 A128 A129 A130 A131 A132 A133 A134 A135 A136 A137 A138 A139 A140 A141 A142 A143 A144 A145 A146 A147 A148 A149 A150 A151 A152 A153 A154 A155 A156 A157 A158 A159 A160 A161 A162 A163 A164 A165
Name
A#[04] RESERVED_A126 BNR# BPRI# TRDY# DEFER# REQ#[2] REQ#[3] HITM# DBSY# RS#[1] BR2# BR0# ADS# AP#[0] VID_CORE[2] VID_CORE[1] VID_CORE[4] SMBALERT# VID_L2[2] VID_L2[1] VCC_SM PWR_EN[0]
Signal Buffer Type
AGTL+ Ground CONNECT AGTL+ Ground AGTL+ Input AGTL+ Input Ground AGTL+ Input AGTL+ Ground AGTL+ AGTL+ Ground AGTL+ AGTL+ Input Ground AGTL+ Input AGTL+ Ground AGTL+ AGTL+ Ground Open Short Open Short Ground Open Short SMBus Aler Ground Open Short Open Short Ground AGTL+ Supply AGTL+ Supply Ground SMBus Input SMBus Supply Ground SMBus Input SMBus Input Ground Short PWR_EN[1]
B124 B125 B126 B127 B128 B129 B130 B131 B132 B133 B134 B135 B136 B137 B138 B139 B140 B141 B142 B143 B144 B145 B146 B147 B148 B149 B150 B151 B152 B153 B154 B155 B156 B157 B158 B159 B160 B161 B162 B163 B164 B165 A#[03] A#[06]
Name
Signal Buffer Type
AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ AGTL+ Cache AGTL+ Input AGTL+ Cache AGTL+ Input AGTL+ Cache AGTL+ Input AGTL+ Input Cache AGTL+ Input AGTL+ Cache SMBus Input Open Short Cache Open Short Open Short Cache Open Short Open Short Cache AGTL+ Supply AGTL+ Supply Cache SMBus Clock SMBus Data Cache CONNECT Connect Connect
VCC_L2 AERR# REQ#[0] VCC_L2 REQ#[1] REQ#[4] VCC_L2 LOCK# DRDY# VCC_L2 RS#[0] HIT# VCC_L2 RS#[2] VCC_L2 BR3# BR1# VCC_L2 RSP# AP#[1] VCC_L2 VID_CORE[3] VCC_L2 VID_CORE[0] VID_L2[0] VCC_L2 VID_L2[4] VID_L2[3] VCC_L2 VCC_L2 SMBCLK SMBDA VCC_L2 RESERVED_B163
Pentium® XeonProcessor
Table Signal Listing Order Name (Sheet
B124 A124 A121 B125 B122 B121 A123 A120 B117 B119 A116 A118 B114 A115 B116 A113 A112 B110 B111 A109 A110 B107 B113 B105 A107 B108 B104 A104 A106 B102 A101 A103 B101 A144 B127 A145 B146 A#[03] A#[04] A#[05] A#[06] A#[07] A#[08] A#[09] A#[10] A#[11] A#[12] A#[13] A#[14] A#[15] A#[16] A#[17] A#[18] A#[19] A#[20] A#[21] A#[22] A#[23] A#[24] A#[25] A#[26] A#[27] A#[28] A#[29] A#[30] A#[31] A#[32] A#[33] A#[34] A#[35] A20M# ADS# AERR# AP#[0] AP#[1] BCLK
Table Signal Listing Order Name (Sheet
A100 A127 A129 A142 B143 A141 B142 BERR# BINIT# BNR# BP#[2] BP#[3] BPM#[0] BPM#[1] BPRI# BR0# BR1# BR2# BR3# CPU_SENSE D#[00] D#[01] D#[02] D#[03] D#[04] D#[05] D#[06] D#[07] D#[08] D#[09] D#[10] D#[11] D#[12] D#[13] D#[14] D#[15] D#[16] D#[17] D#[18] D#[19] D#[20] D#[21] D#[22] D#[23] D#[24] D#[25]
Name
Signal Buffer Type
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ System Clock
Name
Signal Buffer
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+ AGTL+ Input AGTL+ Input AGTL+ Input Voltage Sense AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
Pentium® XeonProcessor
Table Signal Listing Order Name (Sheet
A138 A132 D#[26] D#[27] D#[28] D#[29] D#[30] D#[31] D#[32] D#[33] D#[34] D#[35] D#[36] D#[37] D#[38] D#[39] D#[40] D#[41] D#[42] D#[43] D#[44] D#[45] D#[46] D#[47] D#[48] D#[49] D#[50] D#[51] D#[52] D#[53] D#[54] D#[55] D#[56] D#[57] D#[58] D#[59] D#[60] D#[61] D#[62] D#[63] DBSY# DEFER#
Table Signal Listing Order Name (Sheet
B134 B164 B165 B137 A136 B133 A165 B128 B130 A133 A135 B131 A126
Name
Signal Buffer Type
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input
Name
DEP#[0] DEP#[1] DEP#[2] DEP#[3] DEP#[4] DEP#[5] DEP#[6] DEP#[7] DRDY# FERR# FLUSH# FRCERR HIT# HITM# IERR# IGNNE# INIT# LINT[0] LINT[1] LOCK# L2_SENSE PICCLK PICD[0] PICD[1] PRDY# PREQ# PWR_EN[0] PWR_EN[1] PWRGOOD REQ#[0] REQ#[1] REQ#[2] REQ#[3] REQ#[4] RESERVED_A126 RESERVED_A26
Signal Buffer
AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Connect Connect Connect Connect CMOS Output CMOS Input AGTL+ AGTL+ AGTL+ CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ Voltage Sense APIC Clock Input CMOS CMOS AGTL+ Output CMOS Input Short PWR_EN[1] Short PWR_EN[0] CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ CONNECT CONNECT
Pentium® XeonProcessor
Table Signal Listing Order Name (Sheet
B163 B140 B136 A139 B139 B145 A163 A162 A159 A151 B160 B161 A130
Table Signal Listing Order Name (Sheet
B100 B103 B106 B109 B112 B115 TRST# VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_L2 VCC_L2 VCC_L2 VCC_L2
Name
RESERVED_A83 RESERVED_B163 RESERVED_B22 RESERVED_B24 RESERVED_B25 RESERVED_B3 RESERVED_B34 RESERVED_B83 RESERVED_B84 RESERVED_B9 RESET# RS#[0] RS#[1] RS#[2] RSP# SELFSB0 SELFSB1 SLP# SMBALERT# SMBCLK SMBDA SMI# STPCLK# TEST_25_A62 TEST_VCC_CORE_A23 TEST_VCC_CORE_B27 TEST_VSS_A11 TEST_VSS_A98 TEST_VSS_B4 TEST_VTT_A82 THERMTRIP# TRDY#
Signal Buffer Type
CONNECT CONNECT CONNECT CONNECT CONNECT CONNECT CONNECT CONNECT CONNECT CONNECT AGTL+ Input AGTL+ AGTL+ Input AGTL+ Input AGTL+ Input AGTL+ Input SMBus Input SMBus Input SMBus Input CMOS CMOS CMOS Input SMBus Aler SMBus Clock SMBus CMOS Input CMOS Input Clock Input Output Pull Pull VCC_CORE Pull VCC_CORE Pull down Pull down Pull down Pull CMOS Output Input AGTL+ Input
Name
Signal Buffer
Input Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Core Cache Cache Cache Cache
Pentium® XeonProcessor
Table Signal Listing Order Name (Sheet
B118 B120 B123 B126 B129 B132 B135 B138 B141 B144 B147 B150 B153 B156 B159 B162 A160 B151 A148 A147 B149 A150 B152 A154 A153 B155 B154 A102 A105 A108 A111 A114 A117 A119 A122 A125 A128
Table Signal Listing Order Name (Sheet
A131 A134 A137 A140 A143 A146 A149 A152 A155 A158 A161 A164
Name
VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_L2 VCC_SM VCC_TAP VID_CORE[0] VID_CORE[1] VID_CORE[2] VID_CORE[3] VID_CORE[4] VID_L2[0] VID_L2[1] VID_L2[2] VID_L2[3] VID_L2[4]
Signal Buffer Type
Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache Cache SMBus Supply Supply Open Short Open Short Open Short Open Short Open Short Open Short Open Short Open Short Open Short Open Short Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
Name
Signal Buffer
Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground Ground
Pentium® XeonProcessor
Table Signal Listing Order Name (Sheet
A156 A157 B157 B158 B148
Name
Signal Buffer Type
Ground Ground Ground AGTL+ Supply AGTL+ Supply AGTL+ Supply AGTL+ Supply AGTL+ Supply AGTL+ Supply AGTL+ Supply AGTL+ Supply SMBus Input
Pentium® XeonProcessor
Boxed Proces
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