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PENTIUM® XEONPROCESSOR with 256KB Cache
Binary compatible with applications running previous members Intel microprocessor family Optimized 32-bit applications running advanced 32-bit operating systems Dynamic Independent architecture: separate dedicated external System dedicated internal cache operating full processor core speed Power Management capabilities System Management mode Multiple low-power states Single Edge Contact (S.E.C.) cartridge packaging; S.E.C. cartridge delivers high performance processing technology mid-range high-end servers workstations. Supports SC330 Interface system speeds data transfer between processor system Integrated high performance16KB instruction 16KB data, nonblocking, level-one cache Available 256KB unified, nonblocking 8-way associative leveltwo cache Enables systems which scaleable processors 64GB physical memory SMBus interface advanced manageability features Streaming SIMD Extensions enhanced video, sound performance
Intel® Pentium® XeonProcessor with 256KB Cache designed midrange high-end servers workstations, binary compatible with previous Intel Architecture processors. Intel Pentium XeonProcessor with 256KB Cache, hereafter referred Pentium Xeon processor MHz+ provides best performance available applications running advanced operating systems such Windows* Windows UNIX*. Pentium Xeon processor MHz+ scalable processors multiprocessor system extends power Pentium processor with features designed make this processor right choice powerful workstation, advanced server management, mission-critical applications. MHz+ Pentium Xeon Processor-based workstations offer memory architecture required most demanding workstation applications workloads. Specific features MHz+ Pentium Xeon Processor address platform manageability meet needs robust environment, maximize system time ensure optimal configuration operation servers. Pentium Xeon processor MHz+ enhances ability server platforms monitor, protect, service processor environment.
Order Number: 245305-004 August 2000
Information this document provided solely enable Intel products. Intel assumes liability whatsoever, including infringement patent copyright, sale Intel products except provided Intel's Terms Conditions Sale such products. Information contained herein supersedes previously published specifications these devices from Intel.
PENTIUM® XEONPROCESSOR with 256KB Cache
Information this document provided connection with Intel products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have order number referenced this document, other Intel literature, obtained calling 1-800-548-4725, visiting Intel's website http://www.intel.com. Copyright Intel Corporation 1999, 2000. *Third-party brands names property their respective owners.
PENTIUM® XEONPROCESSOR with 256KB Cache TABLE CONTENTS PRODUCT EATURES INTRODUCTION.6 TERMINOLOGY.7 S.E.C. CARTRIDGE TERMINOLOGY. REFERENCES. ELECTRICAL SPECIFICATIONS SYSTEM VREF. POWER GROUND PINS. DECOUPLING GUIDELINES. 3.3.1 VCC_CORE 3.3.2 LEVEL CACHE DECOUPLING.10 3.3.3 SYSTEM AGTL+ DECOUPLING.10 CLOCK FREQUENCIES SYSTEM CLOCK RATIOS. 3.4.2 MIXING PROCESSORS DIFFERENT FREQUENCIES.12 VOLTAGE IDENTIFICATION SYSTEM UNUSED PINS TEST PINS SYSTEM SIGNAL GROUPS. 3.7.2 ASYNCHRONOUS SYNCHRONOUS SYSTEM SIGNALS CCESS PORT (TAP) CONNECTION AXIMUM RATINGS 3.10 PROCESSOR SPECIFICATIONS 3.11 AGTL+ SYSTEM SPECIFICATIONS. 3.12 SYSTEM SPECIFICATIONS. SIGNAL QUALITY.31 CLOCK SIGNAL QUALITY SPECIFICATIONS. AGTL+ SIGNAL QUALITY SPECIFICATIONS. 4.2.1 AGTL+ Ringback Tolerance Specifications.32 4.2.2 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES NON-GTL+ SIGNAL QUALITY SPECIFICATIONS. 4.3.1 2.5V Signal Overshoot/Undershoot Guidelines 4.3.2 BCLK Overshoot/Undershoot Guidelines Specifications.36 4.3.3 Measuring BCLK Overshoot/Undershoot.37 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION 4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE PROCESSOR FEATURES POWER STATES CLOCK CONTROL. 5.1.1 NORMAL STATE STATE 1.39 5.1.2 AUTO HALT POWER DOWN STATE STATE 5.1.3 STOP-GRANT STATE STATE 5.1.4 HALT/GRANT SNOOP STATE STATE 4.40 5.1.5 SLEEP STATE STATE 5.41 5.1.6 CLOCK CONTROL.41 SYSTEM ANAGEMENT (SMBUS) INTERFACE 5.2.1 PROCESSOR INFORMATION ROM.42 5.2.2 SCRATCH EEPROM 5.2.3 PROCESSOR INFORMATION SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS.46 5.2.4 THERMAL SENSOR.47 5.2.5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS 5.2.6 THERMAL SENSOR REGISTERS 5.2.7 SMBus Device Addressing.51 THERMAL SPECIFICATIONS DESIGN CONSIDERATIONS THERMAL SPECIFICATIONS. 6.1.1 POWER DISSIPATION 6.1.2 PLATE FLATNESS SPECIFICATION PROCESSOR THERMAL ANALYSIS. 6.2.1 THERMAL SOLUTION PERFORMANCE.55 6.2.2 THERMAL PLATE HEAT SINK INTERFACE MANAGEMENT GUIDE.56
PENTIUM® XEONPROCESSOR with 256KB Cache 6.2.3 MEASUREMENTS THERMAL SPECIFICATIONS.57 MECHANICAL SPECIFICATIONS EIGHT CARTRIDGE CONNECTOR ATING DETAILS SUBSTRATE EDGE FINGER SIGNAL LISTING. INTEGRATION TOOLS.74 -TARGET PROBE (ITP). 8.1.1 PRIMARY FUNCTION 8.1.2 DEBUG PORT CONNECTOR DESCRIPTION 8.1.3 KEEP CONCERNS.75 8.1.4 ADDITIONAL INTEGRATION TOOL MECHANICAL KEEP OUTS 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS.76 8.1.6 DEBUG PORT SIGNAL NOTES.78 8.1.7 Using Communicate processor.80 LOGIC NALYZER INTERCONNECT (LAI) TRACE CAPTURE TOOL CONSIDERATIONS. 8.2.1 Trace Capture Tool System Design Considerations.81 8.2.1 Trace Capture tool Mechanical Keep Outs.81 BOXED PROCESSOR SPECIFICATIONS INTRODUCTION. ECHANICAL SPECIFICATIONS. 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS 9.2.2 BOXED PROCESSOR HEATSINK WEIGHT.84 9.2.3 BOXED PROCESSOR RETENTION MECHANISM.84 THERMAL SPECIFICATIONS. 9.3.1 Boxed Processor Cooling Requirements.85 9.3.2 Boxed Processor Passive Heatsink Performance 9.3.2 Optional auxiliary attachment.86 APPENDIX 10.1 LPHABETICAL SIGNALS REFERENCE 10.1.1 A[35:03]# (I/O) 10.1.2 A20M# 10.1.3 ADS# (I/O) 10.1.4 AERR# (I/O) 10.1.5 AP[1:0]# (I/O) 10.1.6 BCLK (I).90 10.1.7 BERR# (I/O) 10.1.8 BINIT# (I/O) 10.1.9 BNR# (I/O).90 10.1.10 BP[3:2]# (I/O) 10.1.11 BPM[1:0]# (I/O) 10.1.12 BPRI# (I).90 10.1.13 BR0# (I/O), BR[3:1]# 10.1.14 BR0# (I/O), BR[3:1]# 10.1.15 CORE_AN_SENSE 10.1.16 D[63:00]# (I/O).92 10.1.17 DBSY# (I/O) 10.1.18 DEFER# 10.1.19 DEP[7:0]# (I/O).92 10.1.20 DRDY# (I/O).92 10.1.21 FERR# (O).93 10.1.22 FLUSH# (I).93 10.1.23 HIT# (I/O), HITM# (I/O).93 10.1.24 HV_EN# (O).93 10.1.25 IERR# 10.1.26 IGNNE# 10.1.27 INIT# 10.1.28 INTR LINT[0].94 10.1.29 LINT[1:0] (I).94 10.1.30 LOCK# (I/O) 10.1.31 L2_SENSE.94 10.1.32 OCVR_EN 10.1.33 OCVR_OK(O) 10.1.34 LINT[1].94
PENTIUM® XEONPROCESSOR with 256KB Cache 10.1.35 PICCLK 10.1.36 PICD[1:0] (I/O) 10.1.37 PRDY# (O).95 10.1.38 PREQ# 10.1.39 PWREN[1:0] 10.1.40 PWRGOOD (I).95 10.1.41 REQ[4:0]# (I/O).97 10.1.42 RESET# 10.1.43 (I/O) 10.1.44 RS[2:0]# (I).97 10.1.45 RSP# 10.1.46 SA[2:0] 10.1.47 SELFSB0 SELFSB1 10.1.48 SLP# (I).99 10.1.49 SMBALERT# 10.1.50 SMBCLK 10.1.51 SMBDAT (I/O) 10.1.52 SMI# (I).99 10.1.53 STPCLK# 10.1.54 10.1.55 (I). 10.1.56 10.1.57 TEST_2.5_[A23, A62, B27] 10.1.58 THERMTRIP# (O). 10.1.59 10.1.60 TRDY# (I). 10.1.61 TRST# 10.1.62 VID_L2[4:0], VID_CORE[4:0] 10.1.63 VIN_SENSE. 10.1.64 10.2 SIGNAL SUMMARIES.101
PENTIUM® XEONPROCESSOR with 256KB Cache
INTRODUCTION
Pentium® Xeonprocessor MHz+, like Pentium® Pro, Pentium® Pentium® III, Pentium® Xeonand Pentium® Xeonprocessor's, implements Dynamic Execution micro-architecture, unique combination multiple branch prediction, data flow analysis, speculative execution. Pentium Xeon processor MHz+ available 256K cache size. Pentium® Xeonprocessor improves upon previous generations Intel 32-bit processors adding Streaming SIMD Extensions. Single Instruction Multiple Data (SIMD) extensions significantly accelerate performance graphics. Besides graphics improvements, extensions also include additional integer cacheability instructions that improve other aspects performance. addition, Pentium Xeon processor MHz+ utilizes variation S.E.C. (Single Edge Contact) package technology first introduced Pentium processor. packaging technology allows Pentium Xeon processor MHz+ implement Dual Independent Architecture 256KB level cache. Level cache integrated processing unit communication occurs full speed processor core. with previous members Pentium Xeon processor family, Pentium Xeon processor MHz+ features built-in direct multiprocessing support. systems with processors, important consider additional power burdens signal integrity issues supporting multiple loads high-speed bus. Pentium Xeon processor MHz+ supports both uni-processor multiprocessor implementations with support processing units each local processor bus, system bus. Pentium Xeon processor MHz+ system operates using GTL+ signaling levels with type buffer utilizing active negation multiple terminations. This logic called Assisted Gunning Transistor Logic, AGTL+. Pentium Xeon processor MHz+ uses S.E.C. cartridge package supported SC330 Connector (See Chapter processor mechanical specifications.) Pentium Xeon processor MHz+ includes SMBus interface that allows access several processor features, including memory components (referred processor Information Scratch EEPROM) thermal sensor Pentium Xeon processor MHz+ substrate. Pentium Xeon processor MHz+ system definition uses SC330.1 interface. SC330.1 interface electrical only enhancement SC330 interface that allows supporting dual Pentium Xeon processor MHz+ system running 133Mhz system bus. SC330.1 specification adds required flexibility accommodate control monitoring signals OCVR Cartridge Voltage Regulator). OCVR provides necessary high precision regulation used Intel's latest silicon technology. This document provides information regarding design system using Pentium Xeon processor MHz+ with SC330.1 interface. Certain versions Pentium Xeon processor MHz+ designed compatible with existing Guidelines, allowing easy transition Flexible Mother Board designs. 2.8V Pentium Xeon processor (regardless frequency) designed compatibility with Guidelines. 5/12V Pentium Xeon processor adds flexibility operate either Volts Volts. flexible motherboard specification that incorporates SC330.1 uses same form factor definition existing SC330 processors, adds signals control OCVR remote sensing capabilities. SC330.1 enhancement electrically mechanically compatible with existing baseboards.
PENTIUM® XEONPROCESSOR with 256KB Cache
TERMINOLOGY
TERMINOLOGY
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, non-maskable interrupt occurred. case lines where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', [3:0] `LHLH' also refers High logic level, logic level). term `system bus' refers interface between processor, system core logic other agents. system multiprocessing interface processors, memory I/O. Cache coherency maintained with other agents system through MESI cache protocol supported HIT# HITM# signals. term Pentium Xeon processor MHz+ refers cartridge package that interfaces host system board through SC330.1 connector. Pentium Xeon processor MHz+ includes processor core with integrated cache, OnCartridge Voltage Regulator (OCVR), system termination various system management features. addition, Pentium Xeon processor MHz+ includes thermal plate cooling solution attachment protective cover. Pentium Xeon processor MHz+ system operates using GTL+ signaling levels with type buffer utilizing active negation multiple terminations. This logic called Assisted Gunning Transistor Logic, AGTL+. This document provides information allow user design system using Pentium Xeon processor MHz+.
S.E.C. CARTRIDGE TERMINOLOGY
following terms used this document defined here clarification: Cover processor casing opposite side thermal plate. Pentium® Xeonprocessor MHz+ refers Pentium Xeon Processors that utilize Cartridge Voltage Regulator technology, "OCVR". OCVR regulates CC_CORE (the appropriate cartridge input voltage) required processor core voltage (VCC_CPU). OCVR developed provide necessary regulation guarantee highest possible frequency operation 600+ Pentium Xeon processor. Pentium® Xeonprocessor refers Pentium Xeon Processor 500MHz 550MHz, 100MHz system bus, without OCVR, requires separate CORE voltage sources. (Flexible Motherboard Specification) specifications which design targeted allow forward compatibility with existing future processors. cache Integrated static used maintain recently used information. code locality, maintaining recently used information significantly improve system performance many applications. cache integrated directly processor core. cache -The cache integrated directly processor core Pentium Xeon processor MHz+, located substrate Pentium Xeon processor. 2.8V Pentium Xeon processor refers Pentium Xeon processor MHz+ that powered with +2.8 volts applied VCC_CORE pins. 5/12V Pentium Xeon processor refers Pentium Xeon processor MHz+ that powered with either +5.0 +12.0 volts applied VCC_CORE pins. HV_EN# -pin added SC330.1 definition differentiating 5/12V Pentium Xeon processor from 2.8V Pentium Xeon processor. HV_EN# tied (ground) 5/12V Pentium Xeon processor, high impedance (floating) 2.8V Pentium Xeon processor. This reserved connect) Pentium® Xeonprocessors. Processor substrate structure which components mounted inside S.E.C. cartridge (with without components attached). Processor core processor's execution engine. S.E.C. cartridge processor packaging technology used Pentium Xeon processor family. S.E.C. short "Single Edge Contact" cartridge. Streaming SIMD Extensions instructions supported Intel processors beginning with Pentium® Xeonprocessor. Single Instruction Multiple Data (SIMD) extensions significantly accelerate performance graphics. Besides graphics improvements, extensions also include additional integer cacheability instructions that improve other aspects performance. Thermal plate surface used connect heat sink other thermal solution processor.
Additional terms referred this other related documentation:
PENTIUM® XEONPROCESSOR with 256KB Cache
TERMINOLOGY
processor refers Pentium Xeon processor, Pentium Xeon processor, 600+ Pentium Xeon processor. SC330.1 refers 600+ Pentium Xeon processor's added cartridge functionality. 330.1 interface electrical enhancement interface, supports four processors utilizing system bus, processors utilizing 133MHz system bus. 330.1 interface adds required flexibility accommodate control monitoring signals OCVR. Retention mechanism mechanical component designed hold processor SC330 connector.
References
reader this specification should also familiar with material concepts presented following documents, available from either Intel document center http://developer.intel.com/: Intel Processor Identification CPUID Instruction (Order Number 241618) Pentium® Xeonprocessor Signal Integrity Models, Viewlogic Format Pentium® Xeonprocessor Specification Update (Order Number 244460) SC330 Processor Enabling Technology Vendor List Intel Architecture Software Developer's Manual (Order Number 243193) Volume Basic Architecture (Order Number 243190) Volume Instruction Reference (Order Number 243191) Volume III: System Programming Guide (Order Number 243192) 330-Contact Slot Connector (SC330) Design Guidelines DC/DC converter Guidelines Pentium® Xeonprocessor/Intel® 450NX PCIset AGTL+ Layout Guidelines (Order Number 243790) Pentium® XeonProcessor System Compatibility Guidelines (Order Number 245248) Flexible Motherboard Power Distribution Control Pentium® Xeon Processors (Order Number 245245) Pentium® XeonProcessor MHz+ Thermal Solutions Guidelines (Order Number 245246) Pentium® XeonProcessor MHz+ Guidelines (Order Number 245250)
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
ELECTRICAL SPECIFICATIONS System VREF
Pentium Xeon processor 600MHz+ signals uses variation Pentium processor GTL+ signaling technology. Pentium Xeon processor MHz+ differs from Pentium processor Pentium processor output buffer implementation. buffers that drive most system signals Pentium Xeon processor MHz+ actively driven clock cycle after high transition improve risetimes reduce noise. These signals should still considered open-drain require termination supply that provides high signal level. Because this specification different from standard GTL+ specification, referred Assisted Gunning Transistor Logic (AGTL+) this document. AGTL+ logic GTL+ logic compatible with each other both used same system bus. more information GTL+ specification, Pentium Family Developer's Manual Volume (Order Number 242690). AGTL+ inputs differential receivers that require reference signal (VREF). VREF used receivers determine signal logical logical Pentium Xeon processor MHz+ generates version REF. must generated baseboard other devices AGTL+ system bus. Termination used pull high voltage level control signal integrity transmission line. processor contains oncartridge termination resistors that provide termination AGTL bus. These specifications assume equivalent (FIVE) AGTL+ loads termination resistors ensure proper timings rising falling edges. test conditions described with each specification. Like Pentium Xeonprocessor, timing specifications Pentium Xeon processor MHz+ defined points internal processor packaging. Analog signal simulation system required when developing Pentium Xeon processor MHz+ based systems ensure proper operation over conditions. Pentium® XeonProcessor Signal Integrity Models available simulation.
Power Ground Pins
implementing Cartridge Voltage Regulator (OCVR), Pentium Xeon processor MHz+ eliminates need high precision regulation from flexible baseboard. Note that Pentium Xeon processor MHz+ does require dedicated supply that logic will assume supply required. (Please refer Guidelines details). 2.8V Pentium® Xeonprocessor relies identification pins VCC_ CORE required voltage level ONLY does require separate voltage supply. 5/12V Pentium® Xeonprocessor does require VRM, therefore VID_CORE lines will "open" cartridge (requesting CPU"). signal integrity improvement clean power distribution within S.E.C. package, Pentium Xeon processor MHz+ (power) (ground) inputs (see section complete edge finger signal listing). pins further divided provide different voltage levels components. VCC_CORE inputs processor core account pins, while inputs (1.5V) used provide AGTL+ termination voltage processor. VCC_SMB provided SMBus, VCC_TAP. VCC_SMB, VCC_TAP, VCC_CORE must remain electrically separated from each other. VCC_SMB must connected 3.3V power supply (even SMBus features used) order Pentium Xeon processor MHz+ function properly. baseboard, VCC_CORE pins must connected voltage plane. Similarly, pins must connected system ground plane.
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
Decoupling Guidelines
large number transistors high internal clock speeds, Pentium® Xeonprocessor MHz+ capable generating large average current swings between full power states. This causes voltages power planes below their nominal values bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations reduced lifetime component. 3.3.1 VCC_CORE power input should provide bulk capacitance with Effective Series Resistance (ESR) system designer must also control interconnect resistance from regulator pins) SC330 connector. Simulation required first second order characterization. Bulk decoupling large current swings when part powering entering/exiting power states, provided voltage regulation module (VRM) defined DC-DC Converter Design Guidelines input VCC_ CORE should capable delivering recommended minimum dICCCORE/dt while maintaining required tolerances each which defined Table Flexible Motherboard Power Distribution Control Pentium® Xeon Processors, Order Number 245245. 3.3.2 LEVEL CACHE DECOUPLING Pentium Xeon processor MHz+ does require VCC_L2 pins power.
3.3.3 SYSTEM AGTL+ DECOUPLING Pentium Xeon processor MHz+ contains high frequency decoupling capacitance processor substrate; bulk decoupling system baseboard must provided assure proper AGTL+ operation. High frequency decoupling necessary SC330 connector further improve signal integrity noise picked connector interface.
Clock Frequencies System Clock Ratios
Pentium Xeon processor MHz+ uses clock ratio design which clock multiplied ratio produce processors internal ("core") clock. Pentium Xeon processor MHz+ begins sampling A20M#, IGNNE#, LINT[0], LINT[1] inactive-to-active transition RESET# determine core-frequency busfrequency relationship, immediately begins lock input clock. active-to-inactive transition RESET#, Pentium Xeon processor MHz+ internally latches inputs allow pins used normal functionality. Effectively, these pins must meet large setup time (1mS) active-to-inactive transition RESET# (see RESET# PWRGD relationship figure 41). These pins should then held static least clocks, longer than clocks. Table System Bus-to-Core Frequency Ratio Configuration Ratio BCLK Core Frequency (Safe-LLLL) 2/11 2/13 2/15 (Safe-HHHH) Target Frequency 1000 PWRUP Reg[25:22] 0011 0110 0000 0100 1011 1111 1001 1101 1100 LINT[1] LINT[0] IGNNE# A20M#
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
NOTE: frequency multipliers supported shown Table other combinations will validated supported Intel. Also, each multiplier only valid product frequency indicated Table
Clock multiplying within processor provided internal PLL, requiring constant frequency BCLK input. BCLK frequency ratio cannot changed dynamically during normal operation power modes. BCLK frequency ratio changed when RESET# active, assuming that RESET# specifications met. Figure timing relationship between system multiplier signals, RESET#, normal processor operation. Using CRESET# (CMOS Reset) timing shown Figure circuit Figure used share these configuration signals. component used multiplexer must have outputs that drive higher than 2.5V order meet processor's 2.5V tolerant buffer specifications. shown Figure pull-up resistors between multiplexer processor ohm) force "safe" ratio into processor event that processor powers before multiplexer and/or core logic. This prevents processor from ever seeing ratio higher than final ratio. multiplexer were powered VCC2.5, pull-down resistor could used CRESET# instead four pull-up resistors between multiplexer Pentium® Xeonprocessor MHz+. this case, multiplexer must designed such that compatibility inputs truly ignored, their state unknown. case, compatibility inputs multiplexer must meet input specifications multiplexer. This require level translation before multiplexer inputs unless inputs signals driving them already compatible.
BCLK
RESET#
CRESET#
Ratio Pins#
Final Ratio
Final Ratio
Compatibility
000917
Figure Timing Diagram Clock Ratio Signals
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
A20M# IGNNE# LINT1/NMI LINT0/INTR
Processors
Ratio:
CRESET#
000809 Figure Logical1 Schematic Clock Ratio Sharing NOTES: Signal Integrity issues require this circuit modified. Current Intel chipsets implement CRESET# signal. 3.4.2 MIXING PROCESSORS DIFFERENT FREQUENCIES Mixing components different internal clock frequencies supported been validated Intel. Operating system support multi-processing with mixed frequency components should also considered. Also, Intel does support validate operation processors with different cache sizes. Intel only supports validates multi-processor configurations where processors operate with same system core frequencies have same cache sizes. Similarly, Intel does support validate mixing Pentium® Xeonprocessor MHz+, Pentium® Xeonprocessor, Pentium® Xeonprocessors same system bus, regardless frequency cache sizes.
Voltage Identification
provide power delivery flexibility, Pentium Xeon processor MHz+ available different input voltage versions; version operates Volts other Volts Volts. previous versions Pentium Xeon Pentium Xeon processors, Pentium Xeon processor MHz+ contains five voltage identification (VID) pins, these pins used Pentium Xeon processor MHz+ OCVR voltage selection combination with which incorporates added functionality power delivery schemes. Further details this implementation described Flexible Motherboard Power Distribution Control Pentium® Xeon Processors, Order Number 245245. Pentium Xeon processor MHz+ incorporates (A3, HV_EN#) method identify ability powered power supply. HV_EN# signal used differentiating 5/12V Pentium Xeon processor cartridge from 2.8V Pentium Xeon processor. HV_EN# tied (ground) 5/12V Pentium Xeon processor, high impedance (floating) 2.8V Pentium Xeon processor. This reserved connect) Pentium® Xeonprocessors. Since Cache integrated core, Pentium Xeon processor MHz+ does require code specify cache voltage (the VID_L2 lines Pentium® Xeonprocessor MHz+ left open cartridge). VID_CORE[4:0] controls voltage supply processor, shown Table They driven signals, either open circuit short circuit combination opens shorts defines voltage required processor (the VID_CORE lines 5/12V Pentium® Xeonprocessor left open cartridge). pins support variations processor core voltages among processors SC330 processor family. Table shows
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
recommended range values support processor core. this table refers open refers short ground. definition provided below superset definition previously defined Pentium processor (VID4 used Pentium processor) common Pentium® Xeonprocessor MHz+ (for VCC_ CORE only). power supply must supply voltage that requested must disable itself.
Table Voltage Identification
VID4 NOTES:
processor connected VSS, Open processor; pulled baseboard. DC-DC Converter Design Guidelines and/or DC-DC Converter Design Guidelines output should disabled VCC_CORE values less than 1.80V. Required 2.8V Pentium® Xeonprocessors. Pentium® Xeonprocessor MHz+ does require voltage supply. When installing Pentium Xeon processor MHz+, VCC_L2 VID_L2 lines will "open" cartridge. This setting used combination with HV_EN# (A3) differentiating 2.8V Pentium Xeon processor from 5/12V Pentium Xeon processor cartridges. 5/12V Pentium® Xeonprocessor does require VRM. When installing 5/12V Pentium Xeon processor, VID_CORE lines will "open" cartridge.
VID3
VID2 00110b 01111b
VID1
VID0
VCC_CORE Reserved 1.80 1.85 1.90 1.95 2.00 2.05
core
pins should pulled TTL-compatible level with external resistors power source regulator only required regulator external logic monitoring VID[4:0] signals. power source chosen drive/pull VIDs must guaranteed stable whenever supply voltage regulator non-zero OCVR enabled. invalid while output coming could lead incorrect voltage above VCC_ CORE max. This will prevent possibility processor supply going above VCC_ CORE event failure supply lines. case DC-to-DC converter, this accomplished using input voltage converter line pull-ups. resistor greater than equal ohms used connect signals converter input. DC-DC Converter Design Guidelines further information.
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
System Unused Pins Test Pins
Unless otherwise specified, RESERVED_XXX pins must remain unconnected. Note that pins that newly marked RESERVED this document tied power rail existing baseboards. Connection RESERVED_XXX pins VCC_ CORE, each other other signal result component malfunction incompatibility with future members Pentium® Xeonprocessor MHz+ family. Chapter listing processor edge connector location each reserved pin. TEST_2.5_A62 must connected Volts pull-up resistor between ohms. 5/12V Pentium Xeon processor only, recommended that pins that were previously specified TEST_VCC_CORE_XX (now specified TEST_2.5_XX), connected VCC_2.5 supply through separate resistors baseboard. However, there will damage cartridges existing platforms provide Volts pull-up resistors. TEST_VTT pins must connected supply through individual resistors. TEST_VSS pins must connected individually supply through individual 1K-ohm resistors. PICCLK must always driven with valid clock input, PICD[1:0] lines must pulled-up 2.5V even when APIC will used. separate pull-up resistor 2.5V (keep trace short) required each PICD line. reliable operation, always connect unused inputs appropriate signal level. Unused AGTL+ inputs should left connects; AGTL+ termination processor provides high level. Unused active CMOS inputs should connected 2.5V with ~10K resistor. Unused active high CMOS inputs should connected ground SS). Unused outputs left unconnected. resistor must used when tying bi-directional signals power ground. When tying signal power ground, resistor will also allow system testability. correct operation when using logic analyzer interface, refer Chapter design considerations.
System Signal Groups
order simplify following discussion, system signals have been combined into groups buffer type. system outputs should treated open drain require high-level source provided externally termination pull-up resistor. AGTL+ input signals have differential input buffers, which reference level. AGTL+ output signals require termination 1.5V. this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. AGTL+ buffers employ active negation clock cycle after assertion improve rise times. CMOS, Clock, APIC, inputs each driven from ground 2.5V. CMOS, APIC, outputs open drain should pulled high 2.5V. This ensures only correct operation Pentium Xeon processor MHz+, compatibility with future Pentium Xeon processors MHz+. Timings specified into load resistance defined timing tables. Chapter design considerations debug equipment. SMBus signals should driven using standard 3.3V CMOS logic levels.
PENTIUM® XEONPROCESSOR with 256KB Cache
ELECTRICAL SPECIFICATIONS
Table Processor Groups Group Name AGTL+ Input AGTL+ Output AGTL+ Signals BPRI#, BR[3:1]#1, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:03]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1, D[63:00]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGD2, SMI#, SLP# STPCLK# FERR#, IERR#, THERMTRIP#2 BCLK PICCLK PICD[1:0] TCK, TDI, TMS, TRST# SMBDAT, SMBCLK, SMBALERT#, VCC_ CORE, VCC_TAP, VCC_SMB RESERVED_XXX, SA[2:1], SELFSB[0:1], OCVR_EN, OCVR_OK, VIN_SENSE, CORE_AN_VSENSE, HV_EN#
CMOS Input CMOS Output System Clock APIC Clock APIC I/O3 Input Output3 SMBus Interface Power/Other4
NOTES:
BR0# only BREQ# signal that bi-directional. internal BREQ# signals mapped onto pins based processor's agent Chapter more information. information these signals, Chapter These signals specified 2.5V operation. used AGTL+ termination. system ground. VCC_TAP supply. VCC_SMB supply. Reserved pins must left unconnected. connect each other.
3.7.2 ASYNCHRONOUS SYNCHRONOUS SYSTEM SIGNALS AGTL+ signals synchronous BCLK. CMOS, Clock, APIC, signals applied asynchronously BCLK. APIC signals synchronous PICCLK. signals synchronous TCK. SMBus signals synchronous SMBCLK. SMBCLK asynchronous other clocks.
Access Port (TAP) Connection
Depending voltage levels supported other components Test Access Port (TAP) logic, recommended that Pentium® Xeonprocessor MHz+ first chain followed other components within system. voltage translation buffer should used drive next device chain unless component used that capable accepting 2.5V input. Similar considerations must made TCK, TMS, TRST#. Multiple copies each signal required multiple voltage levels needed within system. NOTE pulled VCCTAP with ~150 ohms Pentium Xeon processor MHz+ cartridge. open drain signal driving this must able deliver sufficient current drive signal low. Also, resistor should exist system design this pin, would parallel with this resistor.
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Debug Port described Chapter Debug Port must placed start chain with first component coming from Debug Port from last component going Debug Port. system, cautious when including empty SC330 connector scan chain. connectors scan chain must have processor termination card installed complete chain between system must support method bypass empty connectors. SC330 terminator substrates should directly TDO. (See Chapter more details.)
Maximum Ratings
Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields. Table Absolute Maximum Ratings Symbol TSTORAGE
VCC_CORE
Parameter Processor storage temperature Supply voltage with respect seen input OCVR processor supply voltage with respect processor supply voltage with respect AGTL+ buffer input voltage with respect CMOS APIC buffer input voltage with respect SMBus buffer input voltage with respect PWR_EN[1:0] current
-0.5
Operating voltage Operating voltage 1.65
Unit
Notes
SMBus CCTAP inGTL inCMOS inSMBus IPWR_EN
-0.3 -0.3 -0.3 -0.3 -0.1
NOTES:
Operating voltage voltage which component designed operate. Table VCC_CORE case Pentium® Xeonprocessor MHz+ voltage input seen input OCVR device which 2.8V product version 12V) another product version. Please contact Intel storage requirements excess year.
3.10
Processor Specifications
voltage current specifications provided Table defined processor edge fingers. processor signal specifications Tables defined Pentium Xeon processor MHz+ core. Each signal trace between processor edge finger processor core carries small amount current finite resistance. current produces voltage drop between processor edge finger core. Simulations should therefore versus these specifications processor core. Chapter processor edge finger signal definitions Table signal grouping. Most signals Pentium Xeon processor MHz+ system AGTL+ signal group. These signals specified terminated specifications these signals listed Table ease connection with other devices, Clock, CMOS, APIC, SMBus signals designed interface non-AGTL+ levels. Pentium Xeon processor MHz+ contain voltage clamp device cartridge substrate between core edge fingers. This device "clamps" 2.5V level CMOS, TAP, APIC signals 1.5V levels, which helps reduce overshoot levels processor core. CMOS, TAP, Clock, APIC signals interface with
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voltage clamp, with exception BCLK, PICCLK PWRGOOD. specifications these pins listed Table Table NOTE Unless otherwise noted, each specification applies Pentium® Xeonprocessors MHz+. Specifications only valid while meeting specifications case temperature, clock frequency input voltages. Care should taken read notes associated with each parameter.
Table Voltage Specifications Symbol CC_CORE Parameter (2.8V Pentium Xeon processor) Unit Notes 2,3,4
CC_CORE
(5/12V Pentium Xeon processor)
4.75 11.4
12.0
5.25 12.6 0.085
4,6,7,8
CC_CORE Tolerance, Static CC_CORE Tolerance, Transient Core voltage static tolerance edge fingers (2.8V Pentium Xeon processor) Processor core voltage transient tolerance edge fingers
(2.8V Pentium Xeon processor)
-0.085
-0.130
0.130
AGTL+ Termination voltage 1.47 1.50 1.53
1.5V ±2%,
CC_SMB CC_TAP
SMBus supply voltage supply voltage
3.135 2.375
2.50
3.465 2.625
3.3V ±5%, 2.5V ±5%,
NOTES:
Unless otherwise noted, specifications this table apply processor frequencies. "FMB" suggested design guideline flexible motherboard design. Failure adhere guidelines impact system upgradeability.
VCC_CORE supplies processor core. refers range points Pentium Xeon processors MHz+.
These voltages targets only. variable voltage source should exist systems event that different voltage required. section more information. Pentium Xeon processor MHz+ does require separate VCC_L2 voltage. Typical Voltage specification along with tolerance specifications provide correct voltage regulation processor. Pentium Xeon processor MHz+ when measurement bandwidth limited 20MHz measured connector back (solder tail) side baseboard. This parameter measured processor edge fingers. SC330 connector specified have self-inductance maximum, pin-to-pin capacitance (maximum MHz), average contact resistance over pins ohms maximum These tolerance requirements, across 20MHz bandwidth, processor edge fingers. requirements processor edge fingers account voltage drops (and impedance discontinuities) processor edge fingers processor core. Voltage must return within static voltage specification within after transient event. SC330 connector specified have self-inductance maximum, pin-to-pin capacitance (maximum MHz), average contact resistance ohms maximum order function with Intel specified voltage regulator module (VRM 8.3). Contact Intel testing details these parameters. 100% tested. Specified design characterization. 5/12V Pentium Xeon processor version operated 12V. specified ±5%. This parameter includes both static (noise ripple) transient tolerances edge fingers. VCC_SMB must connected 3.3V power supply (even SMBus features used) order Pentium Xeon processor MHz+ function properly.
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Table Current Specifications 1,10 Symbol Icc_core 2.74V VCC_CORE) Parameter Icc_core 4.75V VCC_CORE) Icc_core 11.4V VC_CORE) Icc_core 10.0 10.9 12.4 13.1 14.3 16.00 Unit Notes
ISGnt
Termination voltage supply current Stop Grant processor core 2.8V
ICCSLP
Sleep processor core 2.8V
DlccCORE/dt
Current slew rate
A/µs
DlCCV TT/dt
Termination current slew rate
A/µs
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Table Current Specifications 1,10 Symbol Parameter Unit Notes
ICCTAP ICCSMBus
power supply SMBus power supply
22.5
NOTES:
Unless otherwise noted, specifications this table apply processor frequencies. "FMB" suggested design guideline flexible motherboard design. VCC_core/Icc_core supplies processor core, integrated cache OCVR. measurements measured minimum voltage under maximum signal loading conditions. This current required single Pentium® Xeonprocessor MHz+. similar current drawn through termination resistors each load AGTL+ bus. decoupled SC330 cartridge such that negative current flow active pull-up VCC_CORE Pentium Xeon processor MHz+ will seen processor fingers. current specified also AutoHALT state. These maximum values specified design/characterization nominal SC330 edge fingers. Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. VCC_SMB must connected 3.3V power supply (even SMBus features used) order Pentium® Xeonprocessor MHz+ function properly. disabled Pentium Xeon processor MHz+ OCVR draws approximately load 2.8V VCC_CORE from motherboard VRM. your system needs maintain regulation with disabled Pentium Xeon processor MHz+ (OCVR_EN inactive), output minimum load specification should less. specification applicable 2.8V OCVR processors where used power source.
Table AGTL+ Signal Groups, Specifications processor Core Symbol RONN RONP OHTS Parameter Input Voltage Input High Voltage nMOS Resistance pMOS Resistance Output High Voltage Tri-state Leakage current Inputs, Outputs -0.150 +0.2V 0.2V 16.67 Unit Notes 1,4,7
NOTES:
Processor core parameter correlated into 50-ohm resistor 1.5V Pentium Xeon processor MHz+. +3%. Vout +5%. processor core drives high only clock cycle. then drives tri-states outputs. specified Table 100% tested. Specified design characterization. This specification corresponds VOL_MAX 0.3V when taken into effective 50-ohm load 1.5V Pentium Xeon processor MHz+. Vil/Vih guaranteed with respect parameters. Specified under load conditions operating point zero current V=VTT conditions.
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Table CMOS, TAP, Clock APIC Signal Groups, Specifications processor edge fingers Symbol
(PICCLK PWRGD only)
Parameter Input Voltage Input High Voltage
-0.150
2.625 2.625 2.625 ±100 ±100
Unit
Notes 2.5V maximum, 2.5V maximum, Parameter measured 14mA outputs open-drain 2.5V
Output Voltage Output High Voltage Input Leakage Current Output Leakage Current Capacitance
NOTES:
2.625V. VOUT 2.625V. Total capacitance processor core voltage clamp device. Does include cartridge trace capacitance. Applies CMOS, TAP, Clock, APIC signals except BCLK, PICCLK PWRGOOD. This parameter applies PICCLK. This parameter applies PWRDG. Maximum processor core specified 0.2V. Minimum processor core specified 0.2V.
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Table SMBus Signal Group, Specifications processor edge fingers Symbol IOL2 Parameter Input Voltage Input High Voltage Output Voltage Output Current Output Current Input Leakage Current Output Leakage Current -0.3 VCCSMB VCC_SMB 3.465 Unit Except SMBALERT# SMBALERT# 3.3V maximum Notes
NOTES:
SMBALERT# open drain signal.
Table OCVR Control Signals, Specifications processor edge fingers Symbol
OCVR_EN
Parameter Input Voltage
Unit
Notes
OCVR_EN
Input High Voltage
OCVR_OK
Output Voltage
-1.5mA
OCVR_OK
Output High Voltage
NOTES:
Driver configured open drain connected 3.3V (Vcc_SMB) through resistor. Vih_max (absolute) 5.25VDC when OCVR powered. OCVR processor operating, such initial system power there power input processor, input should driven such that more than flow into input (assuming connected ground). This equivalent using 270-ohm higher pull-up resistor tied typical supply only source driving input high.
3.11
AGTL+ System Specifications
Table below lists parameters controlled within Pentium® Xeonprocessor MHz+ taken into consideration during simulation. input buffers determine valid high levels using reference voltage REF) that generated internally processor cartridge from VREF should same level other AGTL+ logic using voltage divider baseboard. important that baseboard impedance held tight possible that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. Layout Guidelines (section 2.4) impedance recommendations.
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Table Internal Parameters AGTL+ Symbol Parameter Termination Resistor Reference Voltage 50mV 50mV Units Notes
NOTES:
Pentium Xeon processor MHz+ contains AGTL+ termination resistors processor. VREF generated processor substrate.
3.12
System Specifications
system timings specified this section defined Pentium Xeon processor MHz+ core pins unless otherwise noted. Timings tested processor core during manufacturing. NOTE: Timing specifications T45-T49 reserved future use. system specifications AGTL+ signal group relative rising edge BCLK input. AGTL+ timings referenced both `1'-logic levels unless otherwise specified.
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Table System Specifications (Clock) processor Core Pins Parameter System Frequency 132.29 BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 0.75 0.75 1.25 1.25 ±150 133.71 133.33 @>2.0V @<0.5V 0.5V-2.0V 2.0V-0.5V Unit Figure Notes
NOTES:
Unless otherwise noted, specifications this table apply Pentium Xeon processor MHz+ frequencies. timings AGTL+ signals referenced BCLK rising edge 1.25V processor core pin. AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00V processor core pins. timings CMOS signals referenced BCLK rising edge 1.25V processor core pin. CMOS signal timings (compatibility signals, etc.) referenced 1.25V processor core pins. internal core clock frequency derived from processor system clock. system clock core clock ratio determined during initialization described 6.2. Table shows supported ratios each processor. BCLK period allows +0.5 tolerance clock driver variation. CK98WS Clock Synthesizer/Driver Specification further information. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25V processor core pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. CK98WS Clock Synthesizer/Driver Specification further details. 100% tested. Specified design characterization clock driver requirement. This frequency range specified CK98WS Clock Synthesizer/Driver Specification, guaranteed design only (not tested).
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Table AGTL+ Signal Group, System Specifications processors Core ohms Terminated 1.5V T10: Parameter AGTL+ Output Valid Delay AGTL+ Input Setup Time AGTL+ Input Hold Time RESET# Pulse Width -0.05 0.80 1.00 2.65 Unit Figure Figure Figure Figure Figure Notes
NOTES:
These specifications tested during manufacturing. Valid delay timings these signals processor core assume ohms termination 1.5V. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously clock. After ratio A20M#, IGNNE# LINT[1:0] stable, VCC_CORE, BCLK within specification, PWRGD asserted. Figure Specification minimum 0.40V swing from VREF VREF This assumes edge rate .3V/ns
Table CMOS, TAP, Clock APIC Signal Groups, Specifications processor Core T14: Parameter CMOS Input Pulse Width, except PWRGD LINT[1:0] Unit BCLKs Figure Figure Notes Active Inactive states
T14B: LINT[1:0] Input Pulse Width T15: PWRGD Inactive Pulse Width
BCLKs BCLKs
Figure Figure Figure
NOTES:
These specifications tested during manufacturing. Valid delay timings these signals specified into ohms 2.5V. When driven inactive after VCC_CORE, BCLK become stable. PWRGD must remain below VIL_MAX from Table until voltage planes meet voltage tolerance specifications Table BCLK BCLK specifications Table least clock cycles. PWRGD must rise glitch-free monotonically 2.5V. BCLK signal meets specification within 150ns turning then PWRGD Inactive Pulse Width specification waived BCLK start after PWRGD asserted. PWRGD must still remain below VIL_MAX until voltage planes meet voltage tolerance specifications.
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Table System Specifications (Reset Conditions T16: Parameter Reset Configuration Signals (A[14:05]#, BR0#, FLUSH#, INIT#) Setup Time Reset Configuration Signals (A[14:05]#, BR0#, FLUSH#, INIT#) Hold Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]#) Hold Time Unit BCLKs Figure Figure Notes Before deassertion RESET After clock that deasserts RESET# Before deassertion RESET# After assertion RESET# After clock that deasserts RESET#
T17:
BCLKs
Figure
T18:
Figure
T19:
BCLKs
Figure
T20:
BCLKs
Figure Figure
NOTES:
Reset, clock ratio defined these signals must safe value (their final lower multiplier) within this delay unless PWRGD being driven inactive.
Table System Specifications (APIC Clock APIC I/O) processor Core T21: Parameter PICCLK Frequency 33.3 Unit Figure Notes
T22: T23: T24: T25: T26: T27: T28:
PICCLK Period PICCLK High Time PICCLK Time PICCLK Rise Time PICCLK Fall Time PICD[1:0] Setup Time PICD[1:0] Hold Time
30.0 12.0 12.0 0.25 0.25
500.0
Figure Figure Figure Figure Figure Figure Figure Figure Figure 2,3,4 2,3,4
T29A: PICD[1:0] Valid Delay (Rising Edge) T29B: PICD[1:0] Valid Delay (Falling Edge)
12.0
NOTES:
These specifications tested during manufacturing. Referenced PICCLK rising edge. open drain signals, valid delay synonymous with float delay. Valid delay timings these signals specified 2.5V.
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Table System Specifications (TAP Connection) processor Core T30: T31: T32: T33: T34: T35: T36: T37: T38: T39: T40: T41: T42: T43: T44: Parameter Frequency Period High Time Time Rise Time Fall Time TRST# Pulse Width TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Non-Test Outputs Valid Delay Non-Test Inputs Setup Time Non-Test Inputs Setup Time Non-Test Inputs Hold Time 13.0 40.0 14.0 10.0 25.0 25.0 25.0 60.0 25.0 25.0 16.667 Unit Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure @1.7V @0.7V (0.7V-1.7V) (1.7V-0.7V) Asynchronous Figure Notes
NOTES:
Unless otherwise noted, these specifications tested during manufacturing. 100% tested. Specified design characterization. added maximum rise fall times every below 16.667 MHz. Referenced rising edge. Referenced falling edge. Valid delay timing this signal specified 2.5V. Non-Test Outputs Inputs normal output input signals (besides TCK, TRST#, TDI, TMS). These timings correspond response these signals operations. During Debug Port operation, normal specified timings rather than signal timings.
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Table SMBus Signal Group, Specifications Edge Fingers T50: T51: T52: T53: T54: T55: T56: T57: T58: T59: Parameter SMBCLK Frequency SMBCLK Period SMBCLK High Time SMBCLK Time SMBCLK Rise Time SMBCLK Fall Time SMBus Output Valid Delay SMBus Input Setup Time SMBus Input Hold Time Free Time Unit Figure Figure Figure Figure Figure Figure Figure Figure Figure Notes
NOTES:
Minimum time allowed between request cycles.
Table OCVR Control Signals, Specifications Edge Fingers Parameter Unit Notes OCVR_EN High Time OCVR_EN Rise Time OCVR_EN Fall Time OCVR_OK Rise Time OCVR_OK Fall Time NOTES:
OCVR_OK output with load external pull-up 3.3V.
10.0 10.0 10.0 30.0 10.0
Figure through Figure used conjunction with specification timings tables.
Clock
T25, (Rise Time) T26, (Fall Time) T23, (High Time) T24, (Low Time) T22, (BCLK, PICCLK, TCK, Period)
1.25
P6CB761z
Figure BCLK, PICCLK, Generic Clock Waveform
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ELECTRICAL SPECIFICATIONS
2.46V SCLK 0.84V 2.97V 0.84V
SMBUSCLK
Figure SMBCLK Clock Waveform
Clock
Signal
Valid
Valid
(Valid Delay) T14, (Pulse Wdith) GTL+ signal group; 1.25V CMOS, APIC signal groups
Figure Valid Delay Timings
Clock
Vclk
Signal
Valid
(Setup Time) (Hold Time) Vclk
000763z
Figure Setup Hold Timings
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BCLK RESET# Configuration (A20M#, IGNNE#, LINT[1:0]) Configuration (A[14:5]#, BR0#, FLUSH#, INIT#) (GTL+ Input Hold Time) Safe Valid
Valid
(GTL+ Input Setup Time) (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time) P6CB-764
Figure System Reset Configuration Timings
BCLK CORE PWRGOOD RESET# Valid Ratio
Configuration (A20M#, IGNNE#, LINT[1:0]) (PWRGOOD Inactive Pulse Width) (RESET# Pulse Width)
(Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) 000765b
Figure Power-On Reset Configuration Timings
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1.25V
TDI, Non-Test Input Signals
1.25V
Non-Test Output Signals
(All Non-Test Inputs Setup Time)
(All Non-Test Inputs Hold Time) (All Non-Test Outputs Valid Delay) (All Non-Test Outputs Float Delay)
P6CB766a
Figure Test Timings (Boundary Scan)
TRST#
1.25V
P6CB-
Figure Test Reset Timings
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SIGNAL QUALITY
SIGNAL QUALITY
Signals driven Pentium® Xeonprocessor MHz+ system should meet signal quality specifications ensure that components read data properly ensure that incoming signals affect long-term reliability component. Specifications provided simulation processor core. Meeting specifications processor core Table through Table ensures that signal quality effects will adversely affect processor operation.
Clock Signal Quality Specifications
Table describes signal quality specifications processor core Pentium Xeon processor MHz+ system clock (BCLK) signal. Figure shows signal quality waveform system clock processor core pads. Table BCLK Signal Quality Specifications Simulation processor Core Parameter BCLK BCLK Absolute Voltage Range -0.7 Rising Edge Ringback Falling Edge Ringback -0.3 2.625 Unit Figure
Notes
NOTES:
Unless otherwise noted, specifications this table apply Pentium Xeon processor MHz+ frequencies. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
000806
Figure BCLK, TCK, PICCLK Generic Clock Waveform processor Core Pins
AGTL+ Signal Quality Specifications
Refer Pentium processor Developer's Manual (Order Number 243341) specification AGTL+.
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4.2.1 AGTL+ Ringback Tolerance Specifications Table provides AGTL+ signal quality specifications Pentium Xeon processors MHz+ simulating signal quality processor core pads. Figure describes signal quality waveform AGTL+ signals processor core pads. more information AGTL+ interface, Pentium processor Developer's Manual (Order Number 243341). Table AGTL+ Signal Groups Ringback Tolerance Specifications processor Core NOTES:
Unless otherwise noted, guidelines this table apply Pentium Xeon processor MHz+ frequencies cache sizes. Specifications edge rate V/nS. values specified design characterization. Please Table maximum allowable overshoot. Ringback between Vref +100mV Vref +200mV Vref -200mV Vref -100mV requires flight time measurements adjusted described Intel® AGTL+ Specification (Pentium® Developers Manual). Ringback below (Vref 100mV) above (Vref 100mV) supported. Intel recommends exceeding ringback value 120mV allow margin other sources system noise. negative value indicates that amplitude ringback above VTT. (i.e. -100mV specifies signal cannot ringback below 100mV). measured relative measured relative 200mV.
Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Squarewave Ringback
0.50 -200
Unit
Figure Figure Figure Figure Figure Figure
Notes
5,7,8
start Clock
2/3VTT +0.2 2/3VTT
-0.2
1.25V
Time Note: High case analogous. 000914a
000914a
Figure High AGTL+ Receiver Ringback Tolerance
4.2.2 AGTL+ OVERSHOOT/UNDERSHOOT GUIDELINES
Overshoot guidelines based magnitude duration overshoot/undershoot pulse (illustrated Figure given Table Overshoot/Undershoot absolute value maximum voltage differential across input buffer relative termination voltage (VTT overshoot/undershoot guideline limits transitions beyond fast signal edge rates. processor damaged repeated Overshoot/Undershoot events tolerant buffers potential large enough (i.e., overshoot/undershoot great enough). Determining impact overshoot/undershoot condition requires knowledge Magnitude, Pulse Duration, Activity Factor.
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4.2.2.1 Overshoot/Undershoot Magnitude Overshoot magnitude describes maximum potential difference between signal reference voltage level, Vss. Undershoot Magnitude describes maximum potential difference between signal (undershoot). While overshoot measured relative using probe (probe signal ground lead VSS), Undershoot must measured relative This accomplished simultaneously measuring plane while measuring signal undershoot. true waveform then calculated oscilloscope itself following oscilloscope data file analysis: Converted Undershoot Waveform Signal Note: This Converted Undershoot Waveform appears positive (overshoot) signal. Note: Overshoot (rising edge) Undershoot (falling edge) conditions separate their impact must determined independently. After conversion, Overshoot/Undershoot Specifications applied Converted Undershoot Waveform using Overshoot/Undershoot Magnitude Pulse Duration Specifications Table Overshoot/Undershoot Magnitude levels must also observe Absolute Maximum Specifications. These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed Pulse Durations. Provided that magnitude Overshoot/Undershoot within Absolute Maximum Specifications, impact Overshoot/Undershoot Magnitude determined based upon Pulse Duration Activity Factor. 4.2.2.2 Overshoot/Undershoot Pulse Duration Overshoot/Undershoot Pulse Duration describes total time that Overshoot/Undershoot event exceeds Overshoot/Undershoot Reference Voltage (Vos_ref 1.635V). This total time could encompass several oscillations above Overshoot/Undershoot Reference Voltage. Thus, multiple Overshoot/Undershoot pulses within single Overshoot/Undershoot event must measured determine total Pulse Duration. Note: Oscillations below Reference Voltage cannot subtracted from total Overshoot/Undershoot Pulse Duration. Note: Multiple Overshoot/Undershoot events occurring within same clock cycle must considered together event. Using worst-case Overshoot/Undershoot Magnitude, together individual Pulse Durations determine total Overshoot/Undershoot Pulse Duration that total event. 4.2.2.3 Overshoot/Undershoot Activity Factor Activity Factor (AF) describes frequency Overshoot/Undershoot occurrence relative Clock. Since highest frequency assertion AGTL+ CMOS signal every other clock, indicates that specific Overshoot Undershoot waveform occurs EVERY OTHER clock cycle (e.g., 1-0-1-0. system switching pattern). Thus, 0.01 indicates that specific Overshoot Undershoot waveform occurs time every cycles. specifications provided Table show Maximum Pulse Duration allowed given Overshoot/Undershoot Magnitude specific Activity Factor. Each Table entry independent others, meaning that Pulse Duration reflects existence Overshoot/Undershoot Events that Magnitude ONLY. platform with overshoot/undershoot that just meets Pulse Duration specific Magnitude where means that there other Overshoot/Undershoot events, even lesser Magnitude (note that then event occurs times other events occur). Note: Activity Factor AGTL+ signals referenced BCLK frequency. Note: Activity Factor CMOS signals referenced PICCLK frequency.
4.2.2.4 Determining System meets Overshoot/Undershoot Specifications overshoot/undershoot specifications listed following tables specify allowable overshoot/undershoot single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events, each which will have their parameters (duration, magnitude). While each overshoot meet overshoot specification, when total impact overshoot events, system fail. guideline ensure system passes overshoot undershoot specifications shown below. Insure signal (CMOS AGTL+) ever exceed 1.635V. only overshoot/undershoot event magnitude occurs, ensure meets over/undershoot specifications following tables. This means that whenever over/undershoot event occurs, always over/undershoots same level.
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multiple overshoots and/or multiple undershoots occur, measure worst-case pulse duration each magnitude compare results against specifications (note: multiple overshoot/undershoot events within clock cycle must have their pulse durations summed together determine total pulse duration). these worst case overshoot undershoot events meet specifications (measured time specifications) table where AF=1, then system passes.
Table AGTL+ Signal Overshoot/Undershoot Limits Processor Core 1,2,3,4,5,6,7,8,9 Overshoot/Undershoot Magnitude
Pulse Duration (nS)
0.01 2.25 NOTES:
0.75
0.42 0.75
Unless otherwise noted, guidelines this table apply Pentium® Xeonprocessor MHz+ frequencies. Overshoot Magnitude Undershoot Magnitude absolute values should never exceed 2.3V under circumstances. Overshoot measured relative VSS. Undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635V. Rinback below cannot subtracted from Overshoots/Undershoots. Lesser Undershoot does allocate longer larger Overshoot. Lesser Overshoot does allocate longer larger Undershoot. OEM's encouraged follow Intel provided layout guidelines. values specified design characterization.
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Figure Maximum Acceptable Overshoot/Undershoot Waveform1,2,3,4,5,6,7,8
NOTES:
Overshoot Magnitude Undershoot Magnitude absolute values should never exceed 2.3V under circumstances. Overshoot measured relative VSS. Undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635V. Rinback below cannot subtracted from Overshoots/Undershoots. Lesser Undershoot does allocate longer larger Overshoot. Lesser Overshoot does allocate longer larger Undershoot. OEM's encouraged follow Intel provided layout guidelines. values specified design characterization.
Non-GTL+ Signal Quality Specifications
There three signal quality parameters defined non-AGTL+ signals: Overshoot/Undershoot, Ringback, Settling Limit. three signal quality parameters shown Figure non-AGTL+ signal group processor core pads Overshoot/Undershoot shown Figure illustrative purposes only help explain Ringback Settling Limit. Refer Figure illustration Overshoot/Undershoot specifications.
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Overshoot Settling Limit
Rising-Edge Ringback Voltage Falling-Edge Ringback
Settling Limit
Time Undershoot
RINGBACK
Figure Non-AGTL+ Overshoot/Undershoot, Settling Limit, Ringback
4.3.1 2.5V Signal Overshoot/Undershoot Guidelines Overshoot/Undershoot guideline limits transitions beyond fast signal edge rates. Refer Figure illustration Overshoot/Undershoot specifications non-AGTL+ signals. processor damaged Overshoot/Undershoot specifications met. Overshoot/Undershoot specification shown Table Table 2.5V Tolerant Signal Group Overshoot/Undershoot Processor Core Pins 1,2,3,4,5,6,7,8,9 Overshoot/Undershoot Pulse Duration (nS) Magnitude 0.01 2.25 2.15 2.05 NOTES:
Activity Factor based period equal Overshoot/Undershoot Magnitude 2.3V Absolute value should never exceeded. Overshoot measured relative VSS. Undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635V. Rinback below cannot subtracted from Overshoots/Undershoots. Lesser Undershoot does allocate longer larger Overshoot. OEM's encouraged follow Intel provided layout guidelines. values specified design characterization.
16.8 30.4
19.2
4.3.2 BCLK Overshoot/Undershoot Guidelines Specifications Unlike AGTL+ CMOS signals, BCLK Specifications provide relaxation activity factor. System designers should ensure that their platforms meet BCLK specifications even under worst-case conditions.
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Intel recommends that platforms meet Absolute Maximum Specifications Overshoot Undershoot BCLK. This ensures that BCLK Buffer will meet specifications regardless Overshoot Undershoot Pulse Duration within Clock cycle with Duty Cycle. Pentium Xeon processors MHz+ maximum Overshoot level 3.3V. Absolute maximum Undershoot -0.7V, where "maximum" defined largest voltage potential below ground. However, Absolute Maximum Specifications relaxed BCLK Undershoot Pulse Duration accounted under worst-case conditions. Thus, system with BCLK Undershoot below -0.7V must ensure that worst case Pulse Duration less than equal allowed Pulse Duration Worst Case Undershoot Magnitude. Table Table BCLK Overshoot/Undershoot Specifications 1,2,3,4,5,6,7 Undershoot Magnitude Pulse Duration (nS) -0.85V -0.8V -0.75V -0.7V -0.65V NOTES:
Overshoot measured relative VSS. Undershoot measured relative VTT. Overshoot/Undershoot Pulse Duration measured relative 1.635V. Rinback below cannot subtracted from Overshoots/Undershoots. Lesser Undershoot does allocate longer larger Overshoot. OEM's encouraged follow Intel provided layout guidelines. values specified design characterization.
3.75 3.75 3.75 3.75
4.3.3 Measuring BCLK Overshoot/Undershoot Overshoot BCLK measured relative GND. probing BCLK with oscilloscope where probe lead makes good contact processor pin, BCLK Overshoot accurately measured determine system meets BCLK Overshoot Absolute Maximum Specifications. Undershoot BCLK also measured relative GND, again probing BCLK with oscilloscope where probe lead makes good contact processor pin. system does meet BCLK Undershoot Absolute Maximum Specifications, then Worst Case Undershoot Magnitude must measured Pulse Duration Undershoot must accounted for. Pulse Duration measurements determine total amount time that BCLK signal spends below GND. Measuring from earliest Falling Edge crossover latest Rising Edge crossover provides worst-case Undershoot Pulse Duration. When compared Specification Table, Pulse Duration Worst Case Undershoot Magnitude then determines system meets BCLK Overshoot/Undershoot Specifications. Note: measured Pulse Duration must less than equal Specified Pulse Duration given Worst Case Undershoot Magnitude. 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION ringback specification voltage receiving that signal rings back after achieving maximum absolute value. (See Figure illustration ringback.) Excessive ringback cause false signal detection extend propagation delay. Violations signal ringback specification allowed 2.5V tolerant signals. Table shows signal ringback specifications 2.5V tolerant signals used simulations processor core. Table Signal Ringback Specifications 2.5V Tolerant Signal Simulation processor Core Input Signal Group Non-AGTL+ Signals Non-AGTL+ Signals Transition Maximum Ringback (with Input Diodes Present) Unit Figure
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4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed total signal swing VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
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PROCESSOR FEATURES Power States Clock Control
Pentium® Xeonprocessor MHz+ allows Auto HALT, Stop-Grant, Sleep states reduce power consumption stopping clock specific internal sections processor, depending each particular state. There Deep Sleep state Pentium Xeon processor MHz+. Refer following sections power states Pentium Xeon processor MHz+. processor fully realize current consumption Stop Grant, Sleep states, must set. 02AH (Hex), must (power default `0') processor stop internal clocks during these modes. more information, Pentium processor Developer's Manual (Order Number 243502). being able recognize transactions during Sleep state, systems allowed have more processors Sleep state other processors Normal Stop Grant states simultaneously. 5.1.1 NORMAL STATE STATE
This normal operating state processor. 5.1.2 AUTO HALT POWER DOWN STATE STATE
Auto HALT power state entered when Pentium Xeon processor MHz+ executes HALT instruction. processor will issue normal HALT cycle BE[7:0]# REQ[4:0]# when entering this state. processor will transition Normal state upon occurrence SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR). RESET# will cause processor immediately initialize itself. SMI# will cause processor execute handler. return from handler either Normal Mode Auto HALT Power Down state. Chapter Intel Architecture Software Developer's Manual Volume System Programming. FLUSH# will serviced during Auto HALT state. on-chip first level caches external second level cache will flushed processor will return Auto HALT state. A20M# will serviced during Auto HALT state; processor will mask physical address (A20#) before look-up either on-chip first level caches external second level cache, before read/write transaction driven bus. system generate STPCLK# while processor Auto HALT Power Down state. processor will generate Stop Grant cycle when enters Stop Grant state from HALT state. processor enters Stop Grant state from Auto HALT state, STPCLK# signal must deasserted before interrupts serviced (see below). When system deasserts STPCLK# interrupt signal, processor will return execution HALT state. processor will generate HALT cycle when re-enters HALT state from Stop Grant state.
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HALT Instruction HALT Cycle Generated Auto HALT Power Down State BCLK running. Snoops interrupts allowed. INIT#, BINIT#, INTR, NMI, SMI#, RESET# Normal State Normal execution.
Snoop Event Occurs Snoop Event Serviced
erte
STPCLK# Asserted
STPCLK# De-asserted
-ass
erte
HALT/Grant Snoop State BCLK running. Service snoops caches.
Snoop Event Occurs
Stop Grant State BCLK running. Snoops interrupts allowed.
Snoop Event Serviced
SLP# Asserted
SLP# De-asserted
Sleep State BCLK running. snoops interrupts allowed.
P6CB757a P6CB757b
Figure Stop Clock State Machine
5.1.3
STOP-GRANT STATE STATE
Stop-Grant state Pentium® Xeonprocessor MHz+ entered when STPCLK# signal asserted. Pentium Xeon processor MHz+ will issue Stop-Grant Transaction Cycle. Exit latency from this mode BLCK periods after STPCLK# signal deasserted. Since AGTL+ signal pins receive power from system bus, these pins should driven (allowing level return minimum power drawn termination resistors this state. addition, other input pins system should driven inactive state. BINIT# will serviced while processor Stop-Grant state. event will latched serviced software upon exit from Stop-Grant state. FLUSH# will serviced during Stop Grant state. RESET# will cause processor immediately initialize itself; processor will stay Stop Grant state. transition back Normal state will occur with deassertion STPCLK# signal. transition HALT/Grant Snoop state will occur when processor detects snoop phase system bus. transition Sleep state will occur with assertion SLP# signal. While Stop Grant State, other interrupts will latched Pentium Xeon processor MHz+, only serviced when processor returns Normal State. 5.1.4 HALT/GRANT SNOOP STATE STATE
Pentium Xeon processor MHz+ will respond snoop phase transactions (initiated ADS#) system while Stop-Grant state Auto HALT Power Down state. When snoop transaction presented upon system bus, processor will enter HALT/Grant Snoop state. processor will stay this state until snoop system been serviced (whether processor another agent system bus). After snoop serviced, processor will return Stop-Grant state Auto HALT Power Down state, appropriate.
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5.1.5 SLEEP STATE STATE
Sleep state very power state which processor maintains context, maintains PLL, stopped internal clocks. Sleep state only entered from Stop-Grant state. Once StopGrant state (verified termination Stop-Grant transaction cycle), SLP# asserted, causing Pentium® Xeonprocessor MHz+ enter Sleep state. system must wait BCLK cycles after completion Stop-Grant cycle before SLP# asserted. system, processors must complete Stop Grant cycle before subsequent BCLK wait assertion SLP# occur. processor Sleep state BCLKs after assertion SLP# pin. latency exit Sleep state BCLK cycles. SLP# recognized Normal, Auto HALT States. Snoop events that occur during transition into Sleep state will cause unpredictable behavior. Therefore, transactions should blocked system logic during these transitions. Sleep state, processor incapable responding snoop transactions latching interrupt signals immediately after assertion SLP# (one exception RESET# which causes processor reinitialize itself). system core logic must detect these events deassert SLP# signal (and subsequently deassert STPCLK# signal interrupts) processor correctly interpret transaction signal transition. Once Sleep state, SLP# deasserted another asynchronous event occurs. transitions assertions signals allowed system while "Pentium Xeon processor MHz+ Sleep state. transition input signal (with exception SLP# RESET#) before processor returned Stop Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop Grant State. RESET# driven active while processor Sleep State normal operation desired, SLP# STPCLK# should deasserted immediately after RESET# asserted. 5.1.6 CLOCK CONTROL
During Auto HALT Power Down Stop-Grant states, processor will continue process snoop phase system cycle. PICCLK signal should removed during Auto HALT Power Down Stop-Grant states. When processor Sleep state, will respond interrupts snoop transactions. PICCLK removed during Sleep state. processor will enter power states until internal queues second level cache empty. When re-entering Normal state, processor will resume processing external cache requests soon requests encountered.
System Management (SMBus) Interface
Pentium Xeon processor MHz+ includes SMBus interface that allows access several processor features, including memory components (referred processor Information Scratch EEPROM) thermal sensor Pentium Xeon processor MHz+ substrate. These devices their features described below. Pentium Xeon processor MHz+ SMBus implementation uses clock data signals SMBus specification. does implement SMBSUS# signals.
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1/16W EEPROM 1/16W INTEL EEPROM
1/16W
1/16W
Core
Stby ALERT# 1/16W
1/16W
1/16W 1/16W 1/16W
1/16W
SMB_V
SMBALERT
Figure Logical1 Schematic SMBus Circuitry
NOTES:
Actual implementation vary. general understanding architecture.
5.2.1 PROCESSOR INFORMATION
Pentium® Xeonprocessor MHz+ implements previously defined fields processor information (PI-ROM) allow visibility core Cartridge Voltage Regulation (OCVR) voltage requirements. These features present SC330 products, used different Pentium Xeon processor MHz+. Pentium Xeon processor MHz+ implements OCVR device. This provides flexibility accommodate products with voltage input 2.8V product version different product version. 2.8V version indicated PI-ROM "OCVR option Input Voltage field, while version indicated "OCVR option Input Voltage PI-ROM field. implementation PI-ROM Pentium Xeon processor MHz+ allows software view desired voltage outputs power source (VRM Power Supply) feeding OCVR OCVR itself. Software could compare those values actual power source/OCVR outputs (using converter), determine power source OCVR operating correctly. implementation PI-ROM gives system designers means determining proper OCVR Output Voltage requirements. Without these fields, baseboard determining OCVR Output Voltage requirements. fields defined Pentium Xeon processor MHz+ coincide closely possible with those Pentium Xeon processor. meaningless (for Pentium Xeon processor MHz+) Cache Voltage" field replaced with more useful "OCVR Output" field. Pentium Xeon processor MHz+ (SC330.1) defined (A56, "VIN_SENSE") that allows baseboard directly measure actual OCVR input voltage (B83, "AN_CORE_VSENSE") that analog representation voltage OCVR output. This voltage compared with desired voltage (indicated field) determine OCVR input output voltage varying from desired levels.
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Systems implementing analog sensing should read PIROM first, then compare that value with measured VIN_SENSE rather than assuming specific value. value AN_CORE_VSENSE implementation dependent cannot assumed particular value. Systems derive benefit monitoring stability, should make assumptions about value. Table text bold represents defined fields Pentium® Xeonprocessor MHz+.
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Table processor Information Format Offset/Section HEADER: PROCESSOR: Bits CORE: Function Data Format Revision EEPROM Size processor Data Address processor Core Data Address Cache Data Address Cartridge Data Address Part Number Data Address Thermal Reference Data Address Feature Data Address Other Data Address Reserved Checksum S-spec/QDF Number Sample/Production Reserved Checksum processor Core Type processor Core Family Notes 4-bit digits Size bytes (MSB first) Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Byte pointer, present Reserved future byte checksum 8-bit ASCII characters Sample only Reserved future byte checksum From CPUID From CPUID (Family processor Core Model From CPUID (Model processor Core Stepping Reserved OCVR option Input Voltage OCVR option Input Voltage Tolerance Reserved Maximum Core Frequency OCVR option Input Voltage OCVR option Input Voltage Tolerance CACHE: Reserved Checksum Reserved Voltage (0=2.8V, 12000=5/12V Edge finger tolerance +/(0=2.8V, 600=5/12V) Reserved future 16-bit binary number MHz) Voltage (2800=2.8V, 5000=5/12V) Edge finger tolerance +/(85=2.8V, 250=5/12V) Reserved future byte checksum Reserved From CPUID
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CARTRIDGE: PART NUMBERS: THERMAL REF.: FEATURES: OTHER: Cache Size Reserved OCVR Output Voltage OCVR Output Voltage Tolerance, High OCVR Output Voltage Tolerance, Reserved Checksum Cartridge Revision Substrate Rev. Software Reserved Checksum processor Part Number processor processor Electronic Signature Reserved Checksum Thermal Reference Byte Reserved Checksum processor Core Feature Flags Cartridge Feature Flags OCVR Present Serial Signature Electronic signature present Thermal Sense Device Present Thermal Reference Byte Present EEPROM Present Core present Cache present Number Devices Chain Reserved Checksum Reserved Present Present Present Present Present Present Present Present Present Present Present Present Present Present Always Zero 4-bit digit Reserved future byte checksum Reserved future Voltage Edge finger tolerance Edge finger tolerance Reserved future byte checksum Four 8-bit ASCII characters 2-bit revision number Reserved future byte checksum Seven 8-bit ASCII characters Fourteen 8-bit ASCII characters 64-bit identification number Reserved future byte checksum below Reserved future byte checksum From CPUID 16-Bit binary number Kbytes)
NOTES:
OCVR Output Voltage tested. Programmed design target.
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5.2.2
SCRATCH EEPROM
Also available SMBus EEPROM that used other data system processor vendor's discretion. This device pull-down control through resistor, implemented previous Pentium® Xeonand Pentium Xeon processors. This will allow EEPROM programmed systems with manipulation this signal. Once programmed, data this EEPROM write protected asserting active-high signal. Scratch EEPROM 1024 part. 5.2.3 PROCESSOR INFORMATION SCRATCH EEPROM SUPPORTED SMBUS TRANSACTIONS Four SMBus packet types associated with PIROM Scratch EEPROM. Each these packet transfers provides device select address read/write bit. remaining parts transfer vary. packets, Send Byte Receive Byte, transfer additional byte after device select. other packets, Write Byte Read Byte, transfer additional bytes after device select. using these four transfer types, complete access EEPROMs possible. Send Byte loads address into memory device that used subsequent access. Send Byte does change contents EEPROM, just address pointer within Table explanation below. Receive Byte gets byte data from memory device. uses address already loaded into EEPROM device returns byte that address. Repetitive Receive Byte access address range possible. Table explanation below. Write Byte transfers both address data byte into memory device. stand-alone write cycle. Table Read Byte transfers address gets byte data from memory device. stand alone read cycle. Table Both ROMs respond SMBus packet types Send Byte, Receive Byte, Read Byte. Scratch EEPROM additionally responds packet type Write Byte. EEPROM devices perform sequential read page write modes that covered SMBus specification. However, four transfers described above, transfer requirements these devices achieved. NOTE: Tables below: indicates start condition (SDA falling while high) indicates stop condition (SDA rising while high) R/W* indicates read/write signal read, write) indicates acknowledge* signal, acknowledge, acknowledge). shaded portions following Tables indicate that SMBus slave device driving while clear portions indicate that SMBus master device under control host driving Table Send Byte SMBus Packet Device Address bits Data bits
Table outlines Send Byte packet, which provides address device later use. start condition followed device select field write bit, which acknowledged device. following data byte really address, which also acknowledged device. Finally stop condition signaled.
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Table Receive Byte SMBus Packet Device Address bits Data bits
Table diagrams Receive Byte packet that performs current address read. start condition followed device select address field read flag. device decodes address drives acknowledge low. data returned device transfer terminated controller providing negative acknowledge stop. Note that there data address provided, only device address. EEPROM internal address counter keeps track address accessed during last read write operation, incremented one. Repeated current address reads will receive data from consecutive addresses. Address roll over will occur when last byte device been read. this event will roll over first byte device.
Table Write Byte SMBus Packet Device Address bits Data Address bits Data bits
Table diagrams Write Byte packet. This effectively Random Address Write function. device select address, data offset address write data provided within packet. device address followed write flag. EEPROM device drives each three acknowledge pulses After Write Byte packet received Scratch EEPROM device enters timed writing mode during which will respond further transfers. This timed writing mode will approximately milliseconds duration.
Table Read Byte SMBus Packet Device Address bits Data Address bits Device Address bits Data bits
5.2.4Table illustrates Read Byte packet. This effectively Random Address Read function. This actually consecutive SMBus transfers, address write followed current address read from same device. address write portion, both device address data address acknowledged EEPROM. second start condition then occurs, followed receive byte read such diagrammed above. From programming perspective, this treated separate transfers. THERMAL SENSOR Pentium® Xeonprocessor MHz+ thermal sensor provides means acquiring thermal data from processor with exceptional degree precision. thermal sensor composed control logic, SMBus interface logic, precision analog-to-digital converter, precision current source. thermal sensor drives small current through junction thermal diode located same silicon processor core. forward bias voltage generated across thermal diode sensed precision converter derives single byte thermal reference data, "thermal byte reading." System management software running processor microcontroller acquire data from thermal sensor thermally manage system. Upper lower thermal reference thresholds individually programmed thermal diode. Comparator circuits sample register where single byte thermal data (thermal byte reading) stored. These circuits compare single byte result against programmable threshold bytes. alert signal Pentium® Xeonprocessor MHz+ SMBus (SMBALERT#) will assert when either threshold crossed. increase usefulness thermal diode thermal sensor, Intel added procedure manufacturing test flow Pentium Xeon processor MHz+. This procedure determines Thermal Reference Byte programs into processor Information ROM. Thermal Reference Byte
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uniquely determined each unit. procedure causes each unit dissipate maximum power (which vary from unit unit) while same time maintaining thermal plate maximum specified operating temperature. Correctly used, this feature permits efficient thermal solution while preserving data integrity. thermal byte reading used conjunction with Thermal Reference Byte processor Information ROM. Byte processor Information contains address this byte, described more detail Section 5.2.5. thermal byte reading from thermal sensor compared this Thermal Reference Byte provide indication difference between temperature processor core instant thermal byte reading temperature processor core under steady state conditions high power maximum TPLATE specifications. nominal precision least significant thermal byte 1°C. Reading thermal sensor explained Section 5.2.6. Pentium® Xeonprocessor SMBus Thermal Reference Guidelines more details further recommendations this feature Pentium Xeon processor MHz+ based systems. thermal sensor feature processor cannot used measure TPLATE. TPLATE specification Chapter must regardless reading processor's thermal sensor order ensure adequate cooling entire Pentium Xeon processor MHz+. thermal sensor feature only available while VCC_ CORE CC_SMB valid levels processor low-power state. 5.2.5 THERMAL SENSOR SUPPORTED SMBUS TRANSACTIONS
thermal sensor responds five SMBus packet types: write byte, read byte, send byte, receive byte, (Alert Response Address). send byte packet used sending one-shot commands only. receive byte packet accesses register commanded last read byte packet. receive byte packet preceded write byte send byte packet more recently than read byte packet, then behavior undefined. Tables through diagram five packet types. these figures, represents SMBus start bit, represents stop bit, `Ack' represents acknowledge, `///' represents negative acknowledge. thermal sensor transmits those bits that shaded, SMBus host controller transmits those bits that non-shaded. Table shows encoding command byte. Table Write Byte SMBus Packet Address bits Write Command bits Data bits
Table Read Byte SMBus Packet Address bits Write Command bits Address bits Read Data bits
Table Send Byte SMBus Packet Address bits Write Command bits
Table Receive Byte SMBus Packet Address bits Read Table SMBus Packet 0001 Read Address Device Address1 Data bits
NOTE:
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This 8-bit field. device that sent alert will respond Packet with address seven most significant bits. least significant undefined return `0'. Section 5.2.5 details Thermal Sensor Device addressing.
Table Command Byte Assignments Register RESERVED RESERVED RESERVED RRHL RRLL RESERVED RESERVED WRHL WRLL OSHT RESERVED Command Reset State 0000 0000 0000 0010 0111 1111 1100 1001 0111 1111 1100 1001 Function Reserved future Read processor core thermal data Read status byte (flags, busy signal) Read configuration byte Read conversion rate byte Reserved future Reserved future Read processor core thermal diode THIGH limit Read processor core thermal diode TLOW limit Write configuration byte Write conversion rate byte Reserved future Reserved future Write processor core thermal diode THIGH limit Write processor core thermal diode TLOW limit shot command (use send byte packet) Reserved future
commands reading writing registers thermal sensor except one-shot command (OSHT). one-shot command forces immediate start conversion cycle. conversion progress when one-shot command received, then command ignored. thermal sensor standby mode when one-shot command received, conversion performed sensor returns standby mode. one-shot command supported when thermal sensor auto-convert mode. thermal sensor auto-convert mode between conversions, then conversion rate timer resets, next automatic conversion takes place after full delay elapses. default command after reset reserved value (00h). After reset, receive byte packets will return invalid data until another command sent thermal sensor. This one-shot feature currently susceptible failure should used (i.e. don't issue one-shot commands) when auto convert mode. 5.2.6 5.2.6.1 THERMAL SENSOR REGISTERS Thermal Reference Registers
processor core thermal sensor internal thermal reference registers contain thermal reference value thermal sensor processor core thermal diodes. This value ranges from +127 -128 decimal expressed two's complement, eight-bit number. These registers saturating, i.e. values above represented decimal, values below -128 represented -128 decimal. 5.2.6.2 Thermal Limit Registers
thermal sensor thermal limit registers; they define high limits processor core thermal diode. encoding these registers same thermal reference registers. diode thermal value equals exceeds limits, then alarm Status Register triggered.
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5.2.6.3 Status Register
status register shown Table indicates which any) thermal value thresholds have been exceeded. also indicates conversion progress open circuit been detected processor core thermal diode connection. status register read required clear alarm bits that set. successful read status register will clear alarm bits that have been set, unless alarm condition persists. Table Thermal Sensor Status Register (MSB) (LSB) 5.2.6.4 Name BUSY RESERVED RESERVED RHIGH RLOW OPEN RESERVED RESERVED Configuration Register Function indicates that device's analog digital converter busy converting. Reserved future Reserved future indicates that processor core thermal diode high temperature alarm activated. indicates that processor core thermal diode temperature alarm activated. indicates open fault connection processor core diode. Reserved future use. Reserved future use.
configuration register controls operating mode (standby auto-convert) thermal sensor. Table shows format configuration register. RUN/STOP (high) then thermal sensor immediately stops converting enters standby mode. thermal sensor will still perform analog digital conversions standby mode when receives one-shot command. RUN/STOP clear (low) then thermal sensor enters auto-conversion mode.
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Table Thermal Sensor Configuration Register (MSB) Name RESERVED RUN/STOP Reset State Function Reserved future use. Standby mode control bit. high, device immediately stops converting, enters standby mode. low, device converts either one-shot mode automatically updates timed basis. Reserved future use.
5.2.6.5
RESERVED
Conversion Rate Register
contents conversion rate register determine nominal rate which analog digital conversions happen when thermal sensor auto-convert mode. Table shows mapping between conversion rate register values conversion rate. indicated Table conversion rate register default state (0.25 nominally) when thermal sensor powered There ±25% error tolerance between conversion rate indicated conversion rate register actual conversion rate. Table Thermal Sensor Conversion Rate Register Register Contents Conversion Rate (Hz) 0.0625 0.125 0.25 Reserved future
5.2.7
SMBus Device Addressing
addresses broadcast across SMBus, memory components claim those form "1010XXYZb". "XX" bits used enable devices cartridge adjacent addresses. hard-wired cartridge (`0') Scratch EEPROM pulled CC_SMB (`1') processor Information ROM. "XX" bits defined processor slot pins SC330 connector. These address pins pulled down ohm) ensure that memory components known state systems that support SMBus, only support partial implementation. read/write serial transaction. thermal sensor internally decodes upper address patterns from form "0011XXXZb", "1001XXXZb" "0101XXXZb". device's addressing, implemented, uses includes Hi-Z state address pin. Therefore thermal sensor supports unique resulting address ranges. Hi-Z state SA2, must left floating. system should drive SA0, will pulled driven) pull-down resistor processor substrate. Attempting drive either these signals Hi-Z state would cause ambiguity memory device address decode, possibly resulting devices responding, thus timing hanging SMBus. before, read/write serial transaction. Note that addresses form "0000XXXXb" reserved should generated SMBus master.
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thermal sensor latches signals power System designers should ensure that these signals valid input levels before thermal sensor powers This should done pulling pins CCSMB 1K-ohm smaller resistor. Additionally, left unconnected achieve tri-state state. designer desires drive with logic designer must ensure that pins valid input levels (see Table before VCCSMB begins ramp. system designer must also ensure that their particular system implementation does excessive capacitance (>50 address inputs. Excess capacitance address inputs cause address recognition problems Figure shows logical diagram connections. Table Table describe address connections they affect addressing devices.
Table Thermal Sensor SMBus Addressing Address (Hex) Upper Address Slot Select 0011 0011 0101 0101 1001 1001 b[7:0] 0011000Xb 0011010Xb 0101001Xb 0101011Xb 1001100Xb 1001110Xb 8-bit Address Word Serial
NOTES:
Upper address bits decoded conjunction with select pins. tri-state state this achieved leaving this unconnected.
Note that system management software must aware slot number-dependent changes address thermal sensor. Table Memory Device SMBus Addressing Address (Hex) Upper Address Slot Select (SA1) (SA0) Memory Device Select Device Addressed
bits A0h/A1h A2h/A3h A4h/A5h A6h/A7h A8h/A9h AAh/ABh ACh/ADh AEh/AFh 1010 1010 1010 1010 1010 1010 1010 1010
Scratch EEPROM processor Information Scratch EEPROM processor Information Scratch EEPROM processor Information Scratch EEPROM processor Information
Though this addressing scheme targeted 4-way systems, more processors supported using multiplexed separate) SMBus implementation.
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THERMAL SPECIFICATIONS
THERMAL SPECIFICATIONS DESIGN CONSIDERATIONS
Pentium® Xeonprocessor MHz+ will thermal plate heat sink attachment. thermal plate interface intended provide multiple types thermal solutions. This chapter will provide necessary data thermal solution developed. Figure thermal plate location.
Figure Thermal Plate View
Thermal Specifications
This section provides power dissipation specifications each variation Pentium Xeon processor MHz+. thermal plate flatness also specified S.E.C. cartridge. 6.1.1 POWER DISSIPATION
Table provides thermal design power dissipation Pentium Xeon processor MHz+. While processor core dissipates majority thermal power, system designer should also aware thermal power dissipated OCVR. Systems should design highest possible thermal power, even processor with lower frequency planned. thermal plate attach location thermal solutions. maximum temperature entire thermal plate surface shown Table processor power dissipated through thermal plate other paths. power dissipation combination power from OCVR, processor core (with integrated Cache), AGTL+ termination resistors. overall system thermal design must comprehend Thermal power. combined power from processor core, including second level cache, OCVR that dissipates through thermal plate Thermal power. heat sink should designed dissipate Thermal power. thermal sensor feature processor cannot used measure TPLATE. TPLATE specification must regardless reading processor's thermal sensor order ensure adequate cooling entire Pentium Xeon processor MHz+.
PENTIUM® XEONPROCESSOR with 256KB Cache
THERMAL SPECIFICATIONS
Table Power Dissipation Frequency Core Power 2.8V OCVR Power 5/12V OCVR Power 2.8V Cartridge Power 5/12V Cartridge Power 2.8V Thermal Power 5/12V Thermal Power AGTL+ Power Tplate Tplate
16.9 18.6 20.4 22.2 24.0 25.9 27.0
20.8 23.0 25.2 27.4 29.6 32.0 33.3
21.6 23.9 26.2 28.5 30.8 33.2 34.6
18.8 20.8 22.8 24.8 26.8 28.9 30.2 37.0
19.2 21.3 23.3 25.4 27.4 29.6 30.8 37.0
NOTES:
These values specified nominal VCC_CORE processor core with integrated cache. Core power indicates combined worst-case power that dissipated processor cache. This value will determined after product been characterized. Cartridge power indicates worst-case power that dissipated processor, cache OCVR. possible AGTL+ bus, processor core full power simultaneously. Thermal power (which should used thermal designs) indicates worst-case power that dissipated processor, cache OCVR (since OCVR does contact Thermal Plate). De-rating thermal design power result exceeding Tplate maximum temperature specification, which result immediate system failure degradation processor's functional lifetime. AGTL+ power worstcase power dissipated termination resistors AGTL+ bus. "FMB" suggested design guideline flexible motherboard design. disabled Pentium Xeon processor MHz+ OCVR draws approximately load 2.8V VCC_CORE from motherboard VRM. your system needs maintain regulation with disabled Pentium Xeon processor MHz+ (OCVR_EN inactive), output minimum load specification should less. Thermal Power specifications have been recently redefined. These values based device characterization reflect silicon design changes lower processor power consumption. Absolute power consumption changed; however, maximum thermal power specifications being updated reflect actual silicon performance. Thermal Power values represent thermal design point required cool Pentium Xeon processor MHz+ platform environment
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THERMAL SPECIFICATIONS
6.1.2
PLATE FLATNESS SPECIFICATION
thermal plate flatness Pentium® Xeonprocessor MHz+ specified 0.010" across entire thermal plate surface, with more than 0.003" step anywhere surface plate, shown Figure
Figure Plate Flatness Reference
Processor Thermal Analysis
6.2.1 THERMAL SOLUTION PERFORMANCE
Processor cooling solutions should attach thermal plate. processor cover designed thermal solution attachment. complete thermal solution must adequately control thermal plate below maximum above minimum specified Table performance thermal solution defined thermal resistance between thermal plate ambient around processor thermal plate ambient). lower thermal resistance between thermal plate ambient air, more efficient thermal solution required thermal plate ambient dependent upon maximum allowed thermal plate temperature (TPLATE), local ambient temperature (TLA thermal plate power (PPLATE). thermal plate ambient (TPLATE PPLATE maximum TPLATE thermal plate power listed Table function system design. Table provides example resultant thermal solution performance Pentium Xeon processor MHz+ different ambient temperatures around processor
Table Example Thermal Solution Performance Thermal Solution Performance Pentium Xeon processor MHz+ watts) thermal plate ambient (°C/watt) 35°C Local Ambient Temperature 40°C 45°C
0.54
0.40
0.27
Theta thermal plate ambient value made primary components: thermal resistance between thermal plate heat sink (theta thermal plate heat sink thermal resistance between heat sink ambient around processor (theta heat sink critical, controllable factor decrease resultant value theta thermal plate heat sink management thermal interface
PENTIUM® XEONPROCESSOR with 256KB Cache
THERMAL SPECIFICATIONS
between thermal plate heat sink. other controllable factor (theta heat sink determined design heat sink airflow around heat sink. General Information thermal interfaces heat sink design constraints found AP-586, Pentium Processor Thermal Design Guidelines (Order Number 243331). 6.2.2 THERMAL PLATE HEAT SINK INTERFACE MANAGEMENT GUIDE
Figure shows suggested interface agent dispensing areas when using either Intel suggested interface agent. Actual user area interface agent selections will determined system issues meeting TPLATE requirements.
Figure Interface Agent Dispensing Areas Thermal Plate Temperature Measurement Points
NOTES:
Interface agent suggestions: ShinEtsu* G749 Thermoset* TC330; Dispense volume adequate ensure required minimum area coverage when cooling solution attached. Areas suggested processor core OCVR products. Recommended cooling solution mating surface flatness greater than 0.007" flatter. Temperature entire thermal plate surface exceed Pentium® Xeonprocessor MHz+ combination interface agent, cooling solution, flatness condition, etc., ensure this condition met. Thermocouple measurement locations expected high temperature locations without external heat source influence. Ensure that external heat sources cause violation TPLATE requirements
PENTIUM® XEONPROCESSOR with 256KB Cache
THERMAL SPECIFICATIONS
6.2.3 6.2.3.1 MEASUREMENTS THERMAL SPECIFICATIONS Plate Temperature Measurement
ensure functional reliable processor operation, processor's thermal plate temperature (TPLATE) must maintained below maximum TPLATE above minimum TPLATE specified Table Power from processor core transferred thermal plate locations Pentium Xeon processor MHz+ products. Figure shows locations PLATE measurement directly above these transfer locations. Thermocouples used measure PLATE special care required ensure accurate temperature measurement. Before taking temperature measurements, thermocouples must calibrated. When measuring temperature surface, errors introduced measurement handled properly. Such measurement errors poor thermal contact between thermocouple junction measured surface, conduction through thermocouple leads, heat loss radiation convection, contact between thermocouple cement heat sink base. minimize these errors, following approach recommended: gauge finer diameter type thermocouples. Intel's laboratory testing done using thermocouple made Omega* (part number: 5TC-TTK-36-36). Attach each thermocouple bead junction surface thermal plate locations specified Figure using high thermal conductivity cements. thermocouple should attached angle heat sink attached thermal plate. heat sink attached thermal plate heat sink does cover location specified TPLATE measurement, thermocouple should attached angle (refer Figure 20). thermocouple should attached angle heat sink attached thermal plate heat sink covers location specified TPLATE measurement (refer Figure 21).
hole size through heat sink base route thermocouple wires should smaller than 0.150" diameter. Make sure there contact between thermocouple cement heat sink base. This contact will affect thermocouple reading.
000899
Figure Technique Measuring TPLATE with Angle Attachment
000900
Figure Technique Measuring TPLATE with Angle Attachment
PENTIUM® XEONPROCESSOR with 256KB Cache
MECHANICAL SPECIFICATIONS
MECHANICAL SPECIFICATIONS
Pentium® Xeonprocessor MHz+ uses S.E.C. cartridge package technology. S.E.C. cartridge contains processor core, OCVR other components. S.E.C. cartridge package connects baseboard through edge connector. Mechanical specifications processor given this section. Section 1.1.1 complete terminology listing. Figure shows thermal plate side view cover side view Pentium Xeon processor MHz+. Figure shows Pentium Xeon processor MHz+ S.E.C. cartridge cooling solution attachment feature details thermal plate depict package form factor dimensions retention enabling features S.E.C. cartridge. processor edge connector defined this document referred "SC330.1". This connector definition mechanically same existing SC300. SC330 connector specifications further details edge connector. Table Table provide edge finger SC330.1 connector signal definitions Pentium Xeon processor MHz+. signal locations SC330 edge connector used signal routing, simulation component placement baseboard.
me001.wmf
Figure Isometric View S.E.C. Cartridge
NOTES: (Use retention holes retention indents optional) SC330 connector specifications, SC330 Connector Specification. dimensions inches figures through
PENTIUM® XEONPROCESSOR with 256KB Cache
MECHANICAL SPECIFICATIONS
Figure S.E.C. Cartridge Cooling Solution Attach Details (Notes follow)
PENTIUM® XEONPROCESSOR with 256KB Cache
MECHANICAL SPECIFICATIONS
Figure S.E.C. Cartridge Retention Enabling Details (Notes follow)
PENTIUM® XEONPROCESSOR with 256KB Cache
MECHANICAL SPECIFICATIONS
Figure Cartridge Retention Enabling Details
Maximum protrusions mechanical heat sink attach media into cartridge during assembly installed condition exceed 0.160" from external face thermal plate. Specified cover retention indent dimension external indent. Indent walls have 1.0degree draft, with wider section external end. Clip extension internal surface retention slots should little possible exceed 0.040". Tapped holes cooling solution attach. torque recommendation screw tapped hole inch-lb.
PENTIUM® XEONPROCESSOR with 256KB Cache
MECHANICAL SPECIFICATIONS
Weight
maximum weight Pentium® Xeonprocessor MHz+ thermal solution approximately grams.
Cartridge Connector Mating Details
staggered edge connector layout Pentium Xeon processor MHz+ makes processor susceptible damage from cartridge insertion while power applied connector. Extra care should taken ensure that this does occur. electrical mechanical integrity processor edge fingers specified insertion/extraction cycles.
Figure Side View Connector Mating Details
NOTES: Dimensional variation when cartridge fully installed substrate bottomed connector. Actual system installed height tolerance subject users manufacturing tolerance SC330 connector baseboard. Retention devices this cartridge must accommodate this cartridge "Float" relative connector, without preload edge contacts axes. (see figure axis orientation) Fully installed dimensions must maintained user's retention device. Cartridge backout from fully installed position exceed 0.020.
Figure View Cartridge Insertion Pressure P
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