3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE

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3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE

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IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS, VOLT TOLERANT BUS-HOLD
Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs, tolerant Supports insertion Available SSOP TSSOP packages
FEATURES:
DESCRIPTION
DRIVE FEATURES: APPLICATIONS:
High Output Drivers: ±24mA Reduced system switching noise
LVCH16373A 16-bit transparent D-type latch built using advanced dual metal CMOS technology. This high-speed, low-power latch ideal temporary storage data. LVCH16373A used implementing memory address latches, ports, drivers. Output Enable Latch Enable controls organized operate each device 8-bit latches 16-bit latch. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. pins LVCH16373A driven from either 3.3V devices. This feature allows device translator mixed 3.3V/5V supply system. LVCH16373A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
3.3V mixed voltage systems Data communication telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4735/2
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM TSTG IOUT Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100
Unit
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
DESCRIPTION
Names Data Inputs
Description Latch Enable Input Output Enable Inputs (Active LOW) 3-State Outputs
SSOP/ TSSOP VIEW
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
FUNCTION TABLE(1)
Inputs Outputs Q(2)
NOTES: HIGH Voltage Level Don't Care Voltage Level High-Impedance Output level before indicated steady-state input conditions were established.
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Latch Outputs enabled Power Dissipation Capacitance Latch Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS(1)
2.7V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Propagation Delay Output Enable Time Output Disable Time Set-up Time, data before HIGH Hold Time, data after HIGH Pulse Width HIGH Output Skew(2) Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
OPPOSITE PHASE INPUT TRANSITION SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH tPHL tPHL
Link
Propagation Delay
Pulse Generator D.U.T.
Link
VLOAD Open CONTROL INPUT
ENABLE
DISABLE
tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ
tPLZ
VLOAD/2
Link
VOUT
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
Link
OUTPUT
OUTPUT tPLH2 tPHL2
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Pulse Width
Link
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
ORDERING INFORMATION
Bus-Hold Temp. Range Family XXXX Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package
373A 16-Bit Transparent D-Type Latch with State Outputs Double-Density, ±24mA Bus-hold -40°C +85°C
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3.3V CMOS 16-BIT IDT74LVCH16373A TRANSPARENT D-TYPE LATCH WITH 3-STATE

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