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Intel® Xeon Processor at 1.40 GHz, 1.50 GHz, 1.70 GHz and 2 GHz

Order Number: 249665-002 September 2001

Intel® Xeon Processor at 1.40 GHz, 1.50 GHz, 1.70 GHz and 2 GHz
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Product Features
Available at 1.40, 1.50, 1.70 and 2 GHz Dual processing server / workstation support Binary compatible with applications running on previous members of the Intel microprocessor line Intel® NetBurst micro-architecture System bus frequency at 400 MHz - Bandwidth up to 3.2 Gbytes / sec Rapid Execution Engine: Arithmetic Logic Units (ALUs) run at twice the processor core frequency Hyper Pipelined Technology Advance Dynamic Execution - Very deep out-of-order execution - Enhanced branch prediction Level 1 Execution Trace Cache stores 12 K micro-ops and removes decoder latency from main execution loops - Includes 8 KB Level 1 data cache
256 KB Advanced Transfer Cache (on-die, full speed Level 2 (L2) cache) with 8-way associativity and Error Correcting Code (ECC) Enables system support of up to 64 GB of physical memory 144 new Streaming SIMD Extensions 2 (SSE2) instructions Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities - System Management mode - Multiple low-power states Advanced System Management Features - Processor Information ROM (PIROM) - OEM Scratch EEPROM - Machine Check Architecture (MCA)
The Intel® Xeon processor is designed for high-performance workstation and server applications. Based on the new Intel® NetBurst micro-architecture, it is binary compatible with previous Intel Architecture processors. The Intel Xeon processor is scalable to two processors in a multiprocessor system providing exceptional performance for applications running on advanced operating systems such as Windows XP, Windows 2000 and UNIX. The Intel Xeon processor extends the power of the Intel® Pentium® III Xeon processor with new features designed to make this processor the right choice for powerful workstation, advanced servers, and mission-critical applications. Advanced features simplify system management and meet the needs of a robust IT environment, resulting in maximized system up time, convenient system management, and optimal configuration.
Order Number: 249665-002 September 2001
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Contents
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Contents
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Contents
Figures
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Contents
Tables
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Revision History
Date of Release May 2001 August 2001 Revision No. -001 -002 Description This is the first release of this datasheet. - Included 2 GHz specifications - Added FC-BGA packaging details - Updated TAP Signal Group Signal Quality and DC Specifications
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Introduction
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Signals on the system bus use Assisted GTL+ (AGTL+) level voltages which are fully described in the appropriate platform design guide (refer to Section 1.3).
Terminology
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
· 603-pin socket -The connector which mates the Intel® Xeon processor to the motherboard.
The 603-pin socket is a surface mount technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment to the platform. See the 603 Pin Socket Design Guidelines for details regarding this socket.
· FC-BGA (Flip Chip Ball Grid Array) package- Microprocessor packaging using "flip
chip" design, where the processor is attached to the substrate face-down, within a ball grid array package. This package is then mounted onto an interposer to interface with the platform.
· Intel® Xeon processor -The entire product including processor core in its OLGA or FCBGA package, integrated heat spreader (IHS), and interposer.
· Integrated Heat Spreader (IHS) -The surface used to attach a heatsink or other thermal
solution to the processor.
· Interposer -The structure on which the processor core package and I / O pins are mounted. · OLGA (Organic Land Grid Array) Package -Microprocessor packaging using "flip chip"
design, where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance, within an organic land grid array package.
specifications are to the pads of the processor core.
· Processor Information ROM (PIR)-A memory device located on the Intel Xeon
· Retention mechanism -The support pieces that are mounted through the motherboard and to
the chassis wall to provide added support and retention for processor heatsinks.
· Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)-A
memory device located on the Intel Xeon processor and addressable via the SMBus which
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can be used by the OEM to store information useful for system management. See Section 7.4 for details on the Scratch EEPROM.
· SMBus-System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the system. It is based on the principals of the operation of the I2C two-wire serial bus from Phillips Semiconductor.
State of Data
The data contained within this document is subject to change. It is the best information that Intel is able to provide by the publication date of this document.
References
The reader of this specification should also be familiar with material and concepts presented in the following documents:
Intel Order Number1 241618
245470 245471 245472 249671 298348 249672 developer.intel.com 249206 249205 249679 249673 developer.intel.com2 developer.intel.com developer.intel.com developer.intel.com developer.intel.com www.sbs-forum.org developer.intel.com
Processor Thermal Solution Functional Specification
Intel® Xeon Processor I / O Buffer Models Intel® Xeon Processor Enabled Components ProE Files Intel Xeon Intel Xeon
Processor Enabled Components IGES Files Processor FloTherm Model
Intel® Xeon Processor Core Boundary Scan Descriptor Language (BSDL) Model System Management Bus Specification, 2.0 Wired for Management Baseline 2.0
NOTES: 1. Contact your Intel representative for the latest revision of the documents without order numbers. 2. The I / O Buffer Models are in IBIS format.
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Intel® Xeon Processor
Electrical Specifications
System Bus and GTLREF
Most Intel® Xeon processor system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Unlike the Intel® Pentium® III Xeon processor family, the termination voltage level for the Intel® Xeon Processor AGTL+ signals is VCC, the operating voltage of the processor core. P6 family processors utilize a fixed 1.5V termination voltage known as VTT . The use of a termination voltage that is determined by the processor core allows better voltage scaling on the system bus for Intel® Xeon processors. Because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. Design guidelines for the Intel Xeon processor system bus are detailed in the appropriate platform design guidelines (refer to Section 1.3). The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board (See Table 11 for GTLREF specifications). Termination resistors are provided on the processor silicon and are terminated to its core voltage (VCC). The on-die termination resistors are a selectable feature and can be enabled or disabled via the ODTEN pin. For end bus agents, on-die termination can be enabled to control reflections on the transmission line. For middle bus agents, on-die termination must be disabled. The Intel 860 chipset provides on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. Note: Some AGTL+ signals do not include on-die termination and must be terminated on the system board. See Table 3 for details regarding these signals. The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. Please refer to http / / www.developer.intel.com to obtain the buffer electrical models, Intel® Xeon Processor I / O Buffer Models.
Power and Ground Pins
For clean on-chip power distribution, Intel® Xeon processors have 155 VCC (power) and 155 VSS (ground) inputs. All power pins must be connected to VCC, while all VSS pins must be connected to the system ground plane. The processor VCC pins must be supplied the voltage determined by the VID (Voltage ID) pins.
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the Intel® Xeon processor is capable of generating large instantaneous current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition.
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Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines.
VCC Decoupling
Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and maintain a low interconnect resistance from the regulator (or VRM pins) to the 603-pin socket. Bulk decoupling is provided on the voltage regulation module (VRM) to meet the needs of large current swings. The power delivery path must be capable of delivering enough current while maintaining the required tolerances (defined in Table 5). For further information regarding power delivery, decoupling, and layout guidelines, refer to the appropriate platform design guidelines.
System Bus AGTL+ Decoupling
The processor integrates a portion of the required high frequency decoupling capacitance on the processor package. However, additional high frequency capacitance must be added to the system board to properly decouple the return currents from the system bus. Bulk decoupling must also be provided by the system board for proper AGTL+ bus operation. Decoupling guidelines are described in the appropriate platform design guidelines.
System Bus Clock (BCLK1:0) and Processor Clocking
BCLK1:0 directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Intel® Xeon processor core frequency is a multiple of the BCLK1:0 frequency. The processor bus ratio multiplier will have a maximum ratio set during manufacturing. Platforms will use the ratio-setting pins, as in previous generation Intel processors, to configure the processor to run at its maximum ratio or lower. This feature is provided to ensure that multiprocessing systems, which typically are not fully populated with processors at the time of purchase, may be upgraded at a later date and have all processors run at the same core frequency. Clock multiplying within the processor is provided by the internal PLL, which requires a constant frequency BCLK1:0 input with exceptions for spread spectrum clocking. Processor DC and AC specifications for the BCLK1:0 inputs are provided in Table 6 and Table 12, respectively. These specifications must be met while also meeting signal integrity requirements as outlined in Chapter 3.0. Unlike previous processors, Intel® Xeon processors utilize differential clocks. Details regarding BCLK1:0 driver specifications are provided in the CK00 Clock Synthesizer / Driver Design Guidelines document. The BCLK1:0 inputs directly control the operating speed of the system bus interface. The processor core frequency must be configured during Reset by using the A20M#, IGNNE#, LINT1 / NMI, and LINT0 / INTR pins (see Table 1). The value on these pins during Reset determines the multiplier that the Phase Lock Loop (PLL) will use for the internal core clock. The processor is limited to the maximum bus-to-core ratio and only the maximum or lower ratios are supported. If a ratio higher than the maximum is chosen, the processor will default to the maximum ratio. The maximum ratio for each processor is equal to the core frequency divided by the bus frequency marked on the processor.
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Phase Lock Loop (PLL) Power and Filter
VCCA and VCCIOPLL are power sources required by the PLL clock generators on the processor silicon. Since these PLLs are analog in nature, they require quiet power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I / O timings as well as internal core timings (i.e. maximum frequency). To prevent this degradation, these supplies must be low pass filtered from VCC. A typical filter topology is shown in Figure 1. The AC low-pass requirements, with input at VCC and output measured across the capacitor (CA or CIO in Figure 1), is as follows:
The filter requirements are illustrated in Figure 2. For recommendations on implementing the filter refer to the appropriate platform design guidelines. Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution
L VCCA CA PLL Processor Core
VSSA CIO R VCCIOPLL L
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Intel® Xeon Processor
Figure 2. Phase Lock Loop (PLL) Filter Requirements
System Bus to Core Frequency Ratios
The frequency multipliers supported are shown in Table 1. Other combinations will not be validated nor supported by Intel. For a given processor, only the ratios which result in a core frequency equal to or less than the frequency marked on the processor are supported.
NOTES: 1. Diagram not to scale. 2. No specifications for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05MHz.
0.2 dB 0 dB -0.5 dB
-34 dB
-28 dB
passband
fpeak
66 MHz
high frequency band
fcore
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Table 1.
Core Frequency to System Bus Multiplier Configuration
Multiplier for System Bus-to-Core Frequency1 1 / 8 1 / 10 1 / 11 1 / 12 1 / 13 1 / 14 1 / 15 1 / 16 1 / 17 1 / 18 1 / 19 1 / 20 Core Frequency 800 MHz 1.00 GHz 1.10 GHz 1.20 GHz 1.30 GHz 1.40 GHz 1.50 GHz 1.60 GHz 1.70 GHz 1.80 GHz 1.90 GHz 2.00 GHz LINT1 / NMI H H H H H H H L L L L L A20M# H H H L L L L H H H H L IGNNE# H L L H H L L H H L L H LINT0 / INTR H H L H L H L H L H L H
NOTES: 1. Refer to the Intel® Xeon Processor Specification Update for processor stepping details.
Mixing Processors
Mixing components operating at different internal clock frequencies is not supported and has not been validated by Intel. Not all operating systems can support multiple processors with mixed frequencies. Intel only supports and validates multi-processor configurations where all processors operate with the same system bus, core frequencies, and VID settings. Mixing of processors of different steppings (as per the CPUID) is supported in limited configurations (stepping IDs must not be separated by more than one stepping). For determining the level of support for mixed steppings, refer to the Intel® Xeon Processor Specification Update. Details on CPUID are provided in the AP-485, Intel Processor Identification and the CPUID Instruction application note.
Voltage Identification
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Table 2.
Voltage Identification Definition
Mixing Processors of Different Voltages
Mixing processors operating at different VID settings (voltages) is not supported and will not be validated by Intel.
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Reserved Or Unused Pins
System Bus Signal Groups
In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I / O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I / O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals whose timings are specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 3 identifies which signals are common clock, source synchronous and asynchronous.
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Table 3.
System Bus Signal Groups
Signal Group AGTL+ Common Clock Input Type Synchronous to BCLK1:0 Signals 1 BPRI#, BR3:1#2, 3, DEFER#, RESET#2, RS2:0#, RSP#, TRDY# ADS#, AP1:0#, BINIT#7, BNR#7, BPM5:0#2, BR0#2, DBSY#, DP3:0#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7 Signals REQ4:0#, A16:3#6 A35:17# AGTL+ Source Synchronous I / O Synchronous to assoc. strobe
AGTL+ Common Clock I / O
Synchronous to BCLK1:0
Associated Strobe ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
D15:0#, DBI0# D31:16#, DBI1# D47:32#, DBI2# D63:48#, DBI3#
AGTL+ Strobes Async GTL+ Input 4 Async GTL+ Output 4 System Bus Clock TAP Input
TAP Output 4 SMBus Interface 8
Power / Other
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Intel® Xeon Processor
Asynchronous GTL+ Signals
Intel® Xeon processors do not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0 / INTR, LINT1 / NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR# and other non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers. All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+ signals, however the outputs are not driven high (during the logical 0-to-1 transition) by the processor (the major difference between GTL+ and AGTL+). Asynchronous GTL+ signals do not have setup or hold time specifications in relation to BCLK1:0. However, all of the asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them. See Table 8 and Table 15 for the DC and AC specifications for the asynchronous GTL+ signal group. See Section 7.2 for additional timing requirements for entering and leaving low power states.
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may be required with each driving a different voltage level. See Table 9 and Table 17 for the DC and AC specifications for the TAP signal group. Refer to Section 9.0 for more detailed information.
Maximum Ratings
Table 4.
Processor Absolute Maximum Ratings
Symbol TSTORAGE VCC VinAGTL+ VinGTL+ VinSMBus IVID Parameter Processor storage temperature Any processor supply voltage with respect to VSS AGTL+ buffer DC input voltage with respect to VSS Async GTL+ buffer DC input voltage with respect to Vss SMBus buffer DC input voltage with respect to Vss Max VID pin current Min -40 -0.5 -0.3 -0.3 -0.3 Max 85 2.1 2.1 2.1 6.0 5 Unit °C V V V V mA 1 2 Notes
NOTE: 1. Please contact Intel for storage requirements in excess of one year. 2. This rating applies to any pin of the processor.
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Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the pin listings and Section 5.2 for the signal definitions. The voltage and current specifications of the processor are detailed in Table 5. The DC specifications for the AGTL+ signals are listed in Table 7. The system bus clock signal group and the SMBus interface signal group are detailed in Table 6 and Table 10, respectively. Previously, legacy signals (CMOS) and Test Access Port (TAP) signals to the processor used low-voltage CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The DC specifications for the asynchronous GTL+ signal group are listed in Table 8 and the TAP signal group Table 9. Table 5 through Table 10 list the DC specifications for the processor and are valid only while meeting specifications for case temperature (TCASE as specified in Chapter 6.0), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.
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Table 5.
Voltage and Current Specifications
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Table 6.
System Bus Differential BCLK DC Specifications
Symbol VL VH VCROSS VOV VUS VRBM VTH Parameter Input Low Voltage Input High Voltage Crossing Voltage Overshoot Undershoot Ringback Margin Threshold Region 0.660 0.45 (VH-VL) N / A N / A 0.200 VCROSS -0.100 Min Typ 0 0.710 0.5 (VH-VL) N / A N / A N / A VCC - 0.30 0.55 (VH-VL) 0.300 0.300 N / A VCROSS+0.100 Max Unit V V V V V V V Figure 5 5 5 5 5 5 5 7 2, 7 3 4 5 6 Notes 1
NOTES:. 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. VH and VL are the voltages observed at the processor. 3. Overshoot is defined as the absolute value of the maximum voltage allowed above the VH level. 4. Undershoot is defined as the absolute value of the maximum voltage allowed below the VSS level. 5. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 6. Threshold Region is defined as a region centered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 7. The VCC referred to in these specifications refers to instantaneous VCC.
Table 7.
AGTL+ Signal Group DC Specifications
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Chapter 3.0. 5. Refer to Intel® Xeon Processor I / O Buffer Models for I / V characteristics. 6. The VCC referred to in these specifications refers to instantaneous VCC.
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Table 8.
Asynchronous GTL+ Signal Group DC Specifications
Symbol VIL VIH VOL VOH IOL ILI ILO Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Current Input Leakage Current Output Leakage Current N / A N / A Min -0.150 GTLREF + (0.1 VCC / 1.3) -0.150 N / A Max GTLREF - (0.1 VCC / 1.3) VCC 0.400 VCC 56 Unit V V V V mA µA µA Notes 1 5 4, 5 2 3, 4, 5 6
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Parameter will be measured at 56 mA (for use with system inputs). 3. All outputs are open-drain. 4. VIH and VOH may experience excursions above VCC. However, input signal drivers must comply with the signal quality specifications in Chapter 3.0. 5. The VCC referred to in these specifications refers to instantaneous VCC. 6. The maximum output current for asynch GTL+ is not specified into the test load shown in Figure 3.
Table 9.
TAP Signal Group DC Specifications
Table 10. SMBus Signal Group DC Specifications (Page 1 of 2)
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Table 10. SMBus Signal Group DC Specifications (Page 2 of 2)
VOL IOL ILI ILO CSMB Output Low Voltage Output Low Current Input Leakage Current Output Leakage Current SMBus Pin Capacitance 0 N / A N / A N / A 0.400 3.0 V mA µA µA pF 4
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. These parameters are based on design characterization and are not tested. 3. All DC specifications for the SMBus signal group are measured at the processor pins. 4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine maximum rise and fall times for SMBus signals.
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AGTL+ System Bus Specifications
Table 11. AGTL+ Bus Voltage Definitions
System Bus AC Specifications
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The timings specified in this section should be used in conjunction with the I / O buffer models provided by Intel. These I / O buffer models, which include package information, are available for the processor in IBIS format. AGTL+ layout guidelines are also available in the appropriate platform design guidelines.
Note:
Care should be taken to read all notes associated with a particular timing parameter.
Table 12. System Bus Differential Clock AC Specifications
T# Parameter System Bus Frequency T1: BCLK1:0 Period T2: BCLK1:0 Period Stability T3: TPH BCLK1:0 Pulse High Time T4: TPL BCLK1:0 Pulse Low Time T5: BCLK1:0 Rise Time T6: BCLK1:0 Fall Time 10.00 N / A 3.94 3.94 175 175 5 5 Min Nom Max 100.0 10.20 150 6.12 6.12 700 700 Unit MHz ns ps ns ns ps ps 5 5 5 5 6 6 5 Figure 2 3 4, 5 Notes1
Table 13. System Bus Common Clock AC Specifications
T# Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width Min 0.20 0.65 0.40 1.00 Max 1.45 N / A N / A 10.00 Unit ns ns ns ms Figure 6 6 6 9 Notes1, 2, 3 4 5 5 6, 7, 8
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Table 14. System Bus Source Synchronous AC Specifications
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Table 15. Asynchronous GTL+ AC Specifications
T# Parameter T35: Async GTL+ input pulse width, except PWRGOOD T36: PWRGOOD to RESET# de-assertion time T37: PWRGOOD inactive pulse width T38: PROCHOT# pulse width T39: THERMTRIP# to power down sequence Min 2 1 10 500 0 0.5 Max N / A 10 N / A Unit BCLKs ms BCLKs us sec 10 10 12 13 5 6 Figure
Notes
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. All AC timings for the Asynchronous GTL+ signals are referenced to the BCLK0 rising edge at Crossing Voltage (VCROSS). All Asynchronous GTL+ signal timings are referenced at GTLREF. 3. These signals may be driven asynchronously. 4. Refer to Section 7.2 for additional timing requirements for entering and leaving low power states. 5. Refer to the PWRGOOD signal definition in Section 5.2 for more detail information on behavior of the signal. 6. Length of assertion for PROCHOT# does not equal internal clock modulation time. Time is allocated after the assertion of PROCHOT# for the processor to complete current instruction execution.
Table 16. System Bus AC Specifications (Reset Conditions)
T# Parameter T45: Reset Configuration Signals (A31:3#, BR1:0#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A31:3#, BR1:0#, INIT#, SMI#, A20M#, IGNNE#, LINT1:0) Hold Time T47: Reset Configuration Signals (A20M#, IGNNE#, LINT1:0) Setup Time T48: Reset Configuration Signals (A20M#, IGNNE#, LINT1:0) Delay Time Min 4 Max Unit BCLKs Figure 9 2 Notes1
BCLKs
ms BCLKs
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Before the de-assertion of RESET# 3. After the clock that de-asserts RESET#. 4. After the assertion of RESET#.
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Table 17. TAP Signal Group AC Specifications
T# Parameter T55: TCK Period T56: TCK Rise Time T57: TCK Fall Time T58: TMS, TDI Rise Time T59: TMS, TDI Fall Time T61: TDI, TMS Setup Time T62: TDI, TMS Hold Time T63: TDO Clock to Output Delay T64: TRST# Assert Time 0 3.0 0.5 2 3.5 Min 60.0 9.5 9.5 8.5 8.5 Max Unit ns ns ns ns ns ns ns ns TTCK Figure 4 4 4 4 4 11 11 11 12 4 4 4 4 5, 8 5, 8 6 7 Notes
Table 18. SMBus Signal Group AC Specifications
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6. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next transaction.
Processor AC Timing Waveforms
The following figures are used in conjunction with the AC timing tables, Table 12 through Table 18.
Note:
Figure 3. Electrical Test Circuit
VCC 600 mils, 42 ohms, 169 ps / in 2.4nH
Rload
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Figure 4. TCK Clock Waveform
Figure 5. Differential Clock Waveform
Tph Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tpl Tp
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Figure 6. System Bus Common Clock Valid Delay Timing Waveform
T0 BCLK1 BCLK0
Common Clock Signal (@ driver) Common Clock Signal (@ receiver)
valid TQ valid TR
valid
Figure 7. System Bus Source Synchronous 2X (Address) Timing Waveform
2.5 ns 5.0 ns 7.5 ns
BCLK1 BCLK0 ADSTB# (@ driver)
TP TR TH valid TS TJ TH TJ valid
A# (@ driver)
ADSTB# (@ receiver)
A# (@ receiver)
valid TN TM
valid
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Figure 8. System Bus Source Synchronous 4X (Data) Timing Waveform
2.5 ns 5.0 ns 7.5 ns
BCLK1 BCLK0 DSTBp# (@ driver)
DSTBn# (@ driver)
D# (@ driver)
DSTBp# (@ receiver)
DSTBn# (@ receiver)
D# (@ receiver)
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Figure 9. System Bus Reset and Configuration Timing Waveform
BCLK1
RESET# Tv Configuration (A20M#, IGNNE#, LINT1:0) Configuration (A14:5#, BR0#, (A31:3, SMI#, FLUSH#, INT#) INIT#, BR1:0#) Ty Safe Tw Valid Tz Valid Tx
PWRGOOD
PCD-764
Figure 10. Power-On Reset and Configuration Timing Waveform
core, VCC, Vcc VREF PWRGOOD Ta RESET# Tb
Configuration (A20M#, IGNNE#, LINT1:0)
Tc Valid Ratio
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Figure 11. TAP Valid Delay Timing Waveform
Figure 12. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
Figure 13. THERMTRIP# Power Down Waveform
THERMTRIP# Vcc
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Figure 14. SMBus Timing Waveform
HD DAT
SU STO
Data t BUF S START S START
P STOP
Figure 15. SMBus Valid Delay Timing Waveform
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Intel® Xeon Processor
System Bus Signal Quality Specifications
Source synchronous data transfer requires the clean reception of data signals and their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. Ringback and signal non-monotinicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines. Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. Additionally, overshoot and undershoot can cause timing degradation due to the build up of inter-symbol interference (ISI) effects. For these reasons, it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. This section documents signal quality metrics used to derive topology and routing guidelines through simulation and all specifications are specified at the processor core (pad measurements). Specifications for signal quality are for measurements at the processor core only and are only observable through simulation. The same is true for all system bus AC timing specifications in Section 2.13. Therefore, proper simulation of the processor system bus is the only means to verify proper timing and signal quality metrics.
System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines
Table 19 describes the signal quality specifications at the processor pads for the processor system bus clock (BCLK) signals. Figure 16 describes the signal quality waveform for the system bus clock at the processor pads.
Table 19. BCLK Signal Quality Specifications
Parameter BCLK1:0 Overshoot BCLK1:0 Undershoot BCLK1:0 Ringback Margin BCLK1:0 Threshold Region Min N / A N / A 0.20 N / A Max 0.30 0.30 N / A 0.10 Unit V V V V Figure 16 16 16 16 2 Notes1
NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This specification is an absolute value.
Datasheet
Intel® Xeon Processor
Figure 16. BCLK1:0 Signal Integrity Waveform
Overshoot BCLK1 VH Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot
System Bus Signal Quality Specifications and Measurement Guidelines
Ringback Guidelines
Many scenarios have been simulated to generate a set of system bus layout guidelines which are available in the appropriate platform design guidelines. Table 20 provides the signal quality specifications for the AGTL+ and asynchronous GTL+ signal groups. Table 21 demonstrates the signal quality specification for the TAP signals. These specifications are for use in simulating signal quality at the processor core pads. Maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in Table 22 through Table 25. System bus ringback tolerance for AGTL+ and asynchronous GTL+ signal groups are shown in Figure 17 (low-to-high transitions) and Figure 18 (high-to-low transitions). The TAP signal group includes hysteresis on the input buffers and thus has relaxed ringback requirements when compared to the other buffer types. Figure 19 shows the system bus ringback tolerance for low-to-high transitions and Figure 20 for high-to-low transitions. The hysteresis values Vt+ and Vt- can be found in Table 9.
Table 20. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups
Signal Group All Signals All Signals Transition 01 10 Maximum Ringback (with Input Diodes Present) GTLREF + 0.100 GTLREF - 0.100 Unit V V Figure 17 18 Notes 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7
NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 3. Specifications are for the edge rate of 0.3 - 4.0V / ns. 4. All values specified by design characterization. 5. Please see Section 3.2.3 for maximum allowable overshoot.
Datasheet
Intel® Xeon Processor
6. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported. 7. Intel recommends simulations not exceed a ringback value of GTLREF + / - 200 mV to allow margin for other sources of system noise.
Figure 17. Low-to-High Receiver Ringback Tolerance for AGTL+ and Async GTL+ Signals
+100 mV GTLREF -100 mV
Noise Margin
Figure 18. High-to-Low Receiver Ringback Tolerance for AGTL+ and Async GTL+ Signals
+100 mV GTLREF -100 mV
Noise Margin
Table 21. Ringback Specifications for TAP Signal Group
Signal Group TAP TAP Transition 01 10 Maximum Ringback (with input diodes present) VT+(max) to VT-(max) VT-(max) to VT+(max) Units V V Figure 19 20 Notes 1, 2, 3, 4, 5 1, 2, 3, 4, 5
NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 3. Specifications are for the edge rate of 0.3 - 4.0V / ns. 4. All values specified by design characterization. 5. Please see Section 3.2.3 for maximum allowable overshoot.
Datasheet
Intel® Xeon Processor
Figure 19. Low-to-High Receiver Ringback Tolerance for TAP Buffers
Threshold Region to switch receiver to a logic 1.
Vt+ (max) Vt+ (min) 0.5 Vcc Vt- (max)
Allowable Ringback
Figure 20. High-to-Low Receiver Ringback Tolerance for TAP Buffers
Allowable Ringback
Vt+ (min) 0.5 Vcc Vt- (max) Vt- (min)
Threshold Region to switch receiver to a logic 0.
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Intel® Xeon Processor
Overshoot / Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS. The overshoot / undershoot specifications limit transitions beyond VCC or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot or undershoot events on any input, output, or I / O buffer if the charge is large enough (i.e., if the over / undershoot is great enough). Determining the impact of an overshoot / undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (AF). Permanent damage to the processor is the likely result of excessive overshoot / undershoot. When performing simulations to determine impact of overshoot and undershoot, ESD diodes must be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. ESD diodes modelled within Intel I / O buffer models do not clamp undershoot or overshoot and will yield correct simulation results. If other I / O buffer models are being used to characterize the processor system bus, care must be taken to ensure that ESD models do not clamp extreme voltage levels. Intel I / O buffer models also contain I / O capacitance characterization. Therefore, removing the ESD diodes from an I / O buffer model will impact results and may yield excessive overshoot / undershoot.
Overshoot / Undershoot Magnitude
Magnitude describes the maximum potential difference between a signal and its voltage reference level. For the Intel® Xeon processor, both are referenced to VSS. It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently. Overshoot / undershoot magnitude levels must observe the absolute maximum specifications listed in Table 22 through Table 25. These specifications must not be violated at any time regardless of bus activity or system state. Within these specifications are threshold levels that define different allowed pulse durations. Provided that the magnitude of the overshoot / undershoot is within the absolute maximum specifications (2.3V for overshoot and -0.65V for undershoot), the pulse magnitude, duration and activity factor must all be used to determine if the overshoot / undershoot pulse is within specifications.
Overshoot / Undershoot Pulse Duration
Pulse duration describes the total time an overshoot / undershoot event exceeds the overshoot / undershoot reference voltage (VCC). The total time could encompass several oscillations above the reference voltage. Multiple overshoot / undershoot pulses within a single overshoot / undershoot event may need to be measured to determine the total pulse duration. Note 1: Oscillations below the reference voltage can not be subtracted from the total overshoot / undershoot pulse duration.
Activity Factor
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Intel® Xeon Processor
Reading Overshoot / Undershoot Specification Tables
Determining if a System Meets the Overshoot / Undershoot Specifications
The overshoot / undershoot specifications listed in the following tables specify the allowable overshoot / undershoot for a single overshoot / undershoot event. However most systems will have multiple overshoot and / or undershoot events that each have their own set of parameters (duration,
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Intel® Xeon Processor
· Absolute Maximum Overshoot magnitude of 2.3V must never be exceeded. · Absolute Maximum Overshoot is measured referenced to VSS, Pulse Duration of overshoot is
measured relative to VCC.
Table 22. Source Synchronous (400MHz) AGTL+ Signal Group Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes.
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Intel® Xeon Processor
Table 23. Source Synchronous (200MHz) AGTL+ Signal Group Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 ns. 3. AF is referenced to associated source synchronous strobes.
Table 24. Common Clock (100MHz) AGTL+ Signal Group Overshoot / Undershoot Tolerance
NOTES: 1. These specifications are measured at the processor pad. 2. BCLK period is 10 ns