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ADJ-702-300

SH7729R CPU

ADJ-702-300
SH7729R CPU
HS7729RSTC01H
CPU CPUCPU
SH7729R CPU CPU SH7729R SH7729R CPU :HS7729RSTC01H CPU CPU CPU HDI HDI HDI CPU CPU HDI OS ® ® Microsoft Windows 98 · SH7729R · SH3, SH3E, SH3-DSP · SuperH RISC engine · SuperH RISC engineC / C++ · SuperH RISC engine · CD-R · Hitachi Embedded Workshop E10A CPU · SH7729R E10A
Microsoft , Windows
1 1.1 1.2 1.3 1.4 1.5 1.6 CPU ............................................................... 1 .................................................................... 2 ................................................................ 2 .................................................................... 3 CD-R ..................................................................... 4 .................................................................... 4
2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 CPU ................................................ 7 HDI .............................................................. 8 HDI .......................................................... 9 .................................................................. 9 .........................................................12 PCMCIA ...........................................................12 .......................................................................13 ...................................................................14 2.9.1 2.9.2 3.1 3.2 3.3 3.4 3.5 3.6 .......................................................................16 ...............................................................16 .............................................................16
3 .......................................................................19 HDI .....................................................................19 HDI .................................................................21 CPU .......................................................22 Monitor Setup........................................22 ..........................................23 3.6.1 ..............................23 3.6.2 .............................................24 ..............................................26 .............................................................26 ...............................................................28 .........................................................30 ...............................................................30
.....................................................................31 .......................................................33 3.13.1 Step In ...................................................34 3.13.2 Step Out ..................................................35 3.13.3 Step Over .................................................36 .............................................................38 .......................................................38 ...............................................................40 ...............................................................43 ...................................................................44
4 4.1 4.2 HDI .................................................................45 .............................................................47 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 5.1 5.2 5.3 5.4 Monitor Setup ......................................47 Breakpoints ................................................48 Add / Edit Breakpoint .................................49 System Status..............................................50 Run Time Count Condition............................51 Cache Control ......................................53 Simulated I / O Window .......................................54 Command Line .............................................54
5 CPU .....................................................................55 .......................................................................56 ...................................................................57 .............................................................58 5.4.1 .................................................58 5.4.2 .........................................59 5.4.3 PCMCIA .................................................69 5.4.4 E10A .......................................78 .................................................................80 CPU .............................................................82 5.6.1 5.6.2 5.6.3 6.1 6.2 ...................................................82 CPU (BSC) ........................83 CPU (BSC)..........................83
7 7.1 7.2 ....................................................97 SCI ..................................................98
7.2.1 SCI ......................................................98 7.2.2 SCI ..................................................99 ............................................................100
SH7729R CPU CPU SH7729R SH7729R (1) SH7729R I / O 167MHz SH7729R167MHz IBM PC CPU RS-232C 1ch (HDI) 15.5Mbyte PCMCIA PCMCIA PCMCIA
IBM PC
CPU CPU (1) (2) (3) (4) (5) (6) (7) 1.6 CPU 2
CPU 1.1 1.1CPU
xxxxxxx xxxxxxx
CD-R HDI
SH7729R CPU
: HS7729RSTC01HJ-P(A) : HS7729RSTC01HE-P(A)
1.5 CD-R
CD-R SH7729R CPU CD-R 1.2 1.2CD-R
HDI SH7729R CPU SH7729R CPU Acrobat Reader Acrobat Reader
PDF HS7729RSTC01HJ PDF HS6400DIIW5SJ PDF HS7729RSTC01HE PDF HS6400DIIW5SE
PDF Acrobat Reader
Pentium 200MHz IBM PC Windows 95Windows 98 Windows NT 5MB 2 4
HDI Windows 95Windows 98 ® Windows NT : 100-240VAC, 50 / 60Hz, 0.6A max. : +5VDC 5A
2.2setup.EXE WindowsNT®4.0 (1) HDI
Hitachi Embedded Workshop HEW 2.1 2.1
HDI HDI.INI Backup HDI for SH7729R CPU board
SH7729R CPU HDI - HDI for SH7729R CPU board .
2.4E10A
CPU CN1
CN6 CN6
CN7 CPU 1 19
PCMCIA
PCMCIA 2.10
0 1 PCMCIA (I / O) PCMCIA0 1
2.10PCMCIA PCMCIA I / O 0 1 PCMCIA PCMCIA
CN1 CN1
CN6 CN6
CN8 CN8
ON ON OFF OFF 3 E10A CPU CPU 167MHz ON 27.75MHz 115200bit / s 57600bit / s ON OFF ON OFF ON OFF 55.5MHz 27.75MHz ON OFF 115200bit / s 57600bit / s ON OFF OFF -ON -ON TCLK (CN3-158pin) (1.8432MHz )
5 V (Vin) 3.3 V (Vout) 1.9 V (CPU)
5.0V 3.3 V 2.6 V 1.9 V 2.6 V
Vcc(5V) CN5
HDI C 10 / HDI CD sort.c sort.abs SYSROF HDI 3.1 3.1
StartHDI for SH7729R CPU boardHDI
3.1Start HDISelect Session OK
3.2Select Session CPU OK
3.3 Link Up HDI Link Up 20
CPU LED(LED1) CPU Monitor Setup CPU 5.5 2.45.4.1 3.54.2.1 2.8
Monitor Setup
· SetupConfigure Platform..Monitor Setup
3.5Monitor Setup ·
3.3Monitor Setup
1 2 Comms Port: Baud Rate: COM1: 115200 COM1, COM2, COM3, COM4 57600bit / s 115200bit / s J I / O SH7729R I / O Registers (View ) CPU ( ) ()CPU
I / O definition file
SH7729R
Download with verify Delete breakpoints when program is reloaded Reset CPU when program has been downloaded
· FileLoad Program..Load Program OffsetFile name 3.6 Open
3.6Load Program.
3.7HDI · OK
HDI · ViewSource..Open · C
3.8Open 24
· sort.cOpenProgram
3.9Program · SetupCustomiseFont Program
1 Programsort · sort BP
3.10Program sort " Break" ROM
· ViewRegistersRegisters
3.11Registers · Registers
3.12RegisterPC · Value"AC000000"OK · RegistersR15
3.13RegisterSP · Value"ACF80000"OK
3.15Program System Status · ViewStatus · System StatusPlatform Break Cause status
3.16System Status System Status 3.4System Status
Session Monitor Session Name Program Name Platform Connected to CPU Mode Cache Status MMU Status I / O definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count CPU CPU CPU ON / OFF MMU ON / OFF I / O (CPU ) CPU Target DLL RunBreak "0h 0min 0s 0ms 0.0us" CPU CPU
Comm port baudrate Memory Target Device Configuration System Memory Resources Loaded Memory Areas Events Resources
Breakpoints · ViewBreakpoints
3.17Breakpoints Breakpoints
Memory main · ViewMemory..Address"main" Format"Word"
3.18Open Memory Window · OKMemory
3.19Word Memory
long a · Program a · Program Instant Watch..
3.20Instant Watch · Add WatchWatch Window
3.21Watch Window Watch Window · Watch Window Add Watch..
3.22Add Watch · max OK Watch Windowlong max
3.23Watch Window Watch Window a
3.24Watch Window
3.25Program
Step In · sort RunStep In Step In
3.26Step In
3.27ProgramStep In 34
· Programsort
Step Out
Step Out · sort RunStep Out Step Out
3.28Step Out
3.29ProgramStep Out · Watch Window a · Step In2 · Watch Window max
3.30ProgramStep InStep In
Step Over
Step Over 1 · Step Inchange 2 · change Run Step OverStep Over
3.31Step Over
3.32ProgramStep Over
3.33ProgramStep Over 37
change Watch Window a
Locals main 5 a, j, i, min, max · ViewLocalsLocals Locals · RunStep In Locals
CPU HDI Breakpoints 255 · ViewBreakpointsBreakpoints · BreakpointsDelete All 38
3.35Breakpoints BreakpointsAdd Add / Edit Breakpoint · change Enable
3.36Add / Edit Breakpoint · OK Breakpoints
3.37Breakpoints · Breakpoints 39
3.38Program ViewStatusSystem Status Breakpoint
3.39System Status
sort · BreakpointsDelete All Program 21 22 BP
3.40Program · ViewStatusSystem Status
3.41System Status System StatusPlatform Run Time Count "0h 0min 0s 0ms 0.0us" · ViewRun Time..Run Time Count Condition 41
· EnableMeasurement Mode OK 0.15us(Max 10min)
3.42Run Time Count Condition Run Time Count Condition System Status 3.6Run Time Count Condition
Enable Measurement Mode
3.43Program System StatusPlatform Run Time Count sort
3.44System Status GoStep InStep OutStep Over
CPU HDI HDI CD-R
File Menu New Session.. Load Session.. Save Session Save Session As.. Load Program.. Initialize Exit Edit Menu Cut Copy Paste Find.. Evaluate.. View Menu Breakpoints Command Line Disassembly.. I / O Area Labels Locals Memory.. Performance Analysis Profile-List Profile-Tree Registers Source.. Status Trace Watch Cache Control.. Run Time.. Localized Dump 4.2.6 3.164.2.5 3.17 3.6.1 3.103.15 4.2.2 3.14 3.11 3.8 3.94.2.4
Monitor Setup
CPU SetupConfigure Platform..
4.1Monitor Setup I / O HDI I / O I / O 9 Monitor Setup
4.2Monitor Setup
1 2 Comms Port: Baud Rate: COM1, COM2, COM3, COM4 J 57600bit / s 115200bit / s I / O SH7729R I / O Registers (View ) CPU ( ) () CPU
I / O definition file:
Download with verify Delete breakpoints when program is reloaded Reset CPU when program has been downloaded
OKCancel
Breakpoints
ViewBreakpoints
4.2Breakpoints Breakpoints 4.3 48
4.3Breakpoints
Enable File / Line Symbol Address Type "" PC breakpoint
4.4 4.4Breakpoints
Add Edit Add / Edit Breakpoint Add / Edit Breakpoint Source
Disable Enable Delete Del All Go to Source
Add / Edit Breakpoint
ViewBreakpoints BreakpointsAddEdit
4.3Add / Edit Breakpoint
Add / Edit Breakpoint 4.5Add / Edit Breakpoint
Breakpoint address Enable
System Status
System StatusCPU View Status
4.4System Status
System Status 4.6System Status
Session Monitor Session Name Program Name Platform Connected to CPU Mode Cache Status MMU Status I / O definition Clock Target DLL Version Monitor Version Run Status Break Cause Run Time Count CPU CPU CPU ON / OFF MMU ON / OFF I / O (CPU ) CPU Target DLL RunBreak "0h 0min 0s 0ms 0.0us" CPU CPU
Comm port baudrate Memory Target Device Configuration System Memory Resources Loaded Memory Areas Events Resources
Run Time Count Condition
Run Time Count ConditionView Run Time..
4.5Run Time Count Condition Run Time Count Condition System Status 4.7Run Time Count Condition
Enable Measurement Mode
Cache Control
Cache Control View Cache Control..
4.6Cache Control Cache ControlCache Control OK 4.9Cache Control
Cache Flush Enable P1 Area write mode P0, U0, P3 Area write mode OK P1 P0, U0, P3
Simulated I / O Window
Simulated I / O Window · CPU ViewSimulated I / O Window Simulated I / O Window Windows( Windows® Simulated I / O Window CPU Clear WindowSimulated I / O Window Copy Paste
4.7Simulated I / O Window CPU 7.3 Simulated I / O Window 7
Command Line
SH7729R CPU Command Line
SDRAM 16Mbyte
GND 512kbyte
SH7729R (167MHz)
RS-232C I / F Hitachi-UDI 9pin D-sub
CPU SH7729R HD6417729RF167 LQFP208pin
CPU DELC-J9PAF-20L9
5.2 CPU CPU CPU · I / O 16bit · CPU · · SDRAM 16Mbyte 15.5Mbyte 0.5Mbyte 32bit · · · PCMCIA
00000000 0 16bit 04000000 CPU 1 (I / O) 08000000 2 0C000000 3 10000000 4 14000000 5 18000000 6 1C000000 CPU 1FFFFFFF PCMCIA I / F SDRAM 32bit
00000000 512kbyte 0007FFFC 00080000 00FFFFFE 01000000 01000000 01FFFFFE 02000000 03FFFFFE 01800000 01800012 01FFFFFE
PCMCIA 01800000 01800002 01800004 01800006 01800008 0180000A 0180000C 0180000E 01800010 PCC01SR PCC0GCR PCCOCSCR PCC0CSCIER PCC1ISR PCC1GCR PCC1CSCR PCC1CSCIER PCCVCR
0C000000 15.5Mbyte 32bit 0CF7FFFF 0CFFFFFF 0FFFFFFC (0.5Mbyte) SDRAM
18000000 0 18800000 1 19000000 0 19800000 1 1A000000 0 I / O 1A800000 1 I / O 1B000000 1BFFFFFF
CPU CPU CPU RS-232C 1ch CPU SCI0 CPU SCI0 9pin D-Sub 57600bit / s 115200bit / s 2.8 5.2 5.3 2.4 5.2
57600bit / s115200bit / s 1bit 1bit 8bit
SH7729R SCI LT1181ACSW CPU DELC-J9PAF-20L9
CD RXD TXD DTR SG DSR RTS CTS RING
N.C. RXD TXD DTR SG DSR RTS CTS N.C.
CPU CPU 5.5 5.6 5.7 5.45.6 CPU SH7729R CPU 3.3V 2.5
5.4CN3
Pin No. Pin No. Pin No. Pin No. (9)
165 GND 166 Reserve 167 GND 168 Reserve 1 2 (1) (2) (3)
169 GND 170 Reserve 171 GND 172 Reserve
173 GND 174 Reserve 175 GND 176 Reserve
177 CKIO 178 GND 179 GND 180 GND
5.4 Reserve CPU 5.4 10 D31:0 A25:0 5.11 5.11
RSTOUT CPU Low
BACK BREQ TCLK NMI WAIT CKIO
5.85.95.115.12 5.85.95.115.12 "" NMI CPU 0 6(PCMCIA ) WAIT OR CPU ", 10" 5.10
5.5CN6
100 GND
5.5 Reserve CPU 5.5 (1) , (2) IRQ4:0 IRQ E10A
5.6CN7
Pin No. 1 2 3 4 5 6 7 8 9 10 Reserve AVSS AN0 / PTL0 AVSS AN1 / PTL1 AVSS AN2 / PTL2 AVSS AN3 / PTL3 AVSS Pin No. 11 12 13 14 15 16 17 18 19 20 AVSS AN5 / PTL5 AVSS AN6 / DA1 / PTL6 AVSS AN7 / DA0 / PTL7 AVSS Reserve AVSS AN4 / PTL4
5.6 Reserve
CKIO BREQ BACK (CPU) BACK A, RD, CSn, RD / WR, CAS, RAS, WEn D
tBREQH tBREQS tBACKD
tCBACKD tCOFF1 tCOFF2
CKIO BREQ BACK (CPU) BACK
tCON1 tBREQS tBREQH tBACKD
A, RD, CSn, RD / WR, CAS, RAS, WEn D
tCON2
5.9(2) 5.7AC
5.1CKIO
U1 SH7729R A25.0 WE3.0 U4-7 QS3384 U8-11 VHC244
3.3V 4.7k9 U12-15
A25.0 VHC244 WE3.0
D31.0
D31.0 3.3V 4.7k9 IRQOUT, STATUS1, 0 CKE BREQ, NMI, WAIT
IRQOUT, STATUS1, 0 CKE
U18 VHC244
U2 FPGA BREQ, NMI, WAIT BACK IRQL4.0, RESETP U19 VHC244
3.3V 4.7k9 BACK, RSTout RESETP U27 LS279
SW1, 2 5V CKIO 10k9 J9
Clock Driver 3.3V 4.7k9 J3
OSC1 55.5MHz
CKIN OSC2 14.7456MHz
TCLK 3.3V RD, CS0, CS2, CS3, CS4, CS5 / CE1A, CS6 / CE1B RD / WR RAS2L, BS, CASLL, CASLH, CASHL, CASHH, RAS3L 10k9 3.3V 10k9 U16 VHC244
TCLK RD, CS0, CS2, CS3, CS4, CS5 / CE1A, CS6 / CE1B, RD / WR RAS2L, BS, CASLL, CASLH, CASHL, CASHH, RAS3L
U17 VHC244
5.11CN3
U1 SH7729R IRL3.0, IRQ3.0 IRQ4 IRQ4 3.3V 4.7k9 RESE CTS2 RTS2 3.3V 4.7k9 RXD1 / 2 TXD1 / 2 SCK1 / 2 3.3V CE2A / 2B DACK0 / 1, DRAK0 / 1 WAKEUP, BACK CAS2L / 2H, RAS2U / 3U 4.7k9 3.3V 4.7k9 3.3V 4.7k9 3.3V 4.7k9 U2 FPGA U19 VHC244 3.3V 4.7k9 3.3V 4.7k9
IRQ3.0
EMRST CTS2 RTS2
3.3V DREQ0 / 1, IOIS16, CA, ADTRG 3.3V PTC7.0, PTD2, PTE7 / 0, PTF7.0, PTG6.0, PTH6 4.7k9 4.7k9
CE2A / 2B DACK0 / 1, DRAK0 / 1, WAKEUP, BACK, CAS2L / 2H, RAS2U / 3U
DREQ0 / 1, IOIS16, CA, ADTRG
PTC7.0, PTD2, PTE7 / 0, PTF7.0, PTG6.0, PTH6
CN7 AN7.0 / PTL7.0 470pF AN7.0 / PTL7.0
5.12CN6, CN7
5.13CN3
PCMCIA
PCMCIA 12 2 2 I / O 3.3V 5V CPU PCMCIA PCMCIA 5.14 PCMCIA 5.8 PCMCIA 5.9
Pin1 O Pin35 1
Pin34
Pin68 PCB PCMCIA
5.14PCMCIA
5.8PCMCIA 0CN9
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 GND PCC0DA3 PCC0DA4 PCC0DA5 PCC0DA6 PCC0DA7 P0CE1 PCC0AD10 P0RD PCC0AD11 PCC0AD9 PCC0AD8 PCC0AD13 PCC0AD14 P0WE1 P0RDY VCCA Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VPPA PCC0AD16 PCC0AD15 PCC0AD12 PCC0AD7 PCC0AD6 PCC0AD5 PCC0AD4 PCC0AD3 PCC0AD2 PCC0AD1 PCC0AD0 PCC0DA0 PCC0DA1 PCC0DA2 P0WP GND Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 GND P0CD1 PCC0DA11 PCC0DA12 PCC0DA13 PCC0DA14 PCC0DA15 P0CE2 P0VS1 P0WE2 P0WE3 PCC0AD17 PCC0AD18 PCC0AD19 PCC0AD20 PCC0AD21 VCCA Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VPPA PCC0AD22 PCC0AD23 PCC0AD24 PCC0AD25 P0VS2 P0RESET P0WAIT NC P0REG P0BVD2 P0BVD1 PCC0DA8 PCC0DA9 PCC0DA10 P0CD2 GND
5.9PCMCIA 1CN9
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 GND PCC1DA3 PCC1DA4 PCC1DA5 PCC1DA6 PCC1DA7 P1CE1 PCC1AD10 P1RD PCC1AD11 PCC1AD9 PCC1AD8 PCC1AD13 PCC1AD14 P1WE1 P1RDY VCCB Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VPPB PCC1AD16 PCC1AD15 PCC1AD12 PCC1AD PCC1AD6 PCC1AD5 PCC1AD4 PCC1AD3 PCC1AD2 PCC1AD1 PCC1AD0 PCC1DA0 PCC1DA1 PCC1DA2 P1WP GND Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 GND P1CD1 PCC1DA11 PCC1DA12 PCC1DA13 PCC1DA14 PCC1DA15 P1CE2 P1VS1 P1WE2 P1WE3 PCC1AD17 PCC1AD18 PCC1AD19 PCC1AD20 PCC1AD21 VCCB Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VPPB PCC1AD22 PCC1AD23 PCC1AD24 PCC1AD25 P1VS2 P1RESET P1WAIT NC P1REG P1BVD2 P1BVD1 PCC1DA8 PCC1DA9 PCC1DA10 P1CD2 GND
CPU PCMCIA · IRQ PCMCIA IRQ1 CPU · PCMCIA PCMCIA 2 2 I / O · 3.3V 5V 70
· PCMCIA 2 8Mbyte PCMCIA 64Mbyte CPU A25A23 1 0 / 1GCRGeneral Control Register20 A25A23 2 5.15
18000000 18800000 19000000 19800000 1A000000 1A800000 1B000000 1BFFFFFF
PCMCIA 5.10 5.10PCMCIA
PCC0(PCC0ISR)
7 P0RDY R R 6 P0WP R 5 P0VS2 R 4 P0VS1 R 3 P0CD2 R 2 P0CD1 R 1 P0BVD2 R 0 P0BVD1
PCC0(PCC0GCR)
0 8Mbyte 64Mbyte 0 3 Bit 7P0DRVE 0PCC0DRV High 1PCC0DRV Low Bit 6P0RES 0PCC0RES Low 1PCC0RES High Bit 5P0PCCTPCMCIA 0 0 1 0 I / O Bit 4-3 0 Bit 2-0P0PA25-23 0 Low 1 High 3
PCC0(PCC0CSCR)
0 IRQ1 Bit 7P0SCDI PCC0CSCIER 3P0CDE 0 1 0 Bit 6 0 Bit 5P0IREQIREQ 0 I / O PCC0RDY / IREQ 1 0 PCC0CSCIER 65(IREQE1-0) 0 0IREQ 1 0 I / O IREQ 72
PCC0 (PCC0CSCIER)
0 PCC0CSCR 1 Bit 7P0CREPCC0GCR 0 CD1High Low CD2High Low PCC0GCR 73
0 GCR 1 GCR Bit 6-5P0IREQE1-0IREQ 0 I / O IREQ PCC0CSCR 5P0IREQ
6 IREQ1 0 0 1 1 5 IREQ0 0 1 0 1 IREQ P0IREQ P0IREQ IREQ Low P0IREQ IREQ P0IREQ IREQ
Bit 4P0SCESTSCHG 0 I / O PCC0BVD1 / STSCHG PCC0CSCR 4 1 0STSCHG 1STSCHG Bit 3P0CDE PCC0CD2PCC0CD1 PCC0CSCR 3 1 0PCC0CD2 / PCC0CD1 1PCC0CD2 / PCC0CD1 Bit 2P0REReady 0 PCC0RDY PCC0CSCR 2 1 I / O 0RDY / BSY 1RDY / BSY Bit 1P0BWE 0 PCC0CSCR 1 1 I / O 0 1 Bit 0P0BDE 0 PCC0CSCR 0 1 I / O 0 1
PCC1(PCC1ISR)
7 P1RDY R R 6 P1WP R 5 P1VS2 R 4 P1VS1 R 3 P1CD2 R 2 P1CD1 R 1 P1BVD2 R 0 P1BVD1
PCC1(PCC1GCR)
1 8Mbyte 64Mbyte 1 3 Bit 7P1DRVE 0PCC1DRV High 1PCC1DRV Low Bit 6P1RES 0PCC1RES Low 1PCC1RES High Bit 5P1PCCT I / O 0 1 1 1 I / O Bit 4-3 0 Bit 2-0P1PA25-23 0 Low 1 High 7
PCC1(PCC1CSCR)
1 IRQ1 Bit 7P1SCDI PCC1CSCIER 3P1CDE 0 1 1 Bit 6 75
PCC1 CSC(PCC1CSCIER)
1 PCC1CSCR 1 Bit 7P1CREPCC1GCR 1 CD1High Low CD2High Low PCC1GCR 0 GCR 1 GCR Bit 6-5P1IREQE1-0IREQ 1 I / O IREQ PCC1CSCR 5P1IREQ
6 IREQ1 0 0 1 1 5 IREQ0 0 1 0 1 IREQ P1IREQ P1IREQ IREQ Low P1IREQ IREQ P1IREQ IREQ
Bit 4P1SCESTSCHG 1 I / O PCC1BVD1 / STSCHG PCC1CSCR 4 1 0STSCHG 1STSCHG Bit 3P1CDE PCC1CD2PCC1CD1 PCC1CSCR 3 1 0PCC1CD2 / PCC1CD1 1PCC1CD2 / PCC1CD1 Bit 2P1REReady 1 PCC1RDY PCC1CSCR 2 1 I / O 0RDY / BSY 1RDY / BSY
Bit 1P1BWE 1 PCC1CSCR 1 1 I / O 0 1 Bit 0P1BDE 1 PCC1CSCR 0 1 I / O 0 1 9
PCC(PCCVCR)
7 R / W 0 6 R / W 0 5 R / W 1 4 R / W 1 3 R / W 0 2 R / W 0 1 R / W 1 0 R / W 1 VCC0SEL1 VCC0SEL0 VPP0SEL1 VPP0SEL0 VCC1SEL1 VCC1SEL0 VPP1SEL1 VPP1SEL0
VCCXSEL1 0 0 1 1 VCCXSEL0 0 1 0 1 VCC OFF 5V 3.3V OFF VPPXSEL1 0 0 1 1 VPPXSEL0 0 1 0 1 VPP 0V VPP VCC Hi-Z
CPU SH7729R E10A Hitachi-UDI CN8 SH7729R H-UDI AUD E10A CPU J11 ON 5.16 Hitachi-UDI CN8 5.11 Hitachi-UDI CN8
Pin 35
Pin 36 Pin 2
Hitachi-UDI
5.16Hitachi-UDI CN8 5.11Hitachi-UDI CN8
CPU 5.17 CPU 5.12 5.12CPU
OSC3 OSC4 CN4 J4J6, J12, J13 J8 TP112 CKIN TEST R4 R79, 11 R12, R149, R151 C23 C24 C28 TCO-711S4 CXO-105D FFC-10 310-93-103 410-93-202 ST-1-3 ST-1-3 ST-1-3 MCR10EZHJ472 MCR10EZHJ103 MCR10EZHJ000 281E6801-337M 281E1002-157M 281M1002-107M 1 1 1 5 1 12 1 1 1 4 3 1 1 1
8817-180-170L
J12 J13 J11 J10
3.3V-GND
HD151015 U41 HD151015 U40
TSSOP-24 TSSOP-24
3.3µF
5V-GND
3.3µF 3.3µF
HD151015 U39
HD151015 U38
VHC244
3.3V-GND
TSSOP-24
HD151015 U37
HD151015 U36
TSSOP-24
HD151015 U35 U34
TSSOP-24
HD151015
VHC244
TSSOP20 TSSOP20
TSSOP-24
8931E-100178S
HD151015 U33
TSSOP-24
HD151015 U32
TSSOP-24
HD151015 U46
TSSOP-24
HD151015 U45 HD151015 U42
TSSOP-24 TSSOP-24
VHC244 U15 U14
TSSOP20
VHC244 U13
VHC244
TSSOP20
LT1301 U47 C47
HD151015 U43
TSSOP-24
TSSOP20
VHC244 U11
TSSOP20
VHC244 U9
VHC244 U8
VHC244
TSSOP20
U48 HRF22 LTC1472CS C42
TSSOP20
LTC1472CS C46
QS3384
PSS-24A
CDRH62B-330M LVTH16543 SSOL056
MB3771
FP-8D
QS3384
PSS-24A
HM5264165 TTP-54D HM5264165 TTP-54D
5V-GND
3.3µF
1.8V-GND
DT-26SH
3.3µF
PA28F400B5-B60 SOP-44
C13 51
EMP7128S TQFP-100
3.3V-GND
3.3µF
XTAL1
LS279 FP-16DA
TP3 C28
3.3µF
49FCT3805
C15 PL-SKT / Q160 40 41
3.3V-GND
SSOP20
C10 R55 C25 1
C11 C20 1
C21 C22 1 C23 C24 CN7
TP5 TP6 TP7
TP9 TP10 TP11 TP12
SW3 D1 U30
HEC0470-01-630 M2T-12AKH1-G5E
U31 LT1084 7620-6002SC FFC-10
LT1084
5.17CPU
D-sub9
10236-5202JL
55.5Mz
1 160 EPM7192 PQFP-160
SH7729R
LQFP-208
3.3µF 3.3V-GND
ABORT
MRESET SW1
C14 SW2
104 105 156 C1 C2 157
SG-8002JA OSC1 / 3 / 4
OSC EXO-3C 14.7456M
LT1181ACS SOL-28
CPU 5.13
SH7729R CPU MMU CACHE TLB CCN INTC UBC CPG WDT BSC DMAC TMU RTC SCI IRDA SCIF I / O PORT ADC DAC CMT DSP AUD H-UDI ASERAM XYCNT XYMEM PCMCIA SDRAM () SDRAM
() - HDI CPU Power on reset is detected.CPU HDI
CPU (BSC)
5.18 (BSC) BSC 5.6.3 CPU (BSC)
1.5µs
START
RTCNT
WTCNT
WTCSR
RTCNT
RTCSR
FRQCR
5.18BSC
CPU (BSC)
CPU CPU BSC CPU BSC CKIO
DRAM DRAM DRAM A5 TP1 1 TP0 0 PCM 0
BST1 BST0 BST1 BST0 BST1 BST0 TP2 0 0 0 0 0 0 0
WAIT SEL 1
WT / IT RSTS WOVF IOVF 1 0 0 0
CSK2 CSK1 CSK0 1 1 1
TPC1 TPC0 RCD1 RCD0 TRWL TRWL TRAS TRAS 1 0 1 0 0
AMX1 AMX0 RFSH R
MODE MODE
STC2 IFC2
PSTB STC1 STC0 IFC1 Y 0 0 0 0
PFC1 PFC0
CMIE CKS2 CKS1 CKS0 OVF 0 0 0 1 0
A6W2 A6W1 A6W0 A5W2 A5W1 A5W0 A4W2 A4W1 A4W0 A3W1 A3W0 A2W1 A2W0 A0W2 A0W1 A0W0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1
STC2 IFC2
PSTB STC1 STC0 IFC1 Y 0 0 1 0
PFC1 PFC0
CMIE CKS2 CKS1 CKS0 OVF 0 0 0 1 0
A6W2 A6W1 A6W0 A5W2 A5W1 A5W0 A4W2 A4W1 A4W0 A3W1 A3W0 A2W1 A2W0 A0W2 A0W1 A0W0 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0
CPU User Break Controller (UBC) Serial Communication Interface (SCI) TRAPA#255 Trap instruction NMISCI 1415 14 Address error Illegal general instruction Illegal slot instruction NMI CPUHDI EXPEVT CPU
6.2 RAM 6.36.4 HDI Run Time Count Condition
6.4 7. CPUHDI CPUONBSC CPU ( )CPUBSC I / OHDI I / O ViewI / O Registers
BSC 5.6.3 CPUBSC I / O 5.45.45.55.6 CPU 16bit J12.8 , , Monitor FLASH Memory, Monitor I / O SDRAMPCMCIA DRAMCPUSDRAM3 NMI 7 IRQ5CTS2 / SCPT7 IRQ5 SDRAM TMU TMU0TMU0 TMU0 SCI CPUSCI0(SCI) Simulated I / O WindowSCI0 7.2SCI SCI1(IrDA)SCI2(SCIF)SCI I / FCPUHDI PCMCIA CPUPCMCIAPCMCIA PCMCIA PCMCIAPCMCIACD0, CD1 PCMCIAP0DRVEP1DRVE E10A E10AE10A 91
Unable to fech register () HDI Initialize OK Save memory
Save memory
Command not ready ()
RAM SLoad ProgramLoad Memory 2Load Program HDI HDICommand Line HDISelect Function( 10) 2n+1 4n+14n+2 4n+3 41 32768 (Watchdog Timer) 6.2
WTCSR(W) WTCNT(W) WTCSR(R) WTCNT(R)
HDIHDI HDI Fill MemoryTest Memory CPUHDI 5"Command not ready" Fill Memory
Watch WindowI / O Registers
SH7729R SCI0Serial Communication Interface CPU PC CPU Simulated I / O Window SCI0 SCI0 PC Simulated I / O WindowCPU 7.1 CPU HDI CD-R SCI0 7.3
· HALT 7.1 SCI0 CPU Simulated I / O Window SCI0 SCI1(IrDA) SCI2(SCIF) HALT HALT HDI HALT
CKS1 CKS0 0 0
CKE1 CKE0 1 1
PINT0PINT7 0 0 0 0
PINT8PINT15 0 0 0
IRQLV BLMS IRLSE IRQ51 IRQ50 IRQ41 IRQ40 IRQ31 IRQ30 IRQ21 IRQ20 IRQ11 IRQ10 IRQ01 IRQ00 L K N S S S S S S S S S S S S 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ICR2, PINTER, IRR0, IRR1, IRR2
SCI0 Hitachi Embedded WorkshopHEW C SH SCI0 Simulated I / O Window 1 HDI Sample
7.1 HEW HEW 1.1(Release 4) HEW Hitachi Embedded Workshop
62 () 1 () 51 () 1 () 96 () 351 () 41 () 24 () 121 () 642 (JA) 236 () 56 () 13-23 () 51 () 41 (9) 8322 (1) 1611 (11) 62 () 211 (7) 632 () 161 (TYG11) 410 (6) 67 (4) 513 () 151 () 312 (8) 1712 () 1112 () 39 () 672 () 1617 () 527 () 345 () 20(FT4) 314 () 15 () 22 () 1110 () 251 () 4986 () 13 () 723 () 18 () 41 () 81 () 531 () 46 () 15 () 110 () 11 () 1223 (6) 945 (3) 634 (3) 211 (2) 435 (2) 728 (3) 122 (2) 114 (6)
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Colophon 1.0