Edition Dec. 2001 6251-561-2PD 9488X 9588X Preliminary Data

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Edition Dec. 2001 6251-561-2PD 9488X 9588X Preliminary Data

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9488X Basic 9588X OCTOPUS Version Cost-effective Picture-In-Picture
Edition Dec. 2001 6251-561-2PD
9488X 9588X
Preliminary Data Sheet
Cost effective Picture-In-Picture (PIP)
Version General Description 9488X 'PIP Basic' 9588X 'OCTOPUS' belong generation costeffective processors that combine high-quality digital signal processing, digital multistandard color decoding AD/DA conversion single chip. Both devices equipped with CVBS input interfaces. addition 9588X also able process input signals displaying high-quality video signals e.g. coming from source.
CMOS
SOIC28-1
Figure
Picture-In-Picture
integrated digital color decoder able decode analog standards (PAL, NTSC SECAM) detects standard automatically. Therefore suited world-wide use. picture reduction from 1/81 original size selectable fine steps possible. transfer functions decimation filters optimally matched selected picture size reduction furthermore adjusted viewer's requirements selectable peaking. maximum luminance 2x81 chrominance pixels line stored memory. Type 9488X 9588X Micronas Package SOIC28-1 SOIC28-1
9488X (B31) 9588X (B31)
Preliminary Data Sheet
4.1.1 4.1.2 4.1.3 4.1.4 4.6.1 4.6.2 4.6.3 4.7.1 4.7.2 4.7.3 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.9.1 4.9.2 4.10 4.10.1 4.10.2 4.10.3 4.10.4 Micronas
Features Configuration Block Diagram System Description Analog Frontend Input Selection AD-Conversion Automatic Gain Control Signal Magnitudes Inset Synchronization Chroma Decoding Standard Search Comb Filtering Luminance Processing Decimation Single Mode Horizontal Vertical Fine Positioning Multi Display Mode Display Control Mixed Standard Applications (S)VGA Support Display standard Picture Positioning Output Signal Processing Luminance Peaking Matrix Framing Colored Background 16:9 Inset Picture Support Parent Clock Generation Select Signal DA-Conversion Switch Contrast, Brightness Peak Level Adjustment Pedestal Level Adjustment Data Slicer Closed Caption Widescreen Signalling (WSS) Indication Data Violence Protection Application Examples Address I2C-Bus Format
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Command Table Command Description Description Absolute Maximum Ratings Recommended Operating Range Characteristics Diagrams Application Circuit
Micronas
9488X (B31) 9588X (B31)
Preliminary Data Sheet Features
Features
Single chip solution: AD-conversion CVBS YUV1), multistandard color decoding, synchronization inset channel, decimation filtering, embedded memory, RGBmatrix, DA-conversion, RGB/YUV switch, data-slicer clock generation integrated chip Analog inputs: CVBS CVBS 1xYUV (SDA 9588X) alternatively Clamping each input ADCs with amplitude resolution Automatic Gain Control (AGC) CVBS Inset Synchronization: Multiple time constants reliable synchronization Automatic recognition lines lines standard Color Decoder: PAL-B/G, PAL-M, PAL-N(Argentina), PAL60, NTSC-M, NTSC4.4 SECAM Adjustable color saturation control NTSC Automatic Chroma Control (-24 Automatic recognition chroma standards: different search strategies selectable Single crystal standards IF-characteristic compensation filter Decimation: sizes between 1/81 adjustable with steps lines pixel Resolution luminance 2x81 chrominance pixels inset line Horizontal vertical filtering dependent picture size Display Features: pixel stored memory Field joint-line free frame mode display Display SVGA screen limited 40kHz) different read frequencies 16:9 compatibility Line doubling mode progressive scan applications Freeze picture Coarse positioning corners parent picture Fine positioning steps pixels lines Output signal processing: switch: insertion external source without processing Digital interpolation anti-imaging
available with 9588X only
Micronas
9488X (B31) 9588X (B31)
Preliminary Data Sheet Features
Adjustable transient improvement luma (peaking) Contrast, Brightness Pedestal Level adjustable Analog outputs: +(B-Y), +(R-Y), -(B-Y), -(R-Y) Three matrices available: NTSC(Japan), NTSC(USA) different background colors 4096 different frame colors Plain frame with variable width height Data Slicing: Slicing closed-caption (CC) wide-screen-signaling (WSS) data Violence blocking capability (V-chip) Several filter data extraction I2C-Bus control (400 kHz) High stability clock generation SOIC28-1 package (SMD) Full 9489X 9589X upward compatibility 9388X 9389X pinout compatibility 3.3V supply voltage input capable)
Micronas
9488X (B31) 9588X (B31)
Preliminary Data Sheet Configuration
Configuration
CVBS1 VREFM CVBS2 VREFL CVBS3 VSSA1 VDDA1 VREFH VSSA2 VDDA2 OUT1 OUT2 OUT3
SOIC28
Figure
Pinning
Figure
Package Outlines
Micronas
9488X (B31) 9588X (B31)
Preliminary Data Sheet Configuration
Numb
Name OUT3 OUT2 OUT1 VDDA2 VSSA2 VREFH VDDA1 VSSA1 CVBS3 VREFL CVBS2 VREFM CVBS1
Type I/TTL I/TTL O/TTL I/ana I/ana I/ana O/ana O/ana O/ana I/ana I/ana I/ana I/ana
Description crystal oscillator (input) external clock input crystal oscillator (output) horizontal sync parent channel vertical sync parent channel I2C-bus data I2C-bus clock digital supply voltage digital ground Address interrupt input external YUV/RGB source input external YUV/RGB source input external YUV/RGB source fast switch input YUV/RGB switch fast blanking output analog output: chrominance signal +(B-Y) -(B-Y) analog output: luminance signal analog output: chrominance signal +(R-Y) -(R-Y) analog supply voltage analog ground uppper reference voltage analog supply voltage analog ground CVBS3 (SDA 9588X) Input lower reference voltage CVBS2 (SDA 9588X) Y/C) Input mid-level reference voltage CVBS1 YUV, 9588X) Input
Input ana=analog Output TTL=Digital (TTL) S=Supply voltage
Table Micronas
Description
9588X (B31)
9488X (B31)
Micronas
Figure
VDDA2VSSA2
DEMUX
VDDA1 VSSA1
VREFH
VREFM 3x7bit
Block Diagram
Block Diagram
Skewcomp. Scaler Decimation Matrix Triple Peaking Oversampling Insertion
VREFL
TRIPLE 3x8bit
eDRAM
Color Decoder
PAL/ SECAM/ NTSC
DUV/DCHR
DCVBS/DY
Frame Generation 512kbit
CVBS1
CVBS2 Memory Controller Display Controller
CVBS3 Inset Sync Processing
Input Select Clamp Gain
Fast RGB/YUV OUT1 Switch OUT2
Data Slicer Acquisition
Sync Sep.
OUT3
Controller
Clock Synthesizer
Parent Sync Processing
INTR
SDA9588X, 9488X: 2x8bit
Preliminary Data Sheet
Block Diagram
XTAL 20.25
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
4.1.1
System Description Analog Frontend Input Selection
analog inset CVBS signal inputs CVBS1-3 9588X resp. 9488X. Each these sources selectable (CVBSEL). CVBS2 CVBS3 used separate inputs. sources connected CVBS1, CVBS2 CVBS3 provided operation 9588X being enabled (YUVSEL). Using external switch 9588X operate applications with both CVBS signals.
CVBSEL
YUVSEL
Input
remark
CVBS1 (VBS) CVBS
CVBS2 CVBS (VBS) (CB)
CVBS3
CVBS (CR)
mode mode (SDA 9588X only)
Table 4.1.2
Input selection
AD-Conversion
signal clamped AD-converted with amplitude resolution 8bit. CVBS signals clamped sync bottom backporch, selectable CLMSTGY. signals always clamped their mid-level during blanking.
Inset Video
CLMPIST
CLAMPI
CLMPID
Figure Micronas
Clamping timing 4-10
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
clamping pulse shifted position (CLMPIST) length (CLMPID) adjust specific application. ADCs driven 20.25 free running crystal clock which related incoming CVBS signal. avoid aliasing subsampling CVBS signal signals should bandlimited 10MHz. same manner signal frequency spectrum (SDA 9588X) should exceed MHz. digital filtering suppresses frequencies above useable spectrum. 4.1.3 Automatic Gain Control
accommodate different CVBS input voltages automatic gain control been implemented. chip works correctly input voltages range from 1.5Vpp. best signal-to-noise ratio, maximum CVBS amplitude recommended available. behavior chosen four possibilities (AGCMDE): sync height serves reference gain control typical application. When using overflow detection only, gain maximum reduced whenever overflow occurs. This procedure will executed again when channel change detected gain control manually reset AGCRES.
Automatic Gain Control Characteristic
Input Voltage
AGCVAL
Figure 4.1.4
characteristic Signal Magnitudes
nominal CVBS signal with color magnitude Vpp. upper headroom left permit signals with 100% color resulting 1.23 Vpp. signal must always contain sync part. levels correspond CVBS levels except missing color burst. After conversion video part clamped black value amplified digital steps. nominal signal levels ensure correct brightness saturation. signal levels conform recommendation. Micronas 4-11
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
upper headroom
CRYC white
upper headroom
0.89
SRUV
burst
black
lower headroom
lower headroom
Figure
CVBS/Y chroma input signal range
upper headroom
CRUV SRUV
upper headroom
lower headroom
lower headroom
Figure
input signal range
Conversion Range CRYC Signal Range Signal Range Conversion Range CRUV Signal Range SRUV
AGCVAL
0.5Vpp 1.2Vpp 1.5Vpp
0.42Vpp 1.0Vpp 1.25Vpp 0.89Vpp 0.8Vpp 0.7Vpp
Table Micronas
conversion range required input signal voltage 4-12
CRUV
CRYC
100% chroma
chroma
burst
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
Inset Synchronization
Horizontal vertical sync pulses separated after elimination high frequency components CVBS signal pass filter. Horizontal sync pulses generated digital phase-locked-loop (DPLL). time constant adjustable between fast slow behavior four steps (PLLITC) consider different input sources (e.g. VCR). Noisy input signals become more stable when noise-reduction enabled (NSRED). Additionally weak input signals from satellite dish ('fishes') become more stable when SATNR enabled. Both should enabled have best available performance. vertical flywheel mode improves vertical sync separation weak signals (VFLYWHL, VFLYWHLMD). Additionally, v-syncs gated VTHRL50/ VTHRH50/60 reject invalid v-syncs. Dependent detected linestandard, VTHRx50 VTHRx60 setting used. operation sync separation forced separately selected work automatically (FLNSTRD).When NOSIGB enabled, colored background shown instead picture when (horizontal) synchronization. detected line standard indicated SYNCSTAT.
Chroma Decoding Standard Search
system able decode NTSC signals with subcarrier 3.58MHz 4.43MHz (PAL B/M/N/60, NTSC M/4.4) well SECAM signals with 4.05/4.2MHz subcarrier. system forced certain standard, automatic standard detection used (CSTAND). automatic standard detection, some standards which likely received ignored improve detection process. Depending detected line standard (525 lines) color standard detection circuit searches signals (NTSC-M PAL-M NTSC44) signals (PAL-B SECAM PAL-N) respectively. Within each line standard, standard detected consequently switching from another. This standard detection process slow fast behavior (LOCKSP). slow behavior, fields used detect standard, whereas fields used fast behavior. unsuccessful within this time period system tries detect another standard.For SECAM detection, choice between different recognition levels possible (SCMIDL, SECACCL, SECDIV) evaluated burst position selectable (BGPOS).
Micronas
4-13
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
CSTANDEX NTSCM PAL60 PAL-N PAL-M PAL-B SECAM NTSC
Table
Considered color standards automatic standard detection
getting chrominance information digitized video signal multiplied with regenerated color subcarrier once in-phase once phase-shifted 90°. After lowpass filtering digital available NTSC. subcarrier regenerated digital PLL. SECAM operation runs free generates line-wise alternating subcarriers. CORDIC structure demodulates frequency-modulated signals. following SECAM de-emphasis filter characteristic adjustable (DEEMP). chroma signal filtered before demodulation means selectable IFprefilter (IFCOMP).
gain [dB]
3.58
IFCOMP '00' IFCOMP '01'
DEEMP '00' DEEMP '01'
gain [dB]
DEEMP '10' DEEMP '11'
IFCOMP '10'
frequency [MHz]
frequency [MHz]
Figure
SECAM de-emphasis filter characteristic IF-compensation filter characteristic
Control (HUE) influences phase demodulation subcarrier between -44.8° 43.4° steps 1.4°. This provided NTSC only adjustment ineffective SECAM signals. reference subcarrier generation crystal stable clock 20.25000 MHz. order avoid color standard detection problems, maximum deviation this Micronas 4-14
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
frequency should exceed 100ppm. good locking behavior maximum deviation 40ppm recommended. small frequency adjustment (-150 +310 ppm) possible using crystal with small frequency deviations (SCADJ). test purposes, CPLL allows open loop chroma PLL. deviations chroma signal 30dB, stable output amplitude after chroma decoding achieved (Automatic Chroma Control). chroma signal (color burst) below selectable threshold (CKILL), color will switched off. Alternatively color-killer bypassed color switched under conditions (COLON). setting ACCFIX, automatic chroma control disabled default value. CKILL Table color always color always COLON color killed damping
Color-killer adjustment
bandwidth chroma filter adjustable CHRBW. bandwidth depends whether decoder SECAM operation not. change CHRBW does result chrominance position shift screen. CKSTAT read gives information whether color switched off. STDET indicates detected color standard. Additionally PALID PALDET signal whether signal applied. Comb Filtering
Depending selected picture size color standard, comb filtering performed luminance chrominance. comb filter uses spectral interleaving encoded luminance chrominance separate both without cross artifacts. Thus cross-color cross-luminance suppressed effectively. NTSC sources, comb filtering performed picture sizes. reduced bandwidth horizontal vertical direction strong reduction cross artifacts achieved signals. same applies luminance signal SECAM signals.
Micronas
4-15
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
Luminance Processing
A/D-converted CVBS signal digitally clamped back porch. Depending transmitted standard operational area, offset between black- blanking level found incoming signal ('7.5 IRE'). some applications black offset desired, controlling done using LMOFST. positive negative offset added signal before scaling.
Received signal
BLACK value BLANK value
Processed signal
BLACK value BLANK value
standard signals
LMOFST='00' additional offset)
LMOFST='10' (reduction LSB)
BLACK value BLANK value
BLACK value BLANK value
B/G/H/I/N standard signals
LMOFST='00' additional offset)
LMOFST='01' (addition LSB)
Figure
Black level correction luminance signal
color carrier removed CVBS signal means notch filter. corresponding color carrier (3.58 MHz) only standard detected permanently. This prevents luminance sharpness being changed within standard search process. signals notch disabled.A special peaking applied notch-filter (NADJ) make steeper. fine adjustment delaycompensation between luminance chrominance, YCDEL allows luminance shifting steps 50ns. 4.6.1 Decimation Single Mode
Luminance chrominance signals filtered horizontal vertical direction. coarse horizontal vertical picture size (1/3, 1/4, 1/6) independently programmable with SIZEHOR SIZEVER. fine adjustment steps pixel lines possible HSHRINK VSHRINK, which allows correct aspect ratio multistandard applications (50/60 mixed mode, (S)VGA). main decimation factors, stored number pixel lines listed following tables. Micronas 4-16
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
SIZEHOR Table
horizontal scaling
Pixel line (B-Y) (R-Y)
Number stored pixel line dependent SIZEHOR
SIZEVER
vertical scaling
lines lines source lines source
only used compatibility with other 948xX/958xX types Number stored lines field
Table
Micronas
4-17
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
2,00 2,02 2,05 2,08 2,10 2,13 2,16 2,19 2,22 2,25 2,28 2,31 2,35 2,38 2,41 2,45 2,49 2,53 2,57 2,61 2,66 2,70 2,74 2,80 2,84 2,89 2,95
3,00 3,04 3,11 3,17 3,23 3,29 3,37 3,44 3,51 3,60 3,67 3,76 3,84 3,94 4,05 4,16 4,27 4,38 4,50 4,63 4,77 4,91 5,06 5,22 5,41 5,59 5,78
6,00 6,23 6,48 6,75 7,04 7,35 7,70 8,10 8,52 8,99 9,51 10,12 10,64
Table
Number stored pixel line dependent HSHRNK
Micronas
4-18
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
lines
lines
lines
lines
3,00 3,07 3,14 3,21 3,30 3,38 3,47 3,56 3,66 3,77 3,89 4,00 4,13 4,25 4,41 4,56 4,72 4,88 5,06 5,28 5,50 5,75
3,09 3,19 3,28 3,38 3,49 3,61 3,73 3,87
6,00 6,28 6,61 6,94 7,31 7,78 8,25 8,81 9,42 10,17 11,02
6,00 6,38 6,75 7,22 7,73 8,30 9,00 9,80 10,78
4,01 4,15 4,31 4,69 5,13 5,39
Table 4.6.2
Number stored lines field dependent VSHRNK Horizontal Vertical Fine Positioning
picture sizes pre-centered inside frame. addition, necessary vertical horizontal acquisition area shifted vertical horizontal direction. 4.6.3 Multi Display Mode
9488X 9588X offer feature display sub-picture more than once. picture size arrangement depends display mode (DISPMOD) SIZEHOR SIZEVER. Hence variable scaling possible these modes.
Micronas
4-19
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
Display Mode
DISPMOD
Size SIZEHOR/ SIZEVER HSRHNK/ VSHRNK X1/9 1/16
Picture configuration single mode
Pixel
Lines
upon another (same content) upon another (same content)
Table
Multi-display modes
display modes shown appendix. sizes partial pictures listed table 4-9. Display Control
on-chip memory capacity kbits. Provided that same standard video sources applied inset parent channel, jointline-free frame mode display possible. This means that every incoming field processed displayed 9488X/SDA 9588X processor. result high vertical time resolution. this purpose standard analyzed internally frame mode display blocked automatically, described restrictions fulfilled. Then only every second incoming field shown (field mode). Field mode normally shows jointlines. This caused update memory during read out. result that part picture contains picture information other part contains earlier written field. switching from frame mode free artifacts. Activation frame-mode display blocked automatically least following conditions fulfilled: Inset parent channel have same field repetition frequency. This means that frame mode possible only 50Hz inset parent sources 60Hz inset parent sources. Interlace signal detected inset parent channel. progressive scan (S)VGA display therefore only field mode possible. some VCRs trick mode, often interlace detected also. number lines within predefined range inset (FMACTI) parent (FMACTP) channel (assuming standard signals according ITU)
Micronas
4-20
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
FMACTP Table 4-10
parent standard
number lines field 310.315 290.325 260.265 250.275
FMACTI
inset standard
number lines field 310.315 290.325 260.265 250.275
Required number lines frame mode display
system forced field mode means FIESEL. Either first second field selectable. 'One both' takes every second field independent field number. This meant sources generating only field (e.g. video-games). progressive scan conversion systems HDTV (S)VGA displays line doubling mode available (PROGEN). Every line inset picture read twice. Memory writing stopped FREEZE bit. field stored memory then continuously read. picture decimation done before storing, picture size frozen picture changed. Depending phase between inset parent signals correction display raster read data performed. Synchronization memory reading with parent channel achieved processing parent horizontal vertical synchronization signals. Horizontal vertical pulses provided. signals horizontal synchronization vertical synchronization. HSPINV VSPINV respectively allow inversion expected signal polarity.
VSPDEL VSPDEL max=151 (75) field window
VSPD
(internal)
field window tH/2 (16) (32)
values brackets apply 100Hz systems
Figure Micronas
Field detection phase adjustment vertical pulse (VSP) 4-21
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
external signals come from different devices with different delay paths, phase between V-sync H-sync adjustable (VSPDEL). incorrect setting VSPDEL result wrong unreliable field detection parent channel. Normally noise reduction incoming parent vertical pulse performed. With this function missing vertical pulses compensated. circuit works 50/60 applications well progressive 100/120Hz application. (S)VGA signals supposed very stable therefore supported noise suppression. means VSPNSRQ, vertical noise suppression switched off. great variety combinations inset parent frequencies possible. following table shows some constellations:
frame correct aspect Inset Parent mode ratio Frequency Frequency (HSP/VSP) (single pip) correct aspect vertical ratio noise (multi display) suppression selectable
100i 120i 100i 120i (S)VGA (S)VGA
standard signals supposed valid some parent frequencies. Please refer Chapter 4.7.1 Available Features with varying inset parent standards
Table 4-11
Micronas
4-22
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
4.7.1
Mixed Standard Applications (S)VGA Support
(kHz) (µs) THact( lines/ active fdot (MHz) scan correct aspect ratio
remark (Napel Naline
720X576@50Hz (TV) 702X488@60Hz (TV) 720X576@100Hz 702X488@120Hz 720X576@50Hz progressive) 702X488@60Hz progressive) 640X480@60Hz (VGA) 640X480@72Hz (VGA) 640X480@75Hz (VGA) 800X600@56Hz (SVGA) 800X600@60Hz (SVGA) 800X600@72Hz (SVGA) 800X600@75Hz (SVGA) 800X600@85Hz (SVGA) 1024X768@43Hz (SVGA) Table 4-12 Micronas
15.6 15.7 31.2 31.2 31.2 31.2 31.5 37.9 37.5 35.2 37.9 48.1 46.9 53.7 35.5
64.0 63.6 32.0 31.8 32.0 31.8 31.8 26.4 26.7 28.4 26.4 20.8 21.3 18.6 28.2
52.0 52.7 26.0 26.4 26.0 26.4 25.4 20.3 20.3 22.2 20.0 16.0 16.2 14.2 22.8
625/ 525/ 625/ 525/ 625/ 525/ 525/ 520/ 500/ 625/ 625/ 666/ 625/ 631/ 817/
13.5 13.5 25.2 31.5 31.5 36.0 40.0 50.0 49.5 56.3 44.9
interlace interlace interlace interlace progressive progressive progressive progressive progressive progressive progressive progressive progressive progressive interlace
Examples supported parent signals 4-23
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
9488X resp. 9588X allow multiple scan rates desktop video applications, compatible 100Hz sets. features provided 'normal' operating modes auto detected 50Hz parent inset standards. modes (100/120Hz progressive) supported line frequency- pixel clock doubling detected automatically. Even 16:9 picture tube correct aspect ratio displayed selecting approbiate parent clock. video synthesizer generates also special pixel clock display (see chapter 5.5.9 details). (S)VGA consists variety scan rates correct aspect ratio adjustable modes with parent clock (HZOOM) because limited count frequencies. single only, correct aspect ratio maintained vertical horizontal scaler (HSHRINK VSHRINK). possible display (S)VGA sources parent display, long horizontal frequency lower than signal does contain more than 1023 lines. progressive scan mode, PROGEN must set. Additionally field-mode should forced prevent unallowed frame-mode displaying (FIESEL). (S)VGA normally does display raster generated vertical noise suppression, VSPNSRQ should disabled. (S)VGA signals inset channel supported. PROGEN Table 4-13 4.7.2 READD Expected input signal signal interlace signals interlace (reserved) (S)VGA signal progressive
Selection display field repetition Display standard
single-PiP, number displayed lines depends selected picture size signal standard. multi picture display, number displayed lines depends selected picture size signal standard parent signal. Additionally, standard forced DISPSTD.
Micronas
4-24
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
DISPSTD
DISPMOD
Display Standard depends detected inset standard (single pip) depends detected parent standard (multi display) display always lines mode display always lines mode freeze last detected display standard size
Table 4-14
Display standard selection
lines picture shown with lines parent signal, some lines missing bottom picture. lines picture shown with lines display standard, missing lines bottom filled with background color. 4.7.3 Picture Positioning
display position inset picture programmable corners parent picture (CPOS). From there moved middle Picture with POSHOR POSVER. corner positions centered coarsely screen with POSOFH POSOFV. Depending coarse position, corner remains stable when changing picture size. CPOS Coarse Position upper left upper right lower left lower right Reference corner upper left upper right lower left lower right increasing POSVER down down increasing POSHOR right left right left
Table 4-15
Coarse Positioning
Starting every coarse position, picture movable horizontal locations pixel increments) vertical locations line increments). pixel width screen depends selected HZOOM factor. Even POP-positions (Picture Outside Picture) 16:9 applications possible.
Micronas
4-25
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
POSHOR
CPOS='01' CPOS='00'
POSVER POSVER
CPOS='10'
POSHOR
CPOS='11'
Figure 4.8.1
Coarse Positioning Output Signal Processing Luminance Peaking
improve picture sharpness, peaking filter which amplifies higher frequencies input signal implemented. amount peaking varied seven steps YPEAK. setting '000' switches peaking. value '011' recommended. This provides good compromise between sharpness impression annoying aliasing. characteristic possible settings shown fig. (4-9)
gain [dB]
YPEAK '000' YPEAK '001' YPEAK '111' YPEAK '110' YPEAK '101' YPEAK '100' YPEAK '011' YPEAK '010'
normed frequency
Figure Micronas
Characteristics selectable peaking factors 4-26
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
emphasized frequency depends adjusted decimation. gain maximum always located before band-limit ensuring optimal picture impression. Peaking additionally increased PKBOOST. Coring should switched YCOR reduce noise, which also amplified when peaking enabled. coring stage front peaking filter, noise will peaked. 4.8.2 Matrix
chip contains three different matrices, suited standards, suited NTSC-Japan suited NTSC-USA, which selected MAT. signal OUTFOR switches between output output. signal UVPOLAR inverts channels results Y-U-V output. standard magnitudes angles color-difference signals UV-plane defined follows: matrices characteristics (B-Y) 2.028 2.028 2.028 Magnitudes (R-Y) 1.14 1.582 2.028 (G-Y) 0.608 0.608 (B-Y) Angles (R-Y) (G-Y) NTSC (Japan) NTSC (USA) (reserved) Standard
Table 4-16
color saturation adjusted with SATADJ register steps between 1.875. Values above clip chrominance signals. 4.8.3 Framing Colored Background
Figure 4-10 Normal frame frame Micronas 4-27
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
With FRSEL colored frame added inset picture. chip display different types frames, simple monochrome frame more sophisticated frame giving three dimensional impression. frame elements always placed outside inset picture, except inner shade three dimensional frame inner frame multipip-mode. There shift inset picture position inset frame width modified. 4096 frame colors programmable FRY, FRU, FRV, bits each component. Horizontal vertical width frame programmable independently FRWIDH FRWIDHV. desired, frame color displayed over whole size whole picture size main channel when PIPBG accordingly.
Picture background picture frame frame color shades dark/light
background background color frame color
Figure 4-11 Selectable picture configurations background colors programmable BGY, BGU, BGV, bits each component. Alternatively BGFRC sets background frame color. 4.8.4 16:9 Inset Picture Support
remove dark stripes 16:9 inset pictures vertical display area reducable with VPSRED. number omitted lines depends vertical decimation factor.
Micronas
4-28
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
vertical decimation factor
displayed lines (50Hz)
displayed lines (50Hz) with reduction
displayed lines (60Hz)
displayed lines (60Hz) with reduction
Figure 4-12 Number lines without with reduction vertical picture size
Figure 4-13 16:9 inset picture without with reduction vertical picture size 4.8.5 Parent Clock Generation
phase output signals locked rising edge horizontal sync pulse. frequency varies certain range ensure correct aspect ratio 16:9 applications depending HZOOM. horizontal vertical scaling used display frequencies. display format 16:9 16:9 Table 4-17 Micronas inset picture format 16:9 desired format 16:9 16:9 required parent frequency 20.25 value HZOOM
Format conversion using HZOOM 4-29
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
4.8.6
Select Signal
controlling external switch select signal supplied. delay this signal programmable adaptation different external output signal processing devices (SELDEL). SELDOWN sets this output tristate (high-resistance).
frame
signal OUTx
picture
SELDEL
Figure 4-14 Select timing DA-Conversion Switch
9588X/SDA 9488X include three 7bit DA-converters. Brightness (BRTADJ), Contrast (CON) overall amplitude (PKLR, PKLG, PKLB) output signal adjustable. External signals connected inputs IN1.3. forcing input high-level these signals switched outputs OUT1.3 while internal signals switched off. input signal passed through output. setting RGBINS determines wether insertion possible which source, external picture PiP, gets priority.
Micronas
4-30
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
RGBINS='10' PIPON='1'
RGBINS='11' PIPON='1'
RGBINS='00' PIPON='1'
RGBIN='1X' PIPON='0'
VDDA1
VREFM
VDDA2
OUT1
OUT2
VREFL
VSSA1
CVBS1
CVBS2
CVBS3
VREFH
VSSA2
OUT3
RGB/VYU
Figure 4-15 Visualization RGB/YUV insertion external signals each clamped reference levels DACs force uniform black levels each channel. clamping needs careful adjustment especially applications. position length blanking pulse well clamping pulse adjustable (CLPPOS, CLPLEN). READD (100Hz mode), pulses shortened half. HZOOM influences adjustment range clamping blanking pulse because modified clock frequency, pulse length kept nearly constant.
Parent Video
allowed range
BLANKP
CLAMPP
Figure 4-16 horizontal blanking timing
Micronas
4-31
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
READD
CLPDEL
CLPLEN
(µs) Blanking Start
(µs) Blanking Duration
(µs) Clamping Start
(µs) Clamping Duration
Table 4-18 4.9.1
-1.5 -1.5 -11.0 -0.8 -5.5 -0.8 -5.5
10.5 10.5
-6.4 -7.3 -3.2 -3.6
horizontal blanking timing Contrast, Brightness Peak Level Adjustment
peak level adjustment modifies magnitude each channel separately. should used adapt once signal levels following stage. contrast adjustment influences three channels allows further increase peak level magnitude. effect brightness adjustment depends selected output mode (RGB/YUV). mode changes offset OUT2 signal only while mode changes offset three channels same time. brightness increase 20%. 4.9.2 Pedestal Level Adjustment
pedestal level adjustment controlled signals BLKLR, BLKLG, BLKLB enables correction small offset errors, possibly appearing successive blanking stage processor. This adjustment effect setup level during active line interval each channel like brightness adjustment enhanced resolution LSB. maximum possible offset amounts LSBs. mode (OUTFOR '1') action depends setting BLKINVR BLKINVB. BLKINVR (BLKINVB) active offset applies blank level (BU) channel during clamping interval shifting setup level negative direction. mode (OUTFOR '0') BLKINVR BLKINVB have effect.
Micronas
4-32
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
Mode BLKINVR BLKINVB BLKINVR BLKINVB
BLKLR BLKLB
BLKLR BLKLB
BLKLR BLKLB
BLKLR BLKLB
Mode
BLKLR BLKLB BLKLG
BLKLR BLKLB BLKLG
Figure 4-17 Pedestal level adjustment 4.10 Data Slicer
Depending SERVICE, Closed Caption data ('Line 21') (Widescreen signalling) sliced digital data slicer read from interface. line number sliced data selectable with SELLNR. Therefore processed different regions (e.g. with Closed Caption data assumed conform with standards EIA-608 EIA-744-A. data assumed conform with (2nd edition, 1996). 4.10.1 Closed Caption
closed caption data stream contains different data services. field (line captions text pages transmitted whereas field (line 284) caption CC3, CC4, text data transmitted. more information please refer above mentioned standards. well prefiltered data provided alternatively. With built-in programmable XDS-Filter (XDSCLS), program-rating information ('V-chip') well Micronas 4-33
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
others filtered out. filter reduce traffic save calculation power main controller. class filter selected, incoming data (both fields) sliced provided interface. When more class filters chosen, only data field sliced. combination class filters allowed. Each 'CLASS' divided into 'TYPES' which sorted XDS-secondary filter (XDSTPE). combination type filter allowed. Some type filter require appropriate class filter. 4.10.2 Widescreen Signalling (WSS)
mode (SERVICE='1') filtering possible. sliced data passed output registers. this case XDSTPE selects field number data sliced. Europe carries instance information about aspect ratio movie mode. 4.10.3 Indication Data
sliced possibly filtered data available DATAA DATAB. corresponding status bits DATAV SLFIELD. When data were received, DATAV becomes controller must read DATAA, DATAB status information. After both data bytes were read DATAV becomes until data arrives. must ensured that data polling activated once field (16.7 every second field (33.3 ms), depending slicer configuration inset field frequency. field number data DATAA DATAB found SLFIELD. more XDS-class filter activated, SLFIELD contains always '1'. Additionally (INT) flag that data received. Default this tri-state mode compatible with Micronas SDA9388X/9389X devices. also configured IRQCON output single short pulse when data available behave equal DATAV. last case output remains active until data registers DATAA/DATAB read. Both modes useful avoid continuos polling bus. micro-controller initiates transfers only when required.
while (1){ i2c_read pip4_adr, status_reg_adr, status (status data_valid_mask) i2c_read_inc pip4_adr, dataa_reg_adr, dataa, datab, status process_data dataa, datab, status Figure 4-18 Example pseudo-code reading data Micronas 4-34
9488X (B31) 9588X (B31)
Preliminary Data Sheet System Description
4.10.4
Violence Protection
rating information sent program rating packet current (sometimes future) class data stream. only this information desired corresponding filter (class 01h, type 05h) should used suppress other data. class/packet bytes (0105h) precede bytes rating information. Each sequence closed end-of-packet byte (0fh) checksum. This checksum complements byte truncated bytes 00h. Except comparison received rating with adjusted user rating threshold micro-controller should check parity each byte validate checksum avoid miss-interpretation wrong received data. 9488X/SDA 9588X offer some alternatives blocking channel completely switching (fig. (4-19)).
"Warning Message"
THIS PROGRAM CONTAINS VIOLENT SCENES
"Blue Screen"
"Mosaic"
Figure 4-19 Possibilities blocking Mosaic mode (MOSAIC) hides details picture reduced sharpness increased aliasing. picture looks scrambled less perceptible.
Micronas
4-35
9488X (B31) 9588X (B31)
Preliminary Data Sheet Application Examples
Application Examples
following figures show 100/120Hz applications with Micronas Featurebox 9400/01. chip supports addresses owns switch dual-PiP applications easy implement. arrangement best possible performance shown fig. (5-1).
additional source
IN1-3
SDA9588X
SDA9588X
CVBS (Y/C, YUV)
SDA9588X
HSP/VSP OUT1-3 +3.3V
9400
IN1-3
CVBS (Y/C, YUV)
SDA9588X
HSP/VSP OUT1-3
additional sources
H/V1H
H/V2H
CVBS (Y/C)
analog digital Frontend
YUV1H
Featurebox i.e.SDA 9400
YUV2H
Backend i.e. SDA9380
Figure
9588X application with insertion front Featurebox
output 'OCTOPUS' connected RGB) input video processor main channel. 4:2:2 processing within 9400 inset picture remains brilliant.
SDA9588X
CVBS (Y/C, YUV)
SDA9588X
HSP/VSP OUT1-3
9400
additional sources
CVBS (Y/C)
H/V1H
H/V2H
analog digital Frontend
YUV1H
Featurebox i.e. 9400
YUV2H
Backend i.e. SDA9380
Figure
9588X application with insertion behind featurebox
Connecting 9588X directly input processor possible well. picture generated from 9588X device, other from featurebox. This cheap implementation preserves chroma inset channel full bandwidth, although only field mode possible picture. output OSD/ Text processor switch 9588X. Micronas 5-36
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Address Write Address1 Read Address1 (D6h) (D7h)
Table
Primary Address (pin 9='low-level') (DEh) (DFh)
Write Address2 Read Address2 Table WRITE READ
Secondary Address (pin 'high-level') I2C-Bus Format 1101x110 Subaddress Data Byte ****
1101x110 Subaddress 1101x111 Data Byte
Start condition Repeated start condition Acknowledge Stop condition Acknowledge Write operation possible registers 00h-21h 2Eh-37h only, read operation possible registers 2Ah-2Ch only. automatic address increment function implemented.
Micronas
6-37
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Command Table
Subadd (Hex) PIPON CPOS1 CPOS0
Data Byte READD PROGEN FIESEL1 FIESEL0
YUVSEL
POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0 POSVER7 POSVER6 POSVER5 POSVER4 POSVER3 POSVER2 POSVER1 POSVER0 VFP3 VFP2 VFP1 FREEZE PIPBG1 VSPNSRQ VPSRED VERBLK VFP0 MOSAIC PIPBG0 VSPDEL4 FRWIDH2 HFP3 HFP2 HFP1 HFP0
DISPSTD1 DISPSTD0 FPSTD1 HSPINV FRSEL RGBINS1 AGCRES CVBSEL1 PLLITC1 CSTAND2 BGPOS IFCOMP1 SATNR CONADJ3 BRTADJ3 TRIOUT PKLR7 PKLG7 PKLB7 FPSTD0 VSPINV INFRM RGBINS0
SIZEHOR1 SIZEHOR0 SIZEVER1 SIZEVER0 FMACTP VSPDEL3 FRWIDH1 HZOOM2 VSPDEL2 FRWIDH0 SELDEL2 CLPDEL2 AGCVAL1 HZOOM1 VSPDEL1 FRWIDV1 SELDEL1 CLPDEL1 AGCVAL0 HZOOM0 VSPDEL0 FRWIDV0 SELDEL0 CLPDEL0 NOSIGB LMOFST0 YCDEL0 CKILL0 CHRBW0 HUE0 SCADJ0 BLKLR0 BLKLG0 BLKLB0 PKLR0 PKLG0 PKLB0
SELDOWN SELDEL3 CLPDEL3 AGCVAL2
DISPMOD1 DISPMOD0 CLPDEL4 AGCMD1 CVBSEL0 PLLITC0 CSTAND1 (reserved) IFCOMP0 FMACTI CONADJ2 BRTADJ2 REFINT PKLR6 PKLG6 PKLB6 AGCMD0 CLMPID1 AGCVAL3
CLMPID0 BLKVCHYS BLKCVAL LMOFST1 YCDEL3 YCDEL2 YCDEL1 CKILL1 CHRBW1 HUE1 SCADJ1 BLKLR1 BLKLG1 BLKLB1 PKLR1 PKLG1 PKLB1
BLKVCFIL (reserved) CSTAND0 DEEMP1 HUE5 CPLLOF CONADJ1 BRTADJ1 BLKINVR PKLR5 PKLG5 PKLB5 CSTDEX1 DEEMP0 HUE4 SCADJ4 CONADJ0 BRTADJ0 BLKINVB PKLR4 PKLG4 PKLB4
CSTDEX0 (reserved) COLON HUE3 SCADJ3 BLKLR3 BLKLG3 BLKLB3 PKLR3 PKLG3 PKLB3 ACCFIX HUE2 SCADJ2 BLKLR2 BLKLG2 BLKLB2 PKLR2 PKLG2 PKLB2
Micronas
6-38
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subadd (Hex) MAT1 OUTFOR (reserved) SATADJ3 XDSCLS4 UVSEQ (reserved) MAT0 UVPOLAR BGFRC SATADJ2 XDSCLS3 MPIPBG (reserved) BGY1 BGU1 BGV1 SATADJ1 XDSCLS2 SERVICE PALIDL2
Data Byte FRY3 FRU3 FRV3 YPEAK2 XDSCLS0 SELLNR0 FRY2 FRU2 FRV2 YPEAK1 XDSTPE2 IRQCON2 PIPBLK FRY1 FRU1 FRV1 YPEAK0 XDSTPE1 IRQCON1 (reserved) FRY0 FRU0 FRV0 YCOR XDSTPE0 IRQCON0 PALIDL0
BGY0 BGU0 BGV0 SATADJ0 XDSCLS1 SELLNR1
PALIDL1_1 PALIDL1_0
POSOFV2 POSOFV1 POSOFV0 POSOFH4 POSOFH3 POSOFH2 POSOFH1 POSOFH0 (reserved) (reserved) (reserved) FRMMD DATAA7 DATAB7 PALDET (reserved) (reserved) (reserved) (reserved) (reserved) PIPSTAT DATAA6 DATAB6 (reserved) (reserved) (reserved) SYNCST1 DATAA5 DATAB5 DEVICE1 (reserved) SCMIDL2 VSHRNK4 VSHRNK3 VSHRNK2 VSHRNK1 VSHRNK0 HSHRNK4 HSHRNK3 HSHRNK2 HSHRNK1 HSHRNK0 (reserved) SYNCST0 DATAA4 DATAB4 DEVICE0 (reserved) SCMIDL1 DWCOR CKSTAT DATAA3 DATAB3 PRNSTD (reserved) SCMIDL0 PKBOOST CLPLEN1 STDET2 DATAA2 DATAB2 PALID (reserved) SECDIV STDET1 DATAA1 DATAB1 DATAV (reserved) CLPLEN0 STDET0 DATAA0 DATAB0 SLFIELD (reserved) BELLIIR
SCMREL1 SCMREL0 PALINC1 ADLCK NSRED2 PALINC2
LOCKSP1 LOCKSP0 SECACCL2 SECACCL1 SECACCL0 SECACC
NADJ2 NADJ1
ADLCKSE ADLCKCC CLRANGE1 CLRANGE0 NSRED1
NADJ0 ENLIM
NSRED0
SLLTHD1
SLLTHD0
ISHFT1
ISHFT0
DTECT5060 VTHRL50_6 VTHRL50_5 VTHRL50_4 VTHRL50_3 VTHRL50_2 VTHRL50_1 VTHRL50_0
BCOROFF VTHRL60_6 VTHRL60_5 VTHRL60_4 VTHRL60_3 VTHRL60_2 VTHRL60_1 VTHRL60_0
VTHRH50_ VTHRH50_ VTHRH50_ VTHRH500 VTHRH60_ VTHRH60_ VTHRH60_ VTHRH60_
CLMSTGY SLLTHDVP SLLTHDV2 SLLTHDV1 SLLTHDV0 VFLYWHLM1 VFLYWHLM0 VFLYWHL
Micronas
6-39
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subadd (Hex)
Data Byte
VDETIFS
CLMPIST3
VDETITC
CLMPIST2
VLP1
CLMPIST1
VLP0
CLMPIST0
FLNSTRD1 FLNSTRD0 CLMPCHRY CLMPCHRY LATENCY LATENCY0 FILTBRST CLMPIST4
After power grey marked data bits '1', other `0`.
Micronas
6-40
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Command Description
Subaddress PIPON switches insertion insertion insertion
CPOS upper left position upper right position lower left position lower right position
Coarse position coarse positioning picture
YUVSEL select mode CVBS source source
Select
READD PROGEN
Read Double Mode double read frequency compatibility with systems that (e.g.100 progressive) display with single read frequency oversampling display with double read frequency Progressive Scan Enable compatibility with progressive scan systems each line read once (normal operation) each line read twice (line doubling operation)
Micronas
6-41
9488X (B31) 9588X (B31)
Preliminary Data Sheet
FIESEL frame mode possible) field mode (first field only)
Field Select field frame display mode
field mode (second field only) field mode (one both)
Subaddress POSHOR D7-D0 Horizontal Picture Position horizontal position adjustment steps pixel shift direction depends coarse positioning picture
Subaddress POSVER D7-D0 Vertical Picture Position vertical position adjustment steps lines shift direction depends coarse positioning picture
Subaddress pixel (0.7 µs), most left position pixel, nominal center position Horizontal Fine Positioning changes position horizontal acquisition window steps pixel pixel (-0.8 µs), most right position image Note values refer undecimated picture
Micronas
6-42
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Vertical Fine Positioning changes position vertical acquisition window steps line lines, most upper position image lines, nominal center position lines, most right position Note values refer undecimated picture
Subaddress DISPSTD Display Standard selects line standard display depends detected inset standard display always line mode display always line mode freeze last detected display standard size Freeze Picture interrupts inset picture writing displays still picture live picture still picture Mosaic Mode hides picture details, intended with parental control mosaic mode mosaic mode
FREEZE MOSAIC
Micronas
6-43
9488X (B31) 9588X (B31)
Preliminary Data Sheet
SIZEHOR horizontal decimation reduction reduction reduction reduction
Horizontal Size
SIZEVER vertical decimation reduction reduction reduction reduction
Vertical Size
Subaddress FPSTD Force Parent Standard forces parent standard following modes auto-detect parent standard 50Hz/625 lines parent standard forced 60Hz/525 lines parent standard forced freeze last detected standard Background Display selects background display visible, background display invisible, background display visible, full screen background display invisible, background display full screen background
PIPBG
Micronas
6-44
9488X (B31) 9588X (B31)
Preliminary Data Sheet
FMACTP HZOOM
Frame Mode Activation Parent selects parent condition activation frame mode Frame mode active standard parent video sources only Frame mode active some nonstandard sources also Horizontal Zoom selects parent (display) clock frequency 27.34 20.25 35.27 25.43 26.67 20.63 34.17MHz 28.04
Subaddress HSPINV VSPINV Horizontal Sync Pulse Inversion inverts polarity inversion, raising edge sync reference inverted, falling edge sync reference Vertical Sync Pulse Inversion inverts polarity inversion, raising edge sync reference inverted, falling edge sync reference
Micronas
6-45
9488X (B31) 9588X (B31)
Preliminary Data Sheet
VSPNSRQ
Vertical Sync Pulse Noise Reduction activates automatic insertion that generates vertical sync pulses case missing external VSPDEL Vertical Sync Pulse Delay delay vertical sync pulse steps parent clocks delay maximum delay, 4096 clocks parent frequency Note delay depends HZOOM
Subaddress FRSEL INFRM VPSRED reduction reduction inner frame inner frame Vertical Picture Size Reduction reduces vertical picture size suppress black bars 16:9 programs normal frame shaded frame with impression Inner Frame activation actives inner frame pix. width, lines height) displ. mode Frame Select selects between normal frame shaded frame
Micronas
6-46
9488X (B31) 9588X (B31)
Preliminary Data Sheet
FRWIDH pixel
Frame Width Horizontal adjusts horizontal width frame steps pixel horizontal frame
FRWIDV lines vertical frame
Frame Width Vertical adjusts vertical width frame steps line
Subaddress RGBINS Insertion controls insertion external RGB/YUV sources external insertion possible, input inactive external insertion forced (FSW external insertion with possible (priority input) external insertion with possible (priority PIP)
VERBLK
Vertical Blanking switches vertical blanking mode blanking level outputs only during line-blanking intervals blanking level outputs during line-blanking intervals fieldblanking intervals, lines following parent vertical synchronization pulse blanked
Micronas
6-47
9488X (B31) 9588X (B31)
Preliminary Data Sheet
SELDOWN SELDEL open source output output
Select Down switches driver type output
Select Delay adjusts delay select signal clock periods display clock clock periods display clock clock cycles display clock
Subaddress DISPMOD single mode x1/9 (same content) x1/16 (same content) (reserved) Display Mode selects display modes with equal pictures
CLPDEL
Clamping Delay delay clamping pulse external RGB/YUV inputs steps parent clock periods delay maximum delay, clock periods parent frequency
Micronas
6-48
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress AGCRES AGCMD controls operation evaluation sync height overflow evaluation sync height only evaluation overflow only fixed (gain depends AGCVAL) Automatic Gain Control Value input voltage Signal Behavior controls behavior synchronization possible source applied) noisy picture colored background input voltage value fixed mode (AGCMD='11') input voltage resets normal operation reset Mode Automatic Gain Control Reset
AGCVAL
NOSIGB
Micronas
6-49
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress CVBSEL select CVBS source CVBS1 CVBS2 (Y@CVBS2 C@CVBS3) CVBS3 Clamping Duration adjusts duration clamping pulse (inset channel) 0.5µs 0.9µs 1.2µs 1.5µs Blankvalue hysteresis Blankvalue generation (sync-tip clamping only) without hysteresis with hysteresis Clamping correction offset (back-porch clamping only) CVBS Select
CLMPID
BLKVCHYS BLKVCVAL
Micronas
6-50
9488X (B31) 9588X (B31)
Preliminary Data Sheet
LMOFST offset offset offset offset
Luminance Offset modifies black blank level offset
Subaddress PLLITC VCR1 (very fast) VCR2 (very slow) Blankvalue filtering (sync-tip clamping only) lowpass filter lowpass filter Delay pixel (0.35 pixel adjusts delay between luminance chrominance pixel (-0.4 with respect undecimated picture) Inset Time Constant switches time constant inset
BLKVCFIL YCDEL
Micronas
6-51
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress CSTAND Color Standard forces desired color standard automatic standard identification NTSC-M PAL-N (Argentina) PAL-M NTSC44 PAL-B SECAM PAL60 Color Standard Exclusion excludes standards from automatic standard identification ignore PAL-M PAL-N ignore SECAM, B/G, PAL60, NTSC4.4 ignore PAL-M /PAL-N NTSC-M ignore PAL-M PAL-N NTSC4.4 PAL60 Standard Identification Speed sets speed color standard recognition medium fast Color Killer Threshold damping color carrier switch color color always Note only valid color killer active (COLON='0'), values approximative
CSTDEX
LOCKSP CKILL
Micronas
6-52
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress BGPOS normal position delayed Burst Gate Position adjusts position burst gate
DEEMP Filter1 recommendation Filter2 Filter3
Deemphase Selection adjusts SECAM deemphase filter
COLON ACCFIX CHRBW wide medium reserved small wide SECAM small medium active disable color killer color killer active color forced
Color
Disable Automatic Chroma Control disables automatic chroma control (ACC) fixed (ACC nominal value) Chroma Bandwidth remark adjusts chroma bandwidth
Micronas
6-53
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress IFCOMP filtering chroma bandpass active IF-compensation bandpass (6dB/octave) reserved 43.4° skin color becomes redish Control phase color subcarrier NTSC -44.8° remark skin color becames greenish IF-Compensation Filter equalizes IF-stage characteristic
Subaddress SATNR FMACTI disabled enabled Frame Mode Activation Inset sets inset condition activation frame mode frame mode only active standard inset video sources enhanced frame mode activation range Satellite Noise Reduction stabilizes horizontal satellite signals (,,fishes")
Micronas
6-54
9488X (B31) 9588X (B31)
Preliminary Data Sheet
CPLLOF chroma active
Chroma opens loop chroma (only test servicing) chroma opened (free running oscillator)
SCADJ
Color Subcarrier Adjustment color subcarrier frequency fine adjustment max. negative deviation (-150 ppm) default (for nominal crystal frequency max. positive deviation (+310 ppm)
Subaddress CONADJ +30% contrast increase Blanking Level +7.5LSB offset adjusts pedestal level OUT1 channel steps 0.5LSB pedestal nominal contrast Contrast Adjustment adjusts contrast picture, acts OUT1-OUT3
BLKLR
Micronas
6-55
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress BRTADJ Brightness Adjustment adjusts brightness picture, acts OUT1-OUT3 mode (YUVFOR '0') OUT1 mode (YUVFOR '1') nominal brightness +20% brightness increase Blanking Level Green +7.5LSB offset adjusts pedestal level OUT2 channel steps 0.5LSB pedestal
BLKLG
Subaddress TRIOUT REFINT BLKINVR normal refresh fast refresh Blanking Inversion inverts sign OUT1 channel offset (BLKLR) offset added during active picture offset added during blanking Tristate Output sets OUT1-OUT3 tristate mode (high resistance) normal operation, outputs active pins OUT1-3 tri-state mode Refresh Intervall changes refresh rate eDRAM Note keep
Micronas
6-56
9488X (B31) 9588X (B31)
Preliminary Data Sheet
BLKINVB
Blanking Inversion Blue inverts sign OUT3 channel offset (BLKLB) offset added during active picture offset added during blanking
BLKLB +7.5LSB offset
Blanking Level Blue adjusts pedestal level OUT3 channel steps 0.5LSB pedestal
Subaddress PKLR Peak Level peak peak output voltage OUT1 channel Note
values refer contrast (CONADJ) brightness (BRTADJ) minimum
Micronas
6-57
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress PKLG Peak Level Green peak peak output voltage OUT2 channel Note
values refer contrast (CONADJ) brightness (BRTADJ) minimum
Subaddress PKLB Peak Level Blue peak peak output voltage OUT2 channel Note
values refer contrast (CONADJ) brightness (BRTADJ) minimum
Subaddress Micronas EBU- Matrix NTSC-Japan Matrix NTSC-USA Matrix (reserved) 6-58 Matrix Select selects matrix coefficients conversion
9488X (B31) 9588X (B31)
Preliminary Data Sheet
D5-D4
Background Color adjusts background color component values gives MSBs background signal Frame Color adjusts frame color component value gives MSBs frame signal
D3-D0
Subaddress OUTFOR UVPOLAR D5-D4 Output Format switches between output output output signals, matrix active output signals Polarity switches between inverted output, influence mode output output Background Color adjusts background color component values gives MSBs background signal Frame Color adjusts frame color component value gives MSBs frame signal
D3-D0
Subaddress
Micronas
6-59
9488X (B31) 9588X (B31)
Preliminary Data Sheet
BGFRC D5-D4
Background Frame Color selects background color table frame color table background color background color according BGY, BGU, background color according FRY, FRU, Background Color adjusts background color component values gives MSBs background signal Frame Color adjusts frame color component value gives MSBs frame signal
D3-D0
Subaddress SATADJ YPEAK peaking recommended value strongest peaking 1.875 times saturation Peaking Adjustment adjusts luminance peaking nominal saturation color Color Saturation Adjustment adjusts color saturation steps
Micronas
6-60
9488X (B31) 9588X (B31)
Preliminary Data Sheet
YCOR coring 1LSB coring
Coring Enable suppresses noise introduced peaking
Subaddress XDSCLS XDSTPE XDS-Secondary Filter Type 01h, 01h, 02h, 03h, 04h, 0Dh, 01h, 04h, 05h, 01h, 02h, 03h, 04h, 05h, 0Dh, Class Select Closed Caption XDS-Primary Filter (Class) transparent, filtering 'Current' class selected 'Future' class selected 'Channel' class selected 'Miscellaneous' class selected 'Public Services' class selected Type Select Meaning filtering program rating time information only band only information time information program rating band program rating information program rating field Note behavior these bits depends selected dataservice
Micronas
6-61
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress UVSEQ MPIPBG SERVICE SELLNR IRQCON Closed Caption Widescreen Signalling (WSS) Select Line Number line number data service field (field1) [NTSC] (283), [PAL (280) [NTSC] (284), [PAL (281) [PAL B/G] (329) [PAL B/G] (330) remark Closed Caption Closed Caption black IRE) same background color Data Service Select selects data service slicing correct exchanged Multi-PIP Background selects background color multi-PIP mode Sequence changes multiplex sequence (valid only YUVSEL='1')
Interrupt Request Configuration output tri-state (high-Z) interrupt, when data received (pos. polarity) interrupt, when data received (neg. polarity) equivalent DATAV both registers (pos. polarity) 6-62 pulse length approximately remark
Micronas
9488X (B31) 9588X (B31)
Preliminary Data Sheet
IRQCON
Interrupt Request Configuration output equivalent DATAV both registers (neg. polarity) inset V-pulse (50ns) inset field inset clamping pulse pulse length 50ns high=first field, second field only test purpose remark
Subaddress PALIDL2 1/16 PAL/NTSC identifikation level sensitivity identification PAL/NTSC signals
PALIDL1
PAL/NTSC identifikation level sensitivity identification PAL/NTSC signals
PIPBLK PALIDL Micronas blank blanks
Blank blanks picture setting background color
Level sensitivity identification PAL/NTSC signals high rejection PAL/NTSC rejection PAL/NTSC 6-63
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress POSOFV lines Position Offset Horizontal +240 pixel pixel horizontal position offset steps pixel -256 pixel lines lines Position Offset Vertical vertical position offset steps lines
POSOFH
Subaddress VSHRNK max. possible shrink Vertical Shrink changes vertical size steps lines shrink, picture size according SIZEVER Note max. usable value depends SIZEVER
Subaddress
Micronas
6-64
9488X (B31) 9588X (B31)
Preliminary Data Sheet
HSHRNK
Horizontal Shrink changes horzontal size steps pixel shrink, picture size according SIZEHOR max. possible shrink Note max. usable value depends SIZEVER
Subaddress DWCOR PKBOOST CLPLEN clamping pulse length 3.75us 2.5us 1.25us normal peaking values double peaking values Clamping Pulse Length Blanking Duration Note (reserved) normal operation Peaking Boost influences peaking YPEAK (A2h) test only
10.5
clamping pulse length blanking also influenced setting READD HZOOM
Micronas
6-65
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress FRMMD PIPSTAT SYNCST locked CVBS signal locked CVBS signal Color Killer Status chroma Inset Synchronization Status inset synchronization locked CVBS signal Frame Mode Indication displays field frame mode field mode, field repeated twice frame mode, both fields displayed Status indication visibility PIP, corresponds PIPON
CKSTAT
Micronas
6-66
9488X (B31) 9588X (B31)
Preliminary Data Sheet
STDET
Standard Detection detected color standard nonstandard standard detected NTSC-M PAL-M NTSC44 PAL60 PAL-N SECAM PAL-B/G
Subaddress DATAA D7-D0 First Data Byte first word sliced data, MSB,
Subaddress DATAB D7-D0
Second Data Byte
second word sliced data, MSB,
Subaddress PALDET DEVICE Micronas Micronas
identification
identifikation (algorithm
Device Identification 9488X (PIP Basic) 9489X (PIP Advanced) 9588X (OCTOPUS) 9589X (SOPHISTIUS) 6-67
9488X (B31) 9588X (B31)
Preliminary Data Sheet
PRNSTD
Parent Standard Detection status parent (display) standard detection 60Hz field frequency detected 50Hz field frequency detected
PALID
Identification identification signal (algorithm NTSC signal signal Note valid STDET= '000'
DATAV SLFIELD first field second field
Data Valid data indication, used data flow control (polling mode) data read data available data received available DATAA DATAB Sliced Data Field Number DATAA DATAB from
Subaddress
SCMREL 1024
Secam rejection level
Micronas
6-68
9488X (B31) 9588X (B31)
Preliminary Data Sheet
SCMIDL
SECAM identifikation level
SCCDIV divide divide
Secam Divider
BELLIIR 17/64 12/64
Bellfilter adjustment
Subaddress
PALINC1 PAL/NTSC identification
increment
Micronas
6-69
9488X (B31) 9588X (B31)
Preliminary Data Sheet
PALINC2 PAL/NTSC identification
increment
LOCKSP fields fields fields fields
Locking speed Duration Chroma Search
SECACCL (reserved)
Secam acceptance level
SECACC disabled enabled
Secam acceptance
Micronas
6-70
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress
ADLCK
Additional lock-detection lock signal lock-signal
ADLCKSEL PALID PALDET
Additional lock-detection selection
ADLCKCC
Additional lock-detection color-killer lock signal lock-signal
CLRANGE NADJ steepest notch broadest notch
Chroma lock-range
Notch Adjustment color-carrier notch adjustment
Micronas
6-71
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress
NSRED 1/16
Noise reduction horizontal
SLLTHD offset
Slicing level threshold
adaptive negative (limited adaptive positive (limited adaptive positive (limited
ISHFT
I-adjustment horizontal
Micronas
6-72
9488X (B31) 9588X (B31)
Preliminary Data Sheet
ENLIM disabled enabled Subaddress
Enable limiter
DETECT5060
Detection signals immediately delayed
VTHRL50 D6-D0 0000000 1111111
Vertical window noise suppression opening 50Hz Note opening first line opening line Opening=4*VTHRL50
Subaddress
BCOROFF coring coring
Blanklevel Coring Blanklevel generation coring (for sync-tip clamping only)
Micronas
6-73
9488X (B31) 9588X (B31)
Preliminary Data Sheet
VTHRL60 D6-D0 0000000 1111111
Vertical window noise suppression opening 60Hz Note opening first line opening line Opening=4*VTHRL60
Micronas
6-74
9488X (B31) 9588X (B31)
Preliminary Data Sheet
Subaddress VTHRH60 D7-D4 0000 1111 closing line 262+60 closing line Vertical window noise suppression closing 60Hz Note Closing=262+4*VTHRH60
VTHRH50 D3-D0 0000
Vertical window noise suppression closing 50Hz Note closing line Closing=312+4*VTHRH50
1111 closing line 312+60 Subaddress CLMPSTGY SLLTHDVP positive negative back-porch clamping sync-tip-clamping Slicing Level Threshold polarity Clamping strategy
Micronas
6-75
9488X (B31) 9588X (B31)
Preliminary Data Sheet
SLLTHDV offset (reserved)
Slicing Level Threshold
adaptive (limited adaptive (limited adaptive (limited
VFLYWHLMD
Vertical Flywheel Mode check correct standard lines deviation allowed lines deviation allowed, check interlace lines deviation allowed, check interlace Vertical Flywheel disabled
VFLYWHL enabled Subaddress FLNSTRD Micronas automatic force 50Hz force (reserved)
Force line standard CVBS/RGB frontend
6-76
9488X (B31) 9588X (B31)
Preliminary Data Sheet
CLMPCHARY
Clamping characteristic Y/CVBS characteristic clamping error clamping current high gain medium gain medium gain gain Vertical Detection Slope normal slow Vertical Detection Integration Time Constant long short Lowpass vertical sync-separation
VDETIFS VDETITC none weak medium
strong Subaddress LATENCY Micronas additional idle-states 6-77 Clamping Latency
9488X (B31) 9588X (B31)
Preliminary Data Sheet
FILTBRST disabled enabled
Burst filter Y/CVBS
CLMPIST D4-D0 00000 11111 8.25
Start clamping pulse Note START=0.5µs+CLMPIST*0.25µs
Micronas
6-78
9488X (B31) 9588X (B31)
Preliminary Data Sheet Description
(XIN) (XQ)
Description schematic
remark crystal oscillator, input used external clocking
(HSP) (VSP)
schmitt-trigger input with high hysteresis, best jitter performance pulses with steep slopes
(SDA) (SCL)
low-side driver used SCL, slope acknowledge limited
slope contr
(I2C)
address selection, only static switch supported
Micronas
7-79
9488X (B31) 9588X (B31)
Preliminary Data Sheet Description
(INT)
schematic
remark
(IN1) (IN2) (IN3)
clamped RGB/YUV video inputs, used open connect with 10nF ground
(FSW)
fast switch input
(SEL)
low-side driver disabled (open source mode)
Micronas
7-80
9488X (B31) 9588X (B31)
Preliminary Data Sheet Description
(OUT3) (OUT2) (OUT1)
schematic
remark RGB/YUV video outputs
(VREFH) (VREFL) (VREFM)
VREFM
reference voltage
VREFL
VREFH
(CVBS3) (CVBS2) (CVBS1)
CVBS1 CVBS2 CVBS3
clamped video inputs
Micronas
7-81
9488X (B31) 9588X (B31)
Preliminary Data Sheet Absolute Maximum Ratings
Absolute Maximum Ratings Parameter Ambient Temperature Storage Temperature Junction Temperature Soldering Temperature Input Voltage Symbol Tstg Tsold Output Voltage Supply Voltages Ptot VESD,HBM -100 -2000 -0.3V -0.3 -0.3V -0.3 -0.3 -0.25 Limit Values min. max. VDD+0.3V VDD+0.3V 0.25 0.86 2000 HBM: 1.5k, 100pF duration <10s except SDA, SCL, HSP, SDA, SCL, HSP, only except only Unit remark
Supply Voltage Differentials Total Power Dissipation Latch-Up Protection robustness
voltages listed referenced ground (0V, VSS) except where noted. Stresses above those listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability. Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit.
Micronas
8-82
9488X (B31) 9588X (B31)
Preliminary Data Sheet Recommended Operating Range
Recommended Operating Range Parameter Supply Voltages Ambient Temperature Signal Frequency Signal Frequency Signal Frequency Signal Rise Time Signal High Time Signal Time Signal Frequency Signal Frequency Signal High Time Signal Time Horizontal Frequency Horizontal Frequency Amplitude synchronization pulse length horizontal synchronization puls length vertical synchronization puls chroma amplitude Input Coupling Capacitors CVBS Source Resistance Symbol min. VDDxx fP2H fP2H Vsync ACHR CCLI 15.734 15.625 50/60 100/120 3.15 15.000 30.000 11.7 Limit Values typ. 15.625 31.250 25.2 max. 3.45 16.250 32.500 burst necessary proper clamping input input scan rate conversion mode mode mode noisefree transition Unit Remark
Main horizontal vertical Sync Inputs: VSP,
Inset Input: CVBS1, CVBS2, CVBS3
RSRCI
Micronas
9-83
9488X (B31) 9588X (B31)
Preliminary Data Sheet Recommended Operating Range
Parameter Input Voltage Range inputs CVBS1-3 Reference Voltage Reference Voltage Middle Reference Voltage High
Symbol min.
Limit Values typ. max.
Unit
Remark dep. setting
Reference Voltages:VREFL, VREFM, VREFH VREFL VREFM VREFH 1.10 1.90 3.15 1.20 2.05 1.30 2.20 VDDA1
RGB/YUV Switch:IN1,IN2,IN3,FSW Input Coupling Capacitors Source Resistance Input Voltage Range inputs IN1-3 Input Voltage Range inputs Address: Input Voltage Range Address Input Voltage Range Address VSA1 VSA2 VDDD CCLS necessary proper clamping
RSRCS
Fast (All values referred min(VIH) max(VIL)) This specification lines need identical with stages specification because optional series resistors between lines pins. Clock Frequency Inactive Time Before Start Transmission Set-Up Time Start Condition Hold Time Start Condition Time Micronas fSCL tBUF tSU;STA tHD;STA tLOW 9-84
9488X (B31) 9588X (B31)
Preliminary Data Sheet Recommended Operating Range
Parameter High Time Set-Up Time DATA Hold Time DATA SDA/SCL Rise/Fall Times Set-Up Time Stop Condition Capacitive Load/Bus Line High-Level Input Voltage Low-Level Input Voltage Spike Duration Inputs Low-Level Output Current Load resistance Load capacitance Frequency
Symbol min. tHIGH tSU;DAT tHD;DAT tSU;STO -0.25V 20+$
Limit Values typ. max.
Unit 5.5V
Remark
$=0.1Cb/pF
Inputs/Output: SDA, also SDA/SCL input stages
Digital Analog Converters (7-bit):OUT1, OUT2, OUT3 fxtal 20.248 20.25 20.252 deviation outside this range will cause color decoding failures deviation outside this range will cause color decoding failures
Crystal Specification: XIN,
Maximum Permissible Frequency Deviation
fmax/ fxtal
-100
10-6
Recommended Permissible Frequency Deviation Micronas
f/fxtal
10-6
9-85
9488X (B31) 9588X (B31)
Preliminary Data Sheet Recommended Operating Range
Parameter Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance
Symbol min.
Limit Values typ. max.
Unit
Remark
operating range functions given circuit description fulfilled.
Micronas
9-86
9488X (B31) 9588X (B31)
Preliminary Data Sheet Characteristics
Characteristics
(Assuming Recommended Operating Conditions) Parameter Average total supply current Digital Inputs (TTL, Input Capacitance Input Leakage Current incl. leakage current output stage IOH=-200µA IOH=-4.5mA IOL=1.6mA, only valid SELDOWN= Symbol min. IDDtot Limit Values typ. max. Unit Remark
High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage 1.5V
Low-Level Input Voltage High-Level Input Voltage Delay Inputs: SDA/SCL Schmitt Trigger Hysteresis Low-Level Output Voltage Low-Level Output Voltage Vhys tested -0.25 VDD+0.5
Input Output: (Referenced SCL; Open Drain Output) IOL=3mA IOL=max
Micronas
10-87
9488X (B31) 9588X (B31)
Preliminary Data Sheet Characteristics
Parameter Output Fall Time from min(VIH) max(VIL) CVBS Input Leakage Current CVBS Input Capacitance Input Clamping Error Input Clamping Current
Symbol min.
Limit Values typ. max. 20+0.1* -100
Unit
Remark 10pFCb40 clamping inactive settled state dependent clamping error
Analog Inputs CVBS1, CVBS2, CVBS3 |ICLP|
max. Input Clamping Current deviation Reference Voltage Difference D.C. Differential Nonlinearity Crosstalk between CVBS Inputs D.C. Differential Nonlinearity Full Range Output Voltage
|ICLPx|/ |ICLP| VREFHVREFL
VDDA1=3.3 VREFH-VREFL
Digital Analog Converters (7-bit): Outputs OUT1, OUT2, OUT3 DNLE -0.5 CON, UAMP, VAMP, YAMP CON, UAMP, VAMP, YAMP
Full Range Output Voltage
Micronas
10-88
9488X (B31) 9588X (B31)
Preliminary Data Sheet Characteristics
Parameter Output Voltage
Symbol min.
Limit Values typ. max.
Unit
Remark CON, UAMP, VAMP, YAMP default, VREF const.
Deviation OUT1-3 (matching) Contrast Increase Output Amplitude Ratio (UOH-UOL)/UOL Brightness Increase Pedestal Level variation Input Voltage Range Bandwith (-3dB) Gain Gain Difference Crosstalk Between Inputs Isolation (off state) Clamping Level Difference Output
CLPE
RL>10k; CL=20pF f<4MHz f=5MHz, (Y-UV) f=5MHz between external internal source VCR1 VCR2
switch; IN1, IN2,
Colordecoder/Synchronization Luminance Processing Horizontal pull-inrange Horizontal pull-inrange fHf/fH fHf/fH 13.3 13.3 17.4 17.4
Micronas
10-89
9488X (B31) 9588X (B31)
Preliminary Data Sheet Characteristics
Parameter Amplitude synchronization pulse length horizontal synchronization pulse length vertical synchronization pulse range range Chroma pull-inrange Data slicer Data level Data height Height Channel Distortion Channel Distortion Max. permissible Noise
Symbol min. Vsync
Limit Values typ. max.
Unit
Remark input signals
CRACC CRAGC
-7.5
nominal crystal frequency 25kHz 50kHz
CD25 CD50
26.6
listed characteristics ensured over operating range integratd circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Micronas
10-90
9488X (B31) 9588X (B31)
Preliminary Data Sheet Diagrams
Diagrams
Figure 11-1 Displaymode with picture sizes 1/16
Figure 11-2 Displaymode with picture size 1/36 with scaling
Micronas
11-91
9488X (B31) 9588X (B31)
Preliminary Data Sheet Diagrams
Figure 11-3 Display mode pictures with same content) Display mode pictures with same content)
Micronas
11-92
9488X (B31) 9588X (B31)
Preliminary Data Sheet Diagrams
Teletext processor optional
R(V) G(Y)
Processor
R(V) G(Y)
Main Channel Decoder Sync
Figure 11-4 General Application with CVBS sources Teletext-Processor
Teletext processor optional
Processor
Main Channel Decoder Sync
Figure 11-5 General Application with source from
Micronas
11-93
9488X (B31) 9588X (B31)
Preliminary Data Sheet Diagrams
gain [dB]
gain [dB]
1/16
frequency [MHz]
frequency [MHz]
YPEAK '010' YPEAK '100' YPEAK '111'
gain [dB]
YPEAK '010' YPEAK '100' YPEAK '111'
1/36
frequency [MHz]
YPEAK '010' YPEAK '100' YPEAK '111'
Figure 11-6 Characteristic (PAL) luminance decimation filter different peaking factors
Micronas
11-94
9488X (B31) 9588X (B31)
Preliminary Data Sheet Diagrams
gain [dB]
gain [dB]
1/16
frequency [MHz]
frequency [MHz]
YPEAK '010' YPEAK '100' YPEAK '111'
gain [dB]
YPEAK '010' YPEAK '100' YPEAK '111'
1/36
frequency [MHz]
YPEAK '010' YPEAK '100' YPEAK '111'
Figure 11-7 Characteristic (NTSC) luminance decimation filter different peaking factors
Micronas
11-95
9488X (B31) 9588X (B31)
Preliminary Data Sheet Diagrams
gain [dB]
gain [dB]
0.25
0.75
1.25 frequency [MHz]
1.75
2.25
0.25
0.75
1.25 frequency [MHz]
1.75
2.25
1/16 1/36
1/16 1/36
gain [dB]
0.25
0.75
1.25 frequency [MHz]
1.75
2.25
1/16 1/36
Figure 11-8 Characteristic chrominance decoder filter (small, medium narrow)
Micronas
11-96
9488X (B31) 9588X (B31)
Preliminary Data Sheet Application Circuit
Application Circuit
CVBS1
CVBS1 CVBS2 CVBS3
20.25
CVBS1 VREFM CVBS2 VREFL
+3.3V
+3.3V
SDA9588X
CVBS3 VSSA1 VDDA1 VREFH VSSA2 VDDA2 OUT1 OUT2 OUT3
+3.3V
+3.3V
Address
RVIN GYIN BUIN
RVOUT GYOUT BUOUT
exact value depends crystal specification
Micronas
12-97
9488X, 9588X
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-561-2PD
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
Micronas

Edition Dec. 2001 6251-561-2PD 9488X 9588X Preliminary Data

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