303xA Programmable Universal Controller Edition April 2002 6251-5
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303xA Programmable Universal Controller
Edition April 2002 6251-565-1PD
303xA
Contents Page Section Title
1.1. 1.2.
Introduction
Features Application Overview
2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.1.7. 2.1.8. 2.1.9. 2.1.10. 2.1.11. 2.1.12. 2.1.13. 2.2. 2.2.1. 2.3. 2.3.1. 2.3.2. 2.4. 2.5. 2.5.1. 2.5.1.1. 2.5.1.2. 2.5.1.3. 2.5.1.4. 2.5.1.5. 2.5.2. 2.5.3. 2.5.3.1. 2.5.3.2. 2.5.4. 2.5.4.1. 2.5.4.2. 2.5.5. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2.
Functional Description
Device Overview 64-MHz ARM7TDMI kByte SRAM kByte Embedded Flash Memory Protection Unit Power Management Unit 12-Mbit/s Function Core General-Purpose I/Os Synchronous Serial Port UARTs IrDA Timer Counters Watchdog Interrupt Controller Real Time Clock ARM7TDMI Processor AHB/APB Buses Memory Clock Generation Clock Utilization Summary Phase-Locked Loop Device Power-on Resets Peripherals Flash Memory Flash Memory Flash Configuration Registers Flash Features Programmable Wait States Flash Programming Erasing Security Application Code SRAM Features General Overview Memory Protection Unit SRAM Remapping Address Space Interface Peripherals Power Management Unit Power States Power Management Register Descriptions
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303xA
Contents, continued Page Section 2.6.2. 2.6.2.1. 2.6.2.2. 2.6.2.3. 2.6.2.4. 2.6.2.5. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.3.3. 2.6.4. 2.6.4.1. 2.6.4.2. 2.6.4.3. 2.6.4.4. 2.6.4.5. 2.6.4.6. 2.6.4.7. 2.6.5. 2.6.5.1. 2.6.5.2. 2.6.5.3. 2.6.5.4. 2.6.5.5. 2.6.5.6. 2.6.6. 2.6.6.1. 2.6.6.2. 2.6.6.3. 2.6.6.4. 2.6.6.5. 2.6.7. 2.6.7.1. 2.6.7.2. 2.6.7.3. 2.6.7.4. 2.6.7.5. 2.6.8. 2.6.8.1. 2.6.8.2. 2.6.8.3. 2.6.8.4. 2.6.8.5. 2.6.8.6. 2.6.8.7. 2.6.8.8. Title Interrupt Controller Features Interrupt List General Overview Programming Guide Interrupt Controller Register Definitions UARTs Features UART Functions UART Register Synchronous Serial Ports Peripheral Operation Modes Primary Modes Secondary Modes Example Communication Waveforms Register Descriptions Interrupt Logic Timers Features Description Initialization Modes Operation Generation Waveforms Register Descriptions Real Time Clock Features Description Standby Mode Register Formats Programming Instructions Watchdog Timer Features Description Watchdog Register Descriptions Watchdog Timer Reset Watchdog Timer Enable Sequence General Purpose Module Features Description Bypass Mode Interrupts Signal Interface Initialization GPIO Address Programming Interface
Micronas
April 2002; 6251-565-1PD
303xA
Contents, continued Page Section Title
3.1. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.4.1. 3.5.4.2. 3.5.4.3. 3.5.5. 3.5.5.1. 3.5.5.2. 3.5.5.3. 3.5.5.4. 3.5.5.5. 3.5.5.6. 3.5.5.7. 3.5.5.8. 3.5.6.
Specifications
Outline Dimensions Connections Short Descriptions Descriptions Special Function Pins Shared GPIO Special Function Pins General Purpose Pins Without Special Function Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Power Consumption Characteristics Digital Outputs Hysteresis Schmitt Trigger Inputs Internal Pull-up Pull-down Resistor Values Characteristics Slave (SCLKx SFRMx Inputs) Master (SCLKx SFRMx Outputs) Timing Diagrams Characteristics CLKOUT Timing Requirement WAKE_UP Timing Requirement TIMER_x Inputs Timing Requirement GPIO Inputs Rise/Fall Times 4-mA 12-mA Outputs Flash Programming Characteristics
List Abbreviations Data Sheet History
April 2002; 6251-565-1PD
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303xA
Watchdog Interrupt Controller with hardware prioritization Real Time Clock (not available packages)
Programmable Universal Controller Introduction Programmable Universal Controller 303xA ideally suited portable consumer devices. equipped with embedded ARM7TDMI processor, highly flexible power management scheme, embedded Flash. Fig. shows simplified functional block diagram 303xA.
Especially suited interface with Micronas' 35x9F 3587F 3590A devices
1.2. Application Overview 303xA meets requirements digital audio players, specific mobile network appliances, digital audio recorders (including water-marking DRM), wireless applications such BluetoothTM. 303xA device offers appropriate security features, embedded Flash, variety communication interfaces, including connectivity.
1.1. Features 64-MHz ARM7TDMI kByte embedded SRAM kByte embedded Flash Memory Protection Unit Secure Mode Controller Power Management Unit with integrated Mbit/s function core with integrated transceiver (PUC 3030A only) dedicated kByte SRAM Master/Slave interface
Supply-Out
303xA
Clock
35x9F 3587F 3590A
Mic/Line-In Headphone-Out
Keyboard
V_Bat-In
General-purpose I/Os Synchronous Serial Port (including master), Mbit/s max. speed master, Mbit/s max. speed slave. UARTs IrDA timer counter
Memory Card e.g. SC-Card
Fig. 1-1: Example application: multistandard secure player /recorder
JTAG Port
Security Controller SRAM kByte Prog. Flash kByte
Transceiver kByte SRAM Function Core
ARM7TDMI
Bridge
Clock Reset Control
Power Management Unit
UARTs with IrDA
Watchdog
Realtime Clock
Interrupt Controller
Sync Serial Ports
GPIO
Timer Counters
Advanced High-performance Advanced Peripheral ARM7TDMI Processor Core GPIO General Purpose Input/Output
Memory Protection Unit Phase-Locked Loop Universal Serial
Fig. 1-2: Simplified functional block diagram 303xA (see also List Abbreviations page 129)
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Functional Description 2.1. Device Overview 2.1.1. 64-MHz ARM7TDMI embedded ARM7TDMI RISC processor runs frequencies MHz. processor associated structures configured little endian operation.
2.1.8. Synchronous Serial Port five provided Synchronous Serial Ports implement Motorola SPI, National Semiconductor Microwire, Texas Instruments Synchronous Serial modes speeds Mbit/s master Mbit/s slave.
2.1.9. UARTs IrDA fully independent UARTs available running maximum rate 115.2 kBaud. Each UART also configured IrDA mode.
2.1.2. kByte SRAM embedded SRAM divided into kBytes zerowait-state memory directly connected AMBA SRAM interface, kBytes contained within space. latter accessible directly from both core ARM7TDMI processor.
2.1.10. Timer Counters Three independent counter timers provided timing control during software routines, using various interrupts which generated. timers also clocked external clock, allowing edge counting pulse width monitoring. addition these timers also used generate periodic waveforms external device.
2.1.3. kByte Embedded Flash embedded Flash connected Flash interface allows storage boot application code. Flash interface also implements protection modes allow secure storage application code data.
2.1.11. Watchdog watchdog timer provides method monitor software activity, reset device lock occurs. programmable timeout range provided allow flexibility.
2.1.4. Memory Protection Unit Memory Protection Unit (MPU) provided managing read write access control ARM7TDMI memory map. also used control Flash SRAM remapping functions.
2.1.12. Interrupt Controller interrupt controller incorporates hardware prioritization interrupt sources. This reduces load processor when dealing with interrupts. interrupts maskable also triggered software.
2.1.5. Power Management Unit Power Management Unit (PMU) provides full control devices power modes, including 'operating', 'idle', 'stand-by', 'off' modes.
2.1.13. Real Time Clock 2.1.6. 12-Mbit/s Function Core compliant function allows communication with host-PC. Included built-in transceiver cell ensuring that minimal external components required. real time clock provides accurate reporting time (hours, minutes seconds) calendar functions (day week, date month, month, year, century). also alarm function (month, date, hour, minute second resolution). real time clock only available where application package permit. 2.1.7. General-Purpose I/Os General Purpose (GPIO) pins used under software control. Many these pins implement shared functionality reduce count device.
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303xA
Timers Watchdog Timer Real Time Clock Power Management Unit ARM7TDMI processor associated structures configured little endian operation.
2.2. ARM7TDMI Processor AHB/APB Buses Programmable Universal Controller 303xA contains embedded ARM7TDMI processor, which operates maximum frequency MHz. Advanced High-Speed (AHB) connects following peripherals ARM7TDMI processor: Flash memory SRAM (Universal Serial Bus) core. Advanced Peripheral (APB) connects following peripherals AHB/APB bridge: UARTs SSPs GPIO Interrupt Controller Table 2-1: List ARM7TDMI Processor Address Space
Base Address (Boot) 0000.0000hex 0008.0000hex 0010.0000hex 0012.0000hex 001A.0000hex 001B.0000hex 001C.0000hex 001C.4000hex 001C.8000hex 001C.C000hex 001D.0000hex 001D.4000hex 001D.8000hex 001D.C000hex 001E.0000hex 001E.4000hex 001E.8000hex 001E.C000hex 001F.0000hex Base Address (Remapped) 0008.0000hex 0000.0000hex 0012.0000hex 001A.0000hex 001B.0000hex 001C.0000hex 001C.4000hex 001C.8000hex 001C.C000hex 001D.0000hex 001D.4000hex 001D.8000hex 001D.C000hex 001E.0000hex 001E.4000hex 001E.8000hex 001E.C000hex 001F.0000hex
2.2.1. Memory Table states base addresses memory mapped Flash, SRAM, peripherals. detailed register offsets, relative base addresses, refer functional descriptions specific components. memory dynamically changed remapping SRAM Flash memory areas. Details this operation found Memory Protection description (see Section 2.5.4. page 21).
Comment Embedded Flash (256KBytes) base address Embedded SRAM (48KBytes) base address base address base address (Test Port Controller) base address Programmable Interrupt Controller base address UART base address UART base address General Purpose base address Serial interface base address (SSP1) Serial interface base address (SSP2) Serial interface base address (SSP3) Serial interface base address (SSP4) Serial interface base address (SSP5, I2S) Timers/Counters base address Watchdog Timer base address Real Time Clock base address Power Management Unit base address
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2.3. Clock Generation 303xA implements powerful flexible clocking scheme order provide maximum flexibility power management provide suitable clocks integrated peripherals. features clock generation scheme oscillator clock inputs, either allowing direct connection crystal oscillator circuit clock source. Software-selectable Phase Locked Loop (PLL) device main system oscillator clock generation logic. Programmable dividers, allowing dynamic, glitch-free configuration wide range system clock frequencies. Automatic relock timing when powered when divider values changed.
Individually programmable clock dividers, dedicated clocks, providing dynamic glitch-free frequency changing. Individually programmable clock enables clocks stop them their phases. Maskable wake-up condition selection. Real Time Clock oscillator, with programmable enable. Real Time Clock support, generating clock from Real Time Clock oscillator clock frequency ranging from 32768 8.372224 MHz. features clock generation controlled means addressable registers Power Management Unit. Fig. shows major blocks clock generation logic.
Programmable Values
Programmable Values
PLLCLK
Clock Divider
System Oscillator Circuit
OSCCLK
PCLK_RTC_INT
System clocks CLKOUT HCLK PCLK_PMU PCLK_WDOG PCLK_APB USB48CLK USB12CLK SSP1-5CLK UART1-2CLK Programmable Enables
PLL_FOUT
Clock Enable Control
enable
Relock Counter
Control
Power Mode Wake-up
Wake-up Control Stand-by Control
PCLK_RTC
Oscillator Circuit
OSCRTCCLK
Divide 16384
Divide
RTCCLK
Programmable Enable
Programmable Divisor
Fig. 2-1: Clock Generation Functional Block Diagram
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clock enable divider blocks used provide control over individual clocks design. Each major clocks enabled disabled, frequency controlled means separate programmable dividers. these options controlled through registers (see Section 2.7.1. page 26). real time clock oscillator into divider circuit, consisting fixed divide 16384 programmable divide 511. programmable element this divider allows oscillator input frequencies range 32.768 8.372224 MHz, still generate required clock, RTCCLK, used Real Time Clock. power mode wake-up control block used interpret information from registers, then place clock generator appropriate power state. Please refer section this data sheet (Section 2.7.1. page details power modes. Table summarizes clocks used generated within 303xA.
303xA provides crystal oscillator circuits, main system operation real time clock standby operation. Both these pads enable either direct clock input crystal connected. main system oscillator subsequent circuitry used generate most required clocks normal operation 303xA. clock dividers sourced from either oscillator clock input, OSCCLK, from output internal PLL, PLL_FOUT. This selection controlled modifying VCO_BYPASS PMU_CLK_EN register (see Section 2.7.1. page 26). output dynamically controlled changing programmable dividers PMU_VCO_DIV register Power Management Unit (PMU, Section 2.3.2. page details update these dividers). control relock counter blocks clock generator ensure safe handling divider changes, allowing output settle before using
Table 2-2: Clocks Clock OSCCLK OSCRTCCLK PLL_FOUT PLLCLK CLKOUT HCLK PCLK_PMU PCLK_WDOG PCLK_RTC _INT
Description Main reference oscillator clock from oscillator clock from Output from Multiplexed clock from OSCCLK PLL_FOUT (i.e bypass PLL) 303xA output, used clock external device (e.g. MASF). Interface ARM7TDMI system clock system clock dedicated Power Management Unit Registers system clock dedicated watchdog Clock generator version Real Time Clock system clock.
Sources input clock input clock output from PLL_FOUT OSCCLK PLLCLK OSCCLK PLLCLK PLLCLK PLLCLK PLLCLK
Divider Range section
Frequency Range 32768 8.372224 801) 1281) MHz1)
shares common divider with HCLK shares common divider with HCLK shares common divider with HCLK
theoretical limit overridden physical constraints
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Table 2-2: Clocks, continued Clock PCLK_APB PCLK_RTC Description system clock (used other peripherals) system clock dedicated Real Time Clock. Generated multiplexing PCLK_RTC_INT (for operating state) OSCRTCCLK (for standby state) sampling clock clock Sampling clock Sampling clock Sampling clock Sampling clock Optional sampling clock This selectable between divided PLLCLK SSP5CLK_IN input. Sampling clock supplied from external device (e.g. MASF) Sampling clock UART Sampling clock UART Count enable Real Time Clock (only used enable PCLK_RTC) Sources PLLCLK PCLK_RTC_INT OSCRTCCLK
Divider Range
Frequency Range
shares common divider with HCLK
USB48CLK USB12CLK SSP1CLK SSP2CLK SSP3CLK SSP4CLK SSP5CLK
PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK PLLCLK SSP5CLK_IN GPIO PLLCLK PLLCLK OSCRTCCLK
MHz2) MHz2)
shares common divider with SSP1CLK shares common divider with SSP1CLK shares common divider with SSP1CLK shares common divider with SSP1CLK MHz1) MHz1)
SSP5CLK_IN UART1CLK UART2CLK RTCCLK
shares common divider with UART1CLK 32768 4194304
theoretical limit overridden physical constraints nominal values dividers PLLCLK=96 also upper limit values
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2.3.1. Clock Utilization Summary Table summarizes utilization clocks module-by-module basis. Table 2-3: Clock Utilization Module JTAG Port ARM7TDMI processor Interface Memory Protection Unit kByte SRAM Interface kByte Flash Interface Interface core Bridge UARTs SSPs GPIO Watchdog Real Time Clock Timer Counters Interrupt Controller Power Management Unit Clock Generator
Clocks Used Within Module TCLK HCLK HCLK HCLK HCLK HCLK, USB12CLK USB48CLK, USB12CLK PCLK_APB PCLK_APB, UART*CLK PCLK_APB, SSP*CLK PCLK_APB PCLK_WDOG PCLK_RTC, RTCCLK1) PCLK_APB PCLK_APB PCLK_PMU OSCCLK, OSCRTCCLK, PLLCLK
RTCCLK used clock registers rather waveform that sampled PCLK_RTC
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303xA
2.3.2. Phase-Locked Loop Device 303xA incorporates embedded Phase Locked Loop (PLL) device, which selected provide source system clocks. configured under software control, providing extraordinarily wide range available frequencies power-down capability. following features available: maximum output frequency MHz. minimum output frequency MHz. Wide input clock frequency range 6-28 MHz. jitter. power consumption power down mode. Software selectable divider values input feedback dividers. Automatic re-lock waiting, where system clocks disabled until output stable. Fig. shows simplified diagram structure PLL. frequency relationship between output frequency source frequency shown equation below.
example, 96-MHz output frequency clock required, from 13-MHz crystal, dividers chosen could Therefore, divider values programmed into PMU_VCO_DIV would (5Ehex) (0Bhex). value register should 005E.000Bhex. Note, that divider values NF=192 NR=26 could have been chosen achieve same frequency relationship, however narrower loop bandwidth (larger divider value) increases output jitter. This lower comparison frequency PFD. Therefore recommended always choose smallest values equivalent divider sets. Range from from Range from from Warning: very high flexibility on-chip clock selection, special care must taken overclock 303xA chip regions chip. division factors clock dividers must proper values, otherwise unpredictable operation damage result (refer Table page details clock constraints).
PLL_FOUT PLL_FIN -NR'
division factors programmable through Power Management Unit PMU_VCO_DIV Register. actual value programmed needs less than required value.
Input Divider
Phase Detector
NR[4:0]
Feedback Divider
NF[8:0]
Fig. 2-2: Simplified Structure
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waveform diagram reset sequence, Fig. this data sheet. Table summarizes these resets asserted depending source reset. internal 303xA signals n_reset, wakeup_rst, soft_rst n_wd_rst, trigger signals four reset sequences, activated follows (refer Section 2.7.1. page information about setting registers): n_reset: 'Reset' input 303xA pulled power-up warm reset. wakeup_rst: conditioned "wake-up" input 303xA, causing wake-up reset from standby state appropriate mask PMU_WAKE_MASK register set. soft_rst: Software induced reset caused writing PMU_RESET register. n_wd_rst: Watchdog Timeout induced reset trigger from watchdog module, described Section 2.6.7. page 101.
2.4. Power-on Resets reset scheme implemented ensure seamless integration with various Micronas audio devices (e.g. 35xxF family). There four main reasons 303xA reset, each which initiates unique reset sequence. four reset circumstances Reset pulled power-on warm reset Wake-up from standby state Software induced reset Watchdog time-out induced reset ensure correct timings reset sequence, there three counters within reset controller. Fig. shows full power-on reset sequence, illustrating three counters. timing this sequence relies counting fixed number oscillator clock edges hence will vary depending oscillator frequency. times shown based system oscillator clock frequency. first counter, OSC_COUNT, enabled whilst main system oscillator clock settling. completion CLKOUT clock enabled. This counter only used during power-on wake-up reset. second counter, EXT_COUNT, ensures sufficient time external Micronas audio device's DC/DC converters supply sufficient power power rest 303xA. this point system clocks enabled within 303xA. Again this counter only used during power-on wake-up reset. third counter, SYS_COUNT, used keep ARM7TDMI processor other peripherals reset, whilst security state machine Flash interface decides security state device (see Section 2.5.2. page 20).
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power supply voltages N_RESET OSCCLK OSC_COUNT CLKOUT EXT_COUNT system clocks (e.g HCLK) SYS_COUNT N_SYSRST 1.14 0x20 0x400 0xE1000
Fig. 2-3: Power-on reset sequence (timing values 28-MHz system oscillator frequency)
Table 2-4: Resets Source Reset nRESET Wake-up Reset Software Reset Watchdog Reset X=not reset source reset reset reset Security Flash Control reset reset Watchdog reset reset Real Time Clock reset Rest Chip reset reset reset reset
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2.5. Peripherals 2.5.1. Flash Memory 2.5.1.1. Flash Memory
0x00060000
Flash Configuration Registers
0x000403FF
INFORMATION AREA kByte)
0x00040000
303xA contains kBytes embedded Flash memory, which split into sections: kByte BOOT area, boot code, kByte USER area, application code, There also kByte INFORMATION area, storing device specific production information, such serial number. These areas illustrated Fig. 2-4. Flash Memory organized rows words width bits, that each contains Bytes. BOOT USER areas, adjacent rows form page 2048 Bytes, whereas INFO area consists single page rows 1024 Bytes. page organization relevant Flash Page Erase cycles. Flash accessed through three separate interfaces: from ARM7TDMI processor, through JTAG port with ARM7TDMI processor debug state, through dedicated parallel flash programming test mode (Parallel using GPIO pins (intended fast mass production programming testing) JTAG parallel interfaces enabled disabled, depending security status device (see Section 2.5.2. page 20). three interfaces have different access rights flash memory. Table summarizes access permissions. rest this section describes accesses from ARM7TDMI processor only, unless otherwise stated. Table 2-5: Access Permissions Interface BOOT Area Read BOOT Area Write USER Area Read USER Area Write INFO Area Read INFO Area Write BOOT Area Page Erase USER Area Page Erase INFO Area Page Erase ARM7TDMI processor BLOCKED unlocked JTAG BLOCKED BLOCKED unlocked JTAG BLOCKED JTAG Parallel
0x00006000
USER AREA (232 kByte)
BOOT AREA kByte)
0x00000000
Fig. 2-4: Flash Memory
BLOCKED
BLOCKED
OK=Access region permitted BLOCKED=Access blocked Security Controller
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2.5.1.2. Flash Configuration Registers
Table 2-6: Flash Configuration Register Flash configuration registers located after INFORMATION (INFO) area Flash offset 0006.0000hex from Flash area base. memory flash configuration registers shown Table 2-6. These fully described Table 2-7. addresses given offset addresses relative Flash configuration register base 0006.0000hex. Example: Writing CONFIG_REG register independent state remap done writing address 80000hex 60000hex 00014hex E0014hex.
Offset 00hex 04hex 08hex 0Chex 10hex 14hex Width Name WAIT_STATE PERF_COUNT BOOT_PROT ADDRESS_REG DATA_REG CONFIG_REG Reset 03hex 0Fhex 00000hex 00000000
00hex
Table 2-7: Flash Configuration Registers Register Address
00hex
Function
WAIT_STATE Register
Field 31:2 Reserved WAIT_VAL
Name
WAIT_STATE
bit[31:2] bit[1:0]
Reserved WAIT_VAL Number added Wait States during Read cycle. (refer Table 2-8) PERF_COUNT
31:6 Reserved PF_COUNT_ PF_COUNT_VAL
04hex
PERF_COUNT Register
Field
bit[31:6] bit[5]
Reserved PF_COUNT_EN When this set, Flash performance counter enabled. between consecutive read accesses Flash long enough allow count expire, embedded Flash device will enter standby state. With this disabled ('0') controller will never enter standby mode, delivering most efficient times terms access speed. PF_COUNT_VAL These bits correspond number cycles after last read access Flash memory will enter standby mode. PF_COUNT_EN must enable value PF_COUNT_VAL. Example: 01111bin 15dec HCLK timeout cycles.
bit[4:0]
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Table 2-7: Flash Configuration Registers, continued Register Address
08hex
Function
BOOT_PROT Register
Field 31:16 Reserved 15:0 BOOT_WR_KEY
Name
BOOT_PROT
bit[31:16] bit[15:0]
Reserved BOOT_WR_KEY BOOT Flash area write enable key. value ABCDhex must written JTAG port, e.g. using debugger, enable further programme/erase accesses BOOT area Flash. Once written, 'ARM7TDMIprocessor'-mode will have full access permissions, allow dedicated embedded software routines programme/erase BOOT area. ADDRESS_REG
17:8 XADR_VAL (row) YADR_VAL (column) Byte address
0Chex
ADDRESS_REG Register
Field
bit[17:8]
XADR_VAL (row) Flash address when SW_SELECT CONFIG_REG) enabled YADR_VAL (column) Flash address when SW_SELECT CONFIG_REG) enabled Byte address These bits ignored. recommended write them '0'. DATA_REG
31:0 DIN_VAL
bit[7:2]
bit[1:0]
10hex
DATA_REG Register
Field
bit[31:0]
DIN_VAL Data Flash data when SW_SELECT enabled
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Table 2-7: Flash Configuration Registers, continued Register Address
14hex
Function
CONFIG_REG Register
Field 31:8 Reserved XE_VAL
Name
CONFIG_REG
WRITE_ PROG_ SELECT PROTECT
ERASE_ Reserved NVSTR_ YE_VAL
Note: DATA_REG ADDRESS_REG with correct information before using this register. bit[31:8] bit[7] bit[6] Reserved SW_SELECT When set, this enables programme erase mode. WRITE_PROTECT This write only when will prevent SW_SELECT from being set. This prevents writes erases flash, until power-on wake reset. PROG_VAL value this register output PROG line Flash when SW_SELECT set. ERASE_VAL value this register output ERASE line Flash when SW_SELECT set. Reserved NVSTR_VAL value this register output NVSTR line Flash when SW_SELECT set. YE_VAL value this register output line Flash when SW_SELECT set. XE_VAL value this register output line Flash when SW_SELECT set.
bit[5]
bit[4]
bit[3] bit[2]
bit[1]
bit[0]
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2.5.1.5. Flash Programming Erasing Writes Erases software controlled through following three Flash configuration registers: ADDRESS_REG: Stores address Flash location programmed. DATA_REG: Stores data programmed into Flash location. CONFIG_REG: Enables direct control control strobes Flash device. set, then corresponding signal forced high Flash, reset then signal low. perform programming cycle flash, following sequence should performed: address flash required written should programmed into ADDRESS_REG. data written should programmed into DATA_REG. CONFIG_REG should then programmed number times order select required sequence control strobes Flash. example typical programming cycle shown Fig. 3-13 page 127. timing symbols parameters defined Table page 127. addition, example typical erase cycle shown Fig. 3-14 page 128. Since required programming times Flash programming cycle order milliseconds, 303xA's internal timers should used correctly time programming sequence.
2.5.1.3. Flash Features following list describes features embedded Flash 303xA device: Separate Software Control Flash Programming (see Section 2.5.1.5.) Hardware security mechanism boot code (see Section 2.5.1.5.) Byte, Halfword Word addressable reads Programmable wait states, permit three wait states inserted during read access. BOOT area write protection disable register, that accessible only through JTAG ports. This allows ARM7TDMI processor program BOOT area Flash.
2.5.1.4. Programmable Wait States required number wait states read accesses Flash depends following: system clock frequency (HCLK) Flash device already standby mode address (XADDR) Flash device changed from previous access last dependencies true, least required after HCLK before read data stable sampled. both false then only access time required. Flash Controller detect read access read read will always less wait state than specified Table into read accesses. value programmed into WAIT_STATE register specifies number wait states reads should always value shown Table 2-8.
Table 2-8: Wait States programmed WAIT_STATE register System Clock Frequency (MHz) >16.6 16.6 Programmed Wait State Value
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303xA
2.5.2. Security Application Code security downloaded application code ensured disabling external interfaces from directly reading stored code Flash. Flash contains readable memory location called Protection Control Register, PCR, located offset address 0001.8000hex. Contents this location will indicate whether Parallel Flash interface, JTAG interface, Test Peripheral Controller interface device operating secure non-secure mode: Secure mode used inhibit accesses Flash from these interfaces, order ensure that application code cannot read. default state device non-secure. Once sensitive application code loaded, programmed either JTAG Parallel Flash interface, enable security. During power wake-up reset, secure mode selected interfaces. During reset Security Controller will read protection control register determine whether non-secure mode then selected. Since ARM7TDMI boot from embedded Flash, this decision made before ARM7TDMI comes reset. This decision will remain fixed until main system reset input cycled again, wake-up from STANDBY state occurs. bits protection control register defined Table 2-9. Table 2-9: Protection Control Register Bits Function JTAG Enable Test Peripheral Controller Enable Parallel Flash Interface Enable 2.5.3. SRAM 2.5.3.1. Features
kByte embedded SRAM accessible with zero wait states sequential accesses AHB. Non-sequential accesses require extra cycle. kBytes embedded SRAM shared between ARM7TDMI processor core Byte-, Halfword-, Word-addressable kByte SRAM buffer store last 32-bit data read. This reduce power consumption, especially THUMB mode Interfaces through (the ARM7TDMI processor JTAG) kByte SRAM remapped address 0hex (see Section 2.5.4.)
2.5.3.2. General Overview 303xA supports kByte memory directly bus. Additional kByte SRAM accessible through interface. Accesses this memory will incur additional wait states. Please refer Section 2.5.5. page details interface. rest this section only applies main kBytes SRAM. buffer SRAM interface stores last data read from SRAM device. Power consumption reduced releasing data ARM7TDMI processor from this internal buffer rather than actually reading SRAM whenever possible. This particularly beneficial when ARM7TDMI processor running THUMB mode instructions only bits wide. Therefore, location SRAM actually holds instructions serviced with only read SRAM.
security protection control register shall under supervision boot software, means unique access key.
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303xA
2.5.4.1. SRAM Remapping REMAP MPUREMAP register defines location SRAM within ARM7TDMI processor's memory map. When (default) Flash based 0008.0000hex mirrored 0000.0000hex, 48KB SRAM located 0010.0000hex. When this SRAM relocated from 0010.0000hex 0000.0000hex. Address space above remapped SRAM that previously occupied mirrored Flash becomes unused causes abort accessed.
2.5.4. Memory Protection Unit Memory Protection Unit (MPU) provides following functionality: manages memory protection within ARM7TDMI core's memory map, controls remapping SRAM ARM7TDMI processor base address. peripheral. Access peripherals including controlled address decoder, dependent upon enable outputs from MPU. consists user-definable segments, each consisting start address MPUSTRTn, address MPUENDn, read enable MPURDEN[n] write enable MPUWREN[n]. start addresses compared with bits through most significant bits used 303xA architecture. current address continually compared against segment address pairs. access address detected (inclusively) within segment's start values then permission ARM7TDMI processor perform current access will granted using state segment's read write enable bits. logic function this mechanism segment shown Fig. 2-5. only active when ARM7TDMI processor USER mode, protection effect other processor operating modes. default values registers dictate that programmed before USER mode entered, otherwise memory accesses will result Data Abort interrupt. Thereafter, also programmed USER mode long, register locations protected.
2.5.4.2. Address Space Table 2-10 page shows registers within MPU. Addresses address offsets, relative base address 001A.0000hex.
segments 1-15 read_en mpurden[0] mpustrt0[10:0] haddr[20:10] mpuend0[10:0] A<=B<=C
mpuwren[0] segments 1-15
write_en
Fig. 2-5: Memory Protection Logic Function
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Table 2-10: Register Offset 000hex Width Name MPUREMAP Comment Reserved REMAP (R/W)
Default 0hex
mirrors Flash ARM7TDMI processor base address remaps SRAM ARM7TDMI processor base address 004hex 008hex 00Chex 010hex 014hex 018hex 01Chex 020hex 024hex 028hex 02Chex 030hex 034hex 038hex 03Chex 040hex 044hex 048hex MPURDEN MPUWREN MPUSEG0 MPUSEG1 MPUSEG2 MPUSEG3 MPUSEG4 MPUSEG5 MPUSEG6 MPUSEG7 MPUSEG8 MPUSEG9 MPUSEG10 MPUSEG11 MPUSEG12 MPUSEG13 MPUSEG14 MPUSEG15 Bits through active high read enables segments through respectively. Bits through active high write enables segments through respectively Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment Start address segment 0000hex 0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex 000.0000hex
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Table 2-11: Registers Register Address
000hex 048hex
Function MPUSEGx Register
Field 31:27 Reserved 26:16 MPUEND[10:0] 15:11 Reserved 10:0 MPUSTRT[10:0]
Name MPUSEGx
This register stores most significant bits Start address MPUSTRTx most significant bits address MPUENDx user-definable memory segment Both, MPUEND[10:0] MPUSTRT[10:0] compared continually with most significant bits [20:10] address bus, thus implying resolution kByte smallest segment quantity that permitted access USER mode. bit[31:27] bit[26:16] bit[15:11] bit[10:0] Reserved MPUEND[10:0] Reserved MPUSTRT[10:0]
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2.5.5. Interface 3030A1) device incorporates specification compliant slave interface with following features: specification 1.1/1.0 compliant, with built transceiver cell. Full speed slave interface with Mbit/s rate. kByte dedicated SRAM. hardware provides following points: EP0: dedicated. software-programmable. programmed with bulk endpoints, interrupt, isochronous endpoints. Suspend mode, which used control 3030A power management. Embedded controller, dedicated housekeeping. Interface with allows access whole address space core from ARM7TDMI processor processor, including SRAM. Three optimized access types from ARM7TDMI processor, including pipelined read free processor other tasks. Application code download embedded controller software from embedded Flash SRAM. architecture core illustrated Fig. 2-6.
core comprises following blocks: Embedded controller: Used control update endpoint registers general housekeeping SRAM. serial interface (SIE): transaction handling transfer data SRAM. kBytes SRAM: Used primarily storing endpoint registers, data buffers application code embedded controller. SRAM also used scratchpad ARM7TDMI processor interface being used (scratchpad functionality also available 3033A). arbiter: arbitration between masters: SIE, embedded controller Test/USB interface. Master: port allow external source (either Test interface) direct control addressable location. master slave devices, used under control embedded controller (functionality also available 3033A). ARM7TDMI processor access region memory within core space, including SRAM. However because clock domain differences between buses, accesses from ARM7TDMI processor take several cycles, hold processor with wait states. exact quantity cycles taken depends relationship between HCLK USB12CLK, traffic load embedded controller bus. allow ARM7TDMI processor complete other system tasks during this time, core memory repeated four times ARM7TDMI processor memory map. Each copy performs different type access core shown Table 2-12 (yyyy address offset within core).
SRAM
Embedded Controller
Arbiter
Transceiver
Master
Interface Embedded Controller
Fig. 2-6: Function Core Functional Diagram
3033A device, interface available, SRAM blocks functional.
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Table 2-12: Core Access Address 0012.yyyyhex Description Initiate byte, half word read write, wait completion. this mode ARM7TDMI processor will held with wait states, until access completed. First pipeline read. Initiates byte, half word read, does wait completion. this mode ARM7TDMI processor immediately released, unless interface busy with previous access. Data read this access invalid. This enables data immediately available next time ARM7TDMI processor performs read. Initiate byte, half word write. this mode ARM7TDMI processor immediately released, unless interface busy with previous access. Pipelined read. Initiates byte, half word read, waits previously requested data. this mode read data supplied will previously addressed data. this successive reads requested, that ARM7TDMI processor free handle data between accesses USB. Initiate byte, half word write. this mode ARM7TDMI processor immediately released, unless interface busy with previous access. Reserved test purposes
0014.yyyyhex
0016.yyyyhex
0018.yyyyhex
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April 2002; 6251-565-1PD
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2.6. Peripherals 303xA device incorporates numerous commonly used peripherals which make device very flexible ideally match demands Micronas' MASF devices. These peripherals accessible ARM7TDMI processor core through AMBA Advanced Peripheral (APB) described following sections.
2.6.1.1.3. STANDBY State This state only valid applications with device packages where Real Time Clock (RTC) available. STANDBY state, clocks both disabled, with exception clocks. further power efficiency, main oscillator also powered down when device STANDBY state. device re-enters OPERATING state when either alarm, plug, suspend, valid wake-up condition detected.
2.6.1. Power Management Unit Power Management Unit used control various power states device.
2.6.1.1. Power States device supports following power-related states: OPERATING State IDLE State STANDBY State Real Time Clock available) State unavailable) Fig. illustrates these states reached.
OPERATING OPERATING clock
2.6.1.1.4. State state, clocks disabled only restarted following power-on warm reset nRESET pin. state only valid available with application device package.
2.6.1.1.1. OPERATING State OPERATING state, peripherals active, depending clocks enabled Power Management Unit. Within OPERATING state, enabled turned off/bypassed.
bypass PMU_CLKS_EN
Reset bypass PMU_CLKS_EN
Power up/Reset
OPERATING main oscillator clock
Write PMU_STANDBY available
Write PMU_IDLE Interrupt Write PMU_STANDBY available
n_reset asserted
available)
IDLE
unmasked wake-up condition detected
2.6.1.1.2. IDLE State
STANDBY available)
IDLE state, clock ARM7TDMI processor watchdog timer clock disabled, while peripherals remain active. device will return OPERATING state interrupt generated from peripherals. will operate OPERATING state.
Fig. 2-7: Power Management Unit: Power States
state GPIO pins preserved during OFF/ STANDBY. This allows optimization power consumption with respect external components pull-up/-down resistors). contents SRAM also preserved during OFF/STANDBY long, device's power supplies remain
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2.6.1.2. Power Management Register Descriptions power management unit peripheral APB, thus will enable software configuration states shown register Table 2-13. Addresses shown offset addresses from base address 001F.0000hex. more detailed descriptions these registers, Table 2-14. Table 2-13: Power Management Register Offset 00hex 04hex 08hex 0Chex 10hex 14hex 18hex 1Chex 20hex 24hex 28hex 2Chex 30hex
Name PMU_VCO_DIV PMU_VCO_DIV_UP PMU_HCLK_DIV PMU_CLKOUT_DIV PMU_UARTCLK_DIV PMU_SSPCLK_DIV PMU_RTCCLK_DIV PMU_USBCLKS_DIV PMU_CLKS_EN PMU_IDLE PMU_STANDBY PMU_RESET PMU_WAKE_SEL
Access
Bits 24:0 31:16 29:0 31:0 31:0 31:0
Description Dividers used (use with PMU_VCO_DIV_UP) Update register dividers Divider used HCLK/PCLK generation Divider used CLKOUT generation Divider used UARTCLK generation (UART 1-2) Divider used SSPCLK generation (SSP 1-5) Divider used RTCCLK generation Divider used USB48CLK USB12CLK generation Enables each controllable clock domain Forces device into IDLE state Forces device into STANDBY state Forces software reset Selects which events cause wake-up
Default 05E.000Bhex 04hex 11hex 3Fhex 3Fhex 002hex 1hex 013F.3711hex unknown1) 0hex
depends type last reset
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Table 2-14: Power Management Unit Registers
Register Address 00hex Function PMU_VCO_DIV Register, Reset 005E.000Bhex
Field 31:25 Reserved 24:16 NF[8:0] 15:5 Reserved NR[4:0]
Name PMU_VCO_DIV
This register stores values used Feedback divider (NF[8:0]) Input divider (NR[4:0]) (note that programmed values need less than their corresponding integer values quotient that realized PLL). When write performed PMU_VCO_DIV_UP register, clock generator stops clocks system phase, before presenting divider values from PMU_VCO_DIV PLL. required settling time then waited, before clocks restarted. this register have effect system, PMU_VCO_DIV_UP register must written with correct key. bit[31:25] bit[24:16] bit[15:5] bit[4:0] 04hex Reserved NF[8:0], feedback divider value Reserved NR[4:0], input divider value PMU_VCO_DIV_UP
15:0 Reserved
PMU_VCO_DIV_UP Register, Reset
Field 31:16 Update
This register must written with correct key, order value PMU_VCO_DIV register have affect system operation. register requires bits [31:16] write data. bit[31:16] 4321
Update This half word must 4321hex force system dividers. Reserved PMU_HCLK_DIV
HCLK_DIV
bit[15:0] 08hex
PMU_HCLK_DIV Register, Reset 0000.0004hex
Field 31:6 Reserved
This register stores divider used within clock generator, dividing multiplexed output clock produce system clock, HCLK. divider also used PCLK_PMU, PCLK_WDOG, PCLK_APB, PCLK_RTC. value this register will stop HCLK. bit[31:16] bit[5:0] 2hex 63hex Reserved HCLK_DIV system clock divider, range
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Table 2-14: Power Management Unit Registers, continued
Register Address 0Chex Function PMU_CLKOUT_DIV Register, Reset 0000.0011hex
Field 31:5 Reserved MF_SEL MASF_DIV
Name PMU_CLKOUT_DIV
This register stores divider used within clock generator, dividing selected clock produce CLKOUT output clock. source clock this division selectable between reference oscillator clock OSCLK multiplexed output clock PLLCLK. value MASF_DIV will stop CLKOUT. bit[31:5] bit[4] Reserved MF_SEL Selects source CLKOUT divider Always main oscillator clock (OSCCLK) multiplexed output clock (PLLCLK) bit[3:0] 01hex 0Fhex MASF_DIV CLKOUT divider, range 1-15dec PMU_UARTCLK_DIV
UART_DIV
10hex
PMU_UARTCLK_DIV Register, Reset 0000.003Fhex
Field 31:6 Reserved
This register stores divider used within clock generator, dividing multiplexed output clock produce dedicated UART clocks, UART1CLK UART2CLK. value will stop UART clocks. following constraints must programmer proper UART operation: UART_DIV HCLK_DIV F_UART(x)CLK 15.0 bit[31:6] bit[5:0] 2hex 63hex Reserved UART_DIV UART clock divider, range 2-63
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Table 2-14: Power Management Unit Registers, continued
Register Address 14hex Function PMU_SSPCLK_DIV Register, Reset 0000.003Fhex
Field 31:6 Reserved
Name PMU_SSPCLK_DIV
SSP_DIV
This register stores divider used within clock generator, dividing multiplexed output clock produce dedicated clocks, SSP1CLK, SSP2CLK, SSP3CLK, SSP4CLK, SSP5CLK. Note that SSP5CLK selected derived from external source, this divider does affect clock used value will stop clocks. following constraints must programmer proper operation: SSP_DIV HCLK_DIV bit[31:6] bit[5:0] 2hex 63hex Reserved SSP_DIV clock divider, range 2-63 PMU_RTCCLK_DIV
RTC_DIV
18hex
PMU_RTCCLK_DIV Register, Reset 0000.0002hex
Field 31:9 Reserved
This register stores divider used within clock generator, dividing oscillator clock input produce required Real Time Clock counter clock, RTCCLK. divider circuit consists fixed 16384 divider programmable divider range 511. This allows required generated from range clock inputs from 32768 8.372224 MHz, increments 16384 value will stop clock. bit[31:9] bit[8:0] 2hex 511hex Reserved RTC_DIV clock divider, range 2-511
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Table 2-14: Power Management Unit Registers, continued
Register Address 1Chex Function PMU_USBCLK_DIV Register, Reset 0000.0001hex
Field 31:1 Reserved USBCLK_
Name PMU_USBCLK_DIV
When this register USB48CLK frequency obtained dividing PLLCLK USB12CLK frequency obtained dividing PLLCLK this configuration nominal operation (when PLLCLK MHz) access core's SRAM PLLCLK frequencies less than equal MHz. When this register USB48CLK frequency obtained dividing PLLCLK USB12CLK frequency obtained dividing PLLCLK this configuration access core's SRAM PLLCLK frequencies above MHz. This register useful when operation needed SRAM should stay accessible system clocks above (PLLCLK above MHz) without violating timing constraints SRAM. bit[31:1] bit[0] Reserved USBCLK_DIV clock divider
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Table 2-14: Power Management Unit Registers, continued
Register Address 20hex Function PMU_CLKS_EN Register, Reset 013F.3711hex
Field 31:30 Reserved 27:25 Reserved CLKOUT 23:22 Reserved
Name PMU_CLKS_EN
OSCRTC RTCCLK CLK_EN
SSP5 SSP4 SSP3 SSP2 SSP1 CLK_EN CLK_EN CLK_EN CLK_EN CLK_EN CLK_EN
Field
15:14 Reserved
Reserved
HCLK
Reserved
VCO_BY PASS
UART2 UART1 Reserved PCLK PCLKW PCLK CLK_EN CLK_EN RTC_EN DOG_EN APB_EN
Enables each controllable clock domain.
bit[31:30] bit[29] bit[28]
Reserved OSCRTCCLK_EN oscillator disabled. RTCCLK_EN generated 1-Hz clock enable disabled. Reserved CLKOUT_EN generated CLKOUT output clock disabled. Reserved USBCLK_EN dedicated clocks (USB12CLK USB48CLK) disabled. SSP5CLK_EN dedicated clock disabled (unless external source). SSP4CLK_EN dedicated clock disabled. SSP3CLK_EN dedicated clock disabled. SSP2CLK_EN dedicated clock disabled. SSP1CLK_EN dedicated clock disabled. Reserved UART2CLK_EN dedicated clock UART disabled. UART1CLK_EN dedicated clock UART disabled. Reserved
bit[27:25] bit[24] bit[23:22] bit[21]
bit[20]
bit[19] bit[18] bit[17] bit[16] bit[15:14] bit[13] bit[12] bit[11]
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Table 2-14: Power Management Unit Registers, continued
Register Address 20hex
(con'd)
Function bit[10] PCLKRTC_EN system clock disabled. controls clock PCLKWDOG_EN system clock watchdog disabled. PCLKAPB_EN system clock disabled peripherals which have dedicated PCLK clocks. Reserved HCLK_EN system clock disabled. Reserved VCO_BYPASS high, powered down bypassed that OSCCLK feeds multiplexer output clock, PLLCLK. low, PLLCLK will generated clock, PLL_FOUT.
Name PMU_CLKS_EN
bit[9] bit[8]
bit[7:5] bit[4] bit[3:1] bit[0]
24hex
PMU_IDLE Register, Reset
Field 31:16 IDLE_KEY 15:0 Reserved
PMU_IDLE
write this register will force state 303xA change from OPERATING mode into IDLE mode. This will immediately disable both HCLK PCLK_WDOG clocks. These will enabled again when edge output NIRQ NFIQ interrupt lines ARM7TDMI core interrupt controller. There delay most cycles writing IDLE register clock being stopped. this reason recommended that least instructions placed directly after IDLE register write. ARM7TDMI processor execution will initially carry from where left when interrupt received, then jump interrupt handler. register requires bits [31:16] write data. bit[31:16] FEDC
IDLE_KEY This half word must FEDChex force system into IDLE state. Reserved
bit[15:0]
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Table 2-14: Power Management Unit Registers, continued
Register Address 28hex Function PMU_STANDBY Register, Reset
Field 31:16 STANDBY_KEY 15:0 Reserved
Name PMU_STANDBY
write this register, with correct key, will force state 303xA change from OPERATING state into STANDBY state, depending whether oscillator active. oscillator inactive, either unavailable, 81-pin package, enabled, state will entered. Otherwise STANDBY state shall entered. either states clocks system, that associated with Real Time Clock, will stopped their phases. Clocks associated with Real Time Clock (OSCRTCCLK, RTCCLK PCLK_RTC) will remain active inactive. clock RTC, PCLK_RTC, will then OSCRTCCLK, instead being derived from multiplexed output clock. leave state power-on warm reset (low reset pin) required. This will return system OPERATING state driven main oscillator clock (PLL bypassed). leave STANDBY state, either power-on warm reset used, unmasked wake-up condition (see PMU_WAKE_SEL register) required. these valid events will result wake-up reset sequence, device will return OPERATING state using main oscillator clock (PLL bypassed). ARM7TDMI processor execution will always begin reset vector 0hex after exiting STANDBY states. bit[31:16] CDEF
STANDBY_KEY This half word must CDEFhex force system into STANDBY state. Reserved
bit[15:0]
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Table 2-14: Power Management Unit Registers, continued
Register Address 2Chex Function PMU_RESET Register, Reset value: unknown, depends source reset
Field 31:16 SOFTRESET_KEY 15:3 Reserved
Name PMU_RESET
WD_RST POWER SOFT_ ON_RST
This register should read after reset sequence, find reason reset. read status bits cleared. write this register used force software reset from system reset controller. bit[31:16] ABCD
SOFTRESET_KEY This field must ABCDhex allow write register. Access: Reserved WD_RST This read only latest reset detected watchdog reset. read access register this cleared. Access: indicates watchdog reset occurred, clears watchdog reset since last read
bit[15:3] bit[2]
bit[1]
POWERON_RST This read only latest reset detected power-on warm reset. read access register this cleared. Access: indicates power-on warm reset occurred, clears power-on warm reset since last read
bit[0]
SOFT_RST Writing this forces software reset only previously After software reset, this read indicate that software reset performed. must cleared reading register, before another software reset performed. Access: indicates software reset occurred, clears software reset since last read forces software reset effect
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Table 2-14: Power Management Unit Registers, continued
Register Address 30hex Function PMU_WAKE_SEL Register, Reset 0000.0000hex
Field 31:4 Reserved
Name PMU_WAKE_SEL
USB_ USB_ RTC_ WAKE_ SENSE
This register used select which sources will generate valid wake-up condition, force 303xA from STANDBY state back into OPERATING state. These sources only valid oscillator clock input OSCRTCCLK active. sources logically ORed form wake-up condition. bit[31:4] bit[3] 01hex Reserved USB_SENSE high, rising edge sense input detected wake-up. USB_SUP high, falling edge suspend mode detected wake-up. RTC_INT high, rising edge interrupt detected wake-up. WAKE_PIN high, rising edge wake-pin input detected wake-up.
bit[2]
01hex
bit[1]
01hex
bit[0]
01hex
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Table 2-15: Interrupt List Interrupt number Interrupt index 26-32 Function Realtime clock interrupt WATCHDOG interrupt Timer interrupt Timer interrupt Timer interrupt interrupt interrupt (SSP interrupt interrupt interrupt interrupt interrupt UART interrupt UART interrupt ARM7TDMI comms ARM7TDMI comms GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt GPIO interrupt used software interrupts only.
2.6.2. Interrupt Controller Since ARM7TDMI processor core provides only interrupt input lines, interrupt controller used manage various on-chip interrupt sources. interrupt controller been designed optimize performance interrupt handling, reducing latency providing priority nesting interrupts.
2.6.2.1. Features Interrupt Sources IRQ, FIQ) Programmable Selection Source Hardware Priority Encoding Selectable Source Type (Hardware Software) Interrupts Maskable Programmable Interrupt Source Type Edge, Triggered Level-Sensitive.
2.6.2.2. Interrupt List Although there possible interrupts, only directly used hardware. remaining only used triggering interrupt through software. interrupt sources listed Table 2-15. interrupt index column used decode IRQSTATUS indexed interrupt status register, defines value write back IRQCOMPLETE register.
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2.6.2.3. General Overview Interrupt Controller process control interrupt sources. these, style interrupts final, programmable source Fast Interrupt (FIQ). service routine offers considerable time advantage over IRQ, combination reduced software hardware requirements. individual sources require held until relevant service routine complete, although this optional. During service interrupt, also possible store pending interrupt request from source, allowing interrupt pending being serviced. default priority encoding provided order interrupt sources given Interrupt List, Table 2-15. lower interrupt index list, higher called 'secondary' priority. modify this default priority ordering, 303xA allows apply eight levels 'primary' priority each sources programming INTxTYPE registers. Note, however, that these only apply sources will have effect FIQ. case, granted higher hardware priority than anyway. rules priority encoder follows: Every source have priority level between programmed software. highest priority, lowest. reset value priority sources. during particular service routine, interrupt source lower priority enabled, source will stored pending until current source complete. during particular service routine, interrupt source higher priority enabled, line will enabled permit ARM7TDMI processor service interrupt.* Interrupt Controller free interrupt sources enabled simultaneously, interrupt source with higher priority granted. sources have equal primary priority specified INTxTYPE register), interrupt source with lower index Interrupt List, Table 2-15, will granted. Source has, example, higher secondary priority than source programmed source enabled during service routine, line will enabled permit ARM7TDMI processor service interrupt. Interrupt sources programmed high level sensitive; rising falling edge
triggered. This, along with priority software controlled through registers INTxTYPE. There multiplexers source input enable each sources software hardware. reset, these multiplexers connect sources directly hardware interrupts. registers IRQSOURCESEL FIQSOURCESEL implement select signals these multiplexers. registers IRQSWSOURCE FIQSWSOURCE used trigger selected software interrupts. After source selection, resulting sources stored read-only register, IRQRAWSTATUS. Depending status mask register, these used generate IRQPENDING read-only register. This processed detect highest priority request list, result passed through status registers, IRQSTATUS IRQSTATUSALL. This, turn used generate relevant outputs. IRQSTATUS register provides encoded index (see Table 2-15) only highest priority interrupt which generating output. This provides easy method jumping appropriate interrupt handler.
2.6.2.4. Programming Guide ARM7TDMI processor levels external interrupt, IRQ. interrupt taken, disable CPSR must clear. CPSR written beginning program code, using specific instructions enable interrupts `running' mode system. stack pointer that particular mode must also set. ARM7TDMI processor documentation contains further, more detailed, information modes associated operating conditions. FIQs have higher priority than IRQs ways: FIQs serviced first when multiple interrupts occur. Servicing causes IRQs disabled, preventing them from being serviced until after handler re-enabled them. This achieved restoring original CPSR from SPSR_FIQ handler.
nested this way, software must stack save original interrupt position.
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Example 2-1: Instructions, Assembly Code Normal Interrupt response routine holds Interrupt Controller Base Address) IrqHandler ROUT lr,lr,#4 STMFD SP!, {lr} r14, SPSR STMFD SP!, {r0-r2,r14}
higher execution speed, vector last entry vector table, which allows handler placed directly vector location sequentially from that address. This removes need branch associated delays. There also banked working registers within ARM7TDMI mode avoiding need saving large number registers stack. interrupt controller accommodate interrupt sources, which will allocated line. This establishes need specific handler capable interrupt prioritization. problem that after single exception IRQ, CPSR will automatically altered disable further IRQs. core achieves this copying contents CPSR into specific SPSR, this case SPSR_IRQ. When routine finished, core will then automatically copy SPSR back into CPSR, thereby re-enabling IRQ. true priority system should permit sources higher priority interrupt current exception during routine. There specific sequence instructions that must take place order ensure that priority encoding handled correctly. Briefly, this exception takes place. Program branches handler from main code. Save link address (R14) stack. Current SPSR (the CPSR will have been automatically copied SPSR when exception took place) store stack. Note that interrupts currently DISABLED. Determine source interrupt: read status Interrupt Controller. line automatically cleared reading status registers. This allows higher priority interrupts generate IRQ. read-modify-write CPSR ENABLE interrupts. Perform specific Interrupt Routine. Read-modify-write CPSR DISABLE interrupts. Write index interrupt handled IRQ_COMPLETE register Interrupt Controller, inform that interrupt been serviced. Restore SPSR from stack. Jump back main program. During step pending interrupts higher priority will break current service attend interrupt (see Example 2-1).
Store return address
Push registers stack Read status ;integer format ;this also clears down ;the line
r1,[r7,#IRQSTATUS]
read-modify-write CPSR enable interrupts CPSR CPSR #0x80 Clear CPSR_c, Write back enable Interrupt
Perform particular routine (Source stored Switch state register used with C-routines.
Read-Modify-Write CPSR disable interrupts CPSR CPSR #0x80 CPSR_c, Write back disable Interrupt
Interrupt r1,[r7,#IRQ_COMP]
Write back index interrupt just handled registers from stack Return address stored
LDMFD SP!, {r0-r2,r14} SPSR, LDMFD SP!, {pc}^
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2.6.2.5. Interrupt Controller Register Definitions Interrupt Controller programmed through ARM7TDMI processor interface. Addresses offsets interrupt controller base address, 001C.0000hex. registers fully described Table 2-17. Table 2-16: Interrupt Controller Register Offset 00hex 04hex 08hex 0Chex 10hex 14hex 18hex 1Chex 20hex 24hex 28hex 2Chex 30hex 34hex 38hex 3Chex 40hex 44hex 48hex 4Chex 50hex 54hex 58hex 5Chex 60hex Width Name IRQRAWSTATUS IRQPENDING IRQSTATUS IRQSTATUSALL IRQMASKSET IRQMASKCLEAR IRQMASK FIQRAWSTATUS FIQSTATUS FIQMASKSET FIQMASKCLEAR FIQMASK FIQSOURCESEL IRQSOURCESEL FIQSWSOURCE IRQSWSOURCE INT0TYPE INT1TYPE INT2TYPE INT3TYPE INT4TYPE INT5TYPE INT6TYPE INT7TYPE INT8TYPE
Default 0000.0000hex 0000.0000hex 0000.0000hex 0000.0000hex FFFF.FFFFhex 0000.0000hex 0000.0000hex 1hex 00hex 0000.0000hex 0hex 0000.0000hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex
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Table 2-16: Interrupt Controller Register Map, continued Offset 64hex 68hex 6Chex 70hex 74hex 78hex 7Chex 80hex 84hex 88hex 8Chex 90hex 94hex 98hex 9Chex A0hex A4hex A8hex AChex B0hex B4hex B8hex BChex C0hex C4hex Width Name INT9TYPE INT10TYPE INT11TYPE INT12TYPE INT13TYPE INT14TYPE INT15TYPE INT16TYPE INT17TYPE INT18TYPE INT19TYPE INT20TYPE INT21TYPE INT22TYPE INT23TYPE INT24TYPE INT25TYPE INT26TYPE INT27TYPE INT28TYPE INT29TYPE INT30TYPE INT31TYPE IRQCOMPLETE FIQCOMPLETE Default 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex 02hex
Important: Ensure that Interrupt Controllers sources MASKED before type registers altered. Disregarding this lead undefined results.
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Table 2-17: Interrupt Controller Read/Write Registers
Register Address 00hex Function IRQRAWSTATUS Register, Reset 0000.0000hex
Field 31:0 Valid Sources
Name IRQRAWSTATUS
Each interrupt source validated according current interrupt type (see INT*TYPE registers) corresponding applicable. bit[31:0] 04hex Valid Sources IRQPENDING
IRQPENDING Register, Reset 0000.0000hex
Field 31:0 Unmasked Valid Sources
Registered logical 'AND' IRQRAWSTATUS IRQMASK registers. bit[31:0] 08hex Unmasked Valid Sources IRQSTATUS
Current Service Status
IRQSTATUS Register, Reset 0000.0000hex
Field 31:6 Reserved
This register states index which source currently being serviced. Reading this status register will clear down line between interrupt controller ARM7TDMI allow other higher priority interrupts generate IRQ. bit[31:6] bit[5:0] 20hex Reserved Current Service Status (index between 32dec)
0Chex
IRQSTATUSALL Register, Reset 0000.0000hex
Field 31:0 Currently Serviced Interrupts
IRQSTATUSALL
This register shows interrupts that either being serviced have been halted following arrival exception higher priority. Reading this status register will clear down line between interrupt controller ARM7TDMI allow other higher priority interrupt generate IRQ. bit[31:0] Currently Serviced Interrupts
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303xA
Table 2-17: Interrupt Controller Read/Write Registers, continued
Register Address 10hex Function IRQMASKSET Register, Reset
Field 31:0 Mask Bits (disable interrupts)
Name IRQMASKSET
bits interrupt mask disable corresponding interrupts. mask IRQMASK register effect. bit[31:0] 14hex Mask Bits (disable interrupts) IRQMASKCLEAR
31:0 Clear Mask Bits (enable interrupts)
IRQMASKCLEAR Register, Reset
Field
Clear bits IRQMASK register enable corresponding interrupts Clear mask bit. effect. bit[31:0] 18hex Clear Mask Bits (enable interrupts) IRQMASK
31:0 Mask Value
IRQMASK Register, Reset FFFF.FFFFhex
Field
Read only register current value interrupt mask. setting clearing IRQMASK register achieved using IRQMASKSET IRQMASKCLEAR registers, respectively. bit[31:0] 1Chex Mask Value (interrupts disabled setting corresponding bit) FIQRAWSTATUS
Valid Source
FIQRAWSTATUS Register, Reset 0000.0000hex
Field 31:1 Reserved
source validated according current type (see INT*TYPE register). bit[31:1] bit[0] Reserved Valid Source: Set, when source been validated
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-17: Interrupt Controller Read/Write Registers, continued
Register Address 20hex Function FIQSTATUS Register, Reset 0000.0000hex
Field 31:1 Reserved
Name FIQSTATUS
Valid Source
This register states whether interrupt currently being serviced. Reading this register clears down line between interrupt controller ARM7TDMI. bit[31:1] bit[0] 24hex Reserved Valid Source FIQMASKSET
31:1 Reserved FIQMask Bits
FIQMASKSET Register, Reset
Field
write FIQMASKSET register sets bit[0] FIQMASK register. bit[31:1] bit[0] 28hex Reserved FIQMASK[0]: recommended write this FIQMASKCLEAR
31:1 Reserved Clear FIQMASK Bits
FIQMASKCLEAR Register, Reset
Field
write FIQMASKCLEAR register clears bit[0] FIQMASK register.
bit[31:1] bit[0] 2Chex
Reserved Clear FIQMask Bit[0] FIQMASK
31:1 Reserved FIQMASK Value
FIQMASK Register, Reset 1hex
Field
Read-only register current value interrupt mask. setting clearing FIQMASK register achieved using FIQMASKSET FIQMASKCLEAR registers, respectively. bit[31:1] bit[0] Reserved Mask Value (FIQ interrupt disabled setting corresponding bit)
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-17: Interrupt Controller Read/Write Registers, continued
Register Address 30hex Function FIQSOURCESEL Register, Reset 00hex
Field 31:6 Reserved Source Select SW/HW Select
Name FIQSOURCESEL
Hardware/software interrupt source select FIQ. bit[31:6] bit[5:1] 1Fhex Reserved Source Select 5-bit number determine interrupt source (number between 31dec) SW/HW Select '1': Source software-driven. '0': Source hardware-driven. 34hex
bit[0]
IRQSOURCESEL Register, Reset 0000.0000hex
Field 31:0 SW/HW Select
IRQSOURCESEL
Hardware/software interrupt source select IRQ. bit[31:0] SW/HW Select `1': source software-driven. `0': source hardware-driven. 38hex FIQSWSOURCE Register, Reset 0hex
Field 31:1 Reserved interrupt source
FIQSWSOURCE
selected FIQSOURCESEL, write 1hex this register acts softwaredriven interrupt source. bit[31:1] bit[0] 3Chex Reserved software interrupt source: Must written cause software interrupt. IRQSWSOURCE
IRQSWSOURCE Register, Reset 0000.0000hex
Field 31:0 software interrupt source
corresponding IRQSOURCESEL, write this register software interrupt source. example: IRQSOURCESEL then setting IRQSWSOURCE will generate Timer interrupt. bit[31:0] software interrupt source
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-17: Interrupt Controller Read/Write Registers, continued
Register Address 40hex BChex Function INT*TYPE Register, Reset 02hex
Field 31:7 Reserved PRIORITY Reserved
Name INT*TYPE
TYPE
bit[31:7] bit[6:4] 000bin 111bin bit[3:2] bit[1:0] 00bin 11bin
Reserved PRIORITY Priority level interrupt, between lowest, highest). Reserved TYPE Type interrupt: High Level Detection Level Detection Rising Edge Detection Falling Edge Detection
Recommended programming TYPE field INTxTYPE registers various on-chip interrupt sources: Function (Int Source) Realtime clock Watchdog Timers USB-SIE SSP5 SSP1, Interrupt Index Recommended TYPE field setting INTxTYPE registers High Level High Level High Level Rising Edge Rising Edge High Level High Level High Level High Level High Level1) don't care
UART1, comms GPIOa, Software interrupts
Note,
13,14 15,16 17.25 26.32
that this recommendation independent interrupt sensitivity type that selected GPIO (see INT_TYPE INT_VALUE INT_ON_ANY registers Section 2.6.8.4. page 106.)
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-17: Interrupt Controller Read/Write Registers, continued
Register Address C0hex Function IRQCOMPLETE Register, Reset
Field 31:6 Reserved Complete Interrupt
Name IRQCOMPLETE
Write-back interrupt index, inform interrupt controller that service complete. each interrupt successfully handled, corresponding index that interrupt, specified Table 2-15 page read from IRQSTATUS, should written back this register enable pending interrupts lower priority serviced next. bit[31:6] bit[5:0] 20hex Reserved Complete Interrupt: Index between 32dec previously read from IRQSTATUS register. FIQCOMPLETE
31:1 Reserved Service Complete
C4hex
FIQCOMPLETE Register, Reset
Field
write this register will inform interrupt controller that service complete. bit[31:1] bit[0] Reserved Service Complete: recommended write this
Micronas
April 2002; 6251-565-1PD
303xA
2.6.3. UARTs independently configurable UART interfaces provided. Since UART interfaces' pins configured standard GPIO pins after reset, pins required application must configured 'Bypass Mode' GPIO module (refer Section 2.6.8.3. page 106).
2.6.3.2. UART Functions main functional blocks each 303xA's UARTs shown Fig. 2-8.
Transmit FIFO
Transmitter
Transmit Signals
2.6.3.1. Features Offers similar functionality industry standard 16C550 UART. Supports rates 115.2 Kbits/second. Separate transmit receive FIFO, each bytes, with maskable level interrupts. FIFOs disabled. Programmable baud rate generator
SIGNALS
Interface register module
Receive FIFO
Receive
Receive Signals
Control Signals FIFO Status Interrupt Generation
Interrupts status
Programmable data size, even parity, stop size. Automatic handling start, stop parity bits. False start detection. Line break generation detection Full support modem handshaking signals Includes IrDA interface, supporting data rates 115.2 Kbits/second half duplex, with power mode. 2.6.3.2.1. AMBA Interface AMBA interface generates read write decodes access status control registers, transmit receive FIFO memories. Register Block stores data written, read across AMBA interface. Fig. 2-8: UART Block Diagram
April 2002; 6251-565-1PD
Micronas
303xA
2.6.3.2.7. Interrupt Generation Logic UART generates interrupt maskable interrupt conditions active.
2.6.3.2.2. Baud Rate Generator baud rate generator incorporates free-running counters that generate internal clocks, Baud16, IrLPBaud16 signal. Baud furnishes timing information UART transmit receive control. Baud16 comprises stream pulses with width UARTCLK clock period, frequency times baud rate. IrLPBaud16 source timing information that used generate pulse width IrDA encoded transmit stream, when low-power mode.
2.6.3.2.8. IrDA Interface IrDA interface forms integral part both UART modules. IrDA multiplexed with standard UART receive transmit lines (see Fig. 2-9). selection multiplexing under control additional register mapped UART address space shown Table 2-18.
2.6.3.2.3. Transmit FIFO transmit receive paths buffered with internal FIFO's, enabling bytes stored both receive transmit data paths. data written across interface stored FIFO until read transmit logic. transmit FIFO disabled behave one-byte holding register.
UART TXDx nSIROUT
2.6.3.2.4. Receive FIFO Receive FIFO 12-bit wide (4-bit flags 8-bit data), 16-word depth FIFO memory buffer. receive logic stores received data, corresponding error bits, receive FIFO until reads across interface. receive FIFO disabled behave like one-byte holding register.
SIRIN RXDx
2.6.3.2.5. Transmit Logic Fig. 2-9: IrDA UART Selection transmit logic performs parallel-to-serial conversion data read from transmit FIFO. Control logic outputs serial stream beginning with start bit, data bits (least significant (LSB) first) followed parity bit, then stop bits. precise content serial stream depends upon programme configuration control registers.
2.6.3.2.6. Receive Logic receive logic performs serial-to-parallel conversion received stream after valid start pulse been detected. Overrun, parity, frame error checking, line break detection also performed: data with associated overrun, parity, framing, break error bits written receive FIFO.
Micronas
April 2002; 6251-565-1PD
303xA
2.6.3.3. UART Register locations brief descriptions UART registers given Table 2-18. Addresses shown relative UART base addresses. UART located base address 001C.4000hex UART located 001C.8000hex
Table 2-18: UART Register Map1)
Address Offset 00hex 04hex 08hex 14hex 18hex 1Chex 20hex 24hex 28hex 2Chex 30hex 34hex 38hex 3Chex 40hex 44hex 48hex FChex 00hex
Type
Width 12/8
Reset Value -hex 0hex -10010-bin 00hex 0000hex 00hex 00hex 0300hex 12hex 000hex 00-hex 00-hex 01hex
Name UARTDR UARTRSR/ UARTECR UARTFR UARTILPR UARTIBRD UARTFBRD UARTLCR_H UARTCR UARTIFLS UARTIMSC UARTRIS UARTMIS UARTICR UARTMuxSel
Description Data read written from interface. bits wide read, write. Receive status register (read)/ Error clear register (write) Reserved Flag register (read only) Reserved IrDA low-power counter register Integer baud rate divider register Reserved, must written Line control register, HIGH byte Control register Interrupt FIFO level select register Interrupt mask set/clear interrupt status Masked interrupt status Interrupt clear register Reserved IrDA/UART selection register
undefined digits after reset
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers
Register Address 00hex Function UARTDR Register, Reset -hex
Field 15:12 Reserved DATA
Name UARTDR
Data read written from interface. bits wide read, bits wide write. bit[15:12] bit[11] Reserved Overrun Error (OE) This data received receive FIFO already full. This cleared once there empty space FIFO character written Break Error (BE) This break condition detected, indicating that received data input held longer than full-word transmission time (defined start, data, parity stop bits). FIFO mode, this error associated with character FIFO. When break occurs, only character loaded into FIFO. next character only enabled after receive data input goes (marking state), next valid start received. Parity Error (PE) When this indicates that parity received data character does match parity selected defined bits UARTLCR_H register. FIFO mode, this error associated with character FIFO. Framing Error (FE) When this indicates that received character have valid stop valid stop FIFO mode, this error associated with character FIFO. DATA Receive (read) data character Transmit (write) character
bit[10]
bit[9]
bit[8]
bit[7:0]
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 04hex Function Combined UARTRSR/UARTECR Register, Reset 0hex
Field Reserved
Name UARTRSR UARTECR
Receive status register (read) Error clear register (write). write this register clears framing-, parity-, break-, overrun errors. data value important. bit[7:4] Reserved, unpredictable when read.
bit[3]
Overrun Error (OE) This data received FIFO already full. Break Error (BE) This break condition detected, indicating that received data input held longer than full-word transmission time (defined start, data, parity, stop bits). Parity Error (PE) When this indicates that parity received data character does match parity selected defined bits UARTLCR_H register. Framing Error (FE) When this indicates that received character have valid stop valid stop This cleared write UARTECR.
bit[2]
bit[1]
bit[0]
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 18hex Function UARTFR Register, Reset -10010-bin
Field 15:9 Reserved
Name UARTFR
TXFE RXFF TXFF RXFE BUSY
Flag register (read only). bit[15:9] bit[8] Reserved Ring Indicator (RI) This complement UART ring indicator (nRIx) modem status input. when modem status input Transmit FIFO Empty (TXFE) meaning this depends state UARTLCR_H register. FIFO disabled, this when transmit holding register empty. FIFO enabled, this when transmit FIFO empty. Receive FIFO Full (RXFF) meaning this depends state UARTLCR_H register. FIFO disabled, this when receive holding register full. FIFO enabled, this when receive FIFO full. Transmit FIFO Full (TXFF) meaning this depends state UARTLCR_H register. FIFO disabled, this when transmit holding register full. FIFO enabled, this when transmit FIFO full. Receive FIFO Empty (RXFE) meaning this depends state UARTLCR_H register. FIFO disabled, this when receive holding register empty. FIFO enabled, this when receive FIFO empty. UART Busy (BUSY) this UART busy transmitting data. This remains until complete byte, including stop bits, been sent from shift register. This soon transmit FIFO becomes non-empty, whether UART enabled not. Data Carrier Detect (DCD) This complement UART data carrier detect (nDCDx) modem status input. when modem status input Data Ready (DSR) UART data ready (nDSRx) modem status input. when modem status input Clear Send (CTS) UART clear send (nCTSx) modem status input. when modem status input
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 20hex Function UARTILPR Register, Reset 00hex
Field ILPDVSR
Name UARTILPR
IrDA low-power counter register. IrLPBaud16 signal generated dividing down UARTCLK signal according low-power divider value written UARTILPR. low-power divider value calculated follows: low-power divider (ILPDVSR) (FUARTCLK FIrLPBaud16) where FIrLPBaud16 nominally 1.8432MHz. Choose divider that 1.42MHz FIrLPBaud16 2.12MHz, that results lowpower pulse duration 1.41-2.11µs (three times period IrLPBaud16). minimum frequency IrLPBaud16 ensures that pulses less than period IrLPBaud16 rejected, that pulses greater than 1.4µs accepted valid pulses. Note, that programming zero value results IrLPBaud16 pulses being generated. bit[7:0] 00hex FFhex ILPDVSR 8-bit low-power divider value. These bits cleared reset. UARTIBRD
24hex
UARTIBRD Integer Baud Rate Register, Reset 0000hex
Field 15:0 BAUD DIVINT
Integer baud rate divider register. Section 2.6.3.3.1. page Section 2.6.3.3.2. page details. bit[15:0] 01hex FFFF
BAUD DIVINT Integer baud rate divider value. These bits cleared reset.
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 2Chex Function UARTLCR_H Register, Reset 00hex
Field 15:8 Reserved WLEN STP2
Name UARTLCR_H
Line control register, HIGH byte. Section 2.6.3.3.2. page details. bit[15:9] bit[7] Reserved Stick Parity Select (SPS) When bits UARTLCR_H register set, parity transmitted checked When bits set, parity transmitted checked When this cleared stick parity disabled. 11hex 10hex 01hex 00hex Word length [1:0] (WLEN) select bits indicate number data bits transmitted received frame follows: bits bits bits bits. Enable FIFOs (FEN) this transmit receive FIFO buffers enabled (FIFO mode). When cleared FIFOs disabled (character mode) that FIFOs become 1-bytedeep holding registers. Stop Bits Select (STP2) this stop bits transmitted frame. receive logic does check stop bits being received. Even Parity Select (EPS) this even parity generation checking performed during transmission reception, which checks even number data parity bits. When cleared then parity performed which checks number This effect when parity disabled Parity Enable (bit being cleared Parity Enable (PEN) this parity checking generation enabled, else parity disabled parity added data frame. Send Break (BRK) this low-level continually output TXDx output, after completing transmission current character. This must asserted least complete frame transmission time order generate break condition. transmit FIFO contents remain unaffected during break condition. normal use, this must cleared
bit[6:5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 30hex Function UARTCR Register, Reset 0300hex
Name UARTCR
Field CTSEn RTSEn ReReRTS served served
Reserved
SIRLP SIREN UART
UARTCR register control register. bits cleared reset, except bits which table below shows assignment UARTCR register bit[15] Hardware Flow Control Enable (CTSEn) this hardware flow control enabled. Data only transmitted when nCTSx signal asserted. Hardware Flow Control Enable (RTSEn) this hardware flow control enabled. Data only requested when there space receive FIFO received. Reserved Reserved Request Send (RTS) This complement UART request send (nRTSx) modem status output. That when programmed output Data Transmit Ready (DTR) This complement UART data transmit ready (nDTRx) modem status output. That when programmed output Receive Enable (RXE) this receive section UART enabled. Data reception occurs either UART signals signals according setting Enable (bit When UART disabled middle reception, completes current character before stopping. Transmit Enable (TXE) this transmit section UART enabled. Data transmission occurs either UART signals, signals according setting Enable (bit When UART disabled middle transmission, completes current character before stopping.
bit[14]
bit[13] bit[12] bit[11]
bit[10]
bit[9]
bit[8]
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 30hex
(con'd)
Function bit[7] Loop Back Enable (LBE) this Enable test register UARTTCR (SIRTEST) then nSIROUT path inverted, through SIRIN path. SIRTEST test register must override normal half-duplex operation. This must requirement accessing test registers during normal operation, SIRTEST must cleared when loopback testing finished.This feature reduces amount external coupling required during system test. this SIRTEST TXDx path through RXDx path. either mode normal mode, when this set, modem outputs also through modem inputs. This cleared reset, which disables loop-back mode. bit[6:3] bit[2] Reserved IrDA Power Mode (SIRLP) This selects IrDA encoding mode. this cleared low-level bits transmitted active high pulse with width 3/16th period. this low-level bits transmitted with pulse width which times period IrLPBaud16 input signal, regardless selected rate. Setting this uses less power, might reduce transmission distances. Enable (SIREN) this IrDA ENDEC enabled. This effect UART enabled being When IrDA ENDEC enabled, data transmitted received nSIROUT SIRIN. TXDx remains marking state (set Signal transitions RXDx modem status inputs have effect. When IrDA ENDEC disabled, nSIROUT remains cleared light pulse generated), signal transitions SIRIN have effect bit[0] UART Enable (UARTEN) this UART enabled. Data transmission reception occurs either UART signals signals according setting Enable (bit When UART disabled middle transmission reception, completes current character before stopping.
Name UARTCR
bit[1]
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 34hex Function UARTIFLS Register, Reset 12hex
Field 15:6 Reserved RXIFLSEL
Name UARTIFLS
TXIFLSEL
UARTIFLS register interrupt FIFO level select register. UARTIFLS register used define FIFO level which UARTTXINTR UARTRXINTR triggered. interrupts generated based transition through level rather than being based level. That design such that interrupts generated when fill level progresses through trigger level. bits reset that trigger level when FIFOs half-way mark. bit[15:6] bit[5:3] 000bin 001bin 010bin 011bin 100bin Reserved RXIFLSEL Receive Interrupt FIFO Level Select (RXIFLSEL) trigger points receive interrupt follows: Receive FIFO becomes full Receive FIFO becomes full Receive FIFO becomes full Receive FIFO becomes full Receive FIFO becomes full 101:111 reserved. bit[2:0] 000bin 001bin 010bin 011bin 100bin TXIFLSEL Transmit Interrupt FIFO Level Select (TXIFLSEL) trigger points transmit interrupt follows: Transmit FIFO becomes full Transmit FIFO becomes full Transmit FIFO becomes full Transmit FIFO becomes full Transmit FIFO becomes full 101:111 reserved.
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 38hex Function UARTIMSC Register, Reset 000hex
Field 15:11 Reserved
Name UARTIMSC
OEIM BEIM PEIM FEIM RTIM TXIM RXIM DSRMI DCD- CTSMI RIMIM
UARTIMSC register interrupt mask set/clear register. read/write register. read this register gives current value mask relevant interrupt. write particular bit, sets corresponding mask that interrupt. write clears corresponding mask. bits cleared when reset. bit[15:11] bit[10] Reserved Overrun Error Interrupt Mask (OEIM) read, current mask OEIM interrupt returned. write mask OEIM interrupt set. write clears mask. Break Error Interrupt Mask (BEIM) read current mask BEIM interrupt returned. write mask BEIM interrupt set. write clears mask. Parity Error Interrupt Mask (PEIM) read current mask PEIM interrupt returned. write mask PEIM interrupt set. write clears mask. Framing Error Interrupt Mask (FEIM) read current mask FEIM interrupt returned. write mask FEIM interrupt set. write clears mask. Receive Timeout Interrupt Mask (RTIM) read current mask RTIM interrupt returned. write mask RTIM interrupt set. write clears mask. Transmit Interrupt Mask (TXIM) read current mask TXIM interrupt returned. write mask TXIM interrupt set. write clears mask. Receive Interrupt Mask (RXIM) read current mask RXIM interrupt returned. write mask RXIM interrupt set. write clears mask. nDSRx Modem Interrupt Mask (DSRMIM) read current mask DSRMIM interrupt returned. write mask DSRMIM interrupt set. write clears mask.
bit[9]
bit[8]
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 38hex
(con'd)
Function bit[2] nDCDx Modem Interrupt Mask (DCDMIM) read current mask DCDMIM interrupt returned. write mask DCDMIM interrupt set. write clears mask. nCTSx Modem Interrupt Mask (CTSMIM) read current mask CTSMIM interrupt returned. write mask CTSMIM interrupt set. write clears mask. nRIx Modem Interrupt Mask (RIMIM) read current mask RIMIM interrupt returned. write mask RIMIM interrupt set. write clears mask.
Name UARTIMSC
bit[1]
bit[0]
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 3Chex Function UARTRIS Register, Reset 000hex
Field 15:11 Reserved
Name UARTRIS
OERIS BERIS PERIS FERIS RTRIS TXRIS RXRIS RMIS RMIS RMIS
UARTRIS register interrupt status register. read-only register. read this register gives current status value corresponding interrupt. write effect. bits, cleared when reset, except modem status interrupt bits, modem status interrupt bits undefined after reset. bit[15:11] bit[10] Reserved Overrun Error Interrupt Status (OERIS) Gives interrupt state (prior masking) UARTOEINTR interrupt Break Error Interrupt Status (BERIS) Gives interrupt state (prior masking) UARTBEINTR interrupt Parity Error Interrupt Status (PERIS) Gives interrupt state (prior masking) UARTPEINTR interrupt Framing Error Interrupt Status (FERIS) Gives interrupt state (prior masking) UARTFEINTR interrupt Receive Timeout Interrupt Status (RTRIS) Gives interrupt state (prior masking) UARTRTINTR interrupt. this case, interrupt cannot unless mask set, this because mask acts enable power saving. That same status read from UARTMIS UARTRIS receive timeout interrupt. Transmit Interrupt Status (TXRIS) Gives interrupt state (prior masking) UARTTXINTR interrupt Receive Interrupt Status (RXRIS) Gives interrupt state (prior masking) UARTRXINTR interrupt nDSRx Modem Interrupt Status (DSRRMIS) Gives interrupt state (prior masking) UARTDSRINTR interrupt nDCDx Modem Interrupt Status (DCDRMIS) Gives interrupt state (prior masking) UARTDCDINTR interrupt nCTSx Modem Interrupt Status (CTSRMIS) Gives interrupt state (prior masking) UARTCTSINTR interrupt nRIx Modem Interrupt Status (RIRMIS) Gives interrupt state (prior masking) UARTRIINTR interrupt
bit[9]
bit[8]
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 40hex Function UARTMIS Register, Reset 00-hex
Field 15:11 Reserved
Name UARTMIS
OEMIS BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS MMIS MMIS MMIS
UARTMIS register masked interrupt status register. read-only register. read this register gives current masked status value corresponding interrupt. write effect. bits cleared when reset, except modem status interrupt bits modem status interrupt bits undefined after reset. bit[15:11] bit[10] Reserved Overrun Error Masked Interrupt Status (OEMIS) Gives masked interrupt state (after masking) UARTOEINTR interrupt Break Error Masked Interrupt Status (BEMIS) Gives masked interrupt state (after masking) UARTBEINTR interrupt Parity Error Masked Interrupt Status (PEMIS) Gives masked interrupt state (after masking) UARTPEINTR interrupt Framing Error Masked Interrupt Status (FEMIS) Gives masked interrupt state (after masking) UARTFEINTR interrupt Receive Timeout Masked Interrupt Status (RTMIS) Gives masked interrupt state (after masking) UARTRTINTR interrupt Transmit Masked Interrupt Status (TXMIS) Gives masked interrupt state (after masking) UARTTXINTR interrupt Receive Masked Interrupt Status (RXMIS) Gives masked interrupt state (after masking) UARTRXINTR interrupt nDSRx Modem Masked Interrupt Status (DSRMMIS) Gives masked interrupt state (after masking) UARTDSRINTR interrupt nDCDx Modem Masked Interrupt Status (DCDMMIS) Gives masked interrupt state (after masking) UARTDCDINTR interrupt nCTSx Modem Masked Interrupt Status (CTSMMIS) Gives masked interrupt state (after masking) UARTCTSINTR interrupt nRIx Modem Masked Interrupt Status (RIMMIS) Gives masked interrupt state (after masking) UARTRIINTR interrupt
bit[9]
bit[8]
bit[7]
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-19: UART Read/Write Registers, continued
Register Address 44hex Function UARTICR Register, Reset
Field 15:11 Reserved FEIC RTIC
Name UARTICR
OEIC BEIC PEIC
TXIC RXIC
Interrupt clear register bit[15:11] bit[10] bit[9] bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2] bit[1] bit[0] 00hex Reserved Overrun Error Interrupt Clear (OEIC) Clears UARTOEINTR interrupt Break Error Interrupt Clear (BEIC) Clears UARTBEINTR interrupt Parity Error Interrupt Clear (PEIC) Clears UARTPEINTR interrupt Framing Error Interrupt Clear (FEIC) Clears UARTFEINTR interrupt Receive Timeout Interrupt Clear (RTIC) Clears UARTRTINTR interrupt Transmit Interrupt Clear (TXIC) Clears UARTTXINTR interrupt Receive Interrupt Clear (RXIC) Clears UARTRXINTR interrupt nDSRx Modem Interrupt Clear (DSRMIC) Clears UARTDSRINTR interrupt nDCDx Modem Interrupt Clear (DCDMIC) Clears UARTDCDINTR interrupt nCTSx Modem Interrupt Clear (CTSMIC) Clears UARTCTSINTR interrupt nRIx Modem Interrupt Clear Status (RIMIC) Clears UARTRIINTR interrupt UARTMuxSel
15:1 Reserved
UARTMuxSel Register, Reset 01hex
Field
IrDA/UART selection register bit[15:1] bit[0] Reserved Multiplexer Select (MS) value selects UART, value selects IrDA
Micronas
April 2002; 6251-565-1PD
303xA
2.6.3.3.1. UARTIBRD Register baud rate divider calculated follows: Baud rate divider BAUDDIV (FUARTCLK/ Baud rate}) where FUARTCLK UART reference clock frequency. value BAUDDIV typically rounded nearest integer value (BAUD DIVINT) then programmed into UARTIBRD register. content UARTIBRD updated until transmission reception current character complete. minimum divide ratio possible maximum 65535 (216 That UARTIBRD invalid when this case. Table 2-20 shows some typical rates their corresponding dividers, given UART clock frequency 7.3728 MHz.
Table 2-20: Typical Baud Rates Dividers f_UARTCLK=7.3728
Programmed Integer Divider 4hex 6hex 8hex Chex 18hex 20hex 30hex C0hex 180hex 105Dhex Rate (bps) 115200 76800 57600 38400 19200 14400 9600 2400 1200
2.6.3.3.2. UARTLCR_H UARTIBRD UARTLCR_H UARTIBRD form single register (UARTLCR) which updated single write strobe generated UARTLCR_H write. order internally update contents UARTIBRD, UARTLCR_H write must always performed end. update UARTIBRD only together with UARTLCR_H: write UARTIBRD then write UARTLCR_H. Table 2-21 truth table SPS, EPS, bits UARTLCR_H register. contents UARTLCR_H register updated until transmission reception current character complete.
Table 2-21: Truth Table UARTLCR_H Register
Parity Enable (PEN) Even Parity Select (EPS) Stick Parity Select (SPS) Parity (transmitted checked) transmitted checked Even parity parity
April 2002; 6251-565-1PD
Micronas
303xA
version SSP(x)CLK. master transmit logic reads value from transmit FIFO carries parallel serial conversion serial data frame logic control signals synchronized SCLK(X), then output externally connected slave through stxd(x) sfrm(x) pins respectively. Simultaneously, master receive logic performs serial parallel conversion incoming synchronous srxd(x) data stream, extracting storing values into receive FIFO, subsequent reading through interface. When configured slave, both SCLK(X) sfrm(x) signals provided attached master used time transmission reception sequence. slave transmit logic, under control master clock, will successively read value from transmit FIFO, performs parallel serial conversion, then output serial data stream through slave stxd(x) pin. master receive logic performs serial parallel conversion incoming srxd(x) data stream, extracting storing values into receive FIFO, subsequent reading through interface. Depending operating mode selected, sfrm(x) output operates active HIGH frame synchronization output Texas Instruments synchronous serial interface format active slave select Motorola National Semiconductor Microwire modes.
2.6.4. Synchronous Serial Ports 303xA device provides five independent Synchronous Serial Ports (SSP). Since interfaces' pins configured standard GPIO pins after reset, pins required application must configured 'Bypass Mode' GPIO module (refer Section 2.6.8.3. page 106).
2.6.4.1. Peripheral Operation general structure each five peripheral blocks available 303xA shown Fig. 2-10.
2.6.4.1.1. Interface Signals transmit receive signals consist following signals: SCLK(x), serial clock SFRM(x), serial data framing signal STXD(x), serial transmit data SRXD(x), serial receive data Note, that interface SSP5 actually interface.
2.6.4.1.2. Transmit Receive Logic When configured master, serial clock connected slave derived from divided
Transmit Signals
SIGNALS
Interface register module
Transmit FIFO Receive FIFO
Transmit Receive Logic
Interface Receive Signals
Clock Prescaler Register Block
Interrupt Generation
Interrupt
Fig. 2-10: General Structure
Micronas
April 2002; 6251-565-1PD
303xA
2.6.4.2. Modes description below applies five SSPs 303xA, where '(x)' signal names between signifying number. five peripherals configured perform both master slave operation five available protocols. Each peripheral comprises core peripheral surrounding sequential logic, termed 'SSP Interface', protocol conversion purposes. core peripheral supports following three primary protocols: Motorola Mode National Semiconductor Microwire Mode Texas Instruments Synchronous Serial Interface Mode addition, secondary protocols supported means interface that 'wraps' core peripheral: Word mode (emulates I2S) Continuous mode more detailed description these secondary modes found Section 2.6.4.4. both, master slave configurations, peripherals perform following: Parallel-to-serial conversion data written internal 16-bit wide, location deep transmit FIFO. Serial-to-parallel conversion received data, buffering similar 16-bit wide, 8-location deep receive FIFO.
SSPs operate with serial clocks MHz, depending whether configured master slave whether data receive only. logical speed constraints summarised below terms derived clocks from clock generator, SSP(x)CLK, (see Section 2.3. page Master duplex with serial clock SSP(x)CLK/2 Slave receive-only with serial clock SSP(x)CLK/3 Slave duplex with serial clock SSP(x)CLK/12
2.6.4.3. Primary Modes When used Texas Instruments SSI, Motorola National Semiconductor Microwire modes, wrapping interface that emulates secondary protocols must configured into 'Transparent' mode. this mode, interface logic feeds relevant signals from core peripheral straight through, allowing direct communication with external device based primary protocols. Transparent mode entered writing relevant bits MODE_SELECT register. DATA_SIZE register does need (see Table 2-22 page 70). primary protocols, peripheral should accordance with instructions contained register programming tables described below.
April 2002; 6251-565-1PD
Micronas
303xA
2.6.4.4.2. Word Mode Word mode converts Texas Instruments Synchronous Serial Interface format 35x9F/ 3587F word mode format. possible activate this mode either master slave modes with unidirectional duplex communication. core peripheral must configured mode. transmitting peripheral, interface circuitry generates word framed protocol that emulates frames with optional 1-bit delay data line. When operating Word mode receiver, interface will translate non-delayed protocol into required mode receiving core peripheral. this mode information must written DATA_SIZE register SSP's interface logic discriminate between data transfers bits transfers either bits, correct framing signal generated. Additionally core peripheral must proper data size SSPCR0 register follows: word width bits, data size core peripheral also configured bits. word width bits, data size core peripheral configured bits. word width bits, data size core peripheral configured bits. word width bits, data size core peripheral configured bits. external master send impulse sfrm(x) length bit-cycle during bit[1] last transferred data word condition. This ignored interface, i.e. this impulse resynchronisation effect.
2.6.4.4. Secondary Modes addition primary protocols, possible configure interfaces support either secondary protocols: Word mode (emulates I2S) Continuous mode These modes have been included ensure seamless interfacing Micronas audio devices (e.g. 35xxF family). facilitate these secondary modes, peripherals provide programmable mode selection data size, specified registers MODE_SELECT DATA_SIZE (see Table 2-22 page 70). MODE_SELECT register allows Word Continous modes selected 'full duplex' 'receive only' SSPs. benefit 'receive only' mode higher available serial clock rate SSP(x)CLK/3 opposed SSP(x)CLK/12, when 303xA acting slave interface. special case SSP5 SSP5CLK source with external clock, such that multiple accurate audio clock (MAS 35x9F/MAS 3587F CLKO) used transmit samples audio streams. This controlled bit[3] MODE_SELECT register.
2.6.4.4.1. Continuous Mode Continuous mode converts Motorola format 35x9F/MAS 3587F continuous format, both master slave modes. core peripheral should configured Motorola mode. This mode writing appropriate value MODE_SELECT register. Master mode will selected corresponding SSPCR1 register been master mode. Continuous mode 303xA support data sizes words, programming DATA_SIZE register. possible activate this mode with either unidirectional duplex communication.
Micronas
April 2002; 6251-565-1PD
303xA
2.6.4.5. Example Communication Waveforms
SCLKx STXDx SFRMx Fig. 2-11: Transmission single frame Word Mode
SCLKx STXDx SFRMx Fig. 2-12: Transmission stream Word Mode with STXDx delayed
SPO=0 SCLKx SPO=1 STXDx SFRMx Fig. 2-13: Transmission single word bits) Motorola Mode with
SPO=0 SCLKx SPO=1 STXDx SFRMx Fig. 2-14: Transmission single word bits) Motorola Mode with
April 2002; 6251-565-1PD
Micronas
303xA
SPO=0 SCLKx SPO=1 STXDx SFRMx(=0) Fig. 2-15: Transmission continuous stream Motorola Mode (SPH
SCLKx STXDx SFRMx Fig. 2-16: Transmission single word bits) Texas Instruments Mode
SCLKx STXDx SFRMx Fig. 2-17: Transmission continuous stream Texas Instruments Mode
SCLKx STXDx SRXDx SFRMx Fig. 2-18: Full duplex communication Texas Instruments Mode
Micronas
April 2002; 6251-565-1PD
303xA
2.6.4.6. Register Descriptions Table 2-22 describes register map. Each five peripherals within 303xA contains same registers. addresses shown offset relative each base address. These follows: 001D.0000hex 001D.4000hex 001D.8000hex 001D.C000hex 001E.0000hex
Table 2-22: Register Offset 00hex 04hex 08hex 0Chex 10hex 14hex 18hex 1Chex Access Width 3/16 Name SSPCR0 SSPCR1 SSPDR SSPSR SSPCPSR SSPIIR/SSPICR MODE_SELECT DATA_SIZE Description Control Register Control Register FIFO (read) FIFO (write) Status Register Clock Prescale Register Interrupt Status Clear Register Mode Select Register Data Size Register Default 00hex 00hex -hex 00hex 00hex 00hex 02hex 00hex
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-23: Read/Write Registers
Register Address 00hex Function SSPCR0 Register, Reset 0000hex
Field 15:8
Name SSPCR0
This register controls various functions within peripheral bit[15:8] 255dec Serial clock rate division factor. value used generate transmit receive rate SSPMS. rate FSSPCLK
CPSDVSR SCR) where CPSDVSR even value from 254, programmed SSPCPSR register value from 255. bit[7] SCLKOUT phase (applicable Motorola frame format only). SCLKOUT polarity (applicable Motorola frame format only). 00bin 11bin Frame format: Motorola frame format synchronous serial frame format National Microwire frame format Reserved, undefined operation bit[3:0] 0000
bit[6]
bit[5:4]
Data Size Select: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved, undefined operation Reserved, undefined operation Reserved, undefined operation 4-bit data 5-bit data 6-bit data 7-bit data 8-bit data 9-bit data 10-bit data 11-bit data 12-bit data 13-bit data 14-bit data 15-bit data 16-bit data.
1111
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-23: Read/Write Registers, continued
Register Address 04hex Function SSPCR1 register, Reset 00hex
Field 31:7 Reserved Reserved
Name SSPCR1
RORIE
This register controls various functions within peripheral bit[31:7] bit[6] bit[5] Reserved, read unpredictable, should written Reserved, must written Master/slave mode select. This modified only when disabled (SSE=0). Device configured master (default). Device configured slave. bit[4] Synchronous serial port enable: operation disabled. operation enabled. bit[3] Loop back mode: Normal serial port operation enabled. Output transmit serial shifter connected input receive serial shifter internally. bit[2] RORIE Receive FIFO overrun interrupt enable: Overrun detection disabled. Overrun condition does generate SSPRORINTR interrupt. Clearing this zero also clears SSPRORINTR interrupt already asserted. Overrun detection enabled. Overrun condition generates SSPRORINTR interrupt. bit[1] Transmit FIFO interrupt enable: Transmit FIFO half-full less condition does generate SSPTXINTR interrupt. Transmit FIFO half-full less condition generates SSPTXINTR interrupt. bit[0] Receive FIFO interrupt enable: Receive FIFO half-full more condition does generate SSPRXINTR interrupt. Receive FIFO half-full more condition generates SSPRXINTR interrupt.
April 2002; 6251-565-1PD
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303xA
Table 2-23: Read/Write Registers, continued
Register Address 08hex Function SSPDR register, Reset -hex
Field 31:16 Reserved 15:0 DATA
Name SSPDR
When SSPDR read, entry receive FIFO (pointed current FIFO read pointer) accessed. data values removed receive logic from incoming data frame, they placed into entry receive FIFO (pointed current FIFO write pointer). When SSPDR written entry transmit FIFO (pointed write pointer), written Data values removed from transmit FIFO value time transmit logic. loaded into transmit serial shifter, then serially shifted onto SSPTXD programmed rate. When data size less than bits selected, user must right-justify data written transmit FIFO. transmit logic ignores unused bits. Received data less than bits automatically right-justified receive buffer. When programmed National Microwire frame format, default size transmit data eight bits (the most significant byte ignored). receive data size controlled programmer. transmit FIFO receive FIFO cleared even when zero. This allows software fill transmit FIFO before enabling SSP. bit[31:16] bit[15:0] Reserved DATA Transmit/Receive FIFO: Read Receive FIFO Write Transmit FIFO. user should right-justify data when programmed data size that less than bits. Unused most significant bits ignored transmit logic. receive logic automatically right-justifies.
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-23: Read/Write Registers, continued
Register Address 0Chex Function SSPSR register, Reset 00hex
Field 31:5 Reserved
Name SSPSR
This register read-only status register which contains bits that indicate FIFO fill status busy status. bit[31:5] bit[4] Reserved, read unpredictable, should written busy flag (read-only): idle. currently transmitting and/or receiving frame transmit FIFO empty. bit[3] Receive FIFO full (read-only): Receive FIFO full. Receive FIFO full. bit[2] Receive FIFO empty (read-only): Receive FIFO empty. Receive FIFO empty. bit[1] Transmit FIFO full (read-only): Transmit FIFO full. Transmit FIFO full. bit[0] Transmit FIFO empty (read-only): Transmit FIFO empty. Transmit FIFO empty.
April 2002; 6251-565-1PD
Micronas
303xA
Table 2-23: Read/Write Registers, continued
Register Address 10hex Function SSPCPSR register, Reset 00hex
Field 31:8 Reserved CPSDVSR
Name SSPCPSR
SSPCPSR clock prescale register specifies division factor which input SSPCLK should internally divided before further use. value programmed into this register should even number between 2-254. least significant programmed number hard-coded zero. number written this register, data read back from this register will have least significant zero. bit[31:8] bit[7:0] 2dec 254dec (even) 14hex Combined SSPIIR/SSPICR register, Reset 00hex
Field 31:3 Reserved
Reserved, read unpredictable, should written CPSDVSR Clock prescale divider. Should even number from 2dec .254dec, depending frequency SSPCLK. least significant always returns zero reads. SSPIIR/SSPICR
RORIS
interrupt status read from interrupt identification register (SSPIIR). write value interrupt clear register (SSPICR, bits 15:0) clears receive FIFO overrun interrupt. This interrupt clearing mechanism addition other mechanism mentioned SSPCR1 register. Therefore, clearing RORIE SSPCR1 register will also clear overrun condition already asserted. bits cleared zero when reset. bit[31:3] bit[15:0] bit[2] Reserved, read unpredictable write this part register clears receive overrun interrupt, regardless data value written. RORIS Read: Receive FIFO overrun interrupt status SSPRORINTR asserted. SSPRORINTR asserted bit[1] Read: transmit FIFO service request interrupt status SSPTXINTR asserted. SSPTXINTR asserted. bit[0] Read: receive FIFO service request interrupt status SSPRXINTR asserted. SSPRXINTR asserted.
Micronas
April 2002; 6251-565-1PD
303xA
Table 2-23: Read/Write Registers, continued
Register Address 18hex Function MODE_SELECT register, Reset 02hex
Field 31:4 Reserved ACLK
Name MODE_SELECT
This register selects operational mode interface circuitry. ACLK field selects SSP-peripheral's main operating clock (SSP5 only). field encodes different modes depending whether operates master slave. bit[31:4] bit[3] Reserved, read unpredictable ACLK This selects main clock SSPCLK peripheral. only functional SSP5. should written SSPs SSP5 peripheral uses internally derived SSPCLK SSP5 peripheral uses exter
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