1.8V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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1.8V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1.8V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
IDT74AUC16374
2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 1.8V Optimized 0.8V 2.7V Operating Range Inputs/outputs tolerant 3.6V Output drivers: ±9mA 2.3V Supports insertion Available TSSOP, TVSOP, VFBGA packages
APPLICATIONS:
high performance, voltage communications systems high performance, voltage computing systems
This 16-bit edge-triggered D-type flip-flop built using advanced CMOS technology. AUC16374 particularly suitable implementing buffer registers, ports, bidirectional drivers, working registers. used 8-bit flip-flops 16-bit flip-flop. positive transition clock (CLK) input, outputs flip-flop take logic levels data inputs. used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operation flip-flop. data retained data entered while outputs high-impedance state. This device fully specified partial power-down applications using IOFF. IOFF circuitry disables outputs, preventing damaging current backflow through device when powered down. ensure high-impedance state during power power down, should tied through pull-up resistor; minimum value resistor determined current-sinking capability driver.
FUNCTIONAL BLOCK DIAGRAM
1CLK
2CLK
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
2003 Integrated Device Technology, Inc.
JANUARY 2003
DSC-6179/5
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
PINOUT CONFIGURATION
1CLK
2CLK
VFBGA
NOTE: Internal Connection
BALL VFBGA PACKAGE LAYOUT
VIEW
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Description Terminal Voltage with Respect (all input terminals) VTERM Terminal Voltage with Respect (any Output terminals highimpedance power-off state) TSTG IOUT Storage Temperature Continuous Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each ±100 +150 -0.5 +3.6 -0.5 +3.6 Unit
1CLK
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz, 2.5V)
Symbol
Parameter Input Capacitance Output Capacitance Input Port Capacitance
Conditions VOUT
Typ.
Max.
Unit
COUT(2) CI(3)
2CLK
NOTES: Applies Control Inputs. Applies Data Outputs. Applies Data Inputs.
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Inputs Output Q(2) xCLK
TSSOP/ TVSOP VIEW
DESCRIPTION
Names xCLK Data Inputs Clock Inputs 3-State Outputs 3-State Output Enable Inputs (Active LOW) Description
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Level before indicated steady-state conditions were established.
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
RECOMMENDED OPERATING CHARACTERISTICS(1)
Symbol Parameter Supply Voltage 0.8V 1.1V 1.3V Input HIGH Voltage Level 1.4V 1.6V 1.65V 1.95V 2.3V 2.7V 0.8V 1.1V 1.3V Input Voltage Level 1.4V 1.6V 1.65V 1.95V 2.3V 2.7V Input Voltage Output Voltage Active State 3-State 0.8V 1.1V HIGH Level Output Current 1.4V 1.65V 2.3V 0.8V 1.1V Level Output Current 1.4V 1.65V 2.3V Input Transition Rise Fall Time Operating Free-Air Temperature Test Conditions Min. 0.65 0.65 0.65 Max. 0.35 0.35 0.35 -0.7 ns/V Unit
NOTE: unused inputs device must held ensure proper operation.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1)
Following Conditions Apply Unless Otherwise Specified: Operating Conditions: -40°C +85°C
Symbol IOFF IOZH IOZL IDDL IDDH IDDZ
NOTE: unused inputs device must held ensure proper operation.
Parameter Input HIGH Current Inputs Input/Output Power Leakage High Impedance Output Current (3-State Output Pins) Quiescent Power Supply Current
Test Conditions 2.7V, 2.7V 2.7V 0.8V 2.7V
Min.
Typ.
Max.
Unit
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 0.8V 2.7V -100µA 0.8V -0.7mA -3mA 1.1V(2) -5mA 1.4V(3) 1.65V -8mA 2.3V(5) -9mA 0.8V 2.7V 100µA 0.8V 0.7mA 1.1V(2) 1.4V 1.65V(4) 2.3V(5) Min. Typ. 0.55 0.25 Max. 0.45 Unit
Output Voltage
NOTES: must within Demonstrates operation Demonstrates operation Demonstrates operation Demonstrates operation
min. max. range shown ELECTRICAL CHARACTERISTICS table appropriate range. -40°C +85°C. nominal 1.2V. nominal 1.5V. nominal 1.8V. nominal 2.5V.
OPERATING CHARACTERISTICS, 25°C(1)
Symbol (each output) CPD(Z) Parameter Power Dissipation Capacitance(2) Outputs Enabled, Output Switching Power Dissipation Capacitance Outputs Disabled, Clock Data Switching Power Dissipation Capacitance(3) Outputs Disabled, Clock Only Switching Test Conditions fDATA 5MHz fCLK 10MHz fOUT 5MHz GND, fDATA 5MHz fCLK 10MHz fOUT switching VDD, fDATA 0MHz fCLK 10MHz fOUT switching VDD, 0.8V 1.2V 1.5V 1.8V 2.5V Unit 24.1 26.2 31.2
13.2
(each clock)
13.8
13.8
14.7
17.5
NOTES: Total device multiple outputs switching clocks inputs switching (each output)} (each clock)}. (each output). This each data where each input output circuit operating 5MHz. clock frequency 10MHz numbers shown minus component. (each clock); this each clock circuit, operating 10MHz.
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SWITCHING CHARACTERISTICS(1)
0.8V 1.2V±0.1V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ fCLOCK Parameter Propagation Delay xCLK Output Enable Time Output Disable Time Clock Frequency Set-up Time, Data before Hold Time, Data after Pulse Duration, HIGH Typ. Min. Max. 1.5V±0.1V Min. Max. 1.8V±0.15V Min. Typ. Max. 2.5V±0.2V Min. Max. Unit
NOTE: TEST CIRCUITS WAVEFORMS. -40°C +85°C.
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
TEST CIRCUITS WAVEFORMS TEST CONDITIONS(1)
Symbol VLOAD 0.8V 2xVDD VDD/2 1.2V±0.1V 2xVDD VDD/2 1.5V±0.1V 2xVDD VDD/2 1.8V±0.15V 2xVDD VDD/2 2.5V±0.2V 2xVDD VDD/2 Unit
Pulse Generator
VLOAD Open
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH tPHL tPHL
D.U.T.
VOUT OPPOSITE PHASE INPUT TRANSITION
Propagation Delay Test Circuits Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTE: Pulse Generator Pulses: Rate 10MHz; slew rate 1V/ns.
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2
DISABLE
tPLZ
VLOAD/2
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tPHZ
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
LOW-HIGH-LOW PULSE
TIMING INPUT
HIGH-LOW-HIGH PULSE
DATA INPUT
Pulse Width
Setup Hold Times
IDT74AUC16374 1.8V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
Temp. Range Bus- Hold Family Device Type Package Temp. Blank Industrial Temperature Range Very Fine Pitch Ball Grid Array Thin Shrink Small Outline Package Thin Very Small Outline Package 16-Bit Edge-Triggered D-Type FlipFlop with 3-State Outputs Double-Density bus-hold 40°C +85°C
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1.8V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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