3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
|
|
|
Top Searches for this datasheet
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available 114-ball LFBGA package
IDT74ALVCH32501
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
High Output Drivers: ±24mA Suitable Heavy Loads
APPLICATIONS:
3.3V high speed systems 3.3V lower voltage computing systems
This 36-bit universal transceiver built using advanced dual metal CMOS technology. ALVCH32501 combines D-type latches Dtype flip-flops allow data flow transparent latched clocked modes. Data flow each direction controlled output-enable (OEAB OEBA), latch enable (LEAB LEBA), clock (CLKAB CLKBA) inputs. A-to-B data flow, device operates transparent mode when LEAB high. When LEAB low, data latched CLKAB held HIGH logic level. LEAB low, data stored latch/ flip-flop low-to-high transition CLKAB. OEAB performs output enable function port. Data flow from port port similar requires using OEBA, LEBA CLKBA. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. This ALVCH32501 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH32501 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1OEAB 1CLKBA 1LEBA 1OEBA 1CLKAB 1LEAB
2OEAB 2CLKBA 2LEBA 2OEBA 2CLKAB 2LEAB
OTHER CHANNELS
OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
©2002 Integrated Device Technology, Inc.
DECEMBER 2002
DSC-4764/2
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
CONFIGURATION
1B10 1B12 1B14 1B15 1B17
2CLKAB
2B10
2B12
2B14
2B15
2B17
1B11
1B13
1B16
1B18
2B11
2B13
2B16
2B18
1CLKAB
1A11
1A13
1CLKBA
1A16 1OEBA
1LEBA
2OEAB
2A11
2CLKBA
2OEBA 2LEBA
1LEAB 1OEAB
2A13
1A18
2LEAB
2A16
2A18
1A10
1A12
1A14
1A15
1A17
2A10
2A12
2A14
2A15
2A17
LFBGA TOPVIEW
BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
VIEW
5.5mm
16mm
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) Terminal Voltage with Respect VTERM(3) Terminal Voltage with Respect TSTG IOUT Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each -0.5 +4.6 -0.5 VCC+0.5 +150 ±100
Unit
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
DESCRIPTION
Names OEAB OEBA LEAB LEBA CLKAB CLKBA Description A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B Clock Input B-to-A Clock Input A-to-B Data Inputs B-to-A 3-State Outputs(1) B-to-A Data Inputs A-to-B 3-State Outputs(1)
FUNCTION TABLE (EACH FLIP-FLOP)(1,2)
Inputs OEAB LEAB CLKAB Outputs B(3) B(4)
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
NOTES: HIGH Voltage Level Voltage Level Don't Care High Impedance LOW-to-HIGH Transition A-to-B data flow shown. B-to-A data flow similar uses OEBA, LEBA, CLKBA. Output level before indicated steady-state conditions were established. Output level before indicated steady-state conditions were established, provided that CLKAB HIGH before LEAB went LOW.
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Test Conditions Min. Typ.(1) -0.7 Max. -1.2 Unit
Quiescent Power Supply Current Variation
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
SWITCHING CHARACTERISTICS(1)
2.5V 0.2V Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSK(O) Parameter Propagation Delay xCLK Propagation Delay Propagation Delay Propagation Delay Output Enable Time OEBA Output Enable Time OEAB Output Disable Time OEBA Output Disable Time OEAB Setup Time, data before Hold Time, data after Setup Time, data before Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
HIGH Hold Time, data after HIGH Pulse Width, HIGH Pulse Width, HIGH Output Skew(2)
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE
Pulse Generator
VLOAD Open
VLOAD/2
ALVC Link
D.U.T.
VOUT
ALVC Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 1.0MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 1.0MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
ALVC Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
ALVC Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
ALVC Link
Pulse Width
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH32501 3.3V CMOS 36-BIT UNIVERSAL TRANSCEIVER WITH 3-STATE OUTPUTS
ORDERING INFORMATION
ALVC Bus-Hold Temp. Range Family XXXX Device Type Package
Low-Profile Fine Pitch Ball Grid Array 36-Bit Universal Transceiver with 3-State Outputs
32-Bit Density, ±24mA Bus-Hold -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com
Tech Support: logichelp@idt.com (408) 654-6459
Other recent searches
ZP-2MH+ - ZP-2MH+ ZP-2MH+ Datasheet
SN65220 - SN65220 SN65220 Datasheet
PM449 - PM449 PM449 Datasheet
PA1704 - PA1704 PA1704 Datasheet
DS3896 - DS3896 DS3896 Datasheet
DS3897 - DS3897 DS3897 Datasheet
DPD-043-003 - DPD-043-003 DPD-043-003 Datasheet
CEP6086L - CEP6086L CEP6086L Datasheet
CEB6086L - CEB6086L CEB6086L Datasheet
APX803 - APX803 APX803 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
