3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
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IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available 96-ball LFBGA package
IDT74ALVCH32374
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
High Output Drivers: ±24mA Suitable Heavy Loads
This 32-bit edge-triggered D-type flip-flop built using advanced dual metal CMOS technology. This high-speed, low-power register ideal buffer register data synchronization storage. Output Enable (OE) clock (CLK) controls organized operate device four 8-bit registers, 16-bit registers, 32-bit register with common clock. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. ALVCH32374 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH32374 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistor.
APPLICATIONS:
3.3V high speed systems 3.3V lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1CLK
3CLK
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
2CLK
4CLK
SEVEN OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
SEVEN OTHER CHANNELS
©2000 Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-4909/1
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
CONFIGURATION
1CLK
2CLK
3CLK
4CLK
LFBGA TOPVIEW
BALL LFBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
VIEW
5.5mm
13.5mm
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) Terminal Voltage with Respect VTERM(3) Terminal Voltage with Respect TSTG IOUT Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each -0.5 +4.6 -0.5 VCC+0.5 +150 ±100
Unit
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
DESCRIPTION
Names xCLK Data Inputs
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Description Inputs xCLK Outputs Q(2)
Clock Inputs 3-State Outputs 3-State Output Enable Inputs (Active LOW)
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
NOTES: HIGH Voltage Level Voltage Level Don't Care High Impedance LOW-to-HIGH Transition Output level before indicated steady-state conditions were established.
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Test Conditions Min. Typ.(1) -0.7 Max. -1.2 Unit
Quiescent Power Supply Current Variation
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
SWITCHING CHARACTERISTICS(1)
2.5V 0.2V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Propagation Delay xCLK Output Enable Time Output Disable Time Setup Time, data before Hold Time, data after Pulse Duration, HIGH Output Skew(2) Parameter Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE
Pulse Generator
VLOAD Open
VLOAD/2
ALVC Link
D.U.T.
VOUT
ALVC Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 1.0MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 1.0MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
ALVC Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
ALVC Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
ALVC Link
Pulse Width
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH32374 3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
ALVC Bus-Hold Temp. Range Family XXXX Device Type Package
Low-Profile Fine Pitch Ball Grid Array 32-Bit Edge Triggered D-Type Flip-Flop with 3-State Outputs 32-Bit Density, ±24mA Bus-Hold -40°C +85°C
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