3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER, DUAL 3-STATE OU
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available SSOP TSSOP packages
IDT74ALVCH16903
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
High Output Drivers: ±24mA Suitable heavy loads
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) VTERM(3) TSTG IOUT Terminal Voltage with Respect Terminal Voltage with Respect (Outputs Only) Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each -0.5 +4.6 -0.5 VCC+0.5 +150 ±100
Unit
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. This value limited 4.6V maximum.
This 12-bit universal driver built using advanced dual metal CMOS technology. This device dual outputs operate buffer edge-triggered register. both modes, parity checked APAR, which arrives cycle after data which applies. YERR output, which produced cycle after APAR, open drain. MODE selects data paths. When MODE low, device operates edge-triggered register. positive transition clock (CLK) input when clock-enable (CLKEN) input low, data setup inputs stored internal registers. positive transition when CLKEN high, only data setup 9A-12A inputs stored their internal registers. When MODE high, device operates buffer data inputs passes directly outputs. 11A/YERREN serves dual purpose; acts normal data also enables YERR data clocked into YERR output register. When used single device, parity output enable (PAROE) must tied high; when parity input/output (PARI/O) low, even parity selected when PARI/O high, parity selected. When used pairs PAROE low, parity output PARI/O cascading second ALVCH16903. When used pairs PAROE high, PARI/O accepts partial parity from first ALVCH16903. buffered output-enable (OE) input used place outputs YERR either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. ALVCH16903 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH16903 "bus-hold" which retains inputs' last state whenever input goes high-impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT COUT Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
3.3V high speed systems 3.3V lower voltage computing systems
NOTE: applicable device type.
logo registered trademark Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4911/2
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
FUNCTIONAL BLOCK DIAGRAM
(1A-11A/YERREN, APAR) 1A-12A, APAR (1A-8A) (11A/YERR APAR Flip Flop (1A-10A) Parity Check APAR (1A-12A) 1Y2-12Y2 1Y1-12Y1
CLKEN (9A-12A, APAR)
Flip Flop
PARI/O
FUNCTION TABLE(1)
Inputs MODE CLKEN Outputs 1Yx-8Yx Y(2) Y(2) 9Yx-12Yx
PARITY FUNCTION TABLE(1)
Inputs PAROE(2) 11A/ YERREN(3) PARI/O INPUTS APAR 1A-10A= Output YERR
NOTES: HIGH Voltage Level Voltage Level Don't Care LOW-to-HIGH Transition Output level before indicated steady-state conditions were established.
NOTES: HIGH Voltage Level Voltage Level Don't Care When used single device, PAROE must tied HIGH. Valid after appropriate number clock pulses have internal register.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
CONFIGURATION
10Y1 10Y2 PAROE 11A/YERREN 11Y1 11Y2 12Y1 12Y2 APAR YERR MODE PARI/O CLKEN
PARI/O FUNCTION TABLE(1)
Inputs PAROE INPUTS 1A-10A 8,10 APAR Output PARI/O
NOTE: This table applies first device cascaded pair ALVCH16903 devices.
DESCRIPTION
Names 1A-12A 1Y1-12Y2 CLKEN MODE YERREN PAROE PARI/O YERR APAR Data Inputs(1) 3-State Data Outputs Clock Input Clock Enable Input (Active LOW) Select Error Signal Output Enable (Active LOW) Parity Output Enable (Active LOW) Parity Input/Output Error Signal (Open Drain) Output Enable Input (Active LOW) Parity Input Description
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
SSOP/ TSSOP VIEW
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOZ(2) ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) YERR Output High Impedance Output Current Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation Control Inputs Data Inputs YERR Output Data Outputs PARI/O 3.3V 3.3V 3.6V 3.6V 2.3V, 18mA 3.3V 3.6V, input 0.6V, other inputs 3.3V 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Test Conditions Min. Typ.(1) Max. Unit
NOTES: Typical values 3.3V, +25°C ambient. ports, parameter includes input leakage current.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
OUTPUT DRIVE CHARACTERISTICS, PORTS
Symbol Parameter 2.3V 3.6V 2.3V Output HIGH Voltage 2.3V 2.7V 2.3V 3.6V 2.3V Output Voltage 2.7V 2.3V High-Level Output Current 2.7V 2.3V 2.7V Low-Level Output Current PARI/O Port YERR Output PARI/O Port Port 24mA, 0.1mA 6mA, 0.7V 12mA, 0.7V 12mA, 0.8V 24mA, 0.8V Port Test Conditions(1) 0.1mA 6mA, 1.7V 12mA, 1.7V 12mA, Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OUTPUT DRIVE CHARACTERISTICS YERR PARI/O
Symbol Parameter PARI/O PARI/O YERR Output only Test Conditions(1)
Min. 12mA, 12mA, 0.8V 24mA
Max. 0.55
Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
OPERATING CHARACTERISTICS BUFFER MODE, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 57.5 3.3V 0.3V Typical 17.5 Unit
OPERATING CHARACTERISTICS REGISTER MODE, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 16.5 3.3V 0.3V Typical 87.5 Unit
SIMULTANEOUS SWITCHING CHARACTERISTICS(1)
Parameter From (Input) tPLH tPHL
NOTE: outputs switching.
(Output)
2.5V 0.2V Min. Max.
2.7V Min. Max.
3.3V 0.3V Min. Max. Unit
Register mode
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
SWITCHING CHARACTERISTICS(1)
2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSK(O) Parameter Propagation Delay, Buffer Mode Propagation Delay, Both Modes YERR Propagation Delay, Both Modes PARI/O Propagation Delay, Both Modes PARI/O Propagation Delay, Both Modes Mode Propagation Delay, Register Mode Propagation Delay, Both Modes YERR Propagation Delay, Both Modes YERR Output Enable Time, Both Modes Output Enable Time, Both Modes PAROE PARI/O Output Disable Time, Both Modes Output Disable Time, Both Modes PAROE PARI/O Set-up Time, Register Mode, 1A-12A before Set-up Time, Buffer Mode, before Set-up Time, Register Mode, APAR before Set-up Time, Buffer Mode, APAR before Set-up Time, Both Modes, PARI/O before Set-up Time, Buffer Mode, 11A/YERREN before Set-up Time, Register Mode, CLKEN before Hold Time, Register Mode, 1A-12A after Hold Time, Buffer Mode, 1A-10A after Hold Time, Register Mode, APAR after Hold Time, Buffer Mode, APAR after Hold Time, Register Mode, PARI/O after Hold Time, Buffer Mode, PARI/O after Hold Time, Buffer Mode, 11A/YERREN after Hold Time, Register Mode, CLKEN after Pulse Width, Output Skew(2) 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 0.25 1.45 0.55 0.25 0.25 Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE
Pulse Generator
VLOAD Open
VLOAD/2
ALVC Link
D.U.T.
VOUT
ALVC Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 1.0MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 1.0MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tREM
ALVC Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
ALVC Link
Pulse Width
ALVC Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
PARAMETER MEASUREMENT INFORMATION 2.7V 3.3V 0.3V
From Output Under Test (see Note Open
TEST tPLZ/tPZL tPHZ/tPZH Open
YERR
Load Circuit
tPHL (see Note tPLH (see Note
TIMING INPUT
2.7V 1.5V 2.7V 1.5V 1.5V INPUT 1.5V 1.5V 2.7V
DATA INPUT
Voltage Waveforms Setup Hold Times
Voltage Waveforms Pulse Duration
OUTPUT CONTROL (low-level enabling) 2.7V Input Output 1.5V 1.5V 1.5V 1.5V OUTPUT WAVEFORM (see Note OUTPUT AVEFORM (see Note
1.5V 2.7V 1.5V tPLZ 1.5V 1.5V 0.3V tPHZ -0.3V
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable DisableTimes
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. tPHL measured 1.5V. tPLH measured +0.3V.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
LOAD CIRCUIT VOLTAGE WAVEFORMS 2.7V 3.3V 0.3V
2.7V 1.5V INPUT tPLH OUTPUT 1.5V 1.5V 1.5V
PARI/O Load Circuit
From Output Under Test PARI/O
Test Point
PARI/O second ALVCH16903
(see Note
(see Note
NOTE: includes probe capacitance.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
PARAMETER MEASUREMENT INFORMATION 2.5V 0.2V
From Output Under Test (see Note Open
TEST tPLZ/tPZL tPHZ/tPZH YERR tPHL (see Note tPLH (see Note
Open
Load Circuit
INPUT
CC/2 CC/2 INPU CC/2
DATA INPU
Voltage Waveforms Setup Hold Times
Voltage Waveforms Pulse Duration
INPUT CONTROL (low-level enabling) Input Output tPHL OUTPUT AVEFORM 2xVcc (see Note TPUT AVEFOR (see Note tPZL
tPLZ 0.15V tPHZ -0.15V
tPZH
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable DisableTimes
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. tPHL measured tPLH measured 0.15V.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
PARAMETER MEASUREMENT INFORMATION 2.5V 0.2V
From Output Under Test PARI/O
Test Point
PARI/O second ALVCH16903
(see Note
(see Note
Load Circuit
Input Output
Voltage Waveforms Propagation Delay Times
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, 2ns. tPLH tPHL same tpd.
From Output Under Test Test Point (see Note Output Input
Load Circuit
Voltage Waveforms Propagation Delay Times
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, 2ns.
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL DRIVER WITH PARITY CHECKER
ORDERING INFORMATION
ALVC Bus-Hold Temp. Range Family Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package 12-Bit Universal Driver with Parity Checker Double-Density, ±24mA Bus-Hold -40°C +85°C
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