3.3V CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL TRANSCEIVER WITH PARITY GEN

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3.3V CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL TRANSCEIVER WITH PARITY GEN

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IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
3.3V CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL TRANSCEIVER WITH PARITY GENERATORS/ CHECKERS BUS-HOLD
MICRON CMOS Technology Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range 2.5V 0.2V CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin Available TSSOP package
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
High Output Drivers: ±24mA Suitable heavy loads
APPLICATIONS:
3.3V high speed systems 3.3V lower voltage computing systems
This 18-bit universal transceiver built using advanced dual metal CMOS technology. ALVCH16901 dual 9-bit dual 9-bit parity transceiver with registers. device operate feed-through transceiver generate/check parity from 8-bit data buses either direction. ALVCH16901 features independent clock (CLKAB CLKBA), latch-enable (LEAB LEBA), dual 9-bit clock enable (CLKENAB CLKENBA) inputs. also provides parity-enable (SEL) parity-select (ODD/EVEN) inputs separate error-signal (ERRA ERRB) outputs checking parity. direction data flow controlled OEAB OEBA. When low, parity functions enabled. When high, parity functions disabled device acts 18-bit registered transceiver. ALVCH16901 been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. ALVCH16901 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
LEAB
CLKENAB CLKENAB
CLKAB OEAB
OEBA
APAR ERRB APAR ERRB
A-Port Parity Generate Check Data
18-Bit Storage
B-Port Parity Generate Check Data
BPAR ERRA BPAR ERRA
18-Bit Storage
ODD/EVEN
CLKBA
CLKENBA CLKENBA
LEBA
logo registered trademark Integrated Device Technology, Inc.
©2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-4582/1
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
CONFIGURATION
TSSOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM(2) Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each -0.5 +4.6 -0.5 VCC+0.5 +150 ±100 VTERM(3) TSTG IOUT
Unit
1CLKENAB
1CLKENBA
LEAB CLKAB
1ERRA 1APAR
LEBA CLKBA
1ERRB 1BPAR
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT COUT Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
DESCRIPTION
Names OEAB OEBA LEAB LEBA xCLKENAB xCLKENBA CLKAB CLKBA xERRA xERRB xAPAR xBPAR ODD/EVEN Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B 9-bit Clock Enables B-to-A 9-bit Clock Enables A-to-B Clock Input B-to-A Clock Input Error-Signal Outputs Error-Signal Outputs Port Parities Port Parities Parity Select Input Parity Enables A-to-B Data Inputs B-to-A 3-State Outputs B-to-A Data Inputs A-to-B 3-State Outputs
2APAR 2ERRA
2BPAR 2ERRB
OEAB
2CLKENAB
OEBA ODD/EVEN
2CLKENBA
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
FUNCTION TABLE(1,2)
Inputs CLKENAB OEAB LEAB CLKAB Outputs B(3) B(3) B(4)
PARITY ENABLE
Inputs OEBA OEAB
Operation Function
Parity checked port generated port Parity checked port generated port Parity checked port port Parity generated port device mode. Parity functions data data disabled; device acts data standard 18-bit data registered transceiver. Isolation
NOTES: HIGH Voltage Level Voltage Level Don't Care LOW-to-HIGH Transition A-to-B data flow shown. B-to-A data flow similar uses OEBA, LEBA, CLKENBA. Output level before indicated steady-state conditions were established. Output level before indicated steady-state conditions were established, provided that CLKAB before LEAB went LOW.
PARITY
OEBA OEAB ODD/EVEN Inputs INPUTS A1-A8 Outputs INPUTS B1-B8 xAPAR xBPAR xAPAR PE(1) PO(2) xERRA xBPAR PE(1) PO(2) xERRB
NOTES: Parity output level that specific side even parity. Parity output level that specific side parity.
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input HIGH Current Input Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 2.3V, -18mA 3.3V 3.6V input 0.6V, other inputs 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 3.6V Test Conditions Min. Typ.(1) -0.7 Max. -1.2 Unit
Quiescent Power Supply Current Variation
NOTE: Typical values 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V 0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical 3.3V 0.3V Typical Unit
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
SWITCHING CHARACTERISTICS(1)
2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Propagation Delay Propagation Delay xBPAR xAPAR Propagation Delay xAPAR xBPAR xBPAR xAPAR Propagation Delay xAPAR xERRA xBPAR xERRB Propagation Delay ODD/EVEN xERRB xERRA Propagation Delay ODD/EVEN xAPAR xBPAR Propagation Delay xAPAR xBPAR Propagation Delay LEBA LEAB Propagation Delay LEBA xAPAR LEAB xBPAR (parity feed through) Propagation Delay LEBA xAPAR LEAB xBPAR (parity generated) Propagation Delay LEBA xERRB LEAB xERRA Propagation Delay CLKBA CLKAB Propagation Delay CLKBA xAPAR CLKAB xBPAR(parity feed through) Propagation Delay CLKBA xAPAR CLKAB xBPAR(parity generated) Propagation Delay CLKBA xERRB CLKAB ERRA Min. Max. 10.2 10.5 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
SWITCHING CHARACTERISTICS (CONTINUED)(1)
2.5V 0.2V Symbol tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ tSK(o) Parameter Output Enable Time OEAB OEBA xBx, xBPAR xAx, xAPAR Output Enable Time OEAB OEBA xERRA xERRB Output Enable Time xERRA xERRB Output Disable Time OEAB OEBA xBx, xBPAR xAx, xAPAR Output Disable Time OEAB OEBA xERRA xERRB Output Disable Time xERRA xERRB Set-up Time, HIGH LOW, xAx, xAPAR xBx, xBPAR before Set-up Time, HIGH LOW, xCLKENAB xCLKENBA before Set-up Time, HIGH LOW, xAx, xAPAR xBx, xBPAR before Hold Time, HIGH LOW, xAx, xAPAR xBx, xBPAR after Hold Time, HIGH LOW, xCLKENAB xCLKENBA after Hold Time, HIGH LOW, xAx, xAPAR xBx, xBPAR after Pulse Width LEAB LEBA HIGH Pulse Width CLKAB CLKBA HIGH Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE
Pulse Generator
VLOAD Open
VLOAD/2
ALVC Link
D.U.T.
VOUT
ALVC Link
Test Circuit Outputs
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 1.0MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 1.0MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
tREM
ALVC Link
INPUT
tPLH1
tPHL1
Set-up, Hold, Release Times
OUTPUT
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT tPLH2 tPHL2
ALVC Link
Pulse Width
ALVC Link
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74ALVCH16901 3.3V CMOS 18-BIT UNIVERSAL TRANSCEIVER WITH PARITY
ORDERING INFORMATION
ALVC Bus-Hold Temp. Range Family Device Type Package
Thin Shrink Small Outline Package 18-Bit Universal Transceiver with Parity Generators/Checkers Double-Density, ±24mA Bus-Hold -40°C +85°C
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
SALES: 800-345-7015 408-727-6116 fax: 408-492-8674 www.idt.com
Tech Support: logichelp@idt.com (408) 654-6459

3.3V CMOS 18-BIT IDT74ALVCH16901 UNIVERSAL TRANSCEIVER WITH PARITY GEN

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