IDT7015S/L True Dual-Ported memory cells which allow simultaneous

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HIGH-SPEED DUAL-PORT STATIC
IDT7015S/L
True Dual-Ported memory cells which allow simultaneous reads same memory location High-speed access Military: 20/25/35ns (max.) Commercial: 12/15/17/20/25/35ns (max.) Low-power operation IDT7015S Active: 750mW (typ.) Standby: (typ.) IDT7015L Active: 750mW (typ.) Standby: (typ.) IDT7015 easily expands data width bits more using Master/Slave select when cascading more than device
BUSY output flag Master BUSY input Slave Busy Interrupt Flag On-chip port arbitration logic Full on-chip hardware support semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single (±10%) power supply Available ceramic 68-pin PGA, 68-pin PLCC, 80pin TQFP Industrial temperature range (-40°C +85°C) available selected speeds
Functional Block Diagram
R/WL R/WR
I/O0L- I/O8L Control BUSYL A12L
(1,2)
Control
I/O0R-I/O8R
BUSYR A12R
(1,2)
Address Decoder
MEMORY ARRAY
Address Decoder
R/WL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
R/WR
SEML INTL
NOTES: MASTER mode: BUSY output push-pull driver SLAVE mode: BUSY input. BUSY outputs outputs non-tri-stated push-pull drivers.
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SEMR INTR
2000
©2000 Integrated Device Technology, Inc. 2954/5
IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
DESCRIPTION:
IDT7015 high-speed Dual-Port Static RAM. IDT7015 designed used stand-alone Dual-Port combination MASTER/SLAVE Dual-Port 18-bit-or-more word systems. Using MASTER/SLAVE Dual-Port approach 18bit wider memory system applications results full-speed, error-free operation without need additional discrete logic. This device provides independent ports with separate control, address, pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits on-chip circuitry each port enter very standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate only 750mW power. IDT7015 packaged ceramic 68-pin PGA, 64-pin PLCC 80-pinTQFP (Thin Quad Flatpack). Military grade product manufactured compliance with latest revision MIL-PRF38535 QML, making ideally suited military temperature applications demanding highest level performance reliability.
INDEX I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
I/O1L I/O0L I/O8L R/WL SEML A12L A11L A10L
Configurations(1,2,3)
IDT7015J J68-1(4) 68-Pin PLCC View(5)
INTL BUSYL BUSYR INTR
I/O7R I/O8R R/WR SEMR A12R A11R A10R
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NOTES: pins must connected power supply. pins must connected ground supply. Package body approximately This package code used reference package diagram. This text does imply orientation Part-marking.
Names (7015)
Left Port R/WL A12L I/O0L I/O8L SEML INTL BUSYL R/WR A12R I/O0R I/O8R SEMR INTR BUSYR Right Port Chip Enable Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master Slave Select Power Ground
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Names
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Configurations
I/O0L I/O8L I/O1L R/WL SEML
INDEX
(1,2,3)
(con't.)
A12L A11L A10L
I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R
INTL BUSYL BUSYR INTR
IDT7015PF PN80-1(4) 80-Pin TQFP View(5)
SEMR
I/O7R I/O8R
R/WR
A11R A10R
A12R
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BUSYL
INTR
A11R A10R A12R
INTL BUSYR
A11L A10L A12L
68-Pin View(5) IDT7015G G68-1(4)
SEML R/WL I/O0L I/O8L I/O7L I/O1R I/O4R I/O6L I/O0R I/O2R I/O3R I/O5R
SEMR R/WR
I/O1L I/O2L I/O4L NOTES: must connected power supply. must connected ground supply. I/O3L I/O5L PN80 package body approximately 14mm 14mm 1.4mm. G68-1 package body approximately INDEX 1.18 1.18 This package code used reference package diagram. This text does imply orientation Part-marking.
I/O7R I/O8R I/O6R
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Truth Table Non-Contention Read/Write Control
Inputs(1) Outputs I/O0-8 High-Z DATA DATA High-Z Deselected: Power-Down Write Memory Read Memory Outputs Disabled
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Mode
NOTE: Condition: A12L A12R
Truth Table Semaphore Read/Write CONTROL(1)
Inputs(1) Outputs I/O0-8 DATA DATA
Mode Read Semaphore Flag Data (I/O0-8) Write I/O0 into Semaphore Flag Allowed
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NOTE: There eight semaphore flags written I/O0 read from I/Os (I/O0 I/O8). These eight semaphores addressed
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect Temperature Under Bias Storage Temperature Output Current Commercial Industrial -0.5 +7.0 Military -0.5 +7.0 Unit
Maximum Operating Temperature Supply Voltage(1,2)
Grade Military Ambient Temperature -55OC +125OC +70OC -40OC +85OC 5.0V 5.0V 5.0V
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TBIAS TSTG IOUT
+125 +150
+135 +150
Commercial Industrial
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NOTES: This parameter There "instant case temperature. Industrial temperature: specific speeds, packages powers contact your sales office.
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. VTERM must exceed more than cycle time 10ns maximum, limited 20mA period VTERM 10%.
Recommended Operating Conditions
Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Min. -0.5
Typ.
Max.
Unit
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NOTES: -1.5V pulse width less than 10ns. VTERM must exceed 10%.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Capacitance
Symbol COUT
+25°C, 1.0mhz, TQFP Package)
Parameter Input Capacitance Output Capacitance Conditions(2) Max. Unit
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NOTES: This parameter determined device characteristics production tested. references interpolated capacitance when input output signals switch from from
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VCC 5.0V 10%)
7015S Symbol |ILI| |ILO| Parameter Input Leakage Current
7015L Max.
Test Conditions 5.5V, VIH, VOUT +4mA -4mA
Min.
Min.
Max.
Unit
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Output Leakage Current Output Voltage Output High Voltage
NOTE: 2.0V, Input leakages undefined.
Output Loads Test Conditions
Input Pulse Levels Input Rise/Fall Times
3.0V Max. 1.5V 1.5V Figures
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Input Timing Reference Levels Output Reference Levels Output Load
DATAOUT BUSY 30pF DATAOUT
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Figure Output Test Load
Figure Output Test Load
(For tWZ, tOW) *Including scope jig.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1,6) (con't.) (VCC 5.0V 10%)
7015X12 Com'l. Only Symbol Parameter Dynamic rating Curre ctive Test Condition Outp Disab fMAX Version IND. IND. IND. IND. IND. Typ.
7015X15 Com'l. Only Typ.
7015X17 Com'l. Only Typ.
Max.
Max.
Max.
Unit
ISB1
tand Curre uts)
SEMR SEML fMAX
ISB2
tand Curre (One uts)
CE"A" CE"B" ctive Outp Disab fMAX SEMR SEML 0.2V 0.2V 0.2V SEMR SEML 0.2V CE"A" 0.2V CE"B" 0.2V SEMR SEML 0.2V 0.2V 0.2V, ctive Disab fMAX
ISB3
Full tandb Curre uts)
ISB4
Full tand Curre (One uts)
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7015X20 Com'l. Military Symbol Parameter Dynamic rating Curre ctive Test Condition Outp Disab fMAX Version IND. IND. IND. IND. IND. Typ. Max.
7015X25 Com'l. Military Typ. Max.
7015X35 Com'l. Military Typ. Max.
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Unit
ISB1
tand Curre uts)
SEMR SEML fMAX
ISB2
tand Curre (One uts)
CE"A" CE"B" ctive Outp Disab fMAX SEMR SEML 0.2V 0.2V 0.2V SEMR SEML 0.2V CE"A" 0.2V CE"B" 0.2V SEMR SEML 0.2V 0.2V 0.2V, ctive Disab fMAX
ISB3
Full tandb Curre uts)
ISB4
Full tand Curre (One uts)
NOTES: part numbers indicates power rating +25°C, production tested. ICCDC 120mA(typ.) fMAX, address I/O'S cycling maximum frequency read cycle 1/tRC, using Test Conditions" input levels means address control lines change. Port either left right port. Port opposite port "A". Industrial temperature: specific speeds, packages powers contact your sales office.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(4,5)
7015X12 Com'l Only Symbol READ CYCLE tACE tAOE tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time
7015X15 Com'l Only Min. Max.
7015X17 Com'l Only Min. Max. Unit
Parameter
Min.
Max.
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Output Enable Access Time Output Hold from Address Change Output Low-Z Time (1,2) Output High-Z Time
(1,2)
Chip Enable Power Time
Chip Disable Power Down Time(2) Semaphore Flag Update Pulse SEM) Semaphore Address Access Time
7015X20 Com'l Military Symbol READ CYCLE tACE tAOE tSOP tSAA Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2)
7015X25 Com'l Military Min. Max.
7015X35 Com'l Military Min. Max. Unit
Parameter
Min.
Max.
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Output High-Z Time(1,2) Chip Enable Power Time Chip Disable Power Down Time
Semaphore Flag Update Pulse SEM) Semaphore Address Access Time
NOTES: Transition measured from Low- High-impedance voltage with load (Figures This parameter guaranteed device characterization tested. access RAM, VIH. access semaphore, VIL. part numbers indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Waveform Read Cycles
ADDR
tACE(4) tAOE
DATAOUT
VALID DATA
BUSYOUT tBDD
(3,4)
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NOTES: Timing depends which signal asserted last, Timing depends which signal de-asserted first, tBDD delay required only cases where opposite port completing write operation same address location. simultaneous read operations BUSY relation valid output data. Start valid data depends which timing becomes effective last tAOE, tACE, tBDD VIH.
Timing Power-Up Power-Down
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage(5,6)
7015X12 Only WRITE CYCLE tSWRD tSPS Write Chip f-Write Valid f-Write t-up Write Puls Write Data Valid f-Write Outp Data
(1,2) (1,2)
7015X15 Only Min. Max.
7015X17 Only Min. Max. Unit
Param eter
Min.
Max.
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rite Enab Outp Outp ctive f-Write Flag Write Flag ntio Wind
(1,2,4)
7015X20 Military WRITE CYCLE tSWRD tSPS Write Chip f-Write
7015X25 Military Min. Max.
7015X35 Military Min. Max. Unit
Param eter
Min.
Max.
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Valid f-Write t-up Write Puls Write Data Valid f-Write Outp Data
(1,2) (1,2)
rite Enab Outp Outp ctive f-Write Flag Write Flag ntio Wind
(1,2,4)
NOTES: Transition measured from Low- High-impedance voltage with Output Test Load (Figure This parameter guaranteed device characterization tested. access RAM, VIH. access semaphore, Either condition must valid entire time. specification must device supplying write data under operating conditions. Although values will vary over voltage temperature, actual will always smaller than actual tOW. part numbers indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Timing Waveform Write Cycle Controlled Timing(1,5,8)
ADDRESS
DATAOUT
DATAIN
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Timing Waveform Write Cycle Controlled Timing(1,5)
ADDRESS
DATAIN
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NOTES: must HIGH during address transitions. write occurs during overlap (tEW memory array writing cycle. measured from earlier R/W) going HIGH write cycle. During this period, pins output state input signals must applied. transition occurs simultaneously with after transition, outputs remain High-impedance state. Timing depends which enable signal asserted last, R/W. This parameter guaranteed device characterization production tested. Transition measured from steady state with Output Test Load (Figure during controlled write cycle, write pulse width must larger (tWZ allow drivers turn data placed required tDW. HIGH during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIH. access Semaphore, VIL. must either condition.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Timing Waveform Semaphore Read after Write Timing, Either Side(1)
tSAA A0-A2 VALID ADDRESS DATAIN VALID tSWRD
Write Cycle Read Cycle
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VALID ADDRESS tACE tSOP DATAOUT VALID(2)
tAOE
NOTES: duration above timing (both write read cycle). "DATAOUT VALID" represents I/O's (I/O0-I/O8) equal semaphore value.
Timing Waveform Semaphore Write Contention(1,3,4)
A0"A"-A2 MATCH
SIDE
R/W"A"
SEM"A" tSPS A0"B"-A2 MATCH
SIDE
R/W"B"
SEM"B"
NOTES: =VIH, =VIH. timing same left right ports. Port"A" either left right port. opposite port from "A". This parameter measured from R/W"A" SEM"A" going high R/W"B" SEM"B" going HIGH. tSPS satisfied, there guarantee which side will obtain semaphore flag.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range(6,7)
7015X12 Only BUSY TIMING (M/S tBAA tBDA tBAC tBDC tAPS tBDD BUSY BUSY BUSY Chip BUSY Chip itratio rity t-up BUSY Valid Data Write BUSY
7015X15 Only Min. Max.
7015X17 Only Min. Max. Unit
Param eter
Min.
Max.
BUSY INPUT TIMING (M/S BUSY rite Write BUSY
PORT-TO-PORT DELAY tWDD tDDD Write Puls Data Write Data Valid Data
7015X20 Military BUSY TIMING (M/S tBAA tBDA tBAC tBDC tAPS tBDD BUSY BUSY BUSY Chip BUSY Chip itratio rity t-up BUSY Valid Data Write BUSY
7015X25 Military Min. Max.
7015X35 Military Min. Max. Unit
Param eter
Min.
Max.
BUSY INPUT TIMING (M/S BUSY rite Write BUSY
PORT-TO-PORT DELAY tWDD tDDD Write Puls Data Write Data Valid Data
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NOTES: Port-to-port delay through cells from writing port reading port, refer "Timing Wave form Write with Port-to-Port Read BUSY (M/S VIH)". ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual) tDDD (actual). ensure that write cycle inhibited Port during contention Port "A". ensure that write cycle completed Port after contention Port "A". part numbers indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Timing Waveform Read with BUSY
ADDR"A"
(2,4,5)
(M/S VIH)
MATCH R/W"A" DATAIN tAPS ADDR"B"
VALID
MATCH tBDA tBDD
BUSY"B" tWDD DATAOUT tDDD
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VALID
NOTES: ensure that earlier ports wins. ignored M/S=V reading port. M/S=VIL (SLAVE), BUSY input. Then this example, BUSY"A"=VIH BUSY"B" input shown above. timing same left right ports. Port either left right port. Port port opposite from Port "A".
Timing Waveform Write with BUSY(3)
R/W"A" BUSY"B"
R/W"B"
NOTES: must both BUSY input (SLAVE) output (MASTER). BUSY asserted port blocking R/W"B", until BUSY"B" goes HIGH. timing same left right ports. Port either left right port. Port port opposite from Port "A".
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Waveform BUSY Arbitration Controlled timing(1) (M/S VIH)
ADDR"A" ADDRESSES MATCH
CE"A" tAPS CE"B" tBAC BUSY"B"
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tBDC
Waveform BUSY Arbitration Cycle Controlled Address Match Timing(1) (M/S VIH)
ADDR"A" tAPS ADDR"B" tBAA BUSY"B"
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ADDRESS
MATCHING ADDRESS tBDA
NOTES: timing same left right ports. Port either left right port. Port port opposite from "A". tAPS satisfied, BUSY signal will asserted side another there guarantee which side BUSY will asserted.
Electrical Characteristics Over Operating Temperature Supply Voltage Range(1,2)
7015X12 Only INTERRUPT tINS tINR t-up Write Inte rrup Inte rrup
7015X15 Only Min. Max.
7015X17 Only Min. Max. Unit
Param eter
Min.
Max.
7015X20 Military INTERRUPT tINS tINR t-up Write Inte rrup Inte rrup
7015X25 Military Min. Max.
7015X35 Military Min. Max. Unit
Param eter
Min.
Max.
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NOTES: part numbers indicates power rating Industrial temperature: specific speeds, packages powers contact your sales office.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Waveform Interrupt Timing
ADDR"A" tAS(3) CE"A"
INTERRUPT ADDRESS
R/W"A" tINS INT"B"
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ADDR"B" CE"B"
INTERRUPT CLEAR ADDRESS
OE"B" tINR INT"B"
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NOTES: timing same left right ports. Port either left right port. Port port opposite from "A". Interrupt Truth Table. Timing depends which enable signal R/W) asserted last. Timing depends which enable signal R/W) de-asserted first.
Truth Table Interrupt Flag(1)
Left Port R/WL A12L-A0L 1FFF 1FFE INTL L(3) H(2) R/WR Right Port A12R-A0R 1FFF 1FFE INTR L(2) H(3) Function Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
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NOTES: Assumes BUSYL BUSYR VIH. BUSY VIL, then change. BUSYR VIL, then change.
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Truth Table Address BUSY Arbitration
Inputs AOL-A12L AOR-A12R MATCH MATCH MATCH MATCH Outputs BUSYL(1) BUSYR(1) Function Normal Normal Normal Write Inhibit(3)
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NOTES: Pins BUSYL BUSY both outputs when part configured master. Both inputs when configured slave. BUSY outputs IDT7015 push-pull, open drain outputs. slaves BUSYX input internally inhibits writes. inputs opposite port were stable prior address enable inputs this port. inputs opposite port became stable after address enable inputs this port. tAPS met, either BUSYL BUSYR will result. BUSYL BUSYR outputs simultaneously. Writes left port internally ignored when BUSYL outputs driving regardless actual logic level pin. Writes right port internally ignored when BUSY outputs driving regardless actual logic level pin.
Truth Table Example Semaphore Procurement Sequence(1,2,3)
Functions Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Left Right Semaphore free Left port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left port semaphore token Semaphore free
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Status
NOTES: This table denotes sequence events only eight semaphores IDT7015. There eight semaphore flags written I/O0 read from I/Os (I/O0 I/O8). These eight semaphores addressed VIH, access semaphores. Refer Semaphore Read/Write Control Truth Table.
Functional Description
IDT7015 provides ports with separate control, address pins that permit independent access reads writes location memory. IDT7015 automatic power down feature controlled controls on-chip power down circuitry that permits respective port into standby mode when selected HIGH). When port enabled, access entire memory array permitted. (INTL) asserted when right port writes memory location 1FFE where write defined Truth Table III. left port clears interrupt address location 1FFE access when =OER =VIL, "don't care". Likewise, right port interrupt flag (INTR) asserted when left port writes memory location 1FFF clear interrupt flag (INTR), right port must access memory location 1FFF. message bits) 1FFE 1FFF isuser-defined since addressable SRAM location. interrupt function used, address locations 1FFE 1FFF used mail boxes still part random access memory. Refer Table interrupt operation.
Interrupts
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
DECODER
BUSY
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Busy Logic
Busy Logic provides hardware indication that both ports have accessed same location same time. also allows accesses proceed signals other side that "busy". BUSY then used stall access until operation other side completed. write operation been attempted from side that receives BUSY indication, write signal gated internally prevent write from proceeding. BUSY logic required desirable applications. some cases useful logically BUSY outputs together BUSY indication interrupt source flag event illegal illogical operation. write inhibit function BUSY logic desirable, BUSY logic disabled placing part slave mode with pin. Once slave mode BUSY operates solely write inhibit input pin. Normal operation programmed tying BUSY pins HIGH. desired, unintended write operations prevented port tying BUSY that port LOW. BUSY outputs IDT7015 master mode, pushpull type outputs require pull resistors operate. these RAMs being expanded depth, then BUSY indication resulting array requires external gate.
MASTER Dual Port BUSY BUSY SLAVE Dual Port BUSY BUSY
BUSY
MASTER Dual Port BUSY BUSY
SLAVE Dual Port BUSY BUSY
Figure Busy chip enable routing both width depth expansion with IDT7015 RAMs.
Width Expansion with Busy Logic Master/Slave Arrays
When expanding IDT7015 array width while using BUSY logic, master part used decide which side array will receive BUSY indication, output that indication. number slaves addressed same address range master BUSY signal write inhibit signal. Thus IDT7015 BUSY output part used master (M/S BUSY input part used slave (M/S shown Figure more master parts were used when expanding width, split decision could result with master indicating BUSY side array another master indicating BUSY other side array. This would inhibit write operations from port part word inhibit write operations from other port other part word. BUSY arbitration, master, based chip enable address signals only. ignores whether access read write. master/slave array, both address chip enable must valid long enough BUSY flag output from master before actual write pulse initiated with signal. Failure observe this timing result glitched internal write inhibit signal corrupted data slave.
left port slows access time right port. Both ports identical function standard CMOS Static read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE nonsemaphore location. Semaphores protected against such ambiguous situations used system program avoid conflicts non-semaphore portion Dual-Port RAM. These devices have automatic power-down feature controlled Dual-Port enable, SEM, semaphore enable. pins control on-chip power down circuitry that permits respective port into standby mode when selected. This condition which shown Truth Table where both HIGH. Systems which best IDT7015 contain multiple processors controllers typically very HIGH-speed systems which software controlled software intensive. These systems benefit from performance increase offered IDT7015's hardware semaphores, which provide lockout mechanism without requiring complex programming. Software handshaking between processors offers maximum system flexibility permitting shared resources allocated varying configurations. IDT7015 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using semaphores rather than more common methods hardware arbitration that wait states never incurred either processor. This prove major advantage very highspeed systems.
Semaphore Flags Work
semaphore logic eight latches which independent Dual-Port RAM. These latches used pass flag, token, from port other indicate that shared resource use. semaphores provide hardware assist assignment method called "Token Passing Allocation." this method, state semaphore latch used token indicating that shared resource use. left processor wants this resource, requests token setting latch. This processor then verifies success setting latch reading successful, proceeds assume control over shared resource. successful setting latch, determines that right side processor latch first, token using shared resource. left processor then either repeatedly request that semaphore's status remove request that semaphore
Semaphores
IDT7015 extremely fast Dual-Port 8Kx9 Static RAMs with additional address locations dedicated binary semaphore flags. These flags allow either processor left right side Dual-Port claim privilege over other processor functions defined system designer's software. example, semaphore used processor inhibit other from accessing portion DualPort other shared resource. Dual-Port features fast access time, both ports completely independent each other. This means that activity
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IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
perform another task occasionally attempt again gain control token test sequence. Once right side relinquished token, left side should succeed gaining control. semaphore flags active LOW. token requested writing zero into semaphore latch released when same side writes that latch. eight semaphore flags reside within IDT7015 separate memory space from Dual-Port RAM. This address space accessed placing input (which acts chip select semaphore flags) using other control pins (Address, R/W) they would used accessing standard static RAM. Each flags unique address which accessed either side through address pins When accessing semaphores, none other address pins effect. When writing semaphore, only data used. level written into unused semaphore location, that flag will zero that side other side (see Table That semaphore only modified side showing zero. When written into same location from same side, flag will both sides (unless semaphore request from other side pending) then written both sides. fact that side which able write zero into semaphore subsequently locks writes from other side what makes semaphore flags useful inter processor communications. thorough discussing this feature follows shortly.) zero written into same location from other side will stored semaphore request latch that side until semaphore freed first side. When semaphore flag read, value spread into data bits that flag that reads data bits flag containing zero reads zeros. read value latched into side's output register when that side's semaphore select (SEM) output enable (OE) signals active. This serves disallow semaphore from changing state middle read cycle write cycle from other side. Because this latch, repeated read semaphore test loop must cause either signal (SEM inactive output will never change. sequence WRITE/READ must used semaphore order guarantee that system level contention will occur. processor requests access shared resources attempting write zero into semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, fact which processor will verify subsequent read (see Table example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written successfully that location will assume control over resource question. Meanwhile, processor right side attempts write zero same semaphore flag will fail, will verified fact that will read from that semaphore right side during subsequent read. sequence READ/WRITE been used instead, system contention problems could have occurred during between read write cycles. important note that failed semaphore request must followed either repeated reads writing into same location. reason this easily understood looking simple logic diagram semaphore flag Figure semaphore request latches feed into semaphore flag. Whichever latch first present zero
semaphore flag will force side semaphore flag other side HIGH. This condition will continue until written same semaphore request latch. Should other side's semaphore request latch have been written zero meantime, semaphore flag will flip over other side soon written into first side's request latch. second side's flag will stay until semaphore request latch written one. From this easy understand that, semaphore requested processor which requested longer needs resource, entire system hang until written into that semaphore request latch. critical case semaphore timing when both sides request single token attempting write zero into same time. semaphore logic specially designed resolve this problem. simultaneous requests made, logic guarantees that only side receives token. side earlier than other making request, first side make request will receive token. both requests arrive same time, assignment will arbitrarily made port other. caution that should noted when using semaphores that semaphores alone guarantee that access resource secure. with powerful programming technique, semaphores misused misinterpreted, software error easily happen. Initialization semaphores automatic must handled initialization program power-up. Since semaphore request flag which contains zero must reset one, semaphores both sides should have written into them initialization from both sides assure that they will free when needed.
Using SemaphoresSome Examples
Perhaps simplest application semaphores their application resource markers IDT7015's Dual-Port RAM. divided into blocks which were dedicated time servicing either left right port. Semaphore could used indicate side which would control lower section memory, Semaphore could defined indicator upper section memory. take resource, this example lower Dual-Port RAM, processor left port could write then read zero Semaphore this task were successfully completed zero read back rather than one), left processor would assume control lower Meanwhile right processor attempting gain control resource after left processor, would read back response zero attempted write into Semaphore this point, software could choose gain control second section writing, then reading zero into Semaphore succeeded gaining control, would lock left side. Once left side finished with task, would write Semaphore then gain access Semaphore Semaphore still occupied right side, left side could undo semaphore request perform other tasks until able write, then read zero into Semaphore right processor performs similar task with Semaphore this protocol would allow processors swap blocks Dual-Port with each other. blocks have particular size even variable, depending upon complexity software using
6.42
IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
semaphore flags. eight semaphores could used divide DualPort other shared resources into eight parts. Semaphores even assigned different meanings different sides rather than being given common meaning shown example above. Semaphores useful form arbitration systems like disk interfaces where must locked section memory during transfer device cannot tolerate wait states. With semaphores, once devices determined which memory area "off-limits" CPU, both devices could access their assigned portions memory continuously without wait states. Semaphores also useful applications where memory "WAIT" state available both sides. Once semaphore handshake been performed, both processors access their assigned
segments full speed. Another application area complex data structures. this case, block arbitration very important. this application processor responsible building updating data structure. other processor then reads interprets that data structure. interpreting processor reads incomplete data structure, major error condition exist. Therefore, some sort arbitration must used between different processors. building processor arbitrates block, locks then able update data structure. When update completed, data structure block released. This allows interpreting processor come back read complete data structure, thereby guaranteeing consistent data structure.
PORT SEMAPHORE REQUEST FLIP FLOP WRITE SEMAPHORE READ
PORT SEMAPHORE REQUEST FLIP FLOP
WRITE
SEMAPHORE READ
2954
Figure IDT7015 Semaphore Logic
6.42
IDT7015S/L High-Speed Dual-Port Static
Military, Industrial Commercial Temperature Ranges
Ordering Information
XXXXX Device Type Power Speed Package Process/ Temperature Range Blank I(1) Commercial (0°C +70°C) Industrial (-40°C +85°C) Military (-55°C +125°C) Compliant MIL-PRF-38535 80-pin TQFP (PN80-1) 68-pin (G68-1) 68-pin PLCC (J68-1) Commercial Only Commercial Only Commercial Only Commercial Military Commercial Military Commercial Military Standard Power Power Dual-Port
2954
7015
NOTE: Industrial temperature range available. specific speeds, packages powers contact your sales office.
Speed nanoseconds
Datasheet Document History
1/11/99: Initiated datasheet document history Converted format Cosmetic typographical corrections Pages Added additional notes configurations Changed drawing format Page Corrected number Replaced logo Page Increased storage temperature parameter Clarified parameter Page Electrical parameters-changed wording from "open" "disabled" Changed ±200mV notes
6/3/99: 11/10/99: 5/19/00:
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IDT7015S/L True Dual-Ported memory cells which allow simultaneous

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