Inverting Logic High-Current 3-State Outputs Drive LSTTL Loads Package

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Inverting Logic High-Current 3-State Outputs Drive LSTTL Loads Package

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SN54HC640, SN74HC640 OCTAL TRANSCEIVERS WITH 3-STATE OUTPUTS
Inverting Logic High-Current 3-State Outputs Drive LSTTL Loads Package Options Include Plastic Small-Outline (DW), Thin Shrink Small-Outline (PW), Ceramic Flat Packages, Ceramic Chip Carriers (FK), Standard Plastic Ceramic DIPs
SN54HC640 PACKAGE SN74HC640 PACKAGE (TOP VIEW)
description
These octal transceivers designed asynchronous two-way communication between data buses. These devices transmit data from from bus, depending upon level direction-control (DIR) input. output-enable (OE) input used disable device buses effectively isolated. SN54HC640 characterized operation over full military temperature range -55°C 125°C. SN74HC640 characterized operation from -40°C 85°C.
FUNCTION TABLE (each transceiver) INPUTS OPERATION data data Isolation
SN54HC640 PACKAGE (TOP VIEW)
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2000, Texas Instruments Incorporated
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SN54HC640, SN74HC640 OCTAL TRANSCEIVERS WITH 3-STATE OUTPUTS
logic symbol
[BA] [AB]
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
logic diagram (positive logic)
Seven Other Transceivers
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC640, SN74HC640 OCTAL TRANSCEIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 58°C/W package 69°C/W package 83°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD
recommended operating conditions (see Note
SN54HC640 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Input transition (rise fall) time 3.15 1.35 1000 SN74HC640 3.15 1.35 1000 UNIT
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC640, SN74HC640 OCTAL TRANSCEIVERS WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS -7.8 3.98 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.15 ±0.1 ±0.01 0.26 0.26 ±100 ±0.5 SN54HC640 ±1000 SN74HC640 3.84 5.34 0.33 0.33 ±1000 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) tdis 25°C SN54HC640 SN74HC640 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC640, SN74HC640 OCTAL TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 25°C SN54HC640 SN74HC640 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS load UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC640, SN74HC640 OCTAL TRANSCEIVERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
PARAMETER Test Point tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open Closed Open Closed Open Open
From Output Under Test (see Note
tdis
LOAD CIRCUIT Input tPLH In-Phase Output tPHL Out-of-Phase Output tPLH tPHL
Output Control (Low-Level Enabling) tPZL Output Waveform (See Note tPZH
tPLZ tPHZ
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
Input
Output Waveform (See Note
VOLTAGE WAVEFORM INPUT RISE FALL TIMES
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES 3-STATE OUTPUTS
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 2000, Texas Instruments Incorporated

Inverting Logic High-Current 3-State Outputs Drive LSTTL Loads Package

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