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Adapting PowerPC 405GP designs PowerNP NPe405
PowerPC Applications Microelectronics Research Triangle Park, ppcsupp@us.ibm.com http://www.chips.ibm.com
Abstract PowerNP NPe405 family PowerPC powered embedded controllers created wired communications applications. designs using NPe405L NPe405H take advantage prior design experience with 405GP head start porting hardware software. This document will outline major differences between 405GP, NPe405L, NPe405H. Overview Functional Changes Table shows feature comparison between 405GP NPe405. Feature
10/100 Ethernet Controller 32-channel HDLC Controller Multi-port HDLC Controller UART (16550) On-Chip Memory Controller (v2.2) Code Decompression External Controller SDRAM Controller Packaging
405GP
(MII) 8-wire, 4-wire 4Kbytes Addr, 8/16/32b Data Master/Slave, banks PC100/133 25mm, E-PBGA 27mm, E-PBGA 35mm, E-PBGA
NPe405L
(MII, RMII, SMII) ports 4Mbps port 8Mbps 9-wire, 8-wire Addr, 8/16b Data Slave only, banks PC100/133 23mm, E-PBGA
NPe405H
(MII, RMII, SMII) ports 4Mbps port 8Mbps port, single channel, 2Mbps each port 9-wire Addr, 8/16/32b Data Master/Slave, banks PC100/133 35mm, E-PBGA
Table 405GP versus NPe405 Feature Differences External Controller (EBC) 1.1.1 NPe405L NPe405L implements only slave interface 405GP number peripheral banks supported limited further reduce count package size, only address bits (4:31) data bits available.
1.1.2 NPe405H NPe405H implements same 405GP. Ethernet Controller ZMII Bridge NPe405 chips feature multiple Ethernet controllers. ZMII bridge provides capability Ethernet controllers connect external Ethernet PHYs that support Reduced Media Independent Interface (RMII), Serial Media Independent Interface (SMII), standard Media Independent Interface (MII). NPe405L allows Ethernet controller mode RMII SMII modes. NPe405H allows Ethernet controllers mode RMII SMII modes.
Available modes MII, SMII, RMII 10Mbps, RMII 100Mbps. modes selected poweron straps (see Strapping). Mixing modes, such RMII SMII, supported. UARTs (16550 compatible) 405GP provides 8-wire interface UART0 4-wire interface UART1. NPe405L 9-wire interface UART0 8-wire interface UART1. Ring Indicator (RI) Data Carrier Detect (DCD) signal UART1 provided GPIO. NPe405H 9-wire interfaces both UART0 UART1. 405GP controller configured perform operations using UART0. NPe405 adds capability perform with UART1. channel assignments UARTs shown Table channel 405GP Assignment NPe405 Assignment
Channel Channel Channel Channel UART0 Receive UART0 Transmit UART1 Receive UART1 Transmit UART0 Receive UART0 Transmit
Table Channel Assignments UARTs Packaging package types assignments 405GP, NPe405L, NPe405H unique. Packaging options each listed Table Refer appropriate datasheet complete package details. Signals Signal Changes default polarity acknowledge (DMAAck(0:3)) request (DMAReq(0:3)) signals changed NPe405 These signals default active low, their polarity programmed DMA0_POL register.
Strapping 3.2.1 NPe405L Strapping NPe405L requires significantly less boot strapping than 405GP. 405GP contains strapping pins configuration clock dividers. During reset, other clocks automatically configured strapping values. contrast, NPe405L's bypassed following power-on system reset internal system clock defaults SysClk input frequency (typically 25-66MHz). further divided down half this frequency. boot code must then program proper frequency, divisors CPC0_PLLMR register. Only strapping resistors required NPe405L. used determine width boot device, pins needed ZMII mode reset. datasheet details. 3.2.2 NPe405H Strapping NPe405H option booting using minimal strapping chip input pins, extensive clocking configuration through interface serial EEPROM. Full details TBD. Multiplexing (GPIO) GPIO assignments method programming GPIO have changed from 405GP NPe405. Table shows GPIO assignments each chip. Note that GPIO0, 24:31 available 405GP. Differences programming GPIO discussed Section 4.4.1. 405GP GPIO Assignments
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 Available TS1E TS2E TS1O TS2O TrcClk PerCS1* PerCS2* PerCS3* PerCS4* PerCS5* PerCS6* PerCS7* IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6
NPe405L GPIO Assignments
TrcClk TS1E TS2E TS1O TS2O DMAReq0* DMAReq1* DMAReq2* DMAReq3* DMAAck0* DMAAck1* DMAAck2* DMAAck3* IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6
NPe405H GPIO Assignments
GPIO TS1E TS2E TS1O TS2O DMAReq0* DMAReq1* DMAReq2* DMAReq3* PerCS4* DMAAck0* DMAAck1* DMAAck2* DMAAck3* PerCS5* IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6
GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31
Available Available Available Available Available Available Available Available
EOT0* [TC0*] EOT1* [TC1*] EOT2* [TC2*] EOT3* [TC3*] UART1_DCD* HDLCEX_Tx_En_A UART1_RI* HDLCEX_Tx_En_B GPIO Only PerWE*
PerCS6* EOT0* [TC0*] EOT1* [TC1*] EOT2* [TC2*] EOT3* [TC3*] PerCS7* PerCS1* PerCS2* PerCS3* TrcClk
Table GPIO Assignments
Programming Model Instruction Compatibility 405GP NPe405 PPC405 core 100% instruction compatible. Because some addresses have changed, highly recommended that code written 405GP ported NPe405 should recompiled. Memory Management Unit (MMU) contained PPC405 core. identical 405GP NPe405. Register 4.3.1 Processor Version Register (PVR) unique every PowerPC implementation. specific PVR. 4.3.2 Special Purpose Registers (SPR) SPRs contained within PPC405 core. only difference Core Configuration Register (CCR0). (LDBE, Load Debug Enable) reserved NPe405. This field related therefore implemented NPe405. 4.3.3 Device Control Registers (DCR) DCRs external processor core used configuration control on-chip peripherals. Some chip-top level DCRs have changed NPe405 addition DCRs added functions. Refer appropriate datasheet
4.3.3.1 Memory Comparison total address space 4Kbytes 405GP NPe405. memory three processors. Table below shows
405GP Function
Reserved Memory Controller External Controller Decompression On-Chip Memory Reserved Registers Reserved Bridge Reserved Power Management Power Management Interrupt Controller Reserved Reserved Reserved Controller Reserved MAL0 (Ethernet) Reserved Reserved Reserved
NPe405L Function
Reserved Memory Controller External Controller Reserved Reserved Reserved Arbiter Reserved PLB-OPB Bridge Reserved Reserved Clock/Power Management Interrupt Controller Interrupt Controller Reserved Miscellaneous Controller Reserved MAL0 (Ethernet) MAL1 (HDLCEX) Reserved Reserved
NPe405H Function
Reserved Memory Controller External Controller Reserved Reserved Reserved Arbiter Performance Counters PLB-OPB Bridge Reserved Reserved Clock/Power Management Interrupt Controller Interrupt Controller Reserved Miscellaneous Controller Reserved MAL0 (Ethernet) MAL1 (HDLCEX) MAL2 (HDLCMP) Reserved
Start Address (0:9)
Address (0:9)
Table Address 4.3.3.2 Chip Control Changes Most changes between 405GP NPe405L with addition functions; however, some basic chip control, clocking power management register functions have been modified. Table below shows changes. 405GP Address
Register Name
CPC0_PLLMR CPC0_CR0
NPe405L Address
Change Description
Configuration/Control address change, assignments GPIO control UART control 405GP GPIO control registers memory-mapped NPe405
CPC0_CR1 CPC0_EPRCSR CPC0_UCR CPC0_JTAGID CPC0_PSR CPC0_ER CPC0_FR CPC0_SR
Strapping address change, assignments CETE field moved from PCIPW field removed Ethernet clocking configuration (New NPe405) UART control configuration (New NPe405) JTAG address changed value strapping 405GP strapping NPe405 Power Management Enable assignments Address Power Management Force assignments Address Power Management Status assignments Address
Table Chip Control Register Changes System Memory system memory 405GP NPe405 family differs only function added, functions present. case where functions present given chip, HDLC example, memory marked reserved. Refer appropriate datasheets system memory maps each device. Memory comparison coming soon. 4.4.1 GPIO Programming Differences 4.4.1.1 GPIO Registers 405GP, GPIO enabled disabled using CPC0_CR0 register. Control GPIO NPe405 chips located within memory mapped registers GPIO peripheral. Table shows GPIO memory mapped registers.
Register
GPIO0_OR GPIO0_TCR GPIO0_OSR GPIO0_TSR GPIO0_ODR GPIO0_IR GPIO0_RR1 GPIO0_RR2 GPIO0_RR3 GPIO0_ISR1 GPIO0_ISR2 GPIO0_ISR3
Address
0xEF600700 0xEF600704 0xEF600708 0xEF600710 0xEF600718 0xEF60071C 0xEF600720 0xEF600724 0xEF600728 0xEF600730 0xEF600738 0xEF600740
Access
Description/Comments
Input Select1 Input Select2 Input Select3
Table NPe405 GPIO Registers
4.4.1.2 Programming NPe405 GPIO Examples program GPIO inputs, outputs, 3-state coming soon.
Interrupts 405GP uses single Universal Interrupt Controller (UIC0), which capable supporting interrupt sources. NPe405H NPe405L have more than possible interrupt sources. result, second added cascade with UIC0. interrupt structure NPe405L subset NPe405H. critical interrupt output UIC1 wired interrupt source UIC0, non-critical interrupt output UIC1 wired interrupt source UIC0. Because this nested structure, interrupts from UIC1 will take longer process because extra read appropriate checking needed. Because different peripheral mix, interrupt assignments from 405GP have changed NPe405. Table Table provide complete interrupt assignments three processors. UIC0 Interrupt
405GP Interrupt Source
UART0 UART1 External Master Channel Channel Channel Channel Ethernet Wake System Error (SERR) Buffer (TXEOB0) Buffer (RXEOB) Descriptor Error (TXDE) Descriptor Error (RXDE) Ethernet External SERR Correctable Error Power Management reserved reserved reserved reserved reserved reserved External External External External External External External
NPe405L Interrupt Source
UART0 UART1 Channel Channel Channel Channel HDLCEX_ACTCMP HDLCEX_SOP HDLCEX_ACTIVELINE HDLCEX_IDLELINE reserved reserved reserved reserved MAL1 Buffer MAL1 Buffer MAL0 Buffer MAL0 Buffer reserved reserved External External External External External External External reserved reserved UIC1 non-critical interrupt UIC1 critical interrupt
NPe405H Interrupt Source
UART0 UART1 Channel Channel Channel Channel HDLCEX_ACTCMP HDLCEX_SOP HDLCEX_ACTIVELINE HDLCEX_IDLELINE HDLCMP_ACTCMP HDLCMP_SOP HDLCMP_ACTIVELINE HDLCMP_IDLELINE MAL1 Buffer MAL1 Buffer MAL0 Buffer MAL0 Buffer MAL2 Buffer MAL2 Buffer External External External External External External External reserved reserved UIC1 non-critical interrupt UIC1 critical interrupt
Table UIC0 Interrupt Sources
UIC1 Interrupt
NPe405L Interrupt Source
Correctable Error Reserved Reserved Reserved Reserved Ethernet Ethernet Reserved Reserved Ethernet Wakeup MAL1 System Error MAL1 Descriptor Error MAL1 Descriptor Error MAL0 System Error MAL0 Descriptor Error MAL0 Descriptor Error Reserved Reserved Reserved HDLCEX Underrun Error HDLCEX Overrun Error HDLCEX Processing Error HDLCEX Retransmit Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
NPe405H Interrupt Source
Correctable Error External Master Power Management Command Written System Error Ethernet Ethernet Ethernet Ethernet Ethernet Wakeup MAL0 System Error MAL1 Descriptor Error MAL1 Descriptor Error MAL0 System Error MAL0 Descriptor Error MAL0 Descriptor Error MAL2 System Error MAL2 Descriptor Error MAL2 Descriptor Error HDLCEX Underrun Error HDLCEX Overrun Error HDLCEX Processing Error HDLCEX Retransmit HDLCMP Underrun Error HDLCMP Overrun Error Performance Counter Reserved Reserved Reserved Reserved Reserved Reserved
Table UIC1 Interrupt Sources (not present 405GP) Code Porting Considerations References 405GP datasheet. NPe405L datasheet NPe405H datasheet 405GP User's Manual
NPe405H User's manual NPe405L User's manual
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