133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential Out
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CY283
133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential Outputs
Features Compliant Intel® CK-408B Clock Synthesizer/Driver Specifications Multiple output clocks different frequencies Four pairs differential outputs, synchronous clocks, three free-running 3V66 clocks 48-MHz clocks reference clock 14.318 clock Spread Spectrum clocking (down spread) Power-down features (PCI_STOP#, PWR_DWN#) Three Select inputs (Mode select Frequency Select) Test Mode support 56-pin SSOP package 56-pin TSSOP package Enables reduction overall system cost Enables ACPI compliant designs Supports four clock frequencies Enables "bed nails" testing Widely available, standard package enables lower cost Benefits Supports next generation Pentium® processors using differential clock drivers Motherboard clock generator Support Multiple CPUs chipset Support slots chipset Supports AGP, DRCG reference Link Supports host controller graphic controller Supports slots chip
Logic Block Diagram
VDD_REF
Configurations
SSOP TSSOP View
VDD_REF XTAL_IN XTAL_OUT GND_REF PCI_F0 VDD_CPU CPU0:3 CPU#0:3 PCI_F1 PCI_F2 VDD_PCI GND_PCI PCI0
Stop Clock Control
XTAL
CPU3 CPU3# CPU0 CPU#0 VDD_CPU CPU1 CPU#1 GND_CPU VDD_CPU CPU2 CPU#2 MULT0 IREF GND_IREF VDD_ GND_ 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA
Freq
Mult0 S1:2 PWR_GD#
Gate
Divider Network
VDD_PCI PCI_F0:2 PCI0:6
PCI1 PCI2 PCI3 VDD_PCI
CY283
PCI_STOP#
PWR_DWN#
VDD_3V66 3V66_0 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN
GND_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PWR_DWN# VDD_CORE GND_CORE PWR_GD#
VDD_48MHz
(48MHz) (48MHz) VCH_CLK/ 3V66_1
SDATA SCLK
SMBus Logic
Cypress Semiconductor Corporation Document 38-07040 Rev.
3901 North First Street
Jose
95134 408-943-2600 Revised April 2002
CY283Pin Summary
Name XTAL_IN XTAL_OUT CPU, CPU# [0:3] 3V66_0 3V66_1/VCH 66IN/3V66_5 66BUFF [0:2] /3V66 [2:4] PCI_F [0:2] [0:6] IREF MULT0 PWR_DWN# PCI_STOP# PWR_GD# Pins Description 3.3V 14.318-MHz clock output 14.318-MHz crystal input 14.318-MHz crystal input Differential clock outputs 3.3V 66-MHz clock output 3.3V selectable through SMBus 66-MHz input buffered 66BUFF 66-MHz clock from internal 66-MHz buffered outputs from 66Input 66-MHz clocks from internal 33-MHz clocks divided down from 66Input divided down from 3V66
clock outputs divided down from 66Input divided down from 3V66 Fixed 48-MHz clock output Fixed 48-MHz clock output Special 3.3V 3-level input Mode selection 3.3V LVTTL inputs frequency selection precision resistor attached this which connected internal current reference 3.3V LVTTL input selecting current multiplier outputs 3.3V LVTTL input Power_Down# (active LOW) 3.3V LVTTL input PCI_STOP# (active LOW) 3.3V LVTTL input level-sensitive strobe used determine when S[1:2] MULT0 inputs valid sampled (Active LOW). PWRGD# sampled LOW, status this output will ignored. SMBus compatible SDATA SMBus compatible Sclk
SDATA SCLK VDD_REF, VDD_PCI, VDD_3V66, VDD_48 MHz, VDD_CPU VDD_CORE GND_REF, GND_PCI, GND_3V66, GND_IREF, VDD_CPU GND_CORE
3.3V power supply outputs
3.3V power supply
Ground outputs
Ground
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CY283Function Table[1]
(MHz) Hi-Z TCLK/2 3V66[0:1] (MHz) Hi-Z TCLK/4 66BUFF[0:2]/ 3V66[2:4] (MHz) 66IN 66IN Hi-Z TCLK/4 66IN/3V66_5 (MHz) Input Input Input Input Hi-Z TCLK/4 PCI_F/PCI (MHz) 66IN/2 66IN/2 Hi-Z TCLK/8 REF0(MHz) 14.318 14.318 14.318 14.318 Hi-Z TCLK USB/DOT (MHz) Hi-Z TCLK/2 Notes
Notes: TCLK test clock driven XTALIN input test mode. "Normal" mode operation. Range reference frequency allowed min. 14.316 nominal 14.31818 MHz, max. 14.32 MHz. Frequency accuracy must +167 match default. Required board level "bed nails" testing. defined Voltage level between 1.0V 1.8V level input functionality. below 0.8V. High above 2.0V.
Swing Select Functions
Mult0 Board Target Trace/Term Reference IREF VDD/(3*Rr) IREF 5.00mA IREF 2.32mA Output Current 4*Iref 6*Iref 1.0V 0.7V
Clock Driver Impedances
Impedance Buffer Name CPU, CPU# PCI, 3V66, 66BUFF 3.135-3.465 3.135-3.465 3.135-3.465 3.135-3.465 Range Buffer Type Type Type Type Type Type Minimum Typical Maximum
Clock Enable Configuration
PWR_DWN# PCI_STOP# IREF*2 CPU# FLOAT 3V66 66BUFF PCI_F USB/DOT VCOS/OSC
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CY283Serial Data Interface (SMBus)
enhance flexibility function clock synthesizer, signal SMBus interface provided according SMBus specification. Through Serial Data Interface, various device functions such individual clock output buffers, individually enabled disabled. CY28329 support both block read block write operations. registers associated with Serial Data Interface initializes default setting upon power-up, therefore this interface optional. Clock device register changes normally made upon system initialization, required. interface also used during system operation power management functions. Data Protocol clock driver serial protocol accepts only Block Writes from controller. bytes must accessed sequential order from lowest highest byte, (most significant first) with ability stop after complete byte been transferred. Indexed bytes allowed. Block write begins with slave address WRITE condition. used SMBus controller data direction bit. zero indicates WRITE condition clock device. slave receiver address 11010010 (D2h). command code 0000 0000 (00h) byte count bytes required transfer. After command code, core logic issues byte count, which describes number additional bytes required transfer, including command code byte count bytes. example, host data bytes send, first byte would number (14h), followed bytes data. byte count byte required minimum byte maximum bytes Figure shows example block write. transfer considered valid after acknowledge corresponding byte count read controller.
Start Slave Address bits
Command Code Byte Count 00000000 bits bits
Data Byte bits
Data Byte bits
Stop
From Master Slave From Slave Master Figure Example Block Write
Data Byte Configuration
Data Byte Control Register Enable, Disable) Affected Pin# -10, -Name [0:6] CPU[3:0] 3V66[1:0] 3V66_1/VCH -PCI [6:0] Description Spread Spectrum Enable Spread Off, Spread Type Power Default
Select MHz/48 MHz, Reserved PCI_STOP# (Does affect PCI_F [2:0] pins) Reflects value sampled Power-up Reflects value sampled Power-up Reserved
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CY283Data Byte Pin# -53, -44, CPU3 CPU3# -CPU2 CPU2# CPU1 CPU1# CPU0 CPU0# Name Mult0 Value CPU3 Output Enable Enabled; Disabled Reserved Reserved Reserved CPU2 Output Enable Enabled; Disabled CPU1Output Enable Enabled; Disabled CPU0 Output Enable Enabled; Disabled Description Type Power Default
Data Byte Pin# PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Name PCI6 Output Enable Enabled; Disabled PCI5 Output Enable Enabled; Disabled PCI4 Output Enable Enabled; Disabled PCI3 Output Enable Enabled; Disabled PCI2 Output Enable Enabled; Disabled PCI1 Output Enable Enabled; Disabled PCI0 Output Enable Enabled; Disabled Description Type Power Default
Data Byte Pin# PCI_F2 PCI_F1 PCI_F0 PCI_F2 PCI_F1 PCI_F0 Name Description Output Enable Output Enable Allow control PCI_F2 with assertion PCI_STOP# Free running; Stopped with PCI_STOP# Allow control PCI_F1 with assertion PCI_STOP# Free running; Stopped with PCI_STOP# Allow control PCI_F0 with assertion PCI_STOP# Free running; Stopped with PCI_STOP# PCI_F2 Output Enable PCI_F1Output Enable PCI_F0 Output Enable Type Power Default Page
Document 38-07040 Rev.
CY283Data Byte Pin# 3V66_0 3V66_1/VCH 66IN/3V66_5 Name 3V66_0 Output Enable Enabled; Disabled 3V66_1/VCH Output Enable Enabled; Disabled 3V66_5 Output Enable Enable; Disable Note: This should used when configured 3V66_5 output. clear this when configured 66IN input. 66BUFF2 66BUFF1 66BUFF0 66-MHz Buffered Output Enable Enabled; Disabled 66-MHz Buffered Output Enable Enabled; Disabled 66-MHz Buffered Output Enable Enabled; Disabled Description Type Power Default
Data Byte Pin# 66BUFF [2:0] 66BUFF [2:0] edge rate control edge rate control Name 66IN 66BUFF propagation delay control Description Type Power Default
Byte Vendor Description Revision Code Revision Code Revision Code Revision Code Vendor Vendor Vendor Vendor Type Power Default
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CY283Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Supply Voltage .-0.5 +7.0V Input Voltage -0.5V VDD+0.5 Storage Temperature (Non-Condensing) -65°C +150°C Max. Soldering Temperature sec) +260°C Junction Temperature. +150°C Package Power Dissipation.1 Static Discharge Voltage (per MIL-STD-883, Method 3015) >2000V
Operating Conditions Over which Electrical Parameters Guaranteed
Parameter VDD_REF, VDD_PCI,VDD_CORE, VDD_3V66, VDD_48 MHz, VDD_CPU, CXTAL Description 3.3V Supply Voltages Operating Temperature, Ambient Input Capacitance XTAL Capacitance Max. Capacitive Load USBCLK, PCICLK, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 Max. 3.465 22.5 14.318 Unit
f(REF)
Electrical Characteristics Over Operating Range
Parameter Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input High Current Input Current High-level Output Current Except Crystal Pads USB, REF, 3V66 USB, REF, 3V66 =6*IRef Configuration REF, DOT, 3V66, DOT, Low-level Output Current REF, DOT, 3V66, IDD3 IDDPD3 IDDPD3 Output Leakage Current 3.3V Shutdown Current 3.3V Shutdown Current Three-state VDD_CORE/VDD3.3 3.465V IREF 2.32 VDD_CORE/VDD3.3 3.465V IREF Type 0.65V Type 0.74V Type 1.00V Type 3.135V Type 1.00V Type 3.135V Type 1.95V Type 0.4V Type =1.95 Type 0.4V 3.3V Power Supply Current VDD_CORE/VDD3.3 3.465V, FCPU 12.9 14.9 0.55 Test Conditions Except Crystal Pads. Threshold voltage crystal pads VDD/2 Min. Max. Unit
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CY283-
Switching Characteristics[7] Over Operating Range
Parameter Vcrossover USB, REF, PCI, 3V66, USB, REF, PCI, 3V66 3V66 [0:1] 66BUFF[0:2] 3V66, 3V66 USB, Output Description Output Duty Rise Time Rising Edge Rate Rising Edge Rate Fall Time Falling Edge Rate Falling Edge Rate CPU-CPU Skew 3V66-3V66 Skew 66BUFF-66BUFF Skew PCI-PCI Skew 3V66-PCI Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Rise/Fall Matching High-level Output Voltage including overshoot Low-level Output Voltage including undershoot Crossover Voltage Cycle[8] Test Conditions Measured 1.5V Measured differential waveform from -0.35V +0.35V Between 0.4V 2.4V Between 0.4V 2.4V Measured differential waveform from -0.35V +0.35V Between 2.4V 0.4V Between 2.4V 0.4V Measured Crossover Measured 1.5V Measured 1.5V Measured 1.5V 3V66 leads. Measured 1.5V Measured Crossover With outputs running Measured 1.5V Measured 1.5V Measured 1.5V Measured 1.5V Measured with test Measured with test loads[9, loads[10] 0.92 -0.2 0.250 Min. Max. 1000 1.45 0.35 0.550 Unit V/ns V/ns
Measured with test loads[10] Measured with test loads[10]
Notes: parameters specified with loaded outputs. Duty cycle measured 1.5V when 3.3V. When 2.5V, duty cycle measured 1.25V. Determined fraction 2*(Trp Trn)/(Trp +Trn) Where rising edge intersecting falling edge. test load 33.2W, 49.9W test circuit.
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CY283Definition Application PWRGD# Signal
VRM8.5 PWRGD#
BSEL0
BSEL1
3.3V 3.3V
3.3V
PWRGD#
CLOCK GENERATOR
GMCH
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CY283Switching Waveforms
Duty Cycle Timing (Single Ended Output)
Duty Cycle Timing (CPU Differential Output)
Outputs Rise/Fall Time
OUTPUT
CPU-CPU Clock Skew
Host_b Host Host_b Host
3V66-3V66 Clock Skew
3V66
3V66
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CY283Switching Waveforms (continued)
PCI-PCI Clock Skew
3V66-PCI Clock Skew
3V66
Clock Cycle-Cycle Jitter
Host_b Host
Cycle-Cycle Clock Jitter
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CY283PWRDWN# Assertion
66BUFF PCI_F (APIC) PWR_DWN# CPU# 3V66 66IN
UNDEF Power Down Rest Generator
Note: PCI_STOP# asserted
PWRDWN# Deassertion
66BUFF1/GMCH 66BUFF0,2 PCI_F (APIC) PWR_DWN# CPU# 3V66 66IN
10-30 min. 100-200 max.
Note: PCI_STOP# asserted
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CY283PWRGD# Timing Diagrams
5/12V PWRGD# [3:0] BSEL [1:0] PWRGD# FROM PWRGD# FROM CORE PWRGD# CLOCK CLOCK STATE State CLOCK CLOCK OUTPUTS
0.2-0.3 delay Wait PWRGD# Sample BSELS
Possible glitch while Clock coming Will gone 0.2-0.3 delay.
State
State
State
Figure Power BEFORE Clock Power
5/12V PWRGD# [3:0] BSEL [1:0] PWRGD# FROM PWRGD# FROM
CORE PWRGD# CLOCK CLOCK STATE State CLOCK LOCK OUTPUTS
0.2-0.3 delay Wait PWRGD# Sample BSELS
State
State
State
Figure Power AFTER Clock Power
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CY283Layout Example
+3.3V Supply
VDDQ3
0.005
Dale ILB1206 2TDKACB2012L-120 Murata BLM21B601S Ceramic Caps 10-22 plane layer 0.005 =VIA respective supply plane layer
Note: Each supply plane strip should have ferrite bead capacitors
CY283
VDDQ3
Document 38-07040 Rev.
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CY283Test Circuit
VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU
19,32,37, OUTPUTS PCI,3V66 Outputs Test Nodes
Test Node
Ref,USB Outputs
CY283
Test Node
Note: Each supply must have individual decoupling capacitor. Note: capacitors must placed close pins physically possible.
Ordering Information
Ordering Code CY28329PVC CY28329ZC Package Type 56-Pin Small Shrunk Outline Package (SSOP) 56-Pin Thin Small Shrunk Outline Package (TSSOP) Operating Range Commercial Commercial
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CY283Package Diagrams
56-Lead Shrunk Small Outline Package
51-85062-*C
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CY283Package Diagrams (continued)
56-Pin Thin Shrink Small Outline Package
Intel Pentium registered trademarks Intel Corporation. products company names mentioned this document trademarks their respective holders.
Document 38-07040 Rev.
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Cypress Semiconductor Corporation, 2002. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.
CY283Revision History
Document Title: CY28329 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential Outputs Document Number: 38-07040 REV. 115133 Issue Date 04/26/02 Orig. Change Description Change Change from Spec number: 38-01147 38-07040 Preliminary Final
Document 38-07040 Rev.
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