SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation outp

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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation outp

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QS5930T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
operation output, outputs Useful Pentium, PowerPC, systems Internal loop filter network noise level outputs <250ps rising edge output skew Balanced drive outputs ±24mA bypass feature frequency testing Internal VCO/2 option wider frequency range Outputs tri-state reset while OE/RST 2000V Latch -300mA Available QSOP package
QS5930T
DESCRIPTION
QS5930T Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock input. outputs available: Q0-Q4, Q/2. Careful layout design ensure 250ps skew between Q0-Q4, outputs. QS5930T includes internal filter which provides excellent jitter characteristics eliminates need external components. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. QS5930T designed cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QSOP package, QS5930T clock driver represents best value small form factor, high-performance clock management products. more information clock driver products, Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK PLL_EN FREQ _SEL
SYNC E/RST
DETECTO FILTER
2000 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-5849
QS5930T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol Rating AVDD,VDD Supply Voltage Ground Max. -0.5 -0.5 Input Voltage Input Voltage (for pulse width 20ns) TSTG Maximum Power Dissipation 85°C) Storage Temperature Range
Unit
OE/RST FEEDBACK AVDD AGND SYNC FREQ_SEL
PLL_EN
+150
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE 1MHz,
Pins COUT Typ. Max. Unit
QSOP VIEW
DESCRIPTION
Name SYNC FREQ_SEL FEEDBACK OE/RST PLL_EN AVDD AGND Reference clock input frequency select. choosing optimal operating frequency depending input frequency. HIGH higher frequencies, lower frequencies. feedback input which connected either output. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched phase, frequency half frequency. Output enable/asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled. enable. Enables disables PLL. Allows SYNC input single-stepped system debug. Power supply output buffers. Power supply phase lock loop other internal circuitries. Ground supply output buffers. Ground supply phase lock loop other internal circuitries. Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: -40°C +85°C, AVDD/VDD
Symbol FMAX_Q FMAX_Q/2 FMIN_Q FMIN_Q/2 Description Frequency, Frequency, Frequency, Frequency, Units
QS5930T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
FREQ_SEL HIGH HIGH Output Used Feedback SYNC (MHz) (allowable range) Min. FMAX _Q/2 FMAX FMAX _Q/2 FMAX Output Frequency Relationships SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC
NOTE: Operation specified SYNC frequency range guarantees that will operate optimal range 28MHz FMAX_Q Operation with Sync inputs outside specified frequency ranges result out-of-lock outputs. FREQ_SEL only affects frequency does affect output frequencies.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, AVDD/VDD
Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level -24mA -100µA Min., 24mA Min., 100µA VOUT GND, Max., Outputs Disabled AVDD Max., AVDD Min. Typ. Max. 0.55 Unit
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDDD Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current Test Conditions Max., OE/RST LOW, SYNC LOW, outputs unloaded Max., Max., Typ. Max. Unit mA/MHz
INPUT TIMING REQUIREMENTS
Symbol tPWC Description Maximum input rise fall times, 0.8V Input Clock Frequency, SYNC Duty Cycle, SYNC
Min.
Max. FMAX
Unit
Input clock pulse, HIGH
NOTES: Output Frequency Frequency Selection tables more detail allowable SYNC input frequencies different speed grades with different FEEDBACK FREQ_SEL combinations. Where pulse witdh implied less than tWPC limit, tWPC limit applies
QS5930T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tPZH tPZL tPHZ tPLZ Parameter Output Skew Between Rising Edges, Q0-Q4 (and Q/2) Output Skew Between Falling Edges, Q0-Q4 (and Q/2) Pulse Width, Q0-Q4, outputs, 80MHz Cycle-to-Cycle Jitter, 33MHz
Min. TCY/2
Max. TCY/2 +400
Unit
SYNC Input Feedback Delay Output Enable Time, OE/RST HIGH Output Disable Time, OE/RST HIGH Output Rise/Fall Times, 0.8V
NOTES: Test Loads Waveforms test load termination. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). Measured open loop mode PLL_EN Jitter characterized with output 20MHz. Frequency Selection Table information proper FREQ_SEL level specified input frequencies. measured device inputs 1.5V, output 28MHz.
QS5930T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TEST LOADS WAVEFORMS
7.0V OUTPUT
OUTPUT
30pF
28pF
TEST CIRCUIT
TEST CIRCUIT
OPERATION
Phase Locked Loop (PLL) circuit included QS5930T provides replication incoming SYNC clock signals. manipulation that signal, such frequency multiplying, performed digital logic following (see block diagram). advantage circuit provide effective zero propagation delay between output input signals. fact, adding delay circuits feedback path, `propagation delay' even negative! simplified schematic QS5930T circuit shown below:
SIMPLIFIED DIAGRAM QS5930T FEEDBACK
INPU PHASE DETECTO
VCO/2
phase difference between output input frequencies feeds which drives outputs. Whichever output back, will stabilize same frequency input. Hence, this true negative feedback closed loop system. most applications, output will optimally have zero phase shift with respect input. fact, internal loop filter QS5930T typically provides within 150ps phase shift between input output.
user wishes vary phase difference (typically compensate backplane delays), this most easily accomplished adding delay circuits feedback path. respective output used feedback will advanced amount delay feedback path. other outputs will retain their proper relationships that output.
QS5930T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
XXXX Device Type Speed Package Process
Blank
Industrial (-40°C +85°C)
Quarter Size Outline Package
-50T -66T
50MHz. max. frequency 66MHz. max. frequency
5930
Skew CMOS Clock Driver with Integrated Loop Filter
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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation outp

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