SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER QS5917T o

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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER QS5917T o

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QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
QS5917T
operation output, output, output Outputs tri-state while Internal loop filter network noise level outputs 500ps output skew, Q0-Q4 disable feature frequency testing Balanced Drive Outputs 24mA 132MHz maximum frequency (2xQ output) Functional equivalent Motorola MC88915 2000V Latch-up -300mA Available QSOP PLCC packages
DESCRIPTION
QS5917T Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock inputs. Eight outputs available: Q0-Q4, 2xQ, Q/2, Careful layout design insures 500ps skew between Q0-Q4, outputs. QS5917T includes internal filter which provides excellent jitter characteristics eliminates need external components. addition, level outputs reduce clock signal noise. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. LOCK output asserts indicate when phase lock been achieved. QS5917T designed high-performance workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. more information clock driver products, Application Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LOCK
FEEDBACK
PLL_EN
FREQ_SEL
SYNC0 SYNC1
PHASE DETECTOR LOOP FILTER
logo registered trademark Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
JULY 2000
DSC-5227/2
QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CONFIGURATION
FEEDBACK REF_SEL SYNC0 AVDD AGND SYNC1 FREQ_SEL
LOCK PLL_EN
FEEDBACK REF_SEL SYNC0 AVDD AGND SYNC1
LOCK
Max.
FREQ_SEL
QSOP VIEW
PLCC VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Supply Voltage Ground Input Voltage Input Voltage (pulse width 20ns) Maximum Power Dissipation 85°C) TSTG Storage Temperature Range -0.5 -0.5 +150
Unit
CAPACITANCE +25°C, 1.0MHz,
QSOP Parameter COUT Typ. Max. Typ. PLCC Unit
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
PLL_EN
QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
DESCRIPTION
Names SYNC SYNC REF_SEL FREQ_SEL FEEDBACK LOCK PLL_EN Reference clock input Reference clock input Reference clock select. When selects SYNC1. When selects SYNC0. frequency select. choosing optimal operating frequency depending input frequency. feedback input which connected user selected output pin. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched frequency, inverted with respect Clock output. Matched phase, frequency double frequency. Clock output. Matched phase, frequency half frequency. lock indication signal. indicates positive lock. indicates that locked outputs synchronized inputs. Asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled (normal operation). enable. When enabled (normal operation). When disabled (for testing purposes). Connection Description
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: -40°C +85°C, AVDD/VDD
Symbol F2XQ FQ/2 Description Frequency, output Frequency, outputs Frequency, output 17.5 Units
QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
SYNC (MHz) FREQ_SEL Output Used Feedback (allowable range) Min. F2XQ F2XQ F2XQ F2XQ F2XQ F2XQ F2XQ F2XQ SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC Output Frequency Relationships Outputs SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC SYNC
NOTE: -132 speed grade, maximum input frequency restricted 100MHz.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, AVDD/VDD
Symbol Parameter Input HIGH Voltage Level Input Voltage Level Output HIGH Voltage Output Voltage Output Leakage Current Input Leakage Current Test Conditions Guaranteed Logic HIGH level Guaranteed Logic level Min., -24mA Min., -100µA Min., 24mA Min., 100µA VOUT GND, Max. AVDD GND, AVDD Max. Min. Typ. Max. 0.55 Unit
NOTE: 12mA -12mA, respectively, LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Input Power Supply Current Input HIGH Dynamic Power Supply Current Test Conditions Max., 3.4V Typ. Max. Unit mA/MHz
NOTES: conditions shown Min. Max., appropriate values specified under Electrical Characteristics. This specification does apply PLL_EN input.
QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INPUT TIMING REQUIREMENTS
Symbol tPWC Input Clock Frequency, Description Maximum input rise fall times, 0.8V SYNC0, SYNC1 Input clock pulse, HIGH Duty cycle, SYNC0, SYNC1 Min. Max. F2XQ Unit
NOTE: specification based output feedback. Frequency Selection Table more detail allowable SYNC input frequencies different feedback combinations.
SWITCHING CHARACTERISTICS(1)
Symbol tSKR tSKF tSKALL tLOCK tPZH tPZL tPHZ tPLZ Output Rise/Fall Times, 0.8V Output Disable Time, HIGH Parameter Output Skew Between Rising Edges, Q0-Q4 Output Skew Between Falling Edges, Q0-Q4 Output Skew, Outputs
Min. TCY/2 0.65
Max. TCY/2 0.65 TCY/2 0.25
Unit
Pulse Width, outputs Pulse Width, Q0-Q4, outputs Cycle-to-Cycle Jitter, 33MHz
TCY/2
SYNC Input Feedback Delay, 28MHz SYNC Input Feedback Delay, 33MHz, 1.5V SYNC Phase Lock Output Enable Time, HIGH
NOTES: Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). Measured open loop mode PLL_EN Jitter characterized using oscilloscope. Measurement taken cycle after jitter. Jitter characterized tested. FREQUENCY SELECTION TABLE information proper FREQ_SEL level specified input frequencies.
QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TEST LOAD
7.0V OUTPUT 20pF
OUTPUT
30pF
TEST CIRCUIT
TEST CIRCUIT
TEST CIRCUIT used output enable/disable parameters. TEST CIRCUIT used other timing parameters.
OPERATION
Phase Locked Loop (PLL) circuit included QS5917T provides replication incoming SYNC clock signals. manipulation that signal, such frequency multiplying inversion performed digital logic following (see block diagram). advantage circuit provide effective zero propagation delay between output input signals. fact, adding delay circuits feedback path, `propagation delay' even negative! simplified schematic QS5917T circuit shown below.
SIMPLIFIED DIAGRAM QS5917T FEEDBACK
INPUT PHASE DETECTOR
phase difference between output input frequencies feeds which drives outputs. Whichever output back, will stabilize same frequency input. Hence, this true negative feedback closed loop system. most applications, output will optimally have zero phase shift with respect input. fact, internal loop filter QS5917T typically provides within 150ps phase shift between input output.
user wishes vary phase difference (typically compensate backplane delays), this most easily accomplished adding delay circuits feedback path. respective output used feedback will advanced amount delay feedback path. other outputs will retain their proper relationships that output.
QS5917T SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
XXXX Device Type Speed Package Process
Blank
Industrial (-40°C +85°C)
Quarter Size Outline Package Plastic Leaded Chip Carrier
-70T -100T -132T 5917T
70MHz Max. Frequency 100MHz Max. Frequency 132MHz Max. Frequency Skew CMOS Clock Driver with Integrated Loop Filter
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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER QS5917T o

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