Available 1.13 GHz, GHz, 933, 866, 800EB, 733, 667, 600EB, 533EB syste
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Pentium® Processor PGA370 Socket 1.13
Available 1.13 GHz, GHz, 933, 866, 800EB, 733, 667, 600EB, 533EB system Available 1.10 GHz, GHz, 900, 850, 800, 750, 700, 650, 600E, 550E, 500E system System frequency ("E" denotes support Advanced Transfer Cache Advanced system buffering; denotes support system where both frequencies available order each given core frequency; Table summary features each line item.) Available versions that incorporate 256-KB Advanced Transfer Cache (on-die, full speed Level (L2) cache with Error Correcting Code (ECC)) Dual Independent (DIB) architecture: Separate dedicated external System dedicated internal high-speed cache Internet Streaming SIMD Extensions enhanced video, sound performance Binary compatible with applications running previous members Intel microprocessor line
Dynamic execution micro architecture Intel Processor Serial Number Power Management capabilities System Management mode Multiple low-power states Optimized 32-bit applications running advanced 32-bit operating systems Flip Chip Grid Array (FC-PGA/FC-PGA2) packaging technology; FC-PGA/FC-PGA2 processors deliver high performance with improved handling protection socketability Integrated high performance 16-KB instruction 16-KB data, nonblocking, level cache 256-KB Integrated Full Speed level cache allows latency read/store operations Double Quad Word Wide (256 bit) cache data provides extremely high throughput read/store operations. 8-way cache associativity provides improved cache rate reads/store operations. Error-correcting code System data Enables systems which scaleable processor
Pentium® processor designed high-performance desktops workstations servers. binary compatible with previous Intel Architecture processors. Pentium processor provides great performance applications running advanced operating systems such Windows* Windows UNIX*. This achieved integrating best attributes Intel processors- dynamic execution, Dual Independent architecture plus Intel MMXtechnology Internet Streaming SIMD Extentions- bringing level performance systems buyers. Pentium processor scaleable processors multiprocessor system extends power Pentium® processor with performance headroom business media, communication internet capabilities. Systems based Pentium processors also include latest features simplify system management lower cost ownership large small business environments. Pentium processor offers great performance today's tomorrow's applications. FC-PGA370 Package
June 2001
Document Number: 245264-08
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Pentium® processor contain design defects errors known errata which cause product deviate from published specifcations. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Intel, Pentium Pentium III, Pentium Pro, Celeron Intel387 trademarks registered trademarks Intel Corporation subsidiaries United States other countries. *Other names brands claimed property others. Copyright Intel Corporation, 2001
Datasheet
Pentium® Processor PGA370 Socket 1.13
Content1.0 Introduction
Terminology. 1.1.1 Package Processor Terminology 1.1.2 Processor Naming Convention.10 Related Documents.11 Processor System VREF Clock Control Power States.14 2.2.1 Normal State-State 2.2.2 AutoHALT Powerdown State-State 2.15 2.2.3 Stop-Grant State-State 2.2.4 HALT/Grant Snoop State-State 2.2.5 Sleep State-State 5.16 2.2.6 Deep Sleep State-State 2.2.7 Clock Control.17 Power Ground Pins 2.3.1 Phase Lock Loop (PLL) Power.18 Decoupling Guidelines 2.4.1 Processor VCCCORE AGTL+ (AGTL) Decoupling Processor System Clock Processor Clocking 2.5.1 Mixing Processors Different Frequencies.20 Voltage Identification Processor System Unused Pins.22 Processor System Signal Groups 2.8.1 Asynchronous Synchronous System Signals 2.8.2 System Frequency Select Signals (BSEL[1:0]) Maximum Ratings.26 Processor Specifications.27 2.10.1 Slew Rate Specifications.33 AGTL AGTL+ System Specifications System Specifications 2.12.1 Buffer Model BCLK/BCLK# PICCLK Signal Quality Specifications Measurement Guidelines AGTL+ AGTL Signal Quality Specifications Measurement Guidelines AGTL+ Signal Quality Specifications Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines 3.3.2 Overshoot/Undershoot Magnitude 3.3.3 Overshoot/Undershoot Pulse Duration.49 3.3.4 Activity Factor 3.3.5 Reading Overshoot/Undershoot Specification Tables.50 3.3.6 Determining System Meets Overshoot/Undershoot Specifications Non-AGTL+ (Non-AGTL) Signal Quality Specifications Measurement
Electrical Specifications
2.10 2.11 2.12
Signal Quality Specifications
Datasheet
Pentium® Processor PGA370 Socket 1.13
Guidelines 3.4.1 Overshoot/Undershoot Guidelines 3.4.2 Ringback Specification. 3.4.3 Settling Limit Guideline
Thermal Specifications Design Considerations
Thermal Specifications. Processor Area Thermal Diode. FC-PGA Mechanical Specifications 5.1.1 FC-PGA2 Mechanical Specifications Processor Markings 5.2.1 Processor Markings FC-PGA2. Recommended Mechanical Keep-Out Zones Processor Signal Listing. Mechanical Specifications Boxed Intel® Pentium® Processor. 6.1.1 Boxed Processor Thermal Cooling Solution Dimensions. 6.1.2 Boxed Processor Heatsink Weight. 6.1.3 Boxed Processor Thermal Cooling Solution Clip Thermal Specifications. 6.2.1 Boxed Processor Cooling Requirements Electrical Requirements Boxed Intel® Pentium® Processor. 6.3.1 Heatsink Power Supply Alphabetical Signals Reference Signal Summaries
Mechanical Specifications
Boxed Processor Specifications
Processor Signal Description
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure1 Second Level (L2) Cache Implementation AGTL+/AGTL Topology Uniprocessor Configuration AGTL+/AGTL Topology Dual-Processor Configuration Stop Clock State Machine Processor VccCMOS Package Routing Differential Clocking Example BSEL[1:0] Example 100/133 Only System Design Slew Rate (23A Load Step).33 Generic Clock Waveform BCLK, PICCLK, Generic Clock Waveform.42 System Valid Delay Timings System Setup Hold Timings.43 System Reset Configuration Timings.43 Platform Power-On Sequence Timings Power-On Reset Configuration Timings.45 BCLK, PICCLK Generic Clock Waveform Processor Pins.47 High AGTL+ Receiver Ringback Tolerance.48 Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform Maximum Acceptable AGTL Overshoot/Undershoot Waveform Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, Ringback Processor Functional Layout FC-PGA.58 FC-PGA FC-PGA2 Package Types Package Dimensions.61 Package Dimensions FC-PGA2.63 FC-PGA2 Flatness Specification.64 Side Processor Markings FC-PGA CPUID 0x686H) Side Processor Markings FC-PGA (for CPUID 0x68AH)).65 Side Processor Markings FC-PGA2 Volumetric Keep-Out FC-PGA FC-PGA2.66 Component Keep-Out Intel® Pentium® Processor Pinout Conceptual Boxed Intel® Pentium® Processor PGA370 Socket Dimensions Mechanical Step Feature Heatsink Base.81 Dimensions Notches Heatsink Base Thermal Airspace Requirement Boxed Intel® Pentium® Processor Heatsinks PGA370 Socket Boxed Processor Heatsink Power Cable Connector Description.84 Motherboard Power Header Placement Relative Boxed Intel® Pentium® Processor
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table1 Processor Identification. Voltage Identification Definition. System Signal Groups System Signal Groups (AGTL)1 Frequency Select Truth Table BSEL[1:0] Absolute Maximum Ratings Voltage Current Specifications Slew Rate Data (23A) AGTL AGTL+ Signal Groups Specifications Non-AGTL+ Signal Group Specifications Non-AGTL Signal Group Specifications Processor AGTL+ Specifications Processor AGTL Specifications System Specifications (SET Clock) System Timing Specifications (Differential Clock) System Specifications (AGTL+ AGTL Signal Group) System Specifications (CMOS Signal Group) System Specifications (Reset Conditions) System Specifications (APIC Clock APIC I/O) Platform Power-On Timings BCLK/PICCLK Signal Quality Specifications Simulation Processor Pins BCLK/PICCLK Signal Quality Specifications Simulation Processor Pins Differential Clock Platform AGTL AGTL+ Signal Groups Ringback Tolerance Specifications Processor Pins Example Platform Information. AGTL+ AGTL Signal Group Overshoot/Undershoot Tolerance Processor Pins AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance CMOS Signal Group Overshoot/Undershoot Tolerance Processor Pins Signal Ringback Specifications Non-AGTL+ Signal Simulations Processor Pins Signal Ringback Specifications Non-AGTL Signal Simulations Processor Pins Intel® Pentium® Processor Thermal Design Power FC-PGA Package Intel® Pentium® Processor FC-PGA2 Package Thermal Design Power. Processor Functional Layout FC-PGA Thermal Diode Parameters Thermal Diode Interface. Intel® Pentium® Processor Package Dimensions Processor Loading Parameters FC-PGA Package Dimensions Intel® Pentium® Processor FC-PGA2 Package Processor Case Loading Parameters FC-PGA2 Signal Listing Order Signal Name Signal Listing Order Number
Datasheet
Pentium® Processor PGA370 Socket 1.13
Heatsink Power Signal Specifications.84 Signal Description Output Signals.92 Input Signals.92 Input/Output Signals (Single Driver).94 Input/Output Signals (Multiple Driver)
Datasheet
Pentium® Processor PGA370 Socket 1.13
Introduction
Intel® Pentium® processor PGA370 socket next member family, Intel IA-32 processor line hereafter will referred "Pentium processor", simply "the processor". processor uses same core offers same performance Pentium processor SC242 connector, utilizes package technology called flip-chip grid array, FC-PGA. This package utilizes same 370-pin zero insertion force socket (PGA370) used Intel® Celeronprocessor. Thermal solutions attached directly back processor core package without thermal plate heat spreader. core frequencies increase, need better power dissipation arises, Integrated Heat Spreader (IHS) been introduced higher frequencies near GHz. package with called FC-PGA2. Pentium processor, like predecessors family processors, implements Dynamic Execution microarchitecture-a unique combination multiple branch prediction, data flow analysis, speculative execution. This enables these processors deliver higher performance than Pentium processor, while maintaining binary compatibility with previous Intel Architecture processors. processor also executes Intel® MMXtechnology instructions enhanced media communication performance just it's predecessor, Pentium processor. Additionally, Pentium processor executes Streaming SIMD (single-instruction, multiple data) Extensions enhanced floating point application performance. concept processor identification, CPUID, extended processor family with addition processor serial number. Refer Intel® Processor Serial Number application note more detailed information. processor utilizes multiple low-power states such AutoHALT, Stop-Grant, Sleep, Deep Sleep conserve power during idle times. processor includes integrated on-die, 256-KB, 8-way associative level-two (L2) cache. cache implements Advanced Transfer Cache Architecture with 256-bit wide bus. processor also includes 16-KB level (L1) instruction cache 16-KB data cache. These cache arrays full speed processor core. with Pentium processor SC242 connector, Pentium processor PGA370 socket dedicated cache bus, thus maintaining dual independent architecture deliver high bandwidth performance (see Figure Memory cacheable addressable memory space, allowing significant headroom desktop systems. Refer Specification Update document this processor determine cacheability cache configuration options specific processor. Specification Update document requested your nearest Intel sales office. processor utilizes same multiprocessing system technology Pentium processor. This allows higher level performance both uni-processor two-way multiprocessor systems. system uses variant GTL+ signaling technology called Assisted Gunning Transceiver Logic (AGTL+/AGTL) signaling technology.
Figure Second Level (L2) Cache Implementation
Processor Core Processor Core
Intel® Pentium® SECC2 Processor
Intel® Pentium® FC-PGA Processor
Datasheet
Pentium® Processor PGA370 Socket 1.13
Terminology
this document, symbol after signal name refers active signal. This means that signal active state (based name signal) when driven level. example, when FLUSH# low, flush been requested. When high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). term "system bus" refers interface between processor, system core logic (a.k.a. chipset components), other agents.
1.1.1
Package Processor Terminology
following terms used often this document explained here clarification:
Pentium processor entire product including internal components. PGA370 socket 370-pin Zero Insertion Force (ZIF) socket which FC-PGA PPGA
packaged processor plugs into.
FC-PGA Flip Chip Grid Array. package technology used Pentium processorfor PGA370 socket.
FC-PGA2 Flip Chip Grid Array with Integrated Heat Spreader (IHS). package
technology used Pentium processors PGA370 socket increased power dissipation away from die. covers very thermal resistance.
Integrated Heat Spreader (IHS) metal cover integral part
CPU. promotes heat spreading away from backside ease thermal constraints.
Advanced Transfer Cache (ATC) cache architecture unique 0.18 micron
Pentium processors. consists microarchitectural improvements that provide higher data bandwidth interface into processor core that completely scaleable with processor core frequency.
Keep-out zone area near FC-PGA packaged processor that system designs
utilize.
Keep-in zone area FC-PGA packaged processor that thermal solutions utilize. OLGA Organic Land Grid Array. package technology core used S.E.C.C.
processors that permits attachment heatsink directly die.
PPGA Plastic Grid Array. package technology used Celeron processors that
utilize PGA370 socket.
Processor this document, term processor generic form Pentium
processor PGA370 socket FC-PGA package.
Processor core processor's execution engine. S.E.C.C. processor package technology called "Single Edge Contact Cartridge". Used
with Intel® Pentium® processors.
S.E.C.C. follow-on S.E.C.C. processor package technology. This differs from itpredecessor that extended thermal plate, thus reducing thermal resistance. Used with Pentium processors latest versions Pentium processor.
Datasheet
Pentium® Processor PGA370 Socket 1.13
SC242 242-contact slot connector (previously referred slot connector) that
S.E.C.C. S.E.C.C. plug into, just Intel® Pentium® processor uses socket cache cache industry designated names.
1.1.2
Processor Naming Convention
letter(s) added certain processors (e.g., 600EB MHz) when core frequency alone uniquely identify processor. Below summary what each letter means well table listing available Pentium processors PGA370 socket. System Frequency Processor with "Advanced Transfer Cache" (CPUID 068xh greater)
Table
Processor Identification
Processor 500E 533EB 550E 600E 600EB 800EB 1.10 1.13 Core Frequency (MHz) 1000 1000 1100 1133 System Frequency (MHz) Cache Size (Kbytes) Cache Type2 CPUID1 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh 068xh
NOTES: Refer Pentium® Processor Specification Update exact CPUID each processor. Advanced Transfer Cache. Cache integrated same processor core. With ATC, interface between processor core Cache 256-bits wide, runs same frequency processor core enhanced buffering.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Related DocumentThe reader this specification should also familiar with material concepts presented following documents 1,2:
Document AP-485, Intel Processor Identification CPUID Instruction AP-585, Pentium Processor GTL+ Guidelines AP-589, Design AP-905, Pentium Processor Thermal Design Guidelines AP-907, Pentium Processor Power Distribution Guidelines AP-909, Intel Processor Serial Number Intel® Architecture Software Developer's Manual Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide Family Processors Hardware Developer's Manual Pentium® Processor Developer's Manual Pentium Processor Datasheet SECC2 Pentium Processor Datasheet PGA370 Pentium® Processor Specification Update Intel Celeron Intel Celeron
Intel Document Number 241618 243330 243334 245087 245085 245125 243193 243190 243191 243192 244001 243502 244452 245264 244453 243658 243748 244410 245025 290675
Processor Datasheet Processor Specification Update
370-Pin Socket (PGA370) Design Guidelines PGA370 Heat Sink Cooling MicroATX Chassis Intel 810E Chipset Platform Design Guide Intel B-step Chipset Platform Design Guide Intel® 815E Chipset Platform Design Guide Intel® Chipset Platform Design Guide Intel Chipset Platform Design Guide CK98 Clock Synthesizer/Driver Design Guidelines Intel 810E Chipset Clock Synthesizer/Driver Specification DC-DC Converter Design Guidelines Pentium Processor PGA370 Socket Buffer Models, XTK/XNS* Format Pentium® Processor BIOS Writer's Guide Extensions Pentium® Processor BIOS Writer's Guide rev. Pentium® Thermal/Mechanical Solution Functional Guidelines Intel®Pentium® Processor FC-PGA2 Package Thermal Design Guide
298234 290631 298021 245338
245335
245241 249660
Datasheet
Pentium® Processor PGA370 Socket 1.13
NOTES: Unless otherwise noted, this reference material found Intel Developer's Website located http://developer.intel.com. complete listing Pentium processor reference material, please refer Intel Developer's Website This material available through Intel field sales representative.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Electrical SpecificationProcessor System VREF
Pentium processor signals variation voltage Gunning Transceiver Logic (GTL) signaling technology. Pentium processor system specification similar specification, enhanced provide larger noise margins reduced ringing. improvements accomplished increasing termination voltage level controlling edge rates. This specification different from specification, referred GTL+. more information GTL+ specifications, GTL+ buffer specification Intel® Pentium® Processor Developer's Manual. Current family processors vary from Pentium processor their output buffer implementation. buffers that drive system signals Celeron, Pentium Pentium processors actively driven clock cycle after high transition improve rise times. These signals should still considered open-drain require termination supply that provides high signal level. Because this specification different from standard GTL+ specification, referred AGTL+, Assisted GTL+ this other documentation. AGTL+ logic GTL+ logic compatible with each other both used same system bus. more information AGTL+ routing, appropriate platform design guide. Note that some Pentium processors with CPUID 068xh support AGTL specification addition AGTL+ specification. AGTL logic AGTL+ logic compatible with each other differences with signal switching levels. Processors that support AGTL specification cannot installed into platforms where chipset only supports AGTL signal levels. more information AGTL AGTL+ routing, please refer appropriate platform design guide. Both AGTL AGTL+ inputs differential receivers which require reference signal (VREF). VREF used receivers determine signal logical logical supplied motherboard PGA370 socket processor core. Local VREF copies should also generated motherboard other devices AGTL+ (AGTL) system bus. Termination (usually resistor each signal trace) used pull high voltage level control reflections transmission line. processor contains on-die termination resistors that provide termination bus, except RESET#. These specifications assume another resistor each signal trace ensure adequate signal quality AGTL+ (AGTL) signals provide backwards compatibility Celeron processor; Table termination voltage specifications AGTL+. Refer Intel® Pentium® Processor Developer's Manual AGTL+ specification. Solutions exist single-ended termination well, though this implementation changes system design eliminate backwards compatibility Celeron processors PPGA package. Single-ended termination designs must still provide AGTL+ (AGTL) termination resistor motherboard RESET# signal. Figure schematic representation AGTL+ (AGTL) topology Pentium processors PGA370 socket. Figure schematic representation AGTL+/AGTL topology dual-processor configuration with Pentium processors PGA370 socket. Both AGTL+ AGTL depend incident wave switching. Therefore, timing calculations AGTL+ AGTL signals based flight time opposed capacitive deratings. Analog signal simulation system including trace lengths highly recommended when designing
Datasheet
Pentium® Processor PGA370 Socket 1.13
system with heavily loaded AGTL+ bus, especially systems using single termination resistors (i.e., those processor die). Such designs will match solution space allowed installation termination resistors baseboard. Figure AGTL+/AGTL Topology Uniprocessor Configuration
Processor
Chipset
Figure AGTL+/AGTL Topology Dual-Processor Configuration
Processor
Chipset
Processor
Clock Control Power StateProcessors allow AutoHALT, Stop-Grant, Sleep, Deep Sleep states reduce power consumption stopping clock internal sections processor, depending each particular state. Figure visual representation processor low-power states.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Stop Clock State Machine
Instruction ycle enerated tate running. noops interrupts allowed. IT#, tate execution.
sserted noop vent ccurs noop vent erviced e-asserted sserted De-asserted
Stop-Grant State entered from AutoHALT
noop vent ccurs noop vent erviced
rant tate running. ervice snoops caches.
tate running. noops interrupts allowed.
sserted
De-asserted
leep tate running. snoops interrupts allow Input topped Input Restarted
Deep leep tate stopped. snoops interrupts allow
B757a
processor fully realize current consumption Stop-Grant, Sleep Deep Sleep states, Model Specific Register (MSR) must set. 02AH (Hex), must (this power default setting) processor stop internal clocks during these modes. more information, Intel Architecture Software Developer's Manual, Volume System Programming Guide located developer.intel.com website.
2.2.1
Normal State-State
This normal operating state processor.
2.2.2
AutoHALT Powerdown State-State
AutoHALT power state entered when processor executes HALT instruction. processor transitions Normal state upon occurrence SMI#, INIT#, LINT[1:0] (NMI, INTR). RESET# causes processor immediately initialize itself. return from System Management Interrupt (SMI) handler either Normal Mode AutoHALT Power Down state. Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide more information. FLUSH# serviced during AutoHALT state, processor will return AutoHALT state.
Datasheet
Pentium® Processor PGA370 Socket 1.13
system generate STPCLK# while processor AutoHALT Power Down state. When system deasserts STPCLK# interrupt, processor returns execution HALT state.
2.2.3
Stop-Grant State-State
Stop-Grant state processor entered when STPCLK# signal asserted. Since AGTL+ signal pins receive power from system bus, these pins should driven (allowing level return VTT) minimum power drawn termination resistors this state. addition, other input pins system should driven inactive state. BINIT# FLUSH# serviced during Stop-Grant state. RESET# causes processor immediately initialize itself, processor stays Stop-Grant state. transition back Normal state occurs with deassertion STPCLK# signal. transition HALT/Grant Snoop state occurs when processor detects snoop system (see Section 2.2.4). transition Sleep state (see Section 2.2.5) occurs with assertion SLP# signal. While Stop-Grant State, SMI#, INIT#, LINT[1:0] latched processor, only serviced when processor returns Normal state. Only occurrence each event recognized serviced upon return Normal state.
2.2.4
HALT/Grant Snoop State-State
processor responds snoop transactions system while Stop-Grant state AutoHALT Power Down state. During snoop transaction, processor enters HALT/Grant Snoop state. processor stays this state until snoop system been serviced (whether processor another agent system bus). After snoop serviced, processor returns Stop-Grant state AutoHALT Power Down state, appropriate.
2.2.5
Sleep State-State
Sleep state very power state which processor maintains context, maintains phase-locked loop (PLL), stopped internal clocks. Sleep state only entered from Stop-Grant state. Once Stop-Grant state, SLP# asserted, causing processor enter Sleep state. SLP# recognized Normal AutoHALT states. Snoop events that occur while Sleep state during transition into Sleep state will cause unpredictable behavior. Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals (with exception SLP# RESET#) allowed system while processor Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior. RESET# driven active while processor Sleep state, held active specified RESET# specification, then processor will reset itself, ignoring transition through Stop-Grant State. RESET# driven active while processor Sleep State, SLP# STPCLK# signals should deasserted immediately after RESET# asserted ensure processor correctly executes reset sequence.
Datasheet
Pentium® Processor PGA370 Socket 1.13
While Sleep state, processor capable entering lowest power state, Deep Sleep state, stopping BCLK input (see Section 2.2.6). Once Sleep Deep Sleep states, SLP# deasserted another asynchronous system event occurs. SLP# minimum assertion BCLK period.
2.2.6
Deep Sleep State-State
Deep Sleep state lowest power state processor enter while maintaining context. Deep Sleep state entered stopping BCLK1 input (after Sleep state entered from assertion SLP# pin). processor Deep Sleep state immediately after BCLK stopped. recommended that BCLK1 input held during Deep Sleep State. Stopping BCLK1 input lowers overall current consumption leakage levels. re-enter Sleep state, BCLK input must restarted. period allow stabilization) must occur before processor considered Sleep state. Once Sleep state, SLP# deasserted re-enter Stop-Grant state. While Deep Sleep state, processor incapable responding snoop transactions latching interrupt signals. transitions assertions signals allowed system while processor Deep Sleep state. transition input signal before processor returned Stop-Grant state will result unpredictable behavior.
2.2.7
Clock Control
BCLK2 provides clock signal processor cache. During AutoHALT Power Down Stop-Grant states, processor will process system snoop. processor does stop clock cache during AutoHALT Power Down Stop-Grant states. Entrance into Halt/Grant Snoop state allows cache snooped, similar Normal state. When processor Sleep Deep Sleep states, does respond interrupts snoop transactions. During Sleep state, internal clock cache stopped. During Deep Sleep state, internal clock cache stopped. internal clock cache restarted only after internal clocking mechanism processor stable (i.e., processor re-entered Sleep state). PICCLK should removed during AutoHALT Power Down Stop-Grant states. PICCLK removed during Sleep Deep Sleep states. When transitioning from Deep Sleep state Sleep state, PICCLK must restarted with BCLK.2
Power Ground PinThe operating voltage Pentium processor PGA370 socket same core cache; VCCCORE. There four pins defined package voltage identification (VID). These pins specify voltage required processor core. These have been added cleanly support voltage specification variations current future processors. clean on-chip power voltage reference distribution, Pentium processors PGA370 socket have VCCCORE, VREF AGTL platforms), VTT, (ground) inputs. VCCCORE inputs supply processor core, including on-die cache. input
processors using AGTL level with differential clocking, deep sleep state entered stopping BCLK BCLK# input. processors using AGTL level with differential clocking this would also include BCLK# signal well.
Datasheet
Pentium® Processor PGA370 Socket 1.13
(1.5 V/1.25 used provide AGTL+/AGTL termination voltage processor, VREF inputs used AGTL+/AGTL reference voltage processor. Note that inputs must connected supply. Refer Section more details. motherboard, VCCCORE pins must connected voltage island island portion power plane that been divided, entire plane). addition, motherboard must implement pins voltage island large trace. Similarly, pins must connected system ground plane. Three additional power related pins exist processors utilizing PGA370 socket. They VCC1.5, VCC2.5 VCCCMOS. VCCCMOS provides CMOS voltage pull-up resistors required system platform. source must provided VCC2.5 source must provided VCC1.5 pin. source VCC1.5 must same supplying VTT. processor routes compatible CMOS voltage source (1.5 through package VCCCMOS output pin. Processors based 0.25 micron technology (e.g., Celeron processor) utilize CMOS buffers. Processors based 0.18 micron technology (e.g., Pentium processor PGA370 socket) utilize CMOS buffers. signal VCOREDET used hardware motherboard detect which CMOS voltage processor requires. VCOREDET connected within processor indicates requirement VCCCMOS. Refer Figure Each power signal must meet specifications stated Table page Figure Processor VCCCMOS Package Routing
2.5V 2.5V Supply VCCCMOS Intel Pentium® Processor
1.5V 1.5V Supply CMOS Signal
CMOS Pullups *ICH Other Logic Note: *Ensure this logic compatible with 1.5V signal levels Intel® Pentium® processor PGA370 socket.
2.3.1
Phase Lock Loop (PLL) Power
highly critical that phase lock loop power delivery processor meets Intel's requirements. pass filter required power delivery pins PLL1 PLL2. This serves isolated, decoupled power source internal PLL. Please refer Phase Lock Loop Power section appropriate platform design guide recommended filter specifications.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Decoupling GuidelineDue large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. fluctuations cause voltages power planes below their nominal values bulk decoupling adequate. Care must taken board design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations event voltage sag) reduced lifetime component event voltage overshoot). Unlike SC242 based designs, motherboards utilizing PGA370 socket must provide high frequency decoupling capacitors power planes processor.
2.4.1
Processor VCCCORE AGTL+ (AGTL) Decoupling
regulator VCCCORE input must capable delivering dICCCORE/dt (defined Table while maintaining required tolerances (also defined Table Failure meet these specifications result timing violations (during VCCCORE sag) reduced lifetime component (during VCCCORE overshoot). processor requires both high frequency bulk decoupling system motherboard proper AGTL+ (AGTL) operation. AGTL+ buffer specification Intel® Pentium® Processor Developer's Manual more information. Also, refer appropriate platform design guide recommended capacitor component placement. minimum recommendation processor decoupling listed below. capacitors should placed within PGA370 socket cavity mounted primary side motherboard. capacitors arranged minimize overall inductance between VCCCORE power pins. VCCCORE decoupling capacitors 1206 package. decoupling capacitors 0603 package. VREF decoupling 0.001 capacitors 0603 package placed near VREF pins. additional decoupling requirements, please refer appropriate platform design guide recommended capacitor component value, quantity placement.
Processor System Clock Processor Clocking
BCLK input directly controls operating speed system interface. AGTL+/ AGTL system timing parameters specified with respect rising edge BCLK input. Coppermine-T processor will implement auto-detect mechanism that will processor either single-ended differential signaling system processor clocking. processor checks signal toggling. this signal toggling then processor operates differential mode. Refer Figure differential clocking example. Resistor values clock topology listed appropriate platform design guide differential implementation.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Note:
References BCLK throughout this document will also imply complement signal, BCLK#, differential implementations when noted otherwise. differential clock input, AGTL system timing parameters specified with respect crossing point rising edge BCLK input falling edge BCLK# input. Family Processors Hardware Developer's Manual further details.
Note:
differential clocking, reference voltage BCLK Family Processors Hardware Developer's Manual re-defined crossing point BCLK BCLK# inputs.
Figure Differential Clocking Example
BCLK Clock Driver BCLK# Processor Chipset
2.5.1
Mixing Processors Different FrequencieIn two-way (multi-processor) systems, mixing processors different internal clock frequencies supported been validated. Pentium processors support variable multiplier ratio; therefore, adjusting ratio setting common clock frequency valid. However, mixing processors same frequency different steppings supported. Details support mixed steppings provided Pentium® Processor Specification Update. Note: Pentium processors PGA370 socket validated dual processor (DP) systems. Refer Pentium® Processor Specification Update determine which processors capable.
Voltage Identification
There four voltage identification pins PGA370 socket. These pins used support automatic selection VCCCORE voltages. These pins signals, either open circuit short circuit processor. combination opens shorts defines voltage required processor core. pins needed cleanly support voltage specification variations current future processors. VID[3:0] defined Table this table refers open refers short ground. voltage regulator must supply voltage that requested disable itself. ensure system ready current future processors, range values bold Table should supported. smaller range will risk ability system migrate higher performance processor and/or maintain compatibility with current processors.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Voltage Identification Definition
VID3 VID2 VID1 VID0 VccCORE 1.30 1.35 1.40 1.45 1.50 1.55 1.603 1.653 1.703 1.753 1.80 1.85 1.90 1.95 2.00 2.05 Core
NOTES: Processor connected VSS. Open processor; pulled baseboard. ensure system ready Pentium Celeron processors, values BOLD Table should supported.
Note that `1111' (all opens) used detect absence processor core given socket long power supply used does affect these lines. Detection logic pull-ups should affect inputs power source (see Section 7.0). pins should pulled TTL-compatible level with external resistors power source regulator only required regulator external logic monitoring VID[3:0] signals. power source chosen must guaranteed stable whenever supply voltage regulator stable. This will prevent possibility processor supply going above specified VCCCORE event failure supply lines. case DC-toDC converter, this accomplished using input voltage converter line pull-ups. resistor greater than equal used connect signals converter input. Note that changes have been made physical connector definitions between Intel-enabled specifications. Note: specification uses five assignments VID[3:0, 25mV] compatible with 8.4. Some Pentium processors with CPUID 068xh capable supporting both specifications. Please refer Pentium Specification Update listing processors that support both specifications.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Processor System Unused PinAll RESERVED pins must remain unconnected unless specifically noted. Connection these pins VCCCORE, VREF, VSS, VTT, other signal (including each other) result component malfunction incompatibility with future processors. Section listing processor location each RESERVED pin. PICCLK must driven with valid clock input PICD[1:0] signals must pulled-up VCCCMOS even when APIC will used. separate pull-up resistor must provided each PICD signal. reliable operation, always connect unused inputs bidirectional signals their deasserted signal level. pull-up pull-down resistor values system dependent should chosen such that logic high (VIH) logic (VIL) requirements met. Table Table specifications non-AGTL+/AGTL signals. Unused AGTL+ AGTL) inputs must properly terminated PGA370 socket motherboards which support Celeron Pentium processors. designs that intend only support Pentium processor, unused AGTL+ inputs will terminated processor's on-die termination resistors thus need terminated motherboard. However, RESET# must always terminated motherboard Pentium processor PGA370 socket does provide on-die termination this input. unused CMOS inputs, active signals should connected through pull-up resistor VCCCMOS meet requirements. Unused active high CMOS inputs should connected through pull-down resistor ground (VSS) meet requirements. Unused CMOS outputs left unconnected. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability.
Processor System Signal GroupTo simplify following discussion, processor system signals have been combined into groups buffer type. family processor system outputs open drain require high-level source provided termination resistors. However, Pentium processor PGA370 socket includes on-die termination. Motherboard designs that also support Celeron processors PPGA package will need provide AGTL+ termination system motherboard well. Platform designs that support dual processor configurations will need provide AGTL+ termination, termination package, socket populated with processor. Please refer Pentium Processor Specification Update complete listing processors that support AGTL AGTL+ specifications. Note that AGTL platforms support Celeron processor PPGA package. Both AGTL+ AGTL input signals have differential input buffers which VREF reference signal. AGTL+ output signals require termination while AGTL output signals require termination 1.25 this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. PWRGOOD, BCLK, PICCLK inputs each driven from ground Other CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, STPCLK#) only tolerant must pulled VCCCMOS. CMOS, APIC, outputs open drain must pulled high VCCCMOS. This ensures correct operation current Pentium Celeron processors.
Datasheet
Pentium® Processor PGA370 Socket 1.13
groups signals contained within each group shown Table Table Refer Section description these signals. Table System Signal Groups
Group Name AGTL+ Input AGTL+ Output AGTL+ CMOS Input3 CMOS Input4 CMOS Output3 System Clock4 APIC Clock4 APIC
Signals BPRI#, BR1# DEFER#, RESET# ,RESET2#, RS[2:0]#, RSP#, TRDY# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#, STPCLK# PWRGOOD FERR#, IERR#, THERMTRIP# BCLK PICCLK PICD[1:0] BSEL[1:0], CLKREF, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL, THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS, VCCCORE, VREF, VSS, VTT, Reserved
Power/Other5
NOTES: Section information these signals. BR0# only BREQ# signal that bidirectional. Section more information. internal BREQ# signals mapped onto BR[1:0]# pins after agent determined. These signals specified VccCMOS (1.5 Pentium processor) operation. These signals tolerant. VCCCORE power supply processor core described Section 2.6. VID[3:0] described Section 2.6. used terminate system generate VREF motherboard. system ground. VCC1.5, VCC2.5, VccCMOS described Section 2.3. BSEL[1:0] described Section 2.8.2 Section 7.0. other signals described Section 7.0. RESET# must always terminated motherboard, on-die termination provided this signal. This signal supported processors. Refer Pentium® Processor Specification Update complete listing processors that support this pin. This signal used control value processor on-die termination resistance. Refer platform design guide recommended pull-down resistor value.
Table
System Signal Groups (AGTL)1 (Sheet
Group Name AGTL Input9 AGTL Output9 Signals BPRI#, BR1#7, DEFER#, RESET#6, RSP#, TRDY#, RS[2:0]# PRDY# A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#2, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#, RP#, A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SLP#, SMI#, STPCLK# PWRGOOD FERR#3, IERR#3, THERMTRIP#3, VID[3:0]13, BSEL[1:0]13
AGTL I/O9 CMOS Input3 CMOS Input (1.8 CMOS Output
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
System Signal Groups (AGTL)1 (Sheet
Group Name System Clock10, (1.25 V/2.5 APIC Clock (2.0 APIC I/O3 Power/Other5 PICCLK11 PICD[1:0] BSEL[1:0], CLKREF10, CPUPRES#, EDGCTRL, PLL[2:1], RESET2#, SLEWCTRL, THERMDN, THERMDP, RTTCTRL8, VCOREDET, VID[3:0], VCC1.5, VCC2.5, VCCCMOS, VCCCORE, VREF, VSS, VTT, Reserved Signal
BCLK, BCLK0#
NOTES: Section information these signals. BR0# only BREQ# signal that bidirectional. Section more information. internal BREQ# signals mapped onto BR[1:0]# pins after agent determined. These signals specified VccCMOS (1.5 Pentium processor) operation. These signals tolerant. VCCCORE power supply processor core described Section 2.6. VID[3:0] described Section 2.6. used terminate system generate VREF motherboard. system ground. VCC1.5, VCC2.5, VccCMOS described Section 2.3. BSEL[1:0] described Section 2.8.2 Section 7.0. other signals described Section 7.0. RESET# must always terminated motherboard, on-die termination provided this signal. This signal supported processors. Refer Pentium® Processor Specification Update complete listing processors that support this pin. This signal used control value processor on-die termination resistance. Refer platform design guide recommended pull-down resistor value. These signals also classified AGTL. Refer Pentium® Processor Specification Update complete listing processors that support AGTL AGTL+ specifications. 10.For differential clock systems, CLKREF becomes BCLK#. Coppermine-T differential clock, this signal been redefined tolerant. 1.25 signal Differential clock application Single-ended clock application. This signal
2.8.1
Asynchronous Synchronous System SignalAll AGTL+ signals synchronous BCLK. CMOS, Clock, APIC, signals applied asynchronously BCLK. APIC signals synchronous PICCLK.
Datasheet
Pentium® Processor PGA370 Socket 1.13
2.8.2
System Frequency Select Signals (BSEL[1:0])
These signals used select system frequency processor. BSEL signals also used chipset system clock generator. Table defines possible combinations signals frequency associated with each combination. frequency selection determined processor(s) driven chipset clock generator. system agents must operate same frequency determined processor. Pentium processor PGA370 socket operates system frequency; system operation supported. Individual processors will only operate their specified front side (FSB) frequency, either MHz, both. Over underclocking system frequency outside specified rating marked package recommended. motherboards that support operation either MHz, BSEL1 signal must pulled logic high resistor located motherboard provided frequency selection signal clock driver/synthesizer. This signal also incorporated into RESET# logic motherboard only operation supported (thus forcing RESET# signal remain active long BSEL1 signal low. BSEL0 signal will float from processor should pulled logic high resistor located motherboard. BSEL0 signal incorporated into RESET# logic motherboard operation unsupported, demonstrated Figure Refer appropriate clock synthesizer design guidelines platform design guide more details frequency select signals. 2-way system design, these BSEL[1:0] signals must connect pins both processors.
Figure BSEL[1:0] Example 100/133 Only System Design
3.3V 3.3V Processor
BSEL0
BSEL1 Note Clock Driver
Note
Note
Chipset
NOTES: Some clock drivers require series resistor their BSEL1 input. Some chipsets connect BSEL[1:0] signals require series resistor. appropriate platform design guide implementation details.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Frequency Select Truth Table BSEL[1:0]
BSEL1 BSEL0 Frequency (unsupported) Reserved
Maximum RatingTable contains processor stress ratings only. Functional operation absolute maximum minimum implied guaranteed. processor should receive clock while subjected these conditions. Functional operating conditions given tables Section 2.10 through Section 2.12. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table
Absolute Maximum RatingSymbol TSTORAGE VccCORE VinAGTL VinCMOS1.5 VinCMOS2.5 IVID ICPUPRES# Parameter Processor storage temperature Processor core voltage termination supply voltage with respect AGTL+ buffer input voltage CMOS buffer input voltage with respect CMOS buffer input voltage with respect current CPUPRES# current -0.5 2.18 2.18 -0.58 -0.3 2.18 2.18 3.18 Unit Note
NOTES: Input voltage never exceed 2.18 Input voltage never below 2.18 Parameter applies CMOS (except BCLK, PICCLK, PWRGOOD) APIC signal groups only. Parameter applies CMOS signals BCLK, PICCLK, PWRGOOD only.
Datasheet
Pentium® Processor PGA370 Socket 1.13
2.10
Processor SpecificationThe processor specifications this section defined PGA370 socket pins (bottom side motherboard). Section processor signal descriptions Section signal listings. Most signals processor system AGTL+ (AGTL) signal group. These signals specified terminated AGTL+ 1.25 AGTL. specifications these signals listed Table page allow connection with other devices, clock, CMOS, APIC signals designed interface non-AGTL+ levels. specifications these pins listed Table page Table through Table list specifications Pentium processor PGA370 socket. Specifications valid only while meeting specifications junction temperature, clock frequency, input voltages. Care should taken read notes associated with each parameter.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Voltage Current Specifications (Sheet
Processor Parameter CPUID 0x681 500E 0x683 0x686 0x681 533EB 0x683 0x686 0x681 550E 0x683 0x686 0x681 600E 0x683 0x686 0x68A 0x681 600EB 0x683 0x686 0x681 1.60 1.60 1.65 1.65 1.60 1.65 1.70 1.65 1.65 1.70 1.75 1.65 1.65 1.70 1.65 0x683 0x686 0x681 0x683 0x686 0x681 0x683 0x686 0x68A 0x681 0x683 0x686 0x68A 0x681 0x683 0x686 0x68A 1.65 1.70 1.65 1.65 1.70 1.65 1.65 1.70 1.75 1.65 1.65 1.70 1.75 1.65 1.65 1.70 1.75 Unit Note
Symbol
Core Freq
VCCCORE
Processor Core
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Voltage Current Specifications (Sheet
Processor Parameter CPUID 0x681 0x683 0x686 0x681 800EB 0x683 0x686 0x68A 0x681 0x683 0x686 0x68A 0x681 0x683 0x686 0x68A 0x686 0x68A 0x683 1.10 1.13 0x686 0x68A 0x68A 0x686 0x686 0x68A 0x68A 0x68A 1.65 1.65 1.70 1.65 1.65 1.70 1.75 1.65 1.65 1.70 1.75 1.65 1.65 1.70 1.75 1.70 1.75 1.65 1.70 1.75 1.75 1.70 1.76 1.75 1.75 1.75 3,4,20 3,4,18,19 3,4,20 Unit Note
Symbol
Core Freq
VCCCORE
Processor Core
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Voltage Current Specifications (Sheet
Processor Parameter CPUID 1.455 1.213 1.365 1.138 1.455 1.169 -0.080 0.001 -0.130 -0.110 -0.025 1.50 1.25 1.50 1.25 1.50 1.25 1.545 1.288 1.635 1.363 1.545 1.331 0.040 0.100 0.080 0.080 0.130 5,16 1.25 5,16,17 1.25 5,17 ±2%, ±6.5%, Unit Note
Symbol
Core Freq
Static AGTL+ termination voltage Static AGTL termination voltage Transient AGTL+ termination voltage Transient AGTL termination voltage Static AGTL+ termination voltage AGTL+ input reference voltage CLKREF input reference voltage Processor core voltage static tolerance level PGA370 socket pins Processor core voltage transient tolerance level PGA370 socket
Vcc1.5 VREF VCLKREF Baseboard VCCCORE Tolerance, Static Baseboard VCCCORE Tolerance, Transient
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Voltage Current Specifications (Sheet
Processor Parameter CPUID 0x683 0x686 0x68A 0x686 0x686 0x686 0x686 0x68A 0x686 0x68A 0x686 0x68A 0x686 0x686 0x68A 0x686 0x68A 0x686 0x68A 0x686 0x68A 0x686 0x68A 0x686 0x68A 0x68A 0x68A 0x68A 10.0 12.0 12.6 12.0 13.0 13.3 14.0 14.8 14.6 15.4 15.0 15.7 16.0 16.0 16.6 16.2 17.3 16.3 17.6 17.0 18.4 17.7 18.8 19.4 20.2 20.2 22.6 22.6 9,20 9,20 Unit Note
Symbol
Core Freq 500E 600E 600EB 667B 733B
ICCCORE
processor core 800EB 1.10 1.13
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Voltage Current Specifications (Sheet
Processor Parameter CPUID A/µs A/µs Table Unit Note
Symbol
Core Freq
ICCCMOS ICLKREF IVTT ISGnt ISLP IDSLP dICCCORE/dt dIvTT/dt
VccCMOS CLKREF voltage supply current Termination voltage supply current Stop-Grant processor core Sleep processor core Deep Sleep processor core Power supply current slew rate Termination current slew rate
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. specifications this table apply only Pentium processor. motherboard compatibility with Celeron processor, Intel® CeleronProcessor Datasheet. VccCORE IccCORE supply processor core on-die cache. "typical voltage" specification with "tolerance specifications" provide correct voltage regulation processor. Vcc1.5 must held while AGTL+ active. required that Vcc1.5 held while processor system static (idle condition). range required design target; will come from transient noise added. This measured PGA370 socket pins bottom side baseboard. These tolerance requirements, across frequency bandwidth, measured processor socket soldered-side motherboard. VCCCORE must return within static voltage specification within after transient event; DC-DC Converter Design Guidelines further details. VREF should generated from voltage divider resistors matched resistors. Refer Intel® Pentium® Processor Developer's Manual more details VREF. Maximum measured typical voltage under maximum signal loading conditions. Voltage regulators designed with minimum equivalent internal resistance ensure that output voltage, maximum current output, greater than nominal (i.e., typical) voltage level VccCORE (VccCORE_TYP). this case, maximum current level regulator, IccCORE_REG, reduced from specified maximum current IccCORE _MAX calculated equation: IccCORE_REG IccCORE_MAX (VccCORE_TYP VccCORE_STATIC_TOLERANCE) VccCORE_TYP 10.The current specified current required single processor. similar amount current drawn through termination resistors opposite AGTL+ bus, unless single-ended termination used (see Section 2.1). current specified also AutoHALT state. 12.Maximum values specified design/characterization nominal VccCORE. 13.Based simulation averaged over duration change current. compute maximum inductance tolerable reaction time voltage regulator. This parameter tested. 14.dIcc/dt specifications measured specified PGA370 socket pins. 15.CLKREF must held 1.25 ±6.5%. This tolerance accounts power supply resistor divider tolerance. recommended that motherboard generate CLKREF reference from either supply. should used risk AGTL+ switching noise coupling this analog reference. 16.Static voltage regulation includes: output initial voltage point adjust, Output ripple noise, Output load ranges specified tables above. 17.This specification applies PGA370 processors operating frequencies higher.
Datasheet
Pentium® Processor PGA370 Socket 1.13
18.This specification only applies S-spec SL4WM. This part request 1.70 however processor should supplied 1.76 Voltage Regulator Circuit VRM. 19.This specification applies only S-spec SL4WM. This value offset from standard specification more Minimum specification. These tolerances measured from 1.70 base, while supplied 1.76 This processor exists both FC-PGA FC-PGA2.
2.10.1
Slew Rate SpecificationThis section contains typical current slew rate data processors covered this design guideline. Actual slew rate values wave-shapes vary slightly depending type size decoupling capacitors used particular implementation.
Figure Slew Rate (23A Load Step)
Socket (23A, CPUID 068xh)
0.0E+00 1.0E-06 2.0E-06 Time 3.0E-06 4.0E-06 5.0E-06
Table
Slew Rate Data (23A) (Sheet
Time (µs) 0.15 9.55 14.4 20.85 23.04 23.44 23.28 22.32 21.63 21.45 21.63
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table
Slew Rate Data (23A) (Sheet
Time (µs) 21.88 22.01
Table
AGTL AGTL+ Signal Groups Specifications
Symbol Parameter Input Voltage Input High Voltage Buffer Resistance Leakage Current inputs, outputs, -0.150 VREF 0.200 VREF 0.200 16.67 ±100 Unit Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. inputs, outputs, pins must comply with signal quality specifications Section 3.0. Minimum maximum given Table page +3%) (0VOUT1.5 V+3%). Refer processor Buffer Models characteristics. Steady state input voltage must above 1.65 below 1.65
Table Non-AGTL+ Signal Group Specifications
Symbol VIL1.5 VIL2.5 VIH1.5 VIH2.5 Output High Voltage Output Current Input Leakage Current Output Leakage Current ±100 ±100 Parameter Input Voltage Input Voltage Input High Voltage Input High Voltage Output Voltage -0.150 -0.58 VCMOS_REF 0.200 2.000 VCMOS_REF 0.200 0.700 3.18 0.400 Unit Notes outputs open-drain
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. Parameter measured (for with inputs). +5%). VOUT +5%). BCLK specifications, refer Table page +3%). VOUT +3%). Applies non-AGTL signals except BCLK, PICCLK, PWRGOOD. Applies non-AGTL signals except BCLK, PICCLK, PWRGOOD.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table Non-AGTL Signal Group Specifications
Symbol VIL1.5 VIL2.5 VIH1.5 VIH2.5 Output High Voltage Output Current Input Leakage Current Output Leakage Current ±100 ±100 Parameter Input Voltage Input Voltage Input High Voltage Input High Voltage Output Voltage -0.150 -0.58 VCMOS_REF 0.200 2.000 VCMOS_REF 0.300 0.700 3.18 0.300 Unit Notes outputs open-drain
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. Parameter measured (for with inputs). +5%); VOUT +5%). BCLK specifications, refer Table page +3%); VOUT +3%). Applies non-AGTL+ signals except BCLK, PICCLK, PWRGOOD. Applies non-AGTL+ signals except BCLK, PICCLK, PWRGOOD. Coppermine-T differential clocking, input voltage (VCMOS_REF 0.300)V.
Datasheet
Pentium® Processor PGA370 Socket 1.13
2.11
AGTL AGTL+ System SpecificationIt recommended that AGTL+ routed daisy-chain fashion with termination resistors VTT. These termination resistors placed electrically between ends signal traces voltage supply generally chosen approximate system platform impedance. valid high levels determined input buffers using reference voltage called VREF. Refer appropriate platform design guide more information Table below lists nominal specification AGTL+ termination voltage (VTT). AGTL+ reference voltage (VREF) generated system motherboard should processor other AGTL+ logic. important that baseboard impedance specified held ±15% tolerance, that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. more details AGTL+ buffer specification, Intel® Pentium® Processor Developer's Manual AP-585, Intel® Pentium® Processor AGTL+ Guidelines.
Table Processor AGTL+ Specifications
Symbol On-die VREF Parameter Termination Voltage Termination Resistor Reference Voltage 0.950 1.50 1.05 Units Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. Pentium processors PGA370 socket contain AGTL+ termination resistors processor die, except RESET# input. Vcc1.5 must held ±9%. required that Vcc1.5 held while processor system idle (static condition). This measured PGA370 socket pins bottom side baseboard. value on-die determined resistor value measured RTTCTRL signal pin. Section more details RTTCTRL signal. Refer recommendation guidelines specific chipset/processor combination. VREF generated motherboard should nominally. Insure that there adequate VREF decoupling motherboard.
Table Processor AGTL Specifications
Symbol On-die VREF Parameter Termination Voltage Termination Resistor Reference Voltage 1.14 1.25 1.308 Units Notes
NOTES: Specifications this table apply Pentium processors frequencies. Please refer Intel® Pentium® Processor Specification Update complete listing processors that support AGTL specification. Pentium processors PGA370 socket contain AGTL termination resistors processor die, except RESET# input. must held 1.25 ±9%. required that held 1.25 while processor system idle (static condition). This measured PGA370 socket pins bottom side baseboard. value on-die determined resistor value measured RTTCTRL signal pin. on-die resistance tolerance ±15%. Section more details RTTCTRL signal. Refer recommendation guidelines specific chipset/processor combination. VREF generated motherboard should nominally. Insure that there adequate VREF decoupling motherboard. Coppermine-T differential clock platform, on-die should Coppermine-T platforms require resistor Coppermine-T platforms require resistor. Tolerance on-die ±10% resistors ±15% resistor
Datasheet
Pentium® Processor PGA370 Socket 1.13
2.12
System SpecificationThe processor system timings specified this section defined socket pins bottom motherboard. Unless otherwise specified, timings tested processor pins during manufacturing. Timings processor pins specified design characterization. Section processor signal definitions. Table through Table list specifications associated with processor system bus. These specifications placed into following categories: Table Table contain system clock specifications, Table contains AGTL+/AGTL specifications, Table contains CMOS signal group specifications, Table contains timings reset conditions, Table covers APIC timing, Table covers power timing. processor system specifications AGTL+/AGTL signal group relative rising edge BCLK input. AGTL+/AGTL timings referenced VREF both logic levels unless otherwise specified. timings specified this section should used conjunction with buffer models provided Intel. These buffer models, which include package information, available Pentium processor FC-PGA package Viewlogic* XTK/XNS* model format (formerly known QUAD format) IBIS format Pentium Processor PGA370 Socket Buffer Models (Electronic Format). AGTL AGTL+ layout guidelines also available appropriate platform design guide. Care should taken read notes associated with particular timing parameter.
2.12.1
Buffer Model
electronic copy Buffer Model AGTL+ CMOS signals available Intel's Developer's Website (http://developer.intel.com). model single processor designs assumes presence motherboard values described Table page
Table System Specifications (SET Clock)1,
Parameter System Frequency BCLK Period BCLK Period Stability BCLK High Time BCLK Time BCLK Rise Time BCLK Fall Time 10.0 ±250 ±250 100.00 133.33 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. timings AGTL+ signals referenced BCLK rising edge 1.25 processor pin. AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor pins.
Datasheet
Pentium® Processor PGA370 Socket 1.13
100% tested. Specified design characterization clock driver requirement. internal core clock frequency derived from processor system clock. system clock core clock ratio determined during initialization. Individual processors will only operate their specified system frequency, either MHz, both. BCLK period allows +0.5 tolerance clock driver variation. appropriate clock synthesizer/ driver specification details. difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load This should measured rising edges adjacent BCLKs crossing 1.25 processor pin. jitter present must accounted component BCLK timing skew between devices. clock driver's closed loop jitter bandwidth must allow PLL-based device track jitter created clock driver. attenuation point, measured into load, should less than kHz. This specification ensured design characterization and/or measured with spectrum analyzer. appropriate clock synthesizer/driver specification details BCLK Rise time measure between V-2.0 BCLK fall time measured between V-0.5 BCLK high time measured period time above BCLK time measured period time below 10.This specification applies Pentium processors operating system frequency MHz. This specification applies Pentium processors operating system frequency
Table System Timing Specifications (Differential Clock)1,
Parameter Clock Period-Average Instantaneous Minimum Clock Period Differential Rise Time Differential Fall Time Waveform Symmetry Differential Cycle Cycle Jitter Differential Duty Cycle Rising Edge Ring Back Falling Edge Ring Back Cross Point Input High Voltage Input Voltage 0.51 0.92 -0.2 0.35 -0.35 0.76 1.45 0.35 0.51 0.92 -0.2 7.30 0.35 -0.35 0.76 1.45 0.35 10.0 10.2 Units Note
NOTES: Measurement taken from differential waveform, defined BCLK BCLK#. Period defined from rising V-crossing next. Measurement taken from differential waveform, voltage range from -0.35 +0.35 Measurement taken from common mode waveform, measure rise/fall time from 0.41 0.86 Rise/fall time matching defined "the instantaneous difference between maximum BCLK rise (fall) minimum BCLK# fall (rise) time, minimum BCLK rise (fall) maximum BCLK# fall (rise) time. "This parameter designed guard waveform symmetry. Period difference measured around V-crossings; measurement taken from differential waveform. rising falling edge ringback voltage specified minimum (rising) them maximum (falling) voltage, differential waveform after passing Vih_diff (rising) Vil_diff (falling) Measured absolute voltage, i.e. single-ended measurement. Includes every cross point both rise fall BCLK. Input high input voltage range measured absolute voltage, i.e. single-ended measurement. internal Core clock frequency derived from processor system clock. system clock core clock ratio determined during initialization. Individual processors will only operate their specified system frequency MHz. Table shows supported ratios each processor 10.Due difficulty accurately measuring clock jitter system, recommended that clock driver used that designed meet period stability specification into test load jitter must accounted component BCLK timing skew between devices. parameters measured processor pins. 12.BCLK/BCLK# must rise/fall monotonically between Vih.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table System Specifications (AGTL+ AGTL Signal Group)1,
Parameter AGTL+ Output Valid Delay AGTL+ Input Setup Time AGTL+ Input Hold Time T10: RESET# Pulse Width 0.40 1.20 0.95 1.00 1.00 3.25 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. These specifications tested during manufacturing. timings AGTL+ signals referenced BCLK rising edge 1.25 processor pins (for AGTL, timings referenced rising edge BCLK falling edge BCLK# processor pins). AGTL+ signal timings (compatibility signals, etc.) referenced 1.00 (2/3 AGTL) processor pins. Valid delay timings these signals specified into VREF with on-die RTT. AGTL platforms, valid delay timings specified into 1.25 VREF with on-die RTT. minimum clocks must guaranteed between active-to-inactive transitions TRDY#. RESET# asserted (active) asynchronously, must deasserted synchronously. 2-way systems, RESET# should synchronous. Specification minimum 0.40 swing from VREF VREF This assumes edge rate 0.3V/ns. Specification maximum (2/3 AGTL) swing from VTT. This assumes edge rate 3V/ns. This should measured after VCCCORE, VTT, VccCMOS, BCLK become stable. 10.This specification applies Pentium processor running system frequency. This specification applies Pentium processor running system frequency. 12.BREQ signals system observe minimum setup time. 13.For AGTL, VREF ±3%.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table System Specifications (CMOS Signal Group)
Parameter T14: CMOS Input Pulse Width, except PWRGOOD T15: PWRGOOD Inactive Pulse Width Unit BCLKs BCLKs Figure Notes Active Inactive states
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies These specifications tested during manufacturing. These signals driven asynchronously. CMOS outputs shall asserted least BCLKs. When driven inactive after VCCCORE, VTT, VCCCMOS, BCLK become stable.
Table System Specifications (Reset Conditions)
Parameter T16: Reset Configuration Signals (A[14:5]#, BR0#, INIT#) Setup Time T17: Reset Configuration Signals (A[14:5]#, BR0#, INIT#) Hold Time Unit BCLKs BCLKs Figure Notes Before deassertion RESET# After clock that deasserts RESET#
NOTE: Unless otherwise noted, specifications this table apply Pentium processor frequencies.
Table System Specifications (APIC Clock APIC I/O)1,
Parameter T21: PICCLK Frequency T22: PICCLK Period T23: PICCLK High Time T24: PICCLK Time T25: PICCLK Rise Time T26: PICCLK Fall Time T27: PICD[1:0] Setup Time T28: PICD[1:0] Hold Time T29a: PICD[1:0] Valid Delay (Rising Edge) T29b: PICD[1:0] Valid Delay (Falling Edge) 30.0 10.5 10.5 0.25 0.25 12.0 33.3 500.0 Unit 1.7V 0.7V (0.7V 1.7V) (1.7V 0.7V) Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. These specifications tested during manufacturing. timings APIC signals referenced PICCLK rising edge 1.25 processor pins. APIC signal timings referenced 0.75 processor pins. Referenced PICCLK rising edge. open drain signals, valid delay synonymous with float delay. Valid delay timings these signals specified into load pulled
Table Platform Power-On Timings2
Parameter T45: Valid Time Before VTT_PWRGD T46: Valid Time Before PWRGOOD T47: RESET# Inactive Valid Outputs T48: RESET# Inactive Drive Signals NOTES: Unit BCLK BCLK Figure Notes
Datasheet
Pentium® Processor PGA370 Socket 1.13
signals, during their invalid states, must guarded against spurious levels from effecting platform during processor power-up sequence. Configuration Input signals include: A[14:5], BR0#, BR1#, INIT#. timing these signals, please refer Table Figure
Note:
Figure through Figure following apply: Figure through Figure used conjunction with Table through Table timings AGTL+ signals processor pins referenced BCLK rising edge 1.25 AGTL+ signal timings (address bus, data bus, etc.) referenced 1.00 processor pins. timings APIC signals processor pins referenced PICCLK rising edge 1.25 APIC signal timings referenced 0.75 processor pins. timings signals processor pins referenced rising edge 0.75 signal timings (TMS, TDI, etc.) referenced 0.75 processor pins.
Figure Generic Clock Waveform
BCLK#
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure BCLK, PICCLK, Generic Clock Waveform
Vringback (rise) Vringback (fall)
diff
diff
T25, T34, (Rise T26, T35, (Fall T23, T32, (High T24, T33, (Low T22, TCK, Period) referenced 0.30V ifferential ode), 0.50V (Single-Ended ode) referenced Vref PICC referenced 0.4V. refernced 0.9V (Differental ode), 2.0V (Single-E nded ode) referenced Vref PICC refernced 1.6V BLCK crossing point rising edge BLCK falling edge BCLK# (Differential ode), BCLK refereced 1.25V (Single-Ended ode), reference 1.0V, referenced osref
Figure System Valid Delay Timing
BCLK# BCLK Valid
T11, T29a, T29b (Valid Delay) T14, (Pulse Width) NOTE: Single-Ended clock uses BCLK only, Differential clock uses BCLK BCLK#
Signal
Valid
Vref AGTL signal group; Vcmosref CMOS, APIC signal group
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure System Setup Hold TimingBCLK# VCross BCLK Valid
VCross Crossing point BLCK BCLK# T12, (Setup Time) NOTE: Single-Ended clock uses BCLK only, Differential clock uses BCLK BCLK# T13, (Hold Time) Vref AGTL signal group; 0.75V APIC signal group
Figure System Reset Configuration TimingBCLK# BCLK
RESET#
Configuration (A[14:5]#, BR0#, BR1#, FLUSH#, INT#)
Valid
(AGTL+ Input Hold Time) NOTE: Single-Ended clock uses BCLK only, (AGTL+ Input Setup Time) Differential clock uses BCLK BCLK# (RESET# Pulse Width) (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Setup Time) (Reset Configuration Signals (A[14:5]#, BR0#, BR1#, FLUSH#, INIT#) Hold Time)
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Platform Power-On Sequence TimingVtt, Vref Vcmosref BSEL[1:0]
Valid
Valid
VTT_PWRGD VCC_Core BCLK# BCLK PICCLK VCC_PWRGD Configuration Inputs RESET# THERMTRIP# PICD[1:0] AGTL Outputs other CMOS Outputs other InputInactive Inactive
Valid Config
Active
Valid
Valid
Valid
Valid
Active
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Power-On Reset Configuration Timing
BCLK CORE, VTT, VREF
PWRGOOD RESET#
VIL,
VIH,
Configuration (A20M#, IGNNE#, INTR, NMI) Valid Ratio (PWRGOOD Inactive Pulse) (RESET# Pulse Width) (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
765a
Datasheet
Pentium® Processor PGA370 Socket 1.13
Signal Quality SpecificationSignals driven processor system should meet signal quality specifications ensure that components read data properly ensure that incoming signals affect long term reliability component. Specifications provided simulation processor pins. Meeting specifications processor pins Table Table Table Table Table ensures that signal quality effects will adversely affect processor operation.
BCLK/BCLK# PICCLK Signal Quality Specifications Measurement GuidelineTable describes signal quality specifications processor pins processor system clock (BCLK) APIC clock (PICCLK) signals. Figure describes signal quality waveform system clock processor pins.
Table BCLK/PICCLK Signal Quality Specifications Simulation Processor Pins
Parameter BCLK PICCLK BCLK PICCLK Absolute Voltage Range BCLK Rising Edge Ringback PICCLK Rising Edge Ringback BCLK Falling Edge Ringback PICCLK Falling Edge Ringback 2.000 2.000 -0.58 2.000 2.000 0.500 0.700 3.18 0.500 0.700 Unit Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK/PICCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Table BCLK/PICCLK Signal Quality Specifications Simulation Processor Pins Differential Clock Platform AGTL
Parameter PICCLK PICCLK PICCLK Absolute Voltage Range PICCLK Rising Edge Ringback PICCLK Falling Edge Ringback 1.60 -0.4 1.60 0.40 0.40 Unit Figure Note
NOTES: Unless otherwise noted, specifications this table apply Pentium processors that support AGTL specification. Refer Intel® Pentium® Processor Specification Update complete listing processors that support AGTL specification.
Datasheet
Pentium® Processor PGA370 Socket 1.13
rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK/PICCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Figure BCLK, PICCLK Generic Clock Waveform Processor PinV3
AGTL+ AGTL Signal Quality Specifications Measurement GuidelineMany scenarios have been simulated generate AGTL+ layout guidelines which available appropriate platform design guide. Refer Intel® Pentium® Processor Developer's Manual (Order Number 243502) AGTL+/AGTL buffer specification. Table provides AGTL+ signal quality specifications processor simulating signal quality processor pins. Pentium processor PGA370 socket maximum allowable overshoot undershoot specifications given duration time detailed Table through Table Figure shows AGTL+/AGTL ringback tolerance Figure shows overshoot/undershoot waveform.
Table AGTL+ Signal Groups Ringback Tolerance Specifications Processor Pins
Parameter Overshoot Minimum Time High Amplitude Ringback Final Settling Voltage Duration Squarewave Ringback 0.50 ±200 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply Pentium processors frequencies. Specifications edge rate 0.8V/ns. Figure generic waveform. values specified design characterization. Please Table maximum allowable overshoot. Ringback between VREF VREF VREF VREF requires flight time measurements adjusted described Intel AGTL+ Specifications (Intel®Pentium®II Developers Manual). Ringback below VREF above VREF supported.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Intel recommends simulations exceed ringback value VREF ±200 allow margin other sources system noise. negative value indicates that amplitude ringback above VREF. (i.e., -100 specifies signal cannot ringback below VREF mV). measured relative VREF. measured relative VREF
Figure High AGTL+ Receiver Ringback Tolerance
Vstart Clock
VREF VREF VREF
0.7V
Time Note: High case analogou
AGTL+ Signal Quality Specifications Measurement GuidelineOvershoot/Undershoot GuidelineOvershoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot guideline limits transitions beyond fast signal edge rates. processor damaged repeated overshoot events tolerant buffers charge large enough (i.e., overshoot great enough). Determining impact overshoot/undershoot condition requires knowledge magnitude, pulse direction activity factor (AF). Permanent damage processor likely result excessive overshoot/undershoot. Violating overshoot/undershoot guideline will also make satisfying ringback specification difficult. When performing simulations determine impact overshoot overshoot, diodes must properly characterized. protection diodes voltage clamps will provide overshoot undershoot protection. diodes modeled within Intel Buffer models clamp undershoot overshoot will yield correct simulation results. other buffer models being used characterize Pentium processor performance, care must taken ensure that models clamp extreme voltage levels. Intel Buffer models also contain capacitance characterization. Therefore, removing diodes from Buffer model will impact results yield excessive overshoot/undershoot.
3.3.1
Datasheet
Pentium® Processor PGA370 Socket 1.13
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes maximum potential difference between signal voltage reference level, (overshoot) (undershoot). While overshoot measured relative using probe (probe signal lead VSS), undershoot must measured relative VTT. This could accomplished simultaneously measuring plane while measuring signal undershoot. Today's oscilloscopes easily calculate true undershoot waveform. true undershoot waveform also obtained with following oscilloscope data file analysis: Converted Undershoot Waveform Signal_measured Note: Note: converted undershoot waveform appears positive (overshoot) signal. Overshoot (rising edge) undershoot (falling edge) conditions separate their impact must determined independently. After true waveform conversion, undershoot/overshoot specifications shown Table through Table applied converted undershoot waveform using same magnitude pulse duration specifications used with overshoot waveform. Overshoot/undershoot magnitude levels must observe Absolute Maximum Specifications listed Table through Table These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed pulse durations. Provided that magnitude overshoot/undershoot within Absolute Maximum Specifications (2.18V), pulse magnitude, duration activity factor must used determine overshoot/undershoot pulse within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes total time overshoot/undershoot event exceeds overshoot/ undershoot reference voltage (Vos_ref 1.635 total time could encompass several oscillations above reference voltage. Multiple overshoot/undershoot pulses within single overshoot/undershoot event need measured determine total pulse duration. Note: Note: Oscillations below reference voltage cannot subtracted from total overshoot/undershoot pulse duration. Multiple Overshoot/Undershoot events occurring within same clock cycle must considered together event. Using worst case Overshoot/Undershoot Magnitude, together individual Pulse Durations determine total Overshoot/Undershoot Pulse Duration that total event.
3.3.4
Activity Factor
Activity Factor (AF) describes frequency overshoot undershoot) occurrence relative clock. Since highest frequency assertion AGTL+ CMOS signal every other clock, indicates that specific overshoot undershoot) waveform occurs EVERY OTHER clock cycle. Thus, 0.01 indicates that specific overshoot undershoot) waveform occurs time every clock cycles. specifications provided Table through Table show Maximum Pulse Duration allowed given Overshoot/Undershoot Magnitude specific Activity Factor. Each Table entry independent others, meaning that Pulse Duration reflects existence overshoot/undershoot events that magnitude only. platform with overshoot/undershoot that
Datasheet
Pentium® Processor PGA370 Socket 1.13
just meets pulse duration specific magnitude where means that there other overshoot/undershoot events, even lesser magnitude (note that then event occurs times other events occur). Note: Note: Activity factor AGTL+ signals referenced BCLK frequency. Activity factor CMOS signals referenced PICCLK frequency.
3.3.5
Reading Overshoot/Undershoot Specification TableThe overshoot/undershoot specification Pentium processor PGA370 socket simple single value. Instead, many factors needed determine what over/undershoot specification addition magnitude overshoot, following parameters must also known: junction temperature processor will operating width overshoot measured above 1.635 Activity Factor (AF). determine allowed overshoot particular overshoot event, following must done: Determine signal group that particular signal falls into. signal AGTL+ signal operating with system bus, Table (100MHz AGTL+ signal group). signal AGTL+ signal operating with 133MHz system bus, Table (133 AGTL+ signal group). signal CMOS signal, Table CMOS signal group). Determine maximum junction temperature (Tj) range processors that system will support (80oC 85oC). Determine Magnitude overshoot (relative VSS) Determine Activity Factor (how often does this overshoot occur?) From appropriate Specification table, read Maximum Pulse Duration allowed. Compare specified Maximum Pulse Duration signal being measured. Pulse Duration measured less than Pulse Duration shown table, then signal meets specifications. above procedure similar undershoots after undershoot waveform been converted look like overshoot. Undershoot events must analyzed separately from Overshoot events they mutually exclusive. Below example showing maximum pulse duration determined given waveform.
Table Example Platform Information
Required Information Signal Group Overshoot Magnitude Activity Factor (AF) Maximum Platform Support AGTL+ 2.13V Measured Value Measured overshoot occurs average every clocks Note
NOTES: Corresponding Maximum Pulse Duration Specification Pulse Duration (measured)
Given above parameters, using Table oC/AF column) maximum allowed pulse duration Since measure pulse duration this particular overshoot event passes overshoot specifications, although this doesn't guarantee that combined overshoot/ undershoot events meet specifications.
Datasheet
Pentium® Processor PGA370 Socket 1.13
3.3.6
Determining System Meets Overshoot/Undershoot SpecificationThe overshoot/undershoot specifications listed following tables specify allowable overshoot/undershoot single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their parameters (duration, magnitude). While each overshoot meet overshoot specification, when total impact overshoot events, system fail. guideline ensure system passes overshoot undershoot specifications shown below. important meet these guidelines; otherwise, contact your Intel field representative. Insure signal (CMOS AGTL+/AGTL) ever exceed 1.635 only overshoot/undershoot event magnitude occurs, ensure meets over/undershoot specifications following tables multiple overshoots and/or multiple undershoots occur, measure worst case pulse duration each magnitude compare results against specifications. these worst case overshoot undershoot events meet specifications (measured time specifications) table (where AF=1), then system passes. following notes apply Table through Table
NOTES: Overshoot/Undershoot Magnitude 2.18 Absolute value should never exceeded Overshoot measured relative VSS. Undershoot measured relative Overshoot/Undershoot Pulse Duration measured relative 1.635 Ringbacks below subtracted from Overshoots/Undershoots Leser Undershoot does allocate longer larger Overshoot OEM's encouraged follow Intel provided layout guidelines. Consult layout guidelines provided specific platform design guide. values specified design characterization
Table AGTL+ AGTL Signal Group Overshoot/Undershoot Tolerance Processor Pins1,2
Overshoot/ Undershoot Magnitude 2.18 2.13 2.08 2.03 1.98 1.93 1.88 Maximum Pulse Duration (ns) 0.01 2.53 4.93 16.6 0.25 0.49 0.91 1.67 Maximum Pulse Duration (ns) 0.01 18.6 1.86 11.4 0.18 0.32
NOTES: BCLK period Measurements taken processor socket pins solder-side motherboard.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table AGTL+/AGTL Signal Group Overshoot/Undershoot Tolerance
Overshoot/Undershoot Magnitude 2.18 2.13 2.08 2.03 1.98 1.93 1.88 Maximum Pulse Duration (ns) 0.01 12.5 0.19 0.37 0.68 1.25 2.28 Maximum Pulse Duration (ns) 0.01 0.14 0.24 0.46 0.84
NOTES: BCLK period Measurements taken processor socket pins solder-side motherboard.
Table CMOS Signal Group Overshoot/Undershoot Tolerance Processor Pins1,
Overshoot/ Undershoot Magnitude 2.18 2.13 2.08 2.03 1.98 1.93 1.88 Maximum Pulse Duration (ns) 0.01 14.8 27.2 0.76 1.48 16.4 Maximum Pulse Duration (ns) 0.01 18.4 0.56 0.96
NOTES: PICCLK period Measurements taken processor socket pins solder-side motherboard.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
Time Dependent Overshoot 2.18V 2.08V 1.98V 1.88V 1.635V Converted Undershoot Waveform
Overshoot Magnitude
Undershoot Magnitude
Overshoot Signal Magnitude Undershoot Signal Magnitude
Time Dependent Undershoot
Figure Maximum Acceptable AGTL Overshoot/Undershoot Waveform
.1ns
Time dependent Overshoot
1.78V 1.62V 1.47V 1.32V
Vos_ref
Vs-.15V -.30V -.46V
Time dependent Undershoot
Datasheet
Pentium® Processor PGA370 Socket 1.13
Non-AGTL+ (Non-AGTL) Signal Quality Specifications Measurement GuidelineThere three signal quality parameters defined non-AGTL+ signals: overshoot/undershoot, ringback, settling limit. three signal quality parameters shown Figure nonAGTL+ signal group.
Figure Non-AGTL+ (Non-AGTL) Overshoot/Undershoot, Settling Limit, Ringback
Overshoot Settling Limit
Rising-Edge Ringback
Falling-Edge Ringback
Settling Limit
Time
Undershoot
NOTES: non-AGTL+ signals except BCLK, PICCLK, PWRGOOD. BCLK, PICCLK, PWRGOOD. BCLK PICCLK signal quality detailed Section 3.1.
3.4.1
Overshoot/Undershoot GuidelineOvershoot undershoot) absolute value maximum voltage above nominal high voltage below VSS. overshoot guideline limits transitions beyond fast signal edge rates (see Figure non-AGTL+ signals). processor damaged repeated overshoot events tolerant buffers charge large enough (i.e., overshoot great enough). Permanent damage processor likely result excessive overshoot/undershoot. Violating overshoot/undershoot guideline will also make satisfying ringback specification difficult. overshoot/undershoot guideline assumes absence diodes input. These guidelines should verified simulations without onchip protection diodes present because diodes will begin clamping tolerant signals beginning approximately above appropriate supply below VSS. signals reaching clamping voltage, this will issue. system should rely diodes overshoot/undershoot protection this will negatively affect life components make meeting ringback specification very difficult.
Note:
undershoot guideline limits transitions exactly described ATGL+/AGTL signals. Figure
Datasheet
Pentium® Processor PGA370 Socket 1.13
3.4.2
Ringback Specification
Ringback refers amount reflection seen after signal switched. ringback specification voltage that signal rings back after achieving maximum absolute value. Figure illustration ringback. Excessive ringback cause false signal detection extend propagation delay. ringback specification applies input each receiving agent. Violations signal ringback specification allowed under circumstances non-AGTL+ (non-AGTL) signals. Ringback simulated with without input protection diodes that added input buffer model. However, signals that reach clamping voltage should evaluated further. Table signal ringback specifications non-AGTL+ signals simulations processor pins.
Table Signal Ringback Specifications Non-AGTL+ Signal Simulations Processor Pins1
Input Signal Group Non-AGTL+ Signals Non-AGTL+ Signals PWRGOOD
Transition
Maximum Ringback (with Input Diodes Present) VCMOS_REF 0.200 VCMOS_REF 0.200 2.00
Unit
Figure
NOTES: Unless otherwise noted, specifications this table apply Pentium processor frequencies. Non-AGTL+ signals except PWRGOOD.
Table Signal Ringback Specifications Non-AGTL Signal Simulations Processor Pins
Input Signal Group Non-AGTL+ Signals Non-AGTL+ Signals PWRGOOD
Transition
Maximum Ringback (with Input Diodes Present) VCMOS_REF 0.200 VCMOS_REF 0.300 2.00
Unit
Figure
NOTES: Unless otherwise noted, specifications this table apply Pentium processor frequencies. Non-AGTL signals except PWRGOOD. Coppermine-T with differential clocking, this signal tolerant.
3.4.3
Settling Limit Guideline
Settling limit defines maximum amount ringing receiving that signal must reach before next transition. amount allowed total signal swing (VHI -VLO) above below final value. signal should within settling limits final value, when either high state state, before transitions again. Signals that within their settling limit before transitioning risk unwanted oscillations which could jeopardize signal integrity. Simulations verify settling limit done either with without input protection diodes present. Violation settling limit guideline acceptable simulations successive transitions show amplitude ringing increasing subsequent transitions.
Datasheet
Pentium® Processor PGA370 Socket 1.10
Thermal Specifications Design ConsiderationThis chapter provides needed data designing thermal solution. However, correct thermal measuring processes, refer AP-905, Intel® Pentium® Processor Thermal Design Guidelines (Document Number 245087). Pentium processor uses flip chip grid array packaging technology junction (Tjunction) case temperature (Tcase) specified.
Thermal SpecificationTable provides thermal design power dissipation maximum temperatures Pentium processor PGA370 socket. Systems should design highest possible processor power, even processor with lower thermal dissipation planned. thermal solution should designed ensure junction temperature never exceeds these specifications.
Table Intel® Pentium® Processor Thermal Design Power FC-PGA Package1
Processor Thermal Design Power CPUID 0686h 13.2 14.0 14.5 15.8 15.8 17.0 17.5 18.3 19.1 19.5 20.8 20.8 22.5 22.9 23.2 24.5 26.1 29.6 Processor Thermal Design Power CPUID 068Ah 19.6 21.9 22.8 23.2 24.5 24.5 25.7 26.1 26.7 27.5 29.0 29.0 33.0 Power Density5 CPUID 068Ah (W/cm2) TJUNCTION Offset Latest Stepping
Processor
Processor Core Frequency (MHz)
System Frequency (MHz)
Maximum TJUNCTION10 (°C)
(°C)
500E 533EB 550E 600E 600EB 800EB
1000 1000 1000 1100
30.5 34.1 35.5 36.1 38.2 38.2 40.0 40.7 41.6 42.8 45.2 45.2 51.4
1.10
NOTES: These values specified nominal VCCCORE processor pins.
Datasheet
Pentium® Processor PGA370 Socket 1.10
Thermal Design Power (TDP) represents maximum amount power thermal solution required dissipate. thermal solution should designed dissipate power without exceeding maximum Tjunction specification. does represent power delivery voltage regulation requirements processor. Refer Table voltage regulation electrical specifications. Tjunctionoffset worst-case difference between thermal reading from on-die thermal diode hottest location processor's core. Power density maximum power processor dissipate (i.e., processor power) divided area over which power generated. Power these processors generated from core area shown Figure TJUNCTION offset values include thermal diode measurement error. Diode measurement error must added TJUNCTION offset value from table, outlined Intel® Pentium® processor Thermal Metrology CPUID-068h Family Processors (Order Number: 245301). Intel characterized Analog Devices AD1021 diode measurement found measurement error This specification only applies S-Spec SL4WM. This part request 1.70 however processor should supplied 1.76 pins (Voltage Regulator Module) voltage regulator circuit. This specification applies processors with CPUID 068AH. exists both FC-PGA FC-PGA2 packages. This specification applies processors with CPUID 0686H. Tjunction minimum specification
Table provides thermal design power dissipation maximum temperatures Pentium processor FC-PGA2 package. Systems should design highest possible processor power, even processor with lower thermal dissipation planned. thermal solution should designed ensure case temperature never exceeds these specifications.
Table Intel® Pentium® Processor FC-PGA2 Package Thermal Design Power
Processor Core Frequency (MHz) 1000 1133 System Frequency (MHz) Processor Thermal Design Power CPUID 068Ah 29.5 31.5 33.9 37.5 Maximum Tcase4 (°C) Additional Note
Processor
1.13
NOTES: These values specified nominal VCCCORE processor pins. Thermal Design Power (TDP) represents maximum amount power thermal solution required dissipate. thermal solution should designed dissipate power without exceeding maximum Tcase specification. does represent power delivery voltage regulation requirements processor. Refer Table voltage regulation electrical specifications. TCaseOffset worst-case difference between maximum case temperature thermal diode temperature processor's core. more information please refer document, Intel® Pentium® Processor FC-PGA2 Package Thermal Design Guide. This processor exists both FC-PGA FC-PGA2 packages.
Processor Area
Figure block diagram Pentium processor layout Table contains Pentium processor layout measurements. layout differentiates processor core from cache area. effect, thermal design power identified Table dissipated entirely from processor core area. Thermal solution designs should compensate this smaller heat flux area assume that power uniformly distributed across entire area.
Datasheet
Pentium® Processor PGA370 Socket 1.10
Figure Processor Functional Layout FC-PGA
Cache Area
Product Label
Area
Core Area (~63% area)
Table Processor Functional Layout FC-PGA
CPUID 0683H 0686H 068AH Area (cm2) 1.046 0.900 0.947 Core Area (cm2) 0.726 0.642 0.642 Cache Area (cm2) 0.320 0.258 0.305
Thermal Diode
Pentium processor PGA370 socket incorporates on-die diode that used monitor temperature (junction temperature). thermal sensor located motherboard, stand-alone measurement kit, monitor temperature processor thermal management instrumentation purposes. Table Table provide diode parameter interface specifications. more information please refer document, Intel® Pentium® Processor FC-PGA2 Package Thermal Design Guide.
Note:
reading thermal sensor connected thermal diode will necessarily reflect temperature hottest location die. This inaccuracies thermal sensor, ondie temperature gradients between location thermal diode hottest location given point time, time based variations temperature measurement. Time based variations occur when sampling rate thermal diode thermal sensor) slower than rate which Tjunction temperature change.
Datasheet
Pentium® Processor PGA370 Socket 1.10
Table Thermal Diode Parameters1
Symbol Parameter Forward Bias Current Diode Ideality Factor 1.0057 1.0080 1.0125 Unit Notes
NOTES: Intel does support recommend operation thermal diode under reverse bias. Characterized with forward bias current µA-300 ideality factor, represents deviation from ideal diode behavior exemplified diode equation: Ifw=Is(e^ ((Vd*q)/(nkT)) where saturation current, electronic charge, voltage across diode, Boltzmann Constant, absolute temperature (Kelvin). 100% tested. Specified design characterization.
Table Thermal Diode Interface
Name THERMDP THERMDN PGA370 Socket AL31 AL29 Description diode anode (p_junction) diode cathode (n_junction)
Datasheet
Pentium® Processor PGA370 Socket 1.13
Mechanical SpecificationThe Pentium processor uses FC-PGA FC-PGA2 package technology. Mechanical specifications processor given this section. FC-PGA2 contains Integrated Heat Spreader (IHS) spread heat generated from die. Section 1.1.1 complete terminology listing. processor utilizes PGA370 socket installation into motherboard. Details socket available 370-Pin Socket (PGA370) Design Guidelines.
Note:
Figure Figure following apply: Unless otherwise specified, following drawings dimensioned inches. dimensions provided with tolerances guaranteed normal production product. Figures drawings labeled "Reference Dimensions" provided informational purposes only. Reference dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference dimensions checked part processor manufacturing. Unless noted such, dimensions parentheses without tolerances reference dimensions. Drawings scale. following figure with package dimensions provided design heatsink clip solutions well demonstrate where pin-side capacitors will located processor. Table includes measurements these dimensions both inches millimeters.
Figure FC-PGA FC-PGA2 Package Type
FC-PGA2
FC-PGA
FC-PGA Mechanical SpecificationThe following figure with package dimensions provided design heatsink clip solutions well demonstrate where pin-side capacitors will located processor. Table includes measurements these dimensions both inches millimeters.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Package Dimension
Table Intel® Pentium® Processor Package DimensionMillimeters Symbol Minimum 3.048 0.431 0.787 1.000 11.226 9.296 Maximum 0.889 1.200 11.329 9.398 Notes Minimum 0.031d 0.039 0.442 0.366 0.925 0.850 1.946 1.790 Nominal 3.302 0.483 Diameter 0.120 0.017 0.100 0.130 0.019 1.954 1.810 0.700 0.700 0.035 Nominal Maximum 0.035 0.047 0.446 0.370 Notes Inche
23.495 21.590 49.428 45.466 0.000 0.000 0.000 2.540 49.632 45.974 17.780 17.780 0.889
0.508 Diametric True Position (Pin-to-Pin)
0.020 Diametric True Position (Pin-to-Pin)
NOTE: Capacitors will placed pin-side FC-PGA package area defined This area keepout zone motherboard designers.
Datasheet
Pentium® Processor PGA370 Socket 1.13
bare processor mechanical load limits that should exceeded during heat sink assembly, mechanical stress testing, standard drop shipping conditions. heatsink attach solution must induce permanent stress into processor substrate with exception uniform load maintain heatsink processor thermal interface. package dynamic static loading parameters listed Table Table following apply: recommended portion processor substrate mechanical reference load bearing surface thermal solutions. Parameters assume uniformly applied loads.
Table Processor Loading Parameters FC-PGA
Parameter Silicon Surface Silicon Edge Dynamic (max)1 Static (max)2 Unit Added Notes
NOTES: This specification applies uniform non-uniform load. This maximum static force that applied heatsink clip maintain heatsink processor interface. Please socket manufacturer's force loading specification also ensure compliance.
Datasheet
Pentium® Processor PGA370 Socket 1.13
5.1.1
FC-PGA2 Mechanical SpecificationThe following figure provided design heatsink clip solutions. Also, used demonstrate where pin-side capacitors will located processor. Table includes measurements these dimensions both inches millimeters.
Figure Package Dimensions FC-PGA2
Table Package Dimensions Intel® Pentium® Processor FC-PGA2 Package
Millimeters Symbol Minimum 3.048 0.431 2.266 0.980 30.800 30.800 Maximum 2.690 1.180 31.200 31.200 Notes Minimum 0.089 0.038 1.212 1.212 1.299 1.299 1.946 1.790 0.000 0.000 0.000 Nominal 3.302 0.483 0.120 0.017 0.100 0.130 0.019 1.954 1.810 0.700 0.700 0.035 Nominal Maximum 0.106 0.047 1.229 1.229 Notes Inche
33.000 33.000 49.428 45.466 0.000 0.000 0.000 2.540 49.632 45.974 17.780 17.780 0.889
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table Package Dimensions Intel® Pentium® Processor FC-PGA2 Package
Millimeters Symbol Minimum Maximum Notes Minimum Maximum Notes 0.508 Diametric True Position (Pin-to-Pin) 0.020 Diametric True Position (Pin-to-Pin) Inche
NOTE: Capacitors will placed pin-side FC-PGA package area defined This area keepout zone motherboard designers.
Table following apply: recommended portion processor substrate mechanical reference load bearing surface thermal solutions. Parameters assume uniformly applied loadTable Processor Case Loading Parameters FC-PGA2
Parameter Surface Edge Corner Transient (max)1, Dynamic (max)2, Static (max)3, Unit
NOTES: Transient loading refers time short duration loading, such during heatsink installation. Dynamic loading refers shock load. This maximum static force that applied heatsink clip maintain heatsink processor interface. Please socket manufacturer's force loading specification also ensure compliance. Maximum static loading listed here does account maximum reaction forces socket tabs pins. Designs must ensure that socket withstand this force.
Figure FC-PGA2 Flatness Specification
Note: Flatness specifications millimeter
Datasheet
Pentium® Processor PGA370 Socket 1.13
Processor MarkingThe following figure exemplifies processor top-side markings provided identification Pentium processor PGA370 socket. Table Table list measurements package dimensions.
Figure Side Processor Markings FC-PGA CPUID 0x686H)
Dynamic Production Mark Example
Static Mark printed substrate supplier pentium logo Country Origin
intel
RB80526PY550266 FFFFFFFF-0001 SSSSS
MALAY
S-spec#
Product Code
Dynamic Laser Mark Swatch
Figure Side Processor Markings FC-PGA (for CPUID 0x68AH))
GRP1LN1: INTEL (m)(c) '01_-_{COO} GRP1LN2: {Speed}/{Cache}/{Bus}/{Voltage}
GRP2LN1: {FPO}-{S/N} GRP2LN2: PENTIUM {S-Spec}
5.2.1
Processor Markings FC-PGA2
following figure exemplifies processor top-side markings provided identification Pentium processor FC-PGA2 socket. Table lists measurements package dimensions. (Note: this package label will also have matrix mark.)
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Side Processor Markings FC-PGA2
GRP1LN1 GRP1LN2
GRP1LN1: INTEL (m)(c) '01_-_{Country Origin} GRP1LN2: {Core freq}/{Cache}/{Bus Freq}/{Voltage}
GRP2LN1 GRP2LN2
GRP2LN1: {FPO}-{S/N} GRP2LN2: PENTIUM {S-Spec}
Recommended Mechanical Keep-Out Zone
Figure Volumetric Keep-Out FC-PGA FC-PGA2
NOTES: This drawing applies FC-PGA2 package. only differences from FC-PGA package Keep-Out drawing follows: height 2.160" changed from 2.100" height 1.118" changed from 1.058". Refer Pentium Thermal/Mechanical Solution Functional Guidelines (see section reference order number) latest information.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Component Keep-Out
Processor Signal Listing
Table Table provide processor definitions. signal locations PGA370 socket used signal routing, simulation, component placement baseboard. Figure provides pin-side view Pentium processor pinout.
Datasheet
Pentium® Processor PGA370 Socket 1.13
Figure Intel® Pentium® Processor Pinout
RESET VREF5 CLKREF PLL1 VREF4 VREF6 REQ1 REQ4 REQ0 BPRI DEFER REQ3 LOCK VREF7 HIHIT TRDY DBSY PWRGD DRDY TRST VID0 VID1
BSEL1 INIT A20M BSEL0 VID3 THRMDN THRMDP VID2 AERR
REQ2 THERM TRIP
EDGCTRL STPCLK IERR V_1.5 IGNNE
FLUSH
FERR
V_CMOS
V_2.5
BCLK RESET2 BERR VREF1 PICCLK VREF3
Side View
PLL2
CTRL LINT0 LINT1
PICD1 PICD0
VREF2
PREQ
DEP7 Dep7 DEP3 DEP2 PRDY SLEW DEP6 DEP4 VREF0 BPM1 CTRL DEP5 DEP1 DEP0 BPM0 CPUPRES
BINIT
pinout
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table Signal Listing Order Signal Name
AH12 AL15 AH10 AK10 AK14 AE33 AN31 AK24 AL11 AN13 Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A20M# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# ADS# AERR# AP0# AP1# BCLK BERR# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ System Clock AGTL+
Table Signal Listing Order Signal Name (Continued)
AH14 AN17 AN29 AJ33 AJ31 Name BINIT# BNR# BP2# BP3# BPM0# BPM1# BPRI# BR0# BR1#8 BSEL0 BSEL1 CLKREF
Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+ AGTL+ Input Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+
CPUPRES# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26#
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table Signal Listing Order Signal Name (Continued)
AL27 AN19 Name D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DEP0# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Input AGTL+
Table Signal Listing Order Signal Name (Continued)
AN27 AC35 AE37 AM22 AM26 AM30 AM34 Name DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DRDY# EDGCTRL FERR# FLUSH# Signal Group AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Power/Other CMOS Output CMOS Input Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table Signal Listing Order Signal Name (Continued)
AB32 AC33 AD34 AF32 AF36 AH34 AJ11 AJ15 AJ19 AJ23 AJ27 AK36 AM10 AM14 AM18 Name Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Signal Listing Order Signal Name (Continued)
AL25 AL23 AE35 AG37 AG33 AK20 AK26 AK18 AH16 AH18 AL19 AL17 Name HIT# HITM# IERR# IGNNE# INIT# LINT0/INTR LINT1/NMI LOCK# PICCLK PICD0 PICD1 PLL1 PLL2 PRDY# PREQ# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other AGTL+ AGTL+ CMOS Output CMOS Input CMOS Input CMOS Input CMOS Input AGTL+ APIC Clock Input APIC APIC Power/Other Power/Other AGTL+ Output CMOS Input CMOS Input AGTL+ AGTL+ AGTL+ AGTL+ AGTL+ Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future Reserved future
Datasheet
Pentium® Processor PGA370 Socket 1.13
Table Signal Listing Order Signal Name (Continued)
AK30 AN23 AH26 AH22 AK28 AC37 AH30 AJ35 AG35 AL33 AN35 AN37 AL29 AL31 AH28 AK32 AN25 AN33 AD36 AB36 AA37 AB34 AD32
Table Signal Listing Order Signal Name (Continued)
AF34 AH24 AH32 AH36 AJ13 AJ17 AJ21 AJ25 AJ29 AK34 AM12 AM16 Name VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE Signal Group Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Ot
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