3.0GHz Phase Noise Frequency Synthesiser DS5077 ISSUE J

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3.0GHz Phase Noise Frequency Synthesiser DS5077 ISSUE J

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SP5768 SP5768
3.0GHz Phase Noise Frequency Synthesiser
DS5077
ISSUE
July 2001
Features
Complete 3.0GHz single chip system Optimised phase noise, with comparison frequencies prescaler Selectable reference division ratio Reference frequency output Selectable charge pump current Integrated loop amplifier Four switching ports power replacement SP5658 5668 Downwards software compatible with SP5658 protection, (Normal handling procedures should observed)
Ordering Information
SP5768/KG/MP1S (Tubes) SP5768/KG/MP1T (Tape Reel) SP5768/KG/QP1S (Tubes) SP5768/KG/QP1T (Tape Reel)
Description
SP5768 single chip frequency synthesiser designed tuning systems 3.0GHz optimized phase noise with comparison frequencies MHz. programmable divider contains front dual modulus 16/17 functioning over full operating range allows coarse tuning upconverter application fine tuning downconverter. Comparison frequencies obtained either from crystal controlled on-chip oscillator from external source. buffered reference frequency output also available drive second SP5768. device also contains switching ports.
Applications
Cable tuning systems Communications systems
COUNT INPUT 16/17 COUNT
REFERENCE DIVIDER
CRYSTAL CRYSTAL
CHARGE PUMP DRIVE
LATCH
LATCH
DATA CLOCK ENABLE DATA INTERFACE
LATCH PORT/ TEST MODE INTERFACE
PORT P0/OP
PORT P1/OC
PORT
PORT
Figure SP5768 block diagram
SP5768
CHARGE PUMP CRYSTAL CRYSTAL ENABLE DATA CLOCK PORT P1/OC PORT
DRIVE INPUT INPUT PORT P0/OP PORT
Figure Connections Diagram
SPOT REF.
MP16 QP16
Electrical Characteristics
These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated. TAMB -40°C 80°C,
Characteristic
Value
3000
Units
Conditions
Supply current input frequency range input voltage
13,14 13,14
200MHz mVrms Figure Figure
input impedance Data, clock enable input high voltage input voltage input current hysterysis Clock rate timing data data hold enable enable hold clock enable
13,14 5,6,4 5,6,4
input conditions
SP5768
Electrical Characteristics (continued)
These characteristics guaranteed either production test design. They apply within specified ambient temperature supply voltage unless otherwise stated. Tamb -40°C 80°C, Characteristic Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency External reference input frequency External reference drive level Buffered reference frequency output output amplitude output impedance Comparison frequency Equivalent phase noise phase detector -148 Value Units Table Vpin1 Vpin1=2V, +5.0V, Tamb 25°C Vpin 16=0.7V Conditions
Figure application Sinewave coupled through blocking capacitor Sinewave coupled through 10nF blocking capacitor coupled, note
0.35 dBc/Hz
2-20MHz
kHz, SSB, with comparison from crystal reference
division ratio Reference division ratio Output ports P0-P3 sink current leakage current 7,8,9,10
131071 Table Note Vport 0.7V Vport
Reference output disabled connecting required Output ports high impedance power with data, clock enable logic
SP5768
Absolute Maximum Ratings
voltages referred Characteristic Supply voltage, input voltage input offset Port voltage Charge pump offset Varactor drive offset Crystal offset Buffered output Data, clock enable offset Storage temperature Junction temperature MP16 thermal resistance, chip ambient chip case Power consumption Vcc=5.5V protection 13,14 13,14 7,8,9,10 5,6,4 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 cc+0.3 cc+0.3 cc+0.3 cc+0.3 cc+0.3 cc+0.3 cc+0.3 +125 +150 Units Vp-p °C/W °C/W ports Mil-std 883B latest revision method 3015 cat.1. Differential Conditions
Functional description
SP5768 contains elements necessary, with exception frequency reference, loop filter external high voltage transistor, control varicap tuned local oscillator, forming complete frequency synthesised source. device allows operation with high comparison frequency fabricated high speed logic, which enables generation loop with excellent phase noise performance, even with high comparison frequencies. package allocation shown Figure block diagram Figure SP5768 controlled standard 3-wire comprising data, clock enable inputs. programming word contains bits, four which used port selection, programmable divider ratio, four bits select reference division ratio, bits R0-R2, Table bits charge pump current, Table remaining access test modes, Table programming format shown Figure clock input disabled enable signal, data therefore only loaded into internal shift registers during enable high clocked into controlling buffers enable high transition. This load also synchronised with programmable divider giving smooth fine tuning. signal internal preamplifier, which provides gain reverse isolation from divider signals. output preamplifier fully programmable counter, which MN+A architecture. counter counter output programmable counter phase comparator where compared both phase frequency domain with comparison frequency. This frequency derived either from board crystal controlled oscillator from external reference source. both cases reference frequency divided down comparison frequency reference divider which programmable into1 ratios descried Table output phase detector feeds charge pump loop amplifier section, which when used with external high voltage transistor loop filter integrates current pulses into varactor line voltage. charge pump current setting described Table buffered crystal reference frequency suitable driving further synthesisers available from required this output disabled connecting programmable divider output divided Fpd/2 comparison frequency, Fcomp switched ports respectively switching device into test mode. test modes described Table
SP5768
+j0.5
+j0.2
-j0.2 Normalised -j0.5
Frequency Markers 500MHz, 1GHz, 1.5GHz 2.4GHz
Figure input impedance
CLOCK
ENABLE DATA
Frequency data
2^16 R2,R1,R0 P1,P0 C1,C0
Programmable divider ratio control bits Reference divider control bits Reference divider mode select Port control bits Charge pump current select Test mode enable
Figure Data format
Current 1000
Table Charge pump current
SP5768
18pF 39pF SP5768
Figure Crystal oscillator application
Table Reference division ratio
RATIO
don't care
FUNCTIONAL DESCRIPTION Normal operation Charge pump sink Charge pump source Charge pump disable Port Fcomp, Fpd/2
Table Test modes
SP5768
INTO
OPERATING WINDOW
1000 FREQUENCY (MHz)
3000
Figure Typical input sensitivity
900MHz
1.6GHz
38.9MHz
1650-2700MHz 1650 -2400MHz
SP5768 SP5748
SP5768 SP5748
10nF
Figure Example double conversion from VHF/UHF frequencies
18pF 39pF 4MHz
+30V 68pF 13k3 BCW31
+12V
Optional application utilising on-board crystal controlled oscillator
REFERENCE CONTROL MICRO ENABLE DATA CLOCK
OSCILLATOR OUTPUT
TUNER
SP5768
Figure Typical application SP5768
SP5768
Application Notes
generic application notes AN168 designing withsynthesisers such SP5768 been written. This covers aspects such loop filter design decoupling. This application note also featured Media Data Book, refer Zarlink Semiconductor Internet Site http://www.zarlink.com.
Loop Bandwidth
majority applications which SP5768 intended require loop filter bandwidth between 2kHz and10kHz. Typically phase noise will specified both 1kHz and10kHz offset. common practice arrange loop filter bandwidth such that 1kHz figure lies within loop bandwidth. Thus phase noise depends synthesiser comparator noise floor, rather than VCO. 10kHz offset figure should depend providing loop designed correctly, underdamped.
Reference Source
SP5768 offers optimal phase noise performance when operated with large step size. This fact that phase noise within loop bandwidth phase comparator frequency noise floor phase comparator frequency
Assuming phase comparator noise floor flat irrespective sampling frequency, this means that best performance will achieved when overall phase comparator division ratio minimum. There ways achieving higher phase comparator sampling frequency:- Reduce division ratio between reference source phase comparator higher reference source frequency. Approach preferred best performance since possible that noise floor reference oscillator degrade phase comparator performance reference division ratio very small.
SP5768
VREF
CHARGE PUMP
INPUTS
DRIVE
inputs
Loop amplifier
PORT
INPUT
BIAS
Disable, Enable, Data Clock inputs
Output Ports
CRYSTAL
CRYSTAL
1.2mA
Reference oscillator
Reference output
Figure Input/Output interface circuits
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3.0GHz Phase Noise Frequency Synthesiser DS5077 ISSUE J

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