SST36VF1601 SST36VF16012.7V 16Mb (x16) Concurrent SuperFlash
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Mbit Concurrent SuperFlash
SST36VF1601
SST36VF16012.7V 16Mb (x16) Concurrent SuperFlash
FEATURES:
Organized Dual Bank Architecture Concurrent Read/Write Operation Mbit Bottom Sector Protection SST36VF1601: Mbit Mbit Single 2.7-3.6V Read Write Operations Superior Reliability Endurance: 100,000 cycles (typical) Greater than years Data Retention Power Consumption: Active Current: typical Standby Current: typical Hardware Sector Protection/WP# Input Protects outermost sectors KWord) larger bank driving unprotects driving high Hardware Reset (RST#) Resets internal state machine reading array data Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Fast Read Access Time Latched Address Data Fast Erase Word-Program (typical): Sector-Erase Time: Block-Erase Time: Chip-Erase Time: Word-Program Time: Chip Rewrite Time: seconds Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility Conforms Common Flash Memory Interface (CFI) JEDEC Standards Flash EEPROM Pinouts command sets Packages Available 48-lead TSOP (12mm 20mm) 48-ball TFBGA (8mm 10mm)
PRODUCT DESCRIPTION
SST36VF1601 CMOS Concurrent Read/ Write Flash Memory manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST36VF1601 writes (Program Erase) with 2.7-3.6V power supply. SST36VF1601 device conforms JEDEC standard pinouts memories. Featuring high performance Word-Program, SST36VF1601 device provides typical Word-Program time µsec. devices Toggle Data# Polling detect completion Program Erase operation. protect against inadvertent write, SST36VF1601 device on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, SST36VF1601 device offered with guaranteed endurance 10,000 cycles. Data retention rated greater than years. SST36VF1601 suited applications that require convenient economical updating program, configuration, data memory. system applications, SST36VF1601 significantly improves performance reliability, while lowering power consumption. SST36VF1601 inherently uses less energy during Erase Program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. SST36VF1601 also improves flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles.
©2002 Silicon Storage Technology, Inc. S71142-07-000 5/02
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Concurrent SuperFlash trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Concurrent SuperFlash SST36VF1601
Data Sheet meet high density, surface mount requirements, SST36VF1601 offered 48-lead TSOP 48-ball TFBGA packages. Figures pinouts.
Word-Program Operation
SST36VF1601 programmed word-by-word basis. Before programming, must ensure that sector, which word which being programmed exists, fully erased. Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load word address word data. During Word-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed typically within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored. After detecting completion Word-Program operation (either through RY/BY# line, Data# Polling, Toggle Bit), host must keep signal minimum duration Program Recovery Time (TPR before valid data read correctly. Please Figures through corresponding timing diagrams.
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
Concurrent Read/Write Operation
Dual bank architecture SST36VF1601 device allows Concurrent Read/Write operation whereby user read from bank while program erase other bank. This operation used when user needs read system code bank while updating data other bank. CONCURRENT READ/WRITE STATE
Bank Read Read Write Write Operation Operation Bank Operation Write Read Operation Read Write
Sector- (Block-) Erase Operation
Sector- (Block-) Erase operation allows system erase device sector-by-sector block-by-block) basis. SST36VF1601 offers both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Figures timing waveforms. commands issued during Sector- Block-Erase operation ignored.
Note: purposes this table, write means perform Block-, Sector-, Chip-Erase Word-Program operations applicable appropriate bank.
Read Operation
Read operation SST36VF1601 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Chip-Erase Operation
SST36VF1601 provides Chip-Erase operation, which allows user erase unprotected sectors/ blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth CE#, whichever occurs first. During Erase operation, only valid Read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
Data# Polling (DQ7)
When SST36VF1601 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector-, Block-, Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart. There recovery time (TBR) required before valid data read data bus. commands entered immediately after becomes true data.
Write Operation Status Detection
SST36VF1601 provides hardware software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. hardware detection uses Ready/Busy# (RY/ BY#) output pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-ofWrite detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Chip-Erase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart. There recovery time (TBR) required before valid data read data bus. commands entered immediately after longer toggles.
Data Protection
SST36VF1601 provides both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Ready/Busy# (RY/BY#)
SST36VF1601 includes Ready/Busy# (RY/BY#) output signal. RY/BY# actively pulled while during internal Erase Program operation progress. RY/BY# open drain output that allows several devices tied parallel external pull resistor. high impedance whenever high RST# low. There recovery time (TBR) required before valid data read data bus. commands entered immediately after RY/BY# goes high.
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Hardware Block Protection
SST36VF1601 provides hardware block protection which protects outermost KWord larger bank. block protected when held low. Figure Block-Protection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed.
Common Flash Memory Interface (CFI)
SST36VF1601 also contains information describe characteristics device. order enter Query mode, system must write three-byte sequence, same Software Entry command with (CFI Query command) address 5555H last byte sequence. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
Hardware Reset (RST#)
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure 16). When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 15). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity.
Product Identification
Product Identification mode identifies device manufacturer. details, Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Word Manufacturer's Device SST36VF1601 0000H 0001H Data 00BFH 2761H
T1.1
Software Data Protection (SDP)
SST36VF1601 provides JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST36VF1601 shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15DQ8 VIH, other value during command sequence.
Product Identification Mode Exit/CFI Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/ Exit command ignored during internal Program Erase operation. Table software command code, Figure timing waveform Figure flowchart.
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
FUNCTIONAL BLOCK DIAGRAM
Memory Address
Address Buffers
KWord Sector Protection) SuperFlash Memory Mbit Bank
RST# RY/BY#
B37.5
SuperFlash Memory Mbit Bank Control Logic Buffers DQ15
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Bottom Sector Protection; KWord Blocks; KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH 001000H 000FFFH 000000H Block Block Block
Bank Bank
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
KWord Sector Protection KWord Sectors)
Block
F38.2
FIGURE SST36VF1601, MBIT CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2002 Silicon Storage Technology, Inc. S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
RST# RY/BY#
Standard Pinout View
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10
F01b.3
FIGURE ASSIGNMENTS 48-LEAD TSOP (12MM
20MM)
VIEW (balls facing down)
SST36VF1601
DQ15
DQ14 DQ13 DQ12 DQ10 DQ11
F01a.7
RST#
RY/BY#
FIGURE ASSIGNMENTS 48-BALL TFBGA (8MM
10MM)
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE DESCRIPTION
Symbol A19-A0 Name Address Inputs Functions provide memory addresses. During Sector-Erase Hardware Sector Protection, A19-A10 address lines will select sector. During Block-Erase A19-A15 address lines will select block. output data during Read cycles receive input data during Write cycles Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers control Write operations reset return device Read mode output status Program Erase Operation RY/BY# open drain output, 100K pull-up resistor required allow RY/BY# transition high indicating device ready read. protect unprotect bottom sectors from Erase Program operation. provide 2.7-3.6V power supply voltage Unconnected pins
T2.6
DQ15-DQ0
Data Input/output
RST# RY/BY#
Chip Enable Output Enable Write Enable Hardware Reset Ready/Busy#
Write Protect Power Supply Ground Connection
TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Manufacturer's (00BFH) Device
T3.6
DOUT High High DOUT High DOUT
Address Sector block address, Chip-Erase Table
VIH, other value. Device 2761H
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software Entry5,6 Query Entry Software Exit/ Exit
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 5555H 5555H 5555H Data2 Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 SAX4 BAX4 5555H Data2
T4.4
Address format A14-A0 (Hex), Addresses A19- VIH, other value, Command sequence. DQ15-DQ8 VIH, other value, Command sequence Program word address Sector-Erase; uses A19-A10 address lines Block-Erase; uses A19-A15 address lines device does remain Software Product Identification mode powered down. With A19-A1 Manufacturer's 00BFH, read with SST36VF1601 Device 2761H, read with
TABLE QUERY IDENTIFICATION STRING1
Address Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
T5.0
Refer publication more details.
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE SYSTEM INTERFACE INFORMATION
Address Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T6.0
TABLE DEVICE GEOMETRY INFORMATION
Address Data 0015H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0008H 0000H 003FH 0000H 0000H 0001H Data Device size Bytes (15H MByte) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number bytes multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Sector Information Number sectors; 256B sector size) 1023 1024 sectors (03FFH 1023) Bytes KByte/sector (0008H Block Information Number blocks; 256B block size) blocks (001FH Bytes KByte/block (0100H 256)
T7.4
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Package Power Dissipation Capability 25°C) 1.0W Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current OPERATING RANGE:
Range Commercial Extended Ambient Temp +70°C -20°C +85°C
2.7-3.6V 2.7-3.6V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Data Sheet TABLE OPERATING CHARACTERISTICS 2.7-3.6V
Limits Symbol Parameter Active Current Read Program Erase Concurrent Read/Write VILC VIHC Standby Current Reset Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 VDD-0.3 CE#=VIHC, VDD=VDD RST# 0.3V VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T8.6
Units
Test Conditions Address input=VIL/VIH, f=1/TRC Min, VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=VIL, OE#=VIH
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T9.2
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T10.0
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND1 TDR1 ILTH1 Parameter Endurance Data Retention Latch Minimum Specification 10,000 Units Cycles Years Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T11.1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 2.7-3.6V
SST36VF1601-70 Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Read Mode Units
T12.9
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase Program operations. This parameter does apply Chip-Erase operations.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH TSCE TBY1
Parameter Word-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Block-Erase Chip-Erase RY/BY# Delay Time Program Recovery Time
Units
TIDA1
T13.7
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
ADDRESSES
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
F22.1
DQ15-0
HIGH-Z
TCLZ
DATA VALID
FIGURE READ CYCLE TIMING DIAGRAM
ADDRESSES 5555 RY/BY# DQ15-0 XXAA XX55 XXA0 DATA VALID TCPH 2AAA 5555 ADDR
WORD (ADDR/DATA) Note: VIH, other value.
F23.15
FIGURE CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
ADDRESSES 5555 RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID TCPH 2AAA 5555 ADDR
F24.12
FIGURE CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESSES TOEH TOES
DATA#
DATA#
DATA
VALID DATA
F41.2
FIGURE DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
ADDRESSES TOEH
READ CYCLES WITH SAME OUTPUTS
VALID DATA
F42.3
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE ADDRESSES 5555 2AAA 5555 5555 2AAA 5555
TSCE
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
F27.8
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minimum timings met. (See Table VIH, other value.
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc. S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
SIX-BYTE CODE BLOCK-ERASE ADDRESSES 5555 2AAA 5555 5555 2AAA
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
F28.10
Note: This device also supports controlled Block-Erase operation. signals interchageable long minimum timings met. (See Table Block Address VIH, other value.
FIGURE CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESSES 5555 2AAA 5555 5555 2AAA
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
F29.10
Note: This device also supports controlled Sector-Erase operation. signals interchageable long minimum timings met. (See Table Sector Address VIH, other value.
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESSES 5555 2AAA 5555 0000 0001
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
TIDA
F30.7
Device 2761H SST36VF1601 Note: VIH, other value.
FIGURE SOFTWARE ENTRY
READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESSES 5555 2AAA 5555
TWPH DQ15-0 XXAA XX55 XX98
F31.3
TIDA
Note: VIH, other value.
FIGURE ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET ADDRESSES 5555 2AAA 5555
DQ15-0
XXAA
XX55
XXF0 TIDA
TWPH
F32.5
Note: VIH, other value.
FIGURE SOFTWARE EXIT/CFI EXIT
RY/BY# RST#
CE#/OE# TRHR
F43.1
FIGURE RST# TIMING (WHEN
INTERNAL OPERATION PROGRESS)
RY/BY# RST#
F44.3
FIGURE RST# TIMING (DURING SECTOR©2002 Silicon Storage Technology, Inc.
BLOCK-ERASE
OPERATION)
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F14.3
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F15.1
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F33.3
Note: VIH, other value.
FIGURE WORD-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
F34.0
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
F35.2
Note: VIH, other value.
FIGURE SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
Note: VIH, other value.
F36.2
FIGURE ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Package Modifier balls Package Type TFBGA (8mm 10mm) TSOP (type 12mm 20mm) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Bank Split Mbit Mbit Device Density Voltage 2.7-3.6V
SST36VF1601
Valid combinations SST36VF1601 SST36VF1601-70-4C-EK SST36VF1601-70-4E-EK
Note:
SST36VF1601-70-4C-BK SST36VF1601-70-4E-BK
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71142-07-000 5/02
Mbit Concurrent SuperFlash SST36VF1601
PACKAGING DIAGRAMS
1.05 0.95 Identifier 0.50
12.20 11.80
0.27 0.17
18.50 18.30
0.15 0.05
DETAIL 1.20 max. 0.70 0.50 20.20 19.80 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads. 0.70 0.50
48-tsop-EK-8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM PACKAGE CODE:
20MM
BOTTOM VIEW VIEW
10.00 0.20 5.60 0.80
0.80 4.00 8.00 0.20
0.30 0.05 (48X) CORNER
CORNER 1.10 0.10
SIDE VIEW
48-tfbga-BK-8x10-300mic-13
0.08 SEATING PLANE 0.21 0.05
Note:
Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.08 actual shape corners slightly different than portrayed drawing.
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) PACKAGE CODE:
10MM
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71142-07-000 5/02
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