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Order this document DSP56366/D
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DSP56366
24-Bit Audio Digital Signal Processor
DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, other digital audio algorithms. DSP56366 uses high performance, single-clock-per-cycle DSP56300 core family programmable CMOS digital signal processors (DSPs) combined with audio signal processing capability Motorola SymphonyDSP family, shown Figure This design provides two-fold performance increase over Motorola's popular Symphony family DSPs while retaining code compatibility. Significant architectural enhancements include barrel shifter, 24-bit addressing, instruction cache, direct memory access (DMA). DSP56366 offers million instructions second (MIPS) using internal clock
MEMORY EXPANSION AREA
TRIPLE TIMER (SPDIF Tx.) INTERFACE HOST INTERFACE ESAI INTERFACE ESAI_1 INTERFACE PROGRAM /INSTR. CACHE PROGRAM Bootstrap MEMORY MEMORY
PIO_EB
PM_EB
PERIPHERAL EXPANSION AREA
ADDRESS GENERATION UNIT CHANNELS UNIT
XM_EB
YM_EB
EXTERNAL ADDRESS SWITCH DRAM SRAM INTERFACE CACHE EXTERNAL DATA SWITCH
ADDRESS
24-BIT DSP56300 Core
CONTROL
INTERNAL DATA
DATA
POWER MNGMNT CLOCK GENERATOR
PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLE PROGRAM ADDRESS GENERATOR DATA 24X24+56->56-BIT 56-BIT ACCUMULATORS BARREL SHIFTER JTAG OnCE
EXTAL RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
BITS
Figure DSP56366 Block Diagram
This document contains information product. Specifications information herein subject change without notice.
Advance Infomation
2000 MOTOROLA, INC.
TABLE CONTENTS SECTION SECTION SECTION SECTION SECTION APPENDIX APPENDIX INDEX SIGNAL/CONNECTION DESCRIPTIONS SPECIFICATIONS PACKAGING DESIGN CONSIDERATIONS ORDERING INFORMATION POWER CONSUMPTION BENCHMARK IBIS MODEL. TECHNICAL ASSISTANCE:
Telephone: Email: Internet:
1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses following conventions:
OVERBAR "asserted" "deasserted" Examples: Used indicate signal that active when pulled (For example, RESET active when low.) Means that high true (active high) signal high that true (active low) signal Means that high true (active high) signal that true (active low) signal high Signal/Symbol
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values VIL, VOL, VIH, defined individual product specifications.
DSP56366 Advance Information
DSP56366 Features
FEATURES
DSP56300 Modular Chassis
Million Instructions Second (MIPS) with clock 3.3V. Object Code Compatible with core. Data with multiplier-accumulator 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support instruction cache support. Six-channel controller. based clocking with wide range frequency multiplications 4096), predivider factors power saving clock divider (2i: Reduces clock noise. Internal address tracing support OnCEfor Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down STOP WAIT low-power standby modes.
On-chip Memory Configuration
7Kx24 Y-Data 8Kx24 Y-Data ROM. 13Kx24 X-Data 32Kx24 X-Data ROM. 40Kx24 Program ROM. 3Kx24 Program 192x24 Bootstrap ROM. Program used Instruction Cache Program patching. 2Kx24 from Data 5Kx24 from Data switched Program resulting 10Kx24 Program RAM.
Off-chip Memory Expansion
External Memory Expansion Port. Off-chip expansion 24-bit word Data memory. Off-chip expansion 24-bit word Program memory. Simultaneous glueless interface SRAM DRAM.
Advance Information MOTOROLA DSP56366
DSP56366 Features
Peripheral Modules
Serial Audio Interface (ESAI): receivers transmitters, master slave. I2S, Sony, AC97, network other programmable protocols. Serial Audio Interface I(ESAI_1): receivers transmitters, master slave. I2S, Sony, AC97, network other programmable protocols ESAI_1 shares four data pins with ESAI, ESAI_1 does support HCKR HCKT (high frequency clocks) Serial Host Interface (SHI): protocols, multi master capability, 10-word receive FIFO, support 24-bit words. Byte-wide parallel Host Interface (HDI08) with support. Triple Timer module (TEC). Digital Audio Transmitter (DAX): serial transmitter capable supporting SPDIF, IEC958, CP-340 AES/EBU digital audio formats. Pins unused peripherals (except SHI) programmed GPIO lines.
144-pin plastic TQFP package.
Documentation
Table lists documents that provide complete description DSP56366 required design properly with part. Documentation available from local Motorola distributor, Motorola semiconductor sales office, Motorola Literature Distribution Center, through Motorola home page Internet (the source latest information). Table
Document Name DSP56300 Family Manual
DSP56366 Documentation
Description Order Number DSP56300FM/AD
Detailed description 56000-family architecture 24-bit core processor instruction Detailed description memory, peripherals, interfaces Electrical timing specifications; package descriptions Brief description chip
DSP56366 User's Manual DSP56366 Technical Data Sheet DSP56366 Product Brief
DSP56366UM/D DSP56366/D DSP56366P/D
Advance Information DSP56366
SECTION SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
input output signals DSP56366 organized into functional groups, which listed Table illustrated Figure 1-1. DSP56366 operated from supply; however, some inputs tolerate special notice this feature added signal descriptions those inputs. Table DSP56366 Functional Signal Groupings
Functional Group Number Signals Port Port Port Port Port Detailed Description Table Table Table Table Table Table Table Table Table 1-10 Table 1-11 Table 1-12 Table 1-13 Table 1-14 Table 1-15
Power (VCC) Ground (GND) Clock Address Data control Interrupt mode control HDI08 ESAI ESAI_1 Digital audio transmitter (DAX) Timer JTAG/OnCE Port
DSP56366 Advance Information
Signal/Connection Descriptions Signal Groupings
Table DSP56366 Functional Signal Groupings (Continued)
Functional Group Notes: Number Signals Detailed Description
Port external memory interface port, including external address bus, data bus, control signals. Port signals GPIO port signals which multiplexed with HDI08 signals. Port signals GPIO port signals which multiplexed with ESAI signals. Port signals GPIO port signals which multiplexed with signals. Port signals GPIO port signals which multiplexed with ESAI_1 signals.
DSP56366 Advance Information
Signal/Connection Descriptions Signal Groupings
PORT ADDRESS
A0-A17 VCCA GNDA
DSP56366
OnCEON-CHIP EMULATION/ JTAG PORT
PORT DATA
D0-D23 VCCD GNDD
PARALLEL HOST PORT (HDI08) Port
HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15] VCCH GNDH
PORT CONTROL
AA0-AA2/RAS0-RAS2 VCCC GNDC
SERIAL AUDIO INTERFACE (ESAI)
SCKT[PC3]
Port
[PC4] HCKT [PC5] SCKR [PC0] [PC1] HCKR [PC2] SDO0[PC11] SDO0_1[PE11] SDO1[PC10] SDO1_1[PE10] SDO2/SDI3[PC9] SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6]
INTERRUPT MODE CONTROL
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET
CLOCK
EXTAL PINIT/NMI PCAP VCCP GNDP
SERIAL AUDIO INTERFACE(ESAI_1)
SCKT_1[PE3]
Port
T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS GNDS
QUIET POWER
VCCQH VCCQL GNDQ
SPDIF TRANSMITTER (DAX)
[PD1] [PD0]
Port
SERIAL HOST INTERFACE (SHI)
MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ
TIMER
TIO0 [TIO0]
Figure Signals Identified Functional Group
DSP56366 Advance Information
Signal/Connection Descriptions Power
POWER
Table Power Inputs
Power Name Description Power-VCCP dedicated use. voltage should well-regulated input should provided with extremely impedance path power rail. There VCCP input. Quiet Core (Low) Power-VCCQL isolated power internal processing logic. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCQL inputs. Quiet External (High) Power-VCCQH quiet power source lines. This input must tied externally other chip power inputs. user must provide adequate decoupling capacitors. There three VCCQH inputs. Address Power-VCCA isolated power sections address drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There three VCCA inputs. Data Power-VCCD isolated power sections data drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There four VCCD inputs. Control Power-VCCC isolated power control drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCC inputs. Host Power-VCCH isolated power HDI08 drivers. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There VCCH input. SHI, ESAI, ESAI_1, Timer Power -VCCS isolated power SHI, ESAI, ESAI_1, Timer. This input must tied externally other chip power inputs. user must provide adequate external decoupling capacitors. There inputs.
VCCP
VCCQL
VCCQH
VCCA
VCCD
VCCC
VCCH
VCCS
GROUND
Table Grounds
Ground Name Description Ground-GNDP ground dedicated use. connection should provided with extremely low-impedance path ground. VCCP should bypassed GNDP 0.47 capacitor located close possible chip package. There GNDP connection.
GNDP
DSP56366 Advance Information
Signal/Connection Descriptions Clock
Table Grounds
Ground Name Description Quiet Ground-GNDQ isolated ground internal processing logic. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDQ connections. Address Ground-GNDA isolated ground sections address drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDA connections. Data Ground-GNDD isolated ground sections data drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There four GNDD connections. Control Ground-GNDC isolated ground control drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDC connections. Host Ground-GNDh isolated ground HD08 drivers. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDH connection. SHI, ESAI, ESAI_1, Timer Ground-GNDS isolated ground SHI, ESAI, ESAI_1, Timer. This connection must tied externally other chip ground connections. user must provide adequate external decoupling capacitors. There GNDS connections.
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
CLOCK
Table Clock Signals
Signal Name Type State during Reset Signal Description
EXTAL
Input
Input
External Clock Input-An external clock source must connected EXTAL order supply clock internal clock generator PLL. This input cannot tolerate Capacitor-PCAP input connecting off-chip capacitor filter. Connect capacitor terminal PCAP other terminal VCCP. used, PCAP tied VCC, GND, left floating.
PCAP
Input
Input
DSP56366 Advance Information
Signal/Connection Descriptions External Memory Expansion Port (Port
Table Clock Signals (Continued)
Signal Name Type State during Reset Signal Description
PINIT/NMI
Input
Input
Initial/Nonmaskable Interrupt-During assertion RESET, value PINIT/NMI written into Enable (PEN) control register, determining whether enabled disabled. After RESET assertion during normal instruction processing, PINIT/NMI Schmitt-trigger input negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized internal system clock. This input cannot tolerate
EXTERNAL MEMORY EXPANSION PORT (PORT
When DSP56366 enters low-power standby mode (stop wait), releases mastership tri-states relevant port signals: A0-A17, D0-D23, AA0/RAS0-AA2/RAS2, CAS.
External Address
Table External Address Signals
Signal Name Type State during Reset Signal Description
A0-A17
Outp
Tri-stated
Address Bus-When master, A0-A17 active-high outputs that specify address external program data memory accesses. Otherwise, signals tri-stated. minimize power dissipation, A0-A17 change state when external memory spaces being accessed.
DSP56366 Advance Information
Signal/Connection Descriptions External Memory Expansion Port (Port
External Data
Table External Data Signals
Signal Name Type State during Reset Signal Description
D0-D23
Input/Output
Tri-stated
Data Bus-When master, D0-D23 active-high, bidirectional input/outputs that provide bidirectional data external program data memory accesses. Otherwise, D0-D23 tri-stated.
External Control
Table External Control Signals
Signal Name Type State during Reset Signal Description
AA0-AA2/ RAS0- RAS2
Outp
Tri-stated
Address Attribute Address Strobe-When defined these signals used chip selects additional address lines. When defined RAS, these signals used DRAM interface. These signals tri-statable outputs with programmable polarity. Column Address Strobe- When master, active-low output used DRAM strobe column address. Otherwise, mastership enable (BME) DRAM control register cleared, signal tri-stated. Read Enable-When master, active-low output that asserted read external memory data (D0-D23). Otherwise, tri-stated. Write Enable-When master, active-low output that asserted write external memory data (D0-D23). Otherwise, tri-stated.
Outp
Tri-stated
Outp
Tri-stated
Outp
Tri-stated
DSP56366 Advance Information
Signal/Connection Descriptions External Memory Expansion Port (Port
Table External Control Signals (Continued)
Signal Name Type State during Reset Signal Description
Input
Ignored Input
Transfer Acknowledge-If master there external activity, master, input ignored. input data transfer acknowledge (DTACK) function that extend external cycle indefinitely. number wait states .infinity) added wait states inserted keeping deasserted. typical operation, deasserted start cycle, asserted enable completion cycle, deasserted before next cycle. current cycle completes clock period after asserted synchronous internal system clock. number wait states determined input control register (BCR), whichever longer. used minimum number wait states external cycles. order functionality, must programmed least wait state. zero wait state access cannot extended deassertion, otherwise improper operation result. operate synchronously asynchronously, depending setting operating mode register (OMR). functionality used while performing DRAM type accesses, otherwise improper operation result. Request-BR active-low output, never tri-stated. asserted when requests mastership. deasserted when longer needs bus. asserted deasserted independent whether DSP56366 master slave. "parking" allows deasserted even though DSP56366 master. (See description "parking" signal description.) request hold (BRH) allows asserted under software control even though does need bus. typically sent external arbitrator that controls priority, parking, tenure each master same external bus. only affected requests external bus, never internal bus. During hardware reset, deasserted arbitration reset slave state. Grant-BG active-low input. asserted external arbitration circuit when DSP56366 becomes next master. When asserted, DSP56366 must wait until deasserted before taking mastership. When deasserted, mastership typically given current cycle. This occur middle instruction that requires more than external cycle execution. proper operation, asynchronous arbitration enable (ABE) register must set.
Outp
Output (deassert
Input
Ignored Input
DSP56366 Advance Information
Signal/Connection Descriptions Interrupt Mode Control
Table External Control Signals (Continued)
Signal Name Type State during Reset Signal Description
Input/ Outp
Input
Busy-BB bidirectional active-low input/output. indicates that active. Only after deasserted pending master become master (and then assert signal again). master keep asserted after ceasing activity regardless whether asserted deasserted. This called "bus parking" allows current master reuse without rearbitration until another device requires bus. deassertion done "active pull-up" method (i.e., driven high then released held high external pull-up resistor). proper operation, asynchronous arbitration enable (ABE) register must set. requires external pull-up resistor.
INTERRUPT MODE CONTROL
interrupt mode control signals select chip's operating mode comes hardware reset. After RESET deasserted, these inputs hardware interrupt request lines. Table Interrupt Mode Control
Signal Name Type State during Reset Signal Description
MODA/IRQA
Input
Input
Mode Select A/External Interrupt Request A-MODA/IRQA active-low Schmitt-trigger input, internally synchronized clock. MODA/IRQA selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. processor stop standby state MODA/IRQA pulled GND, processor will exit stop state. This input tolerant. Mode Select B/External Interrupt Request B-MODB/IRQB active-low Schmitt-trigger input, internally synchronized clock. MODB/IRQB selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input tolerant.
MODB/IRQB
Input
Input
DSP56366 Advance Information
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table Interrupt Mode Control (Continued)
Signal Name Type State during Reset Signal Description
MODC/IRQC
Input
Input
Mode Select C/External Interrupt Request C-MODC/IRQC active-low Schmitt-trigger input, internally synchronized clock. MODC/IRQC selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input tolerant. Mode Select D/External Interrupt Request D-MODD/IRQD active-low Schmitt-trigger input, internally synchronized clock. MODD/IRQD selects initial chip operating mode during hardware reset becomes level-sensitive negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, MODD select initial chip operating modes, latched into when RESET signal deasserted. This input tolerant. Reset-RESET active-low, Schmitt-trigger input. When asserted, chip placed Reset state internal phase generator reset. Schmitt-trigger input allows slowly rising input (such capacitor charging) reset chip reliably. When RESET signal deasserted, initial chip operating mode latched from MODA, MODB, MODC, MODD inputs. RESET signal must asserted during power stable EXTAL signal must supplied while RESET being asserted. This input tolerant.
MODD/IRQD
Input
Input
RESET
Input
Input
PARALLEL HOST INTERFACE (HDI08)
HDI08 provides fast, 8-bit, parallel data port that connected directly host bus. HDI08 supports variety standard buses directly connected number industry standard microcomputers, microprocessors, DSPs, hardware.
1-10
DSP56366 Advance Information
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table Host Interface
Signal Name Type State during Reset Signal Description
H0-H7
Input/ output
Host Data-When HDI08 programmed interface nonmultiplexed host function selected, these signals lines bidirectional, tri-state data bus. Host Address/Data-When HDI08 programmed interface multiplexed host function selected, these signals lines address/data bidirectional, multiplexed, tri-state bus. Port 0-7-When HDI08 configured GPIO, these signals individually programmable input, output, internally disconnected. default state after reset these signals GPIO disconnected. These inputs tolerant. Host Address Input 0-When HDI08 programmed interface nonmultiplexed host function selected, this signal line host address input bus. Host Address Strobe-When HDI08 programmed interface multiplexed host function selected, this signal host address strobe (HAS) Schmitt-trigger input. polarity address strobe programmable, configured active-low (HAS) following reset. Port 8-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected.
HAD0-HAD7
Input/ output
PB0-PB7
Input, output, GPIO disconnected disconnected
Input
HAS/HAS
Input GPIO disconnected
Input, output, disconnected
This input tolerant.
DSP56366 Advance Information
1-11
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description
Input
Host Address Input 1-When HDI08 programmed interface nonmultiplexed host function selected, this signal line host address (HA1) input bus. Host Address 8-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA8) input bus. GPIO disconnected
Input
Input, output, disconnected
Port 9-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant. Host Address Input 2-When HDI08 programmed interface non-multiplexed host function selected, this signal line host address (HA2) input bus. Host Address 9-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA9) input bus. Port 10-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected.
Input
Input GPIO disconnected
PB10
Input, Output, Disconnected
This input tolerant.
1-12
DSP56366 Advance Information
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description
Input
Host Read/Write-When HDI08 programmed interface single-data-strobe host function selected, this signal Host Read/Write (HRW) input. Host Read Data-When HDI08 programmed interface double-data-strobe host function selected, this signal host read data strobe (HRD) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HRD) after reset. Port 11-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant. Host Data Strobe-When HDI08 programmed interface single-data-strobe host function selected, this signal host data strobe (HDS) Schmitt-trigger input. polarity data strobe programmable, configured active-low (HDS) following reset. Host Write Data-When HDI08 programmed interface double-data-strobe host function selected, this signal host write data strobe (HWR) Schmitt-trigger input. GPIO polarity data strobe programmable, configured disconnected active-low (HWR) following reset. Port 12-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HRD/
Input GPIO disconnected
PB11
Input, Output, Disconnected
HDS/
Input
HWR/
Input
PB12
Input, output, disconnected
DSP56366 Advance Information
1-13
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description
Input
Host Chip Select-When HDI08 programmed interface nonmultiplexed host function selected, this signal host chip select (HCS) input. polarity chip select programmable, configured active-low (HCS) after reset. Host Address 10-When HDI08 programmed interface multiplexed host function selected, this signal line host address (HA10) input bus. Port 13-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant. Host Request-When HDI08 programmed interface single host request host function selected, this signal host request (HOREQ) output. polarity host request programmable, configured active-low (HOREQ) following reset. host request programmed driven open-drain output. Transmit Host Request-When HDI08 programmed interface double host request host function selected, this signal transmit host request (HTRQ) output. polarity host request programmable, configured active-low (HTRQ) following reset. host request programmed driven open-drain output. Port 14-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected. default state after reset this signal GPIO disconnected. This input tolerant.
HA10
Input GPIO disconnected
PB13
Input, output, disconnected
HOREQ/ HOREQ
Output
HTRQ/ HTRQ
Output
GPIO disconnected
PB14
Input, output, disconnected
1-14
DSP56366 Advance Information
Signal/Connection Descriptions PARALLEL HOST INTERFACE (HDI08)
Table Host Interface (Continued)
Signal Name Type State during Reset Signal Description
HACK/ HACK
Input
Host Acknowledge-When HDI08 programmed interface single host request host function selected, this signal host acknowledge (HACK) Schmitt-trigger input. polarity host acknowledge programmable, configured active-low (HACK) after reset. Receive Host Request-When HDI08 programmed interface double host request host function selected, this signal receive host request (HRRQ) output. polarity host request programmable, configured active-low (HRRQ) after reset. host request programmed driven open-drain output. Port 15-When HDI08 configured GPIO, this signal individually programmed input, output, internally disconnected.
HRRQ/ HRRQ
Output GPIO disconnected
PB15
Input, output, disconnected
default state after reset this signal GPIO disconnected.
This input tolerant.
DSP56366 Advance Information
1-15
Signal/Connection Descriptions Serial Host Interface
SERIAL HOST INTERFACE
five signals that configured allow operate either mode. Table 1-10 Serial Host Interface Signals
Signal Name Signal Type State during Reset Signal Description
Input output
Tristated Input output
Serial Clock-The signal output when configured master Schmitt-trigger input when configured slave. When configured master, signal derived from internal clock generator. When configured slave, signal input, clock signal from external master synchronizes data transfer. signal ignored defined slave slave select (SS) signal asserted. both master slave devices, data shifted edge signal sampled opposite edge where data stable. Edge polarity determined transfer protocol. Serial Clock-SCL carries clock transactions mode. Schmitt-trigger input when configured slave opendrain output when configured master. should connected through pull-up resistor. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
1-16
DSP56366 Advance Information
Signal/Connection Descriptions Serial Host Interface
Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
MISO
Input output
Master-In-Slave-Out-When configured master, MISO master data input line. MISO signal used conjunction with MOSI signal transmitting receiving serial data. This signal Schmitttrigger input when configured Master mode, output when configured Slave mode, tri-stated configured Slave mode when deasserted. external pull-up resistor required operation. Data Acknowledge-In mode, Schmitt-trigger input when receiving open-drain output when transmitting. should connected through pull-up resistor. carries data transactions. data must stable during high period SCL. data only allowed change when low. When free, high. line only allowed change during time high case start stop events. high-to-low transition line while high unique situation, defined start event. low-to-high transition while high unique situation defined stop event. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant. Master-Out-Slave-In-When configured master, MOSI master data output line. MOSI signal used conjunction with MISO signal transmitting receiving serial data. MOSI slave data input line when configured slave. This signal Schmitttrigger input when configured Slave mode. Tristated Slave Address 0-This signal uses Schmitt-trigger input when configured mode. When configured slave mode, signal used form slave device address. ignored when configured master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state. This input tolerant.
Input opendrain output
Tristated
MOSI
Input output
Input
DSP56366 Advance Information
1-17
Signal/Connection Descriptions Serial Host Interface
Table 1-10 Serial Host Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description
Input
Slave Select-This signal active Schmitt-trigger input when configured mode. When configured Slave mode, this signal used enable slave transfer. When configured master mode, this signal should kept deasserted (pulled high). asserted while configured master, error condition flagged. deasserted, ignores clocks keeps MISO output signal high-impedance state. Tristated Slave Address 2-This signal uses Schmitt-trigger input when configured mode. When configured Slave mode, signal used form slave device address. ignored master mode. This signal tri-stated during hardware, software, individual reset. Thus, there need external pull-up this state.
Input
This input tolerant.
Host Request-This signal active Schmitt-trigger input when configured master mode active output when configured slave mode. When configured slave mode, HREQ asserted indicate that ready next data word transfer deasserted first clock pulse data word transfer. When configured master mode, HREQ input. When asserted external slave device, will trigger start data word transfer master. After finishing data word transfer, master will await next assertion HREQ proceed next transfer. This signal tri-stated during hardware, software, personal reset, when HREQ1-HREQ0 bits HCSR cleared. There need external pull-up this state.
HREQ
Input Output
Tristated
This input tolerant.
1-18
DSP56366 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface
ENHANCED SERIAL AUDIO INTERFACE
Table 1-11 Enhanced Serial Audio Interface Signals
Signal Name Signal Type State during Reset Signal Description High Frequency Clock Receiver-When programmed input, this signal provides high frequency clock source ESAI receiver alternate core clock. When programmed output, this signal serve high-frequency sample clock (e.g., external digital analog converters [DACs]) additional system clock. Port 2-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected.
HCKR
Input output
Input, output, disconnected
GPIO disconnected
This input tolerant.
High Frequency Clock Transmitter-When programmed input, this signal provides high frequency clock source ESAI transmitter alternate core clock. When programmed output, this signal serve high frequency sample clock (e.g., external DACs) additional system clock. Port 5-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
HCKT
Input output
Input, output, disconnected
GPIO disconnected
DSP56366 Advance Information
1-19
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Frame Sync Receiver-This receiver frame sync input/ output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). Input output When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Frame Sync Transmitter-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). GPIO disconnected Input, output, disconnected
GPIO disconnected
Input, output, disconnected
Input output
Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
1-20
DSP56366 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name Signal Type State during Reset Signal Description Receiver Serial Clock-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Transmitter Serial Clock-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. GPIO disconnected Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. SDO5 SDI0 Output Input Input, output, disconnected GPIO disconnected Serial Data Output 5-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0-When programmed receiver, SDI0 used receive serial data into serial receive shift register. Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
SCKR
Input output
GPIO disconnected
Input, output, disconnected
SCKT
Input output
Input, output, disconnected
DSP56366 Advance Information
1-21
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO4 SDI1 Signal Type Output Input Input, output, disconnected GPIO disconnected State during Reset Signal Description Serial Data Output 4-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. SDO3/ SDO3_1 Serial Data Output 3-When programmed transmitter, SDO3 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output Serial Data Input 2-When programmed receiver, SDI2 used receive serial data into serial receive shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Input Port 8-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant. SDO2/ SDO2_1 Serial Data Output 2-When programmed transmitter, SDO2 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output Serial Data Input 3-When programmed receiver, SDI3 used receive serial data into serial receive shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Input Port 9-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant.
Output
SDI2/ SDI2_1
Input GPIO disconnected
PC8/
Input, output, disconnected
Output
SDI3/ SDI3_1
Input GPIO disconnected
PC9/
Input, output, disconnected
1-22
DSP56366 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface
Table 1-11 Enhanced Serial Audio Interface Signals (Continued)
Signal Name SDO1/ SDO1_1 Signal Type State during Reset Signal Description Serial Data Output 1-SDO1 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output GPIO disconnected Port 10-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant. SDO0/ SDO0_1 Serial Data Output 0-SDO0 used transmit data from serial transmit shift register. When enabled ESAI_1 operation, this ESAI_1 Serial Data Output GPIO disconnected Port 11-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. When enabled ESAI_1 GPIO, this Port signal. default state after reset GPIO disconnected. This input tolerant.
Output
PC10/ PE10
Input, output, disconnected
Output
PC11/ PE11
Input, output, disconnected
DSP56366 Advance Information
1-23
Signal/Connection Descriptions Enhanced Serial Audio Interface_1
ENHANCED SERIAL AUDIO INTERFACE_1
Table 1-12 Enhanced Serial Audio Interface_1 Signals
Signal Name Signal Type State during Reset Signal Description Frame Sync Receiver_1-This receiver frame sync input/ output signal. asynchronous mode (SYN=0), operates frame sync input output used enabled receivers. synchronous mode (SYN=1), operates either serial flag (TEBE=0), transmitter external buffer enable control (TEBE=1, RFSD=1). FSR_1 Input output When this configured serial flag pin, direction determined RFSD RCCR register. When configured output flag OF1, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF1, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 1-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate Frame Sync Transmitter_1-This transmitter frame sync input/output signal. synchronous mode, this signal frame sync both transmitters receivers. asynchronous mode, frame sync transmitters only. direction determined transmitter frame sync direction (TFSD) ESAI transmit clock control register (TCCR). Port 4-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
GPIO disconnected
Input, output, disconnected
FST_1
Input output
Input, output, disconnected
GPIO disconnected
1-24
DSP56366 Advance Information
Signal/Connection Descriptions Enhanced Serial Audio Interface_1
Table 1-12 Enhanced Serial Audio Interface_1 Signals
Signal Name Signal Type State during Reset Signal Description Receiver Serial Clock_1-SCKR provides receiver serial clock ESAI. SCKR operates clock input output used enabled receivers asynchronous mode (SYN=0), serial flag synchronous mode (SYN=1). When this configured serial flag pin, direction determined RCKD RCCR register. When configured output flag OF0, this will reflect value SAICR register, data will show synchronized frame sync normal mode slot network mode. When configured input flag IF0, data value will stored SAISR register, synchronized frame sync normal mode slot network mode. Port 0-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate Transmitter Serial Clock_1-This signal provides serial rate clock ESAI. SCKT clock input output used enabled transmitters receivers synchronous mode, enabled transmitters asynchronous mode. GPIO disconnected Port 3-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate SDO5_1 Output Serial Data Output 5_1-When programmed transmitter, SDO5 used transmit data from serial transmit shift register. Serial Data Input 0_1-When programmed receiver, SDI0 used receive serial data into serial receive shift register. GPIO disconnected Port 6-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input cannot tolerate
SCKR_1
Input output
GPIO disconnected
Input, output, disconnected
SCKT_1
Input output
Input, output, disconnected
SDI0_1
Input Input, output, disconnected
DSP56366 Advance Information
1-25
Signal/Connection Descriptions spdif tRANSMITTER Digital Audio Interface
Table 1-12 Enhanced Serial Audio Interface_1 Signals
Signal Name SDO4_1 Signal Type State during Reset Signal Description Serial Data Output 4_1-When programmed transmitter, SDO4 used transmit data from serial transmit shift register. Serial Data Input 1_1-When programmed receiver, SDI1 used receive serial data into serial receive shift register. GPIO disconnected Port 7-When ESAI configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Output
SDI1_1
Input Input, output, disconnected
SPDIF TRANSMITTER DIGITAL AUDIO INTERFACE
Table 1-13 Digital Audio Interface (DAX) Signals
Signal Name Type State During Reset Signal Description
Input
Audio Clock Input-This clock input. When programmed external clock, this input supplies clock. external clock frequency must 256, 384, times audio sampling frequency (256 respectively). GPIO Disconnected Port 0-When configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant. Digital Audio Data Output-This signal audio non-audio output form AES/EBU, CP340 IEC958 data biphase mark format. GPIO Disconnected Port 1-When configured GPIO, this signal individually programmable input, output, internally disconnected. default state after reset GPIO disconnected. This input tolerant.
Input, output, disconnected
Output
Input, output, disconnected
1-26
DSP56366 Advance Information
Signal/Connection Descriptions Timer
TIMER
Table 1-14 Timer Signal
Signal Name Type State during Reset Signal Description
Timer Schmitt-Trigger Input/Output-When timer functions external event counter measurement mode, TIO0 used input. When timer functions watchdog, timer, pulse modulation mode, TIO0 used output. Input Output default mode after reset GPIO input. This changed output configured timer input/output through timer control/status register (TCSR0). TIO0 being used, recommended either define GPIO output immediately beginning operation leave defined GPIO input connected through pull-up resistor order ensure stable logic level this input.
TIO0
Input
This input tolerant.
JTAG/OnCE INTERFACE
Table 1-15 JTAG/OnCE Interface
Signal Name Signal Type State during Reset Signal Description
Input
Input
Test Clock-TCK test clock input signal used synchronize JTAG test logic. internal pull-up resistor.
This input tolerant.
Test Data Input-TDI test data serial input signal used test instructions data. sampled rising edge internal pull-up resistor. This input tolerant. Tristated Test Data Output-TDO test data serial output signal used test instructions data. tri-statable actively driven shift-IR shift-DR controller states. changes falling edge TCK.
Input
Input
Output
DSP56366 Advance Information
1-27
Signal/Connection Descriptions
Table 1-15 JTAG/OnCE Interface (Continued)
Signal Name Signal Type State during Reset Signal Description
Input
Input
Test Mode Select-TMS input signal used sequence test controller's state machine. sampled rising edge internal pull-up resistor. This input tolerant.
1-28
DSP56366 Advance Information
SECTION SPECIFICATIONS
INTRODUCTION
DSP56366 high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs outputs. DSP56366 specifications preliminary from design simulations, fully tested guaranteed. Finalized specifications will published after full characterization device qualifications complete.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage high static voltage electrical fields. However, normal precautions should taken avoid exceeding maximum voltage ratings. Reliability operation enhanced unused inputs pulled appropriate logic voltage level (e.g., either VCC). suggested value pullup pulldown resistor
Note: calculation timing requirements, adding maximum value specification minimum value another specification does yield reasonable sum. maximum specification calculated using worst case variation process parameter values direction. minimum specification calculated using worst case same parameters opposite direction. Therefore, "maximum" value specification will never occur same device that "minimum" value another specification; adding maximum minimum represents condition that never exist.
DSP56366 Advance Information
Specifications Thermal Characteristics
Table Maximum Ratings
Rating1 Supply Voltage input voltages excluding tolerant" inputs3 tolerant" input voltages3 Current drain excluding Operating temperature range Storage temperature Notes: Symbol VIN5 TSTG Value1, Unit
-0.3 +4.0
-0.3 3.95 +105
+125
0.16 -0°C +105°C, Absolute maximum ratings stress ratings only, functional operation maximum guaranteed. Stress beyond maximum rating affect device reliability cause permanent damage device. CAUTION: Tolerant" input voltages must more than 3.95 greater than supply voltage; this restriction applies "power on", well during normal operation. case, input voltages cannot more than 5.75 Tolerant" inputs inputs that tolerate
THERMAL CHARACTERISTICS
Table Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes: Symbol TQFP Value 49.87 9.26 Unit
°C/W °C/W °C/W
Junction-to-ambient thermal resistance based measurements horizontal single-sided printed circuit board SEMI G38-87 natural convection.(SEMI Semiconductor Equipment Materials International, East Middlefield Rd., Mountain View, 94043, (415) 964-5111.) Measurements were done with parts mounted thermal test boards conforming specification EIA/ JESD51-3. Junction-to-case thermal resistance based measurements using cold plate SEMI G30-88, with exception that cold plate temperature used case temperature.
DSP56366 Advance Information
Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
Table Electrical Characteristics6
Characteristics Supply voltage Input high voltage Symbol 3.14 3.46 Unit
D(0:23), ESAI_1(except /IRQ1, RESET, PINIT/NMI JTAG/ESAI/Timer/HDI08/DAX/ ESAI_1(only SDO4_1)/SHI(SPI mode) SHI(I2C mode) EXTAL
SDO4_1)
VIHP VIHP VIHX
3.95 3.95
Input voltage
D(0:23), ESAI_1(except /IRQ1, RESET, PINIT/NMI JTAG/ESAI/Timer/HDI08/DAX/ ESAI_1(only SDO4_1)/SHI(SPI mode) SHI(I2C mode) EXTAL8
Input leakage current High impedance (off-state) input current Output high voltage
SDO4_1)
-0.3
VILP VILP VILX ITSI
-0.3 -0.3 -0.3
(IOH -0.4 mA)5,7 CMOS (IOH µA)5
Output voltage
0.01
(IOL open-drain pins mA)5,7 CMOS (IOL µA)5
Internal supply current2 internal clock 120MHz
0.01
Normal mode Wait mode Stop mode4
supply current Input capacitance5
ICCI ICCW ICCS
DSP56366 Advance Information
Specifications Electrical Characteristics
Table Electrical Characteristics6 (Continued)
Characteristics Notes: Symbol Unit
Refers MODA/IRQA, MODB/IRQB, MODC/IRQC,and MODD/IRQD pins Power Consumption Considerations page provides formula compute estimated current requirements Normal mode. order obtain these results, inputs must terminated (i.e., allowed float). Measurements based synthetic intensive benchmarks. power consumption numbers this specification measured results this benchmark. This reflects typical applications. Typical internal supply current measured with 105°C. Maximum internal supply current measured with 3.46 105°C. Deleted. order obtain these results, inputs, which disconnected Stop mode, must terminated (i.e., allowed float). Periodically sampled 100% tested +105°C, This characteristic does apply PCAP. Driving EXTAL VIHX high VILX value cause additional power consumption current). minimize power consumption, minimum VIHX should lower than maximum VILX should higher than VCC.
DSP56366 Advance Information
Specifications Electrical Characteristics
ELECTRICAL CHARACTERISTICS
timing waveforms shown electrical characteristics section tested with maximum minimum pins except EXTAL, which tested using input levels shown Note previous table. timing specifications, which referenced device input signal, measured production with respect point respective input signal's transition. DSP56366 output levels measured with production test machine reference levels respectively. Note: Although minimum value frequency EXTAL MHz, device test conditions rated speed.
DSP56366 Advance Information
Specifications Internal Clocks
INTERNAL CLOCKS
Table Internal Clocks
Characteristics Internal operation frequency with enabled Internal operation frequency with disabled Internal clock high period With disabled With enabled With enabled Internal clock period With disabled With enabled With enabled Internal clock cycle time with enabled Internal clock cycle time with disabled Instruction cycle time Notes: ICYC 0.49 DF/MF 0.47 DF/MF DF/MF 0.51 DF/MF 0.53 DF/MF 0.49 DF/MF 0.47 DF/MF 0.51 DF/MF 0.53 DF/MF Symbol Expression1, MF)/ (PDF Ef/2
Division Factor External frequency External clock cycle Multiplication Factor Predivision Factor internal clock cycle Clock Generation section DSP56300 detailed discussion PLL.
Family Manual
DSP56366 Advance Information
Specifications EXTERNAL CLOCK OPERATION
EXTERNAL CLOCK OPERATION
DSP56366 system clock externally supplied square wave voltage source connected EXTAL(Figure 2-1).
VIHC EXTAL VILC Midpoint
Note:
midpoint (VIHC VILC).
Figure External Clock Timing
Table Clock Operation
Characteristics Frequency EXTAL (EXTAL Frequency) rise fall time this external clock should maximum. EXTAL input high1, Symbol 120.0
With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6)
EXTAL input low1,
3.89 3.54
157.0
With disabled (46.7%-53.3% duty cycle6) With enabled (42.5%-57.5% duty cycle6)
EXTAL cycle time2
3.89 3.54
157.0 273.1 8.53
With disabled With enabled
Instruction cycle time ICYC
8.33 8.33
With disabled With enabled
ICYC
16.66 8.33
DSP56366 Advance Information
Specifications EXTERNAL CLOCK OPERATION
Table Clock Operation (Continued)
Notes: Characteristics Symbol Measured input transition maximum value enabled given minimum maximum maximum value enabled given minimum maximum indicated duty cycle specified maximum frequency which part rated. minimum clock high time required correct operation, however, remains same lower operating frequencies; therefore, when lower clock frequency used, signal symmetry vary from specified duty cycle long minimum high time time requirements met.
DSP56366 Advance Information
Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS
Table Characteristics
Characteristics frequency when enabled 2/PDF) external capacitor (PCAP VCCP) (CPCAP1) Unit
Notes:
580)
780) 1470
CPCAP value capacitor (connected between PCAP VCCP). recommended value CPCAP computed from following equations: 680)-120, 1100,
DSP56366 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET, STOP, MODE SELECT, INTERRUPT TIMING
Table Reset, Stop, Mode Select, Interrupt Timing6
Characteristics Delay from RESET assertion pins reset value3 Required RESET duration4 Expression 26.0 Unit
Power external clock generator, disabled
1000
416.7 20.8
Power external clock generator, enabled During normal operation
Delay from asynchronous RESET deassertion first external address output (internal reset deassertion)5
Minimum Maximum
Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory access address valid
3.25 20.25 7.50
29.1 30.0
176.2
Caused first interrupt instruction fetch Caused first interrupt instruction execution
Delay from IRQA, IRQB, IRQC, IRQD, assertion general-purpose transfer output valid caused first interrupt instruction execution Delay from address output valid caused first interrupt instruction execute interrupt request deassertion level sensitive fast interrupts1 Delay from assertion interrupt request deassertion level sensitive fast interrupts1
4.25 7.25
37.4 62.4 88.3
3.75 10.94 3.25 10.94
Note
Note
2-10
DSP56366 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Delay from assertion interrupt request deassertion level sensitive fast interrupts1 Expression Unit
DRAM
3.5) 10.94 3.5) 10.94 10.94 2.5) 10.94
Note Note Note Note
SRAM SRAM SRAM
Duration IRQA assertion recover from Stop state Delay from IRQA assertion fetch first instruction (when exiting Stop)2,
active during Stop (PCTL Stop delay enabled (OMR
(128 PLC/2) (23.75 0.5) (8.25 0.5)
active during Stop (PCTL Stop delay enabled (OMR active during Stop (PCTL (Implies Stop Delay)
Duration level sensitive IRQA assertion ensure interrupt service (when exiting Stop)2,
64.6
72.9
active during Stop (PCTL Stop delay enabled (OMR
(128K PLC/2)
active during Stop (PCTL (20.5 0.5) Stop delay enabled (OMR active during Stop (PCTL (implies Stop delay)
Interrupt Requests Rate
45.8
HDI08, ESAI, ESAI_1, SHI, DAX, Timer
12TC 12TC
100.0 66.7 66.7 100.0
IRQ, (edge trigger) (level trigger)
Requests Rate
Data read from HDI08, ESAI, ESAI_1, SHI,
50.0 58.0 16.7
Data write HDI08, ESAI, ESAI_1, SHI, Timer IRQ, (edge trigger)
25.0
DSP56366 Advance Information
2-11
Specifications Reset, Stop, Mode Select, Interrupt Timing
Table Reset, Stop, Mode Select, Interrupt Timing6 (Continued)
Characteristics Delay from IRQA, IRQB, IRQC, IRQD, assertion external memory (DMA source) access address valid Expression 4.25 37.4 Unit
Notes:
When using fast interrupts IRQA, IRQB, IRQC, IRQD defined level-sensitive, timings through apply prevent multiple interrupt service. avoid these timing restrictions, deasserted Edge-triggered mode recommended when using fast interrupts. Long interrupts recommended when using Level-sensitive mode. This timing depends several settings: disable, using external clock (PCTL stabilization delay required recovery time will defined PCTL settings. enable, PCTL shutdown during Stop. Recovering from Stop requires locked. lock procedure duration, Lock Cycles (PLC), range 1000 cycles. This procedure occurs parallel with stop delay counter, stop recovery will when last these events occurs: stop delay counter completes count lock procedure completion. value disable maximum value 4096 (maximum divided desired internal frequency (i.e., 4096/120 34.1 µs). During stabilization period, will constant, their width vary, timing vary well.
Periodically sampled 100% tested RESET duration measured during time which RESET asserted, valid, EXTAL input active valid. When valid, other "required RESET duration" conditions specified above) have been met, device circuitry will uninitialized state that result significant power consumption heat-up. Designs should minimize this state shortest possible duration. does lose lock 0.16 105°C, number wait states (measured clock cycles, number TC). expression compute maximum value.
2-12
DSP56366 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET Pins Reset Value
A0-A17
First Fetch
AA0460
Figure Reset Timing
DSP56366 Advance Information
2-13
Specifications Reset, Stop, Mode Select, Interrupt Timing A0-A17
First Interrupt Instruction Execution/Fetch
IRQA, IRQB, IRQC, IRQD,
First Interrupt Instruction Execution
General Purpose IRQA, IRQB, IRQC, IRQD, General Purpose
Figure External Fast Interrupt Timing
IRQA, IRQB, IRQC, IRQD, IRQA, IRQB, IRQC, IRQD,
AA0463
Figure External Interrupt Timing (Negative Edge-Triggered)
2-14
DSP56366 Advance Information
Specifications Reset, Stop, Mode Select, Interrupt Timing
RESET
MODA, MODB, MODC, MODD, PINIT
IRQA, IRQB, IRQD,
AA0465
Figure Operating Mode Select Timing
IRQA
First Instruction Fetch
AA0466
A0-A17
Figure Recovery from Stop State Using IRQA
IRQA A0-A17
First IRQA Interrupt Instruction Fetch AA0467
Figure Recovery from Stop State Using IRQA Interrupt Service
DSP56366 Advance Information
2-15
Specifications Reset, Stop, Mode Select, Interrupt Timing
A0-A17
Source Address
IRQA, IRQB, IRQC, IRQD, First Interrupt Instruction Execution
AA1104
Figure External Memory Access (DMA Source) Timing
2-16
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
EXTERNAL MEMORY EXPANSION PORT (PORT
SRAM Timing
Table SRAM Read Write Accesses3
Characteristics Symbol Expression1 tRC, Address valid assertion 0.25 1.25 assertion pulse width frequencies: 0.5) deassertion address valid 0.25 1.25 2.25 frequencies: 1.25 2.25 Address valid input data valid assertion input data valid deassertion data valid (data hold time) Address valid deassertion2 Data valid deassertion (data setup time) tAA, tOHZ (tDW) 0.75) 0.25) 0.75) 0.25) 12.0 46.0 87.0 12.7 25.2 16.7 14.7 10.6 Unit
Address valid assertion pulse width
DSP56366 Advance Information
2-17
Specifications External Memory Expansion Port (Port
Table SRAM Read Write Accesses3 (Continued)
Characteristics Symbol Expression1 0.25 Data hold time from deassertion 1.25 2.25 0.75 assertion data active 0.25 -0.25 0.25 deassertion data high impedance 1.25 2.25 1.25 Previous deassertion data active (write) 2.25 3.25 deassertion time 0.75 1.75 2.75 Address valid assertion assertion pulse width 0.25) -4.0 0.25 deassertion address valid 1.25 2.25 16.7 14.7 23.1 10.6 18.9 16.8 25.2 16.7 10.6 18.9 Unit
deassertion time
2-18
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table SRAM Read Write Accesses3 (Continued)
Characteristics Symbol Expression1 0.25 Unit
setup before deassertion4 hold after deassertion Notes:
number wait states specified BCR. Timings 100, guaranteed design, tested. timings measured from case negation: timing relative deassertion edge were remain active
A0-A17 AA0-AA2 D0-D23 Data
AA0468
Figure SRAM Read Access
DSP56366 Advance Information
2-19
Specifications External Memory Expansion Port (Port A0-A17 AA0-AA2 D0-D23 Data
Figure 2-10 SRAM Write Access
2-20
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
DRAM Timing
selection guides provided Figure 2-11 Figure 2-14 should used primary selection only. Final selection should based timing provided following tables. example, selection guide suggests that wait states must used operation when using Page Mode DRAM. However, using information appropriate table, designer choose evaluate whether fewer wait states might used determining which timing prevents operation MHz, running chip slightly lower frequency (e.g., MHz), using faster DRAM becomes available), control factors such capacitive resistive load improve overall system performance.
DRAM Type (tRAC
Note:
This figure should primary selection. exact detailed timings following tables.
Chip Frequency (MHz)
Wait States Wait States
Wait States Wait States
AA047
Figure 2-11 DRAM Page Mode Wait States Selection Guide
DSP56366 Advance Information
2-21
Specifications External Memory Expansion Port (Port
Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
Characteristics Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion deassertion4 Symbol Expression MHz6 1.25 62.5 41.7 100.0 MHz6 66.7 Unit
tCAC tOFF tRSH tRHCP tCAS tCRP
42.5 67.5
21.0 62.7 21.0 52.3 102.2 135.5
25.8 42.5
0.75 0.75 1.75 3.25 4.25 6.25
33.5 96.0 33.5 81.5 156.5 206.5 306.5 21.0 21.0 33.5 96.0 33.7 20.8 70.5 83.2
BRW[1:0]
BRW[1:0] BRW[1:0] BRW[1:0]
202.1 12.7 12.7 21.0 62.7 21.2 12.5 45.5 54.0
deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion
tASC tCAH tRAL tRCS tRCH tWCH tRWL
0.75 0.75 0.25 1.75
2-22
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table DRAM Page Mode Timings, Wait State (Low-Power Applications)1,
Characteristics assertion deassertion Data valid assertion (Write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid assertion data active deassertion data high impedance Symbol Expression 1.75 0.25 0.75 MHz6 Notes: tCWL tWCS tROH 0.75 0.25 83.2 33.5 45.7 71.0 37.2 42.5 12.5 MHz6 54.0 21.0 29.0 46.0 24.7 25.8 Unit
number wait states Page mode access specified DCR. refresh period specified DCR. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows Page Mode DRAM with Wait state (See Figure 2-14.).
Table 2-10 DRAM Page Mode Timings, Wait States1,
Characteristics Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Symbol Expression 1.25 41.1 15.2 30.4 34.4 12.3 24.8 45.4 37.5 Unit
tCAC tOFF
DSP56366 Advance Information
2-23
Specifications External Memory Expansion Port (Port
Table 2-10 DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion deassertion5 Symbol Expression tRSH tRHCP tCAS tCRP 1.75 3.25 tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH 1.25 1.75 1.25 2.75 0.25 0.25 1.75 1.75 1.75 22.5 45.2 18.7 24.4 47.2 62.4 92.8 14.9 11.2 22.5 41.5 15.1 18.5 33.5 33.4 33.6 22.5 10.9 33.9 19.0 17.9 36.6 14.8 19.0 37.8 50.3 75.3 11.6 17.9 33.5 11.8 14.6 26.8 26.8 27.0 17.9 27.3 15.4 Unit
BRW[1:0]
BRW[1:0] BRW[1:0] BRW[1:0]
deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid
2-24
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-10 DRAM Page Mode Timings, Wait States1, (Continued)
Characteristics deassertion data valid6 assertion data active deassertion data high impedance Symbol Expression Notes: 0.75 0.25 11.1 Unit
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM Control Register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. There DRAMs fast enough wait states Page mode 100MHz (See Figure 2-11)
Table 2-11 DRAM Page Mode Timings, Three Wait States1,
Characteristics Page mode cycle time consecutive accesses same direction Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 Symbol Expression 1.25 tCAC tOFF tRSH tRHCP tCAS tCRP 2.25 3.75 4.75 6.75 tASC tCAH tRAL tRCS tRCH 1.25 0.75 35.0 21.0 41.0 16.0 41.5 61.5 11.0 21.0 36.0 13.0 23.0 40.0 Unit
BRW[1:0]
BRW[1:0]
BRW[1:0] BRW[1:0]
deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion
DSP56366 Advance Information
2-25
Specifications External Memory Expansion Port (Port
Table 2-11 DRAM Page Mode Timings, Three Wait States1, (Continued)
Characteristics Symbol tWCH tRWL tCWL tWCS tROH 0.75 0.25 Expression 2.25 3.75 3.25 1.25 18.3 30.5 33.2 28.2 21.0 31.0 18.0 Unit
assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance Notes:
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of page-access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
2-26
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-12 DRAM Page Mode Timings, Four Wait States1,
Characteristics Page mode cycle time consecutive accesses same direction. Page mode cycle time mixed (read write) accesses assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) Last assertion deassertion Previous deassertion deassertion assertion pulse width Last deassertion assertion5 Symbol Expression tCAC tOFF tRSH tRHCP tCAS tCRP 2.75 4.25 5.25 7.25 tASC tCAH tRAL tRCS tRCH tWCH tRWL tCWL tWCS tROH 0.75 0.25 1.25 1.25 3.25 4.75 3.75 1.25 3.25 2.75 3.75 37.5 25.2 46.0 16.8 37.7 54.4 12.7 25.2 37.7 22.9 33.0 35.3 26.9 25.2 33.5 15.9 24.2 20.1 41.7
BRW[1:0]
BRW[1:0] BRW[1:0] BRW[1:0]
deassertion pulse width Column address valid assertion assertion column address valid Last column address valid deassertion deassertion assertion deassertion assertion assertion deassertion assertion pulse width Last assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion assertion Last assertion deassertion assertion data valid deassertion data valid6 assertion data active deassertion data high impedance
DSP56366 Advance Information
2-27
Specifications External Memory Expansion Port (Port
Table 2-12 DRAM Page Mode Timings, Four Wait States1, (Continued)
Notes: Characteristics Symbol Expression
number wait states Page mode access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. timings calculated worst case. Some timings better specific cases (e.g., equals read-after-read write-after-write sequences). BRW[1:0] (DRAM control register bits) defines number wait states that should inserted each DRAM out-of-page access. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ.
A0-A17
Column Address Column Address
Last Column Address
D0-D23
Data Data Data AA0473
Figure 2-12 DRAM Page Mode Write Accesses
2-28
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
A0-A17
Column Address
Column Address
Last Column Address
D0-D23
Data Data Data AA0474
Figure 2-13 DRAM Page Mode Read Accesses
DSP56366 Advance Information
2-29
Specifications External Memory Expansion Port (Port DRAM Type (tRAC
Note:This figure should primary selection. exact detailed timings following tables.
Wait States Wait States
Chip Frequency (MHz)
Wait States Wait States
AA0475
Figure 2-14 DRAM Out-of-Page Wait States Selection Guide
Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1,
Characteristics3 MHz4 Symbol tRAC tCAC tOFF tRAS 1.75 3.25 Expression Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width 2.75 1.25 250.0 83.5 158.5 130.0 55.0 67.5 166.7 54.3 104.3 84.2 34.2 42.5 MHz4 Unit
2-30
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Characteristics3 MHz4 Symbol Expression assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL 1.75 2.75 1.25 1.25 2.25 1.75 1.75 1.25 0.25 1.75 3.25 0.75 0.25 4.75 4.25 2.25 1.75 83.5 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 83.5 158.5 96.0 71.2 33.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 77.0 64.5 54.3 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 54.3 104.3 62.7 46.2 21.3 45.8 95.8 145.5 154.0 137.4 71.0 54.3 52.0 43.7 MHz4 Unit
DSP56366 Advance Information
2-31
Specifications External Memory Expansion Port (Port
Table 2-13 DRAM Out-of-Page Refresh Timings, Four Wait States1, (Continued)
Characteristics3 MHz4 Symbol Expression Notes: assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance tDHR tWCS tCSR tRPC tROH 0.75 0.25 3.25 1.25 158.5 145.7 21.0 58.5 221.0 37.2 192.5 12.5 104.3 95.7 12.7 37.7 146.0 24.7 125.8 MHz4 Unit
number wait states page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Reduced clock speed allows DRAM out-of-page access with four Wait states (See Figure 2-17.).
Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1,
Characteristics4 Symbol tRAC tCAC tOFF tRAS tRSH 3.25 5.75 3.25 Expression3 4.75 4.75 2.25 2.25 Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion 136.4 45.2 83.1 45.2 64.5 26.6 40.0
Unit 112.5 36.6 67.9 36.6 52.9 21.6 31.0
2-32
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 Symbol tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH Expression3 4.75 2.25 1.75 4.25 2.75 3.25 1.75 0.75 3.25 5.75 1.25 0.25 0.25 8.75 7.75 4.75 3.25 5.75 1.75 68.0 30.1 35.9 24.5 59.8 37.7 45.2 22.5 45.2 83.1 56.6 26.5 15.2 41.3 79.1 124.3 128.3 113.1 68.0 45.2 83.1 79.0 18.7 22.5 124.8 39.9 28.5
Unit 55.5 24.1 29.3 19.9 49.1 30.4 36.6 17.9 36.6 67.9 46.0 21.2 11.9 33.3 64.6 101.8 105.1 92.6 55.4 36.6 67.9 64.5 14.8 17.9 102.3 33.3 23.9
assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion
DSP56366 Advance Information
2-33
Specifications External Memory Expansion Port (Port
Table 2-14 DRAM Out-of-Page Refresh Timings, Eight Wait States1, (Continued)
Characteristics4 Symbol Expression3 0.75 0.25 11.1 106.1
Unit 87.3
assertion data valid deassertion data valid assertion data active deassertion data high impedance Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
2-34
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1,
Characteristics4 Symbol tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 4.25 7.75 5.25 6.25 3.75 1.75 5.75 4.25 4.25 1.75 0.75 5.25 7.75 1.75 0.25 11.5 11.75 10.25 5.75 5.25 7.75 2.75 11.5 Expression3 6.25 3.75 120.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 48.5 73.5 56.0 26.0 13.5 45.8 70.8 110.5 113.2 103.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0 55.5 30.5 38.0 29.0 21.5 Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion deassertion assertion
deassertion assertion assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion
DSP56366 Advance Information
2-35
Specifications External Memory Expansion Port (Port
Table 2-15 DRAM Out-of-Page Refresh Timings, Eleven Wait States1, (Continued)
Characteristics4 Symbol 0.75 0.25 Expression3 93.0 Unit
assertion data valid deassertion data valid4 assertion data active deassertion data high impedance Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. asynchronous delays specified expressions valid DSP56366. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States1,
Characteristics3 Symbol tRAC tCAC tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS Expression 8.25 4.75 6.25 9.75 6.25 8.25 4.75 2.75 7.75 6.25 6.25 2.75 0.75 6.25 9.75 133.3 48.1 77.2 48.1 64.7 35.6 27.2 20.9 60.6 48.1 48.1 18.9 48.1 77.2 54.3 37.9 63.0 33.9 40.1 31.2 24.9 Unit
Random read write cycle time assertion data valid (read) assertion data valid (read) Column address valid data valid (read) deassertion data valid (read hold time) deassertion assertion assertion pulse width assertion deassertion assertion deassertion assertion pulse width assertion assertion assertion column address valid deassertion assertion deassertion pulse width address valid assertion assertion address valid Column address valid assertion assertion column address valid assertion column address valid Column address valid deassertion deassertion assertion
2-36
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Table 2-16 DRAM Out-of-Page Refresh Timings, Fifteen Wait States1, (Continued)
Characteristics3 Symbol tRCH tRRH tWCH tWCR tRWL tCWL tDHR tWCS tCSR tRPC tROH 0.75 0.25 Expression 1.75 0.25 15.5 15.75 14.25 8.75 6.25 9.75 4.75 15.5 10.9 45.8 75.0 124.7 126.9 114.4 68.9 48.1 77.2 74.9 35.6 125.2 111.0 Unit
deassertion assertion deassertion assertion
assertion deassertion assertion deassertion assertion pulse width assertion deassertion assertion deassertion Data valid assertion (write) assertion data valid (write) assertion data valid (write) assertion assertion assertion assertion (refresh) deassertion assertion (refresh) assertion deassertion assertion data valid deassertion data valid3 assertion data active deassertion data high impedance Notes:
number wait states out-of-page access specified DCR. refresh period specified DCR. deassertion will always occur after deassertion; therefore, restricted timing tOFF tGZ. Either tRCH tRRH must satisfied read cycles.
DSP56366 Advance Information
2-37
Specifications External Memory Expansion Port (Port A0-A17
Address Column Address
Data AA0476
D0-D23
Figure 2-15 DRAM Out-of-Page Read Access
2-38
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port A0-A17 Address D0-D23 Data
AA0477
Column Address
Figure 2-16 DRAM Out-of-Page Write Access
DSP56366 Advance Information
2-39
Specifications External Memory Expansion Port (Port
AA0478
Figure 2-17 DRAM Refresh Access
2-40
DSP56366 Advance Information
Specifications External Memory Expansion Port (Port
Arbitration Timings
Table 2-17 Asynchronous Arbitration timing
Characteristics
assertion window from input negation. Delay from assertion assertion
Expression
25.8
Unit
21.7
Comments: register must enter Asynchronous Arbitration mode Asynchronous Arbitration mode active, none timings Table 2-17 required. order guarantee timings 250, 251, recommended assert inputs different 56300 devices same bus) overlap manner shown Figure 2-18.
Figure 2-18 Asynchronous Arbitration Timing
DSP56366 Advance Information
2-41
Specifications External Memory Expansion Port (Port
250+251
Figure 2-19 Asynchronous Arbitration Timing Background explanation Asynchronous Arbitration: asynchronous arbitration enabled internal synchronization circuits inputs. These synchronization circuits delay from external signal until exposed internal logic. result this delay, 56300 part assume mastership assert some time after negated. This reason timing 250. Once asserted, there synchronization delay from assertion time this assertion exposed other 56300 components which potential masters same bus. input asserted before that time, situation asserted, negated, cause another 56300 component assume mastership same time. Therefore some non-overlap period between input active another input active required. Timing ensures that such situation avoided.
2-42
DSP56366 Advance Information
Specifications Parallel Host Interface (HDI08) Timing
PARALLEL HOST INTERFACE (HDI08) TIMING
Table 2-18 Host Interface (HDI08) Timing1,
Characteristics3
Read data strobe assertion width4 HACK read assertion width Read data strobe deassertion width4 HACK read deassertion width
Expression
18.3
Unit
Read data strobe deassertion width4 after "Last Data Register" reads5,6, between consecutive CVR, ICR, reads7 HACK deassertion width after "Last Data Register" reads5,6 Write data strobe assertion width8 HACK write assertion width Write data strobe deassertion width8 HACK write deassertion width after ICR, "Last Data Register" writes5 after writes, after TXH:TXM writes (with HBE=0),
27.4
13.2
27.4
16.5
after TXL:TXM writes (with HBE=1)
assertion width deassertion data strobe assertion9 Host data input setup time before write data strobe deassertion8 Host data input setup time before HACK write deassertion Host data input hold time after write data strobe deassertion8 Host data input hold time after HACK write deassertion Read data strobe assertion output data active from high impedance4 HACK read assertion output data active from high impedance Read data strobe assertion output data valid4 HACK read assertion output data valid
24.2
Read data strobe deassertion output data high impedance4 HACK read deassertion output data high impedance Output data hold time after read data strobe deassertion4 Output data hold time after HACK read deassertion
DSP56366 Advance Information
2-43
Specifications Parallel Host Interface (HDI08) Timing
Table 2-18 Host Interface (HDI08) Timing1, (Continued)
Characteristics3 Expression
+9.9 18.2 19.1
Unit
assertion read data strobe deassertion4 assertion write data strobe deassertion8 assertion output data valid hold time after data strobe deassertion9 Address (AD7-AD0) setup time before deassertion (HMUX=1) Address (AD7-AD0) hold time after deassertion (HMUX=1)
A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion9 Read Write A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion9
Delay from read data strobe deassertion host request assertion "Last Data Register" read4, Delay from write data strobe deassertion host request assertion "Last Data Register" write5, Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD 0)5, Delay from data strobe assertion host request deassertion "Last Data Register" read write (HROD open drain Host Request)5, Delay from HACK deassertion HOREQ assertion "Last Data Register" read5 "Last Data Register" write5 other cases Delay from HACK assertion HOREQ deassertion HROD Delay from HACK assertion HOREQ deassertion "Last Data Register" read write HROD open drain Host Request5,
16.7
19.1
300.0
19.1 19.1
35.8 31.6
20.2
300.0
2-44
DSP56366 Advance Information
Specifications Parallel Host Interface (HDI08) Timing
Table 2-18 Host Interface (HDI08) Timing1, (Continued)
Notes:
Characteristics3
Expression Unit
Host Port Usage Considerations DSP56366 User's Manual. timing diagrams below, controls pins drawn active low. polarity programmable. 0.16 +105°C, read data strobe dual data strobe mode single data strobe mode. "last data register" register address which last location read written data transfers. This timing applicable only read from "last data register" followed read from RXL, RXM, registers without first polling RXDF HREQ bits, waiting assertion HOREQ signal. This timing applicable only consecutive reads from these registers executed. write data strobe dual data strobe mode single data strobe mode. data strobe host read (HRD) host write (HWR) dual data strobe mode host data strobe (HDS) single data strobe mode. host request HOREQ single host request mode HRRQ HTRQ double host request mode. this calculation, host request signal pulled resistor open-drain mode.
HACK HD7-HD0
HOREQ
AA1105
Figure 2-20 Host Interrupt Vector Register (IVR) Read Timing Diagram
DSP56366 Advance Information
2-45
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2
HRD, HD0-HD7 HOREQ, HRRQ, HTRQ
AA0484
Figure 2-21 Read Timing Diagram, Non-Multiplexed
2-46
DSP56366 Advance Information
Specifications Parallel Host Interface (HDI08) Timing
HA0-HA2
HWR, HD0-HD7 HOREQ, HRRQ, HTRQ
AA0485
Figure 2-22 Write Timing Diagram, Non-Multiplexed
DSP56366 Advance Information
2-47
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HRD, HAD0-HAD7 Address HOREQ, HRRQ, HTRQ
AA0486
Data
Figure 2-23 Read Timing Diagram, Multiplexed
2-48
DSP56366 Advance Information
Specifications Parallel Host Interface (HDI08) Timing
HA8-HA10
HWR, HAD0-HAD7 Address Data HOREQ, HRRQ, HTRQ
AA0487
Figure 2-24 Write Timing Diagram, Multiplexed
HOREQ (Output)
HACK (Input)
TXH/M/L Write
H0-H7 (Input)
Data Valid
Figure 2-25 Host Write Timing Diagram
DSP56366 Advance Information
2-49
Specifications Parallel Host Interface (HDI08) Timing
HOREQ (Output)
HACK (Input)
Read Data Valid
H0-H7 (Output)
Figure 2-26 Host Read Timing Diagram
2-50
DSP56366 Advance Information
Specifications Serial Host Interface Protocol Timing
SERIAL HOST INTERFACE PROTOCOL TIMING
Table 2-19 Serial Host Interface Protocol Timing
Characteristics1 Mode Filter Mode Bypassed Tolerable spike width clock data Narrow Wide Bypassed Minimum serial clock cycle tSPICC(min) Master Narrow Wide Bypassed Master Serial clock high period Slave Narrow Wide Bypassed Narrow Wide Bypassed Master Serial clock period Slave Narrow Wide Bypassed Narrow Wide Serial clock rise/fall time Master Slave Bypassed assertion first edge CPHA Slave CPHA Bypassed Narrow Wide Bypassed Last edge asserted Slave Narrow Wide Bypassed Data input valid edge (data input set-up time) Master/ Slave Narrow Wide MAX{(20-TC), MAX{(40-TC), 11.7 31.7 Narrow Slave Wide Expression 126.5 32.8 122.8 209.8 126.5 32.8 122.8 209.8 44.2 2000 Unit
DSP56366 Advance Information
2-51
Specifications Serial Host Interface Protocol Timing
Table 2-19 Serial Host Interface Protocol Timing (Continued)
Characteristics1 Mode Filter Mode Bypassed Master/ last sampling edge data input Slave valid assertion data active deassertion data high impedance2 edge data valid (data delay time) Slave Slave Master/ Slave Narrow Wide Bypassed Narrow Wide Bypassed edge data valid (data hold time) assertion data valid (CPHA First sampling edge HREQ output deassertion Master/ Slave Narrow Wide Slave Bypassed Slave Narrow Wide Bypassed Last sampling edge HREQ output deasserted (CPHA deassertion HREQ output deasserted (CPHA deassertion pulse width (CPHA Slave Narrow Wide Slave Slave Bypassed HREQ assertion first edge Master Narrow Wide HREQ deassertion last sampling edge (HREQ set-up time) (CPHA First edge HREQ asserted (HREQ hold time) Expression TC+5 TC+55 TC+106 TC+33 TC+6 tSPICC 30.8 50.8 70.8 13.3 63.3 114.3 50.8 100.8 156.8 50.8 14.3 111.8 164.8 200.3 49.7 139.7 226.7 41.3 50.8 140.8 237.8 Unit
Master
Master
Notes:
3.16 0.16 +105°C, Periodically sampled, 100% tested
2-52
DSP56366 Advance Information
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid
Valid
MOSI (Output) HREQ (Input)
AA0271
Figure 2-27 Master Timing (CPHA
DSP56366 Advance Information
2-53
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Output) (CPOL (Output) MISO (Input)
Valid Valid
MOSI (Output) HREQ (Input)
AA0272
Figure 2-28 Master Timing (CPHA
2-54
DSP56366 Advance Information
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input)
Valid Valid
HREQ (Output)
AA0273
Figure 2-29 Slave Timing (CPHA
DSP56366 Advance Information
2-55
Specifications Serial Host Interface Protocol Timing
(Input) (CPOL (Input) (CPOL (Input) MISO (Output) MOSI (Input)
Valid Valid
HREQ (Output)
AA0274
Figure 2-30 Slave Timing (CPHA
2-56
DSP56366 Advance Information
Specifications Serial Host Interface (SHI)
Protocol Timing
SERIAL HOST INTERFACE (SHI) PROTOCOL TIMING
Table 2-20 Protocol Timing
Characteristics1,2,3 Symbol/ Expression Standard Mode4 Tolerable spike width Filters bypassed Narrow filters enabled Wide filters enabled clock frequency clock cycle free time Start condition set-up time Start condition hold time period high period rise time fall time Data set-up time Data hold time clock frequency Filters bypassed Narrow filters enabled Wide filters enabled data valid Stop condition set-up time HREQ deassertion last edge (HREQ set-up time) First sampling edge HREQ output deassertion Filters bypassed Narrow filters enabled Wide filters enabled TVD;DAT TSU;STO tSU;RQI TNG;RQO 46.7 136.7 224.7 46.7 136.7 224.7 FDSP 10.6 11.8 13.1 28.5 39.7 61.0 FSCL TSCL TBUF TSU;STA THD;STA TLOW THIGH TSU;DAT THD;DAT 1000 Fast Mode5 Unit
DSP56366 Advance Information
2-57
Specifications Serial Host Interface (SHI) Protocol Timing
Table 2-20 Protocol Timing (Continued)
Characteristics1,2,3 Symbol/ Expression Standard Mode4 Last edge HREQ output deasserted Filters bypassed Narrow filters enabled Wide filters enabled HREQ assertion first edge Filters bypassed Narrow filters enabled Wide filters enabled Notes: First edge HREQ asserted (HREQ hold time) tHO;RQI TAS;RQO 46.7 96.7 151.6 46.7 96.7 151.6 Fast Mode5 Unit
TAS;RQI TI2CCP
4440 4373 4373
1041
3.16 0.16 +105°C Pull-up resistor: (min) kOhm Capacitive load: (max) recommended enable wide filters when operating Standard Mode. recommended enable narrow filters when operating Fast Mode.
Programming Serial Clock
programmed serial clock cycle, I2CCP specified value HDM[7:0] bits HCKR (SHI clock control register). expression I2CCP I2CCP (HDM[7:0] HRS) where prescaler rate select bit. When cleared, fixed divide-by-eight prescaler operational. When set, prescaler bypassed. HDM[7:0] divider modulus select bits. divide ratio from (HDM[7:0] $FF) selected.
mode, user select value programmed serial clock cycle from HDM[7:0]
2-58
DSP56366 Advance Information
Specifications Serial Host Interface (SHI)
Protocol Timing
4096
HDM[7:0]
programmed serial clock cycle (TI2CCP rise time (TR), filters selected should chosen order achieve desired serial clock cycle (TSCL), shown Table 2-21. Table 2-21 Serial Clock Cycle (TSCL) generated Master
Filters bypassed Narrow filters enabled Wide filters enabled
TI2CCP 45ns TI2CCP 135ns TI2CCP 223ns
EXAMPLE: clock frequency (i.e. 8.33ns), operating standard mode environment (FSCL (i.e. TSCL 10µs), 1000ns), with wide filters enabled: TI2CCP 10µs 223ns 1000ns 8756ns Choosing gives HDM[7:0] 8756ns 8.33ns 64.67 Thus HDM[7:0] value should programmed (=65). resulting TI2CCP will I2CCP (HDM[7:0] HRS) I2CCP [8.33ns I2CCP [8.33ns 8796.48ns
DSP56366 Advance Information
2-59
Specifications Serial Host Interface (SHI) Protocol Timing
Stop Start Stop
HREQ
AA0275
Figure 2-31 Timing
2-60
DSP56366 Advance Information
Specifications Enhanced Serial Audio Interface Timing
ENHANCED SERIAL AUDIO INTERFACE TIMING
Table 2-22 Enhanced Serial Audio Interface Timing
Characteristics1, Symbol Expression Clock cycle5 Clock high period internal clock tSSICC TXC:max[3*tc; t454] 10.0 10.0 33.3 25.0 27.2 12.5 12.5 19.0 23.0 23.0 19.0 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 36.0 21.0 37.0 22.0 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 CondUnit ition4
external clock
Clock period internal clock
external clock
rising edge (bl) high rising edge (bl) rising edge (wr) high6 rising edge (wr) low6 rising edge (wl) high rising edge (wl) Data setup time before (SCK synchronous mode) falling edge Data hold time after falling edge input (bl, high before falling edge input (wl) high before falling edge input hold time after falling edge Flags input setup before falling edge Flags input hold time after falling edge rising edge (bl) high rising edge (bl) rising edge (wr) high6 rising edge (wr) low6
DSP56366 Advance Information
2-61
Specifications Enhanced Serial Audio Interface Timing
Table 2-22 Enhanced Serial Audio Interface Timing (Continued)
Characteristics1, Symbol Expression 21.0 21.0 21.0 40.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 27.2 21.0 31.0 16.0 34.0 20.0 27.0 31.0 32.0 18.0 27.5 27.5 CondUnit ition4
rising edge (wl) high rising edge (wl) rising edge data enable from high impedance rising edge transmitter drive enable assertion rising edge data valid edge data high rising impedance transmitter drive rising edge enable deassertion input (bl, setup time before falling edge6 input (wl) data enable from high impedance input (wl) transmitter drive enable assertion input (wl) setup time before falling edge input hold time after falling edge Flag output valid after rising edge HCKR/HCKT clock cycle HCKT input rising edge output HCKR input rising edge output
2-62
DSP56366 Advance Information
Specifications Enhanced Serial Audio Interface Timing
Table 2-22 Enhanced Serial Audio Interface Timing (Continued)
Notes: Characteristics1, Symbol Expression CondUnit ition4
3.16 0.16 +105°C, internal clock external clock internal clock, asynchronous mode (asynchronous implies that different clocks) internal clock, synchronous mode (synchronous implies that same clock) length word length word length relative TXC(SCKT pin) transmit clock RXC(SCKR pin) receive clock FST(FST pin) transmit frame sync FSR(FSR pin) receive frame sync HCKT(HCKT pin) transmit high frequency clock HCKR(HCKR pin) receive high frequency clock internal clock, external clock cycle defined Icyc ESAI control register. word-relative frame sync signal waveform relative clock operates same manner bit-length frame sync signal waveform, spreads from serial clock before first clock (same length frame sync signal), until before last clock first word frame. Periodically sampled 100% tested
DSP56366 Advance Information
2-63
Specifications Enhanced Serial Audio Interface Timing
(Input/ Output)
(Bit)
(Word)
First Last
Data
Transmitter Drive Enable
(Bit) (Word)
Note
Flags Note: network mode, output flag transitions occur start each time slot within frame. normal mode, output flag state asserted entire frame period.
AA0490
Figure 2-32 ESAI Transmitter Timing
2-64
DSP56366 Advance Information
Specifications Enhanced Serial Audio Interface Timing (Input/Output) (Bit) (Word) Data (Bit) (Word) Flags
AA0491
First
Last
Figure 2-33 ESAI Receiver Timing
DSP56366 Advance Information
2-65
Specifications Enhanced Serial Audio Interface Timing
HCKT
SCKT(output)
Figure 2-34 ESAI HCKT Timing
HCKR
SCKR (output)
Figure 2-35 ESAI HCKR Timing
2-66
DSP56366 Advance Information
Specifications Digital Audio Transmitter Timing
DIGITAL AUDIO TRANSMITTER TIMING
Table 2-23 Digital Audio Transmitter Timing
Characteristic Expression
frequency (see note) Note: period high duration duration rising edge valid 16.7
Unit
12.5
order assure proper operation DAX, frequency should less than DSP56366 internal clock frequency. example, DSP56366 running internally, frequency should less than MHz.
AA1280
Figure 2-36 Digital Audio Transmitter Timing
DSP56366 Advance Information
2-67
Specifications Timer Timing
TIMER TIMING
Table 2-24 Timer Timing
High Note:
Characteristics
Expression
18.7 18.7
Unit
0.16 +105°C,
AA0492
Figure 2-37 Timer Event Input Restrictions
2-68
DSP56366 Advance Information
Specifications GPIO Timing
GPIO TIMING
Table 2-25 GPIO Timing
Characteristics1 EXTAL edge GPIO valid (GPIO delay time) EXTAL edge GPIO valid (GPIO hold time) GPIO valid EXTAL edge (GPIO set-up time) EXTAL edge GPIO valid (GPIO hold time) Fetch EXTAL edge before GPIO change GPIO rise time GPIO fall time
Expression
10.2
32.8
Unit
4942 Notes:
6.75 TC-1.8
54.5
0.16 +105°C, Valid only when enabled with multiplication factor equal one.
EXTAL (Input) GPIO (Output) GPIO (Input) Valid
A0-A17 Fetch instruction MOVE X0,X:(R0); contains value GPIO contains address GPIO data register.
GPIO (Output)
Figure 2-38 GPIO Timing
DSP56366 Advance Information
2-69
Specifications JTAG Timing
JTAG TIMING
Table 2-26 JTAG Timing
frequencies Notes: Characteristics frequency operation (1/(TC maximum MHz) cycle time Crystal mode clock pulse width measured rise fall times Boundary scan input data setup time Boundary scan input data hold time output data valid output high impedance TMS, data setup time TMS, data hold time data valid high impedance 45.0 20.0 24.0 25.0 22.0 40.0 40.0 44.0 44.0 Unit
0.16 +105°C, timings apply OnCE module data transfers because uses JTAG port interface.
(Input)
AA0496
Figure 2-39 Test Clock Input Timing Diagram
2-70
DSP56366 Advance Information
Specifications JTAG Timing
(Input)
Data Inputs Data Outputs Data Outputs Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid
AA0497
Figure 2-40 Boundary Scan (JTAG) Timing Diagram
(Input) (Input)
Input Data Valid
(Output) (Output) (Output)
Output Data Valid
Output Data Valid
AA0498
Figure 2-41 Test Access Port Timing Diagram
DSP56366 Advance Information
2-71
Specifications JTAG Timing
2-72
DSP56366 Advance Information
SECTION PACKAGING
PIN-OUT PACKAGE INFORMATION
This section provides information about available package this product, including diagrams package pinouts tables describing signals described Section allocated package. DSP56366 available 144-pin TQFP package. Table Table show pin/name assignments packages.
TQFP Package Description
view 144-pin TQFP package shown Figure with pin-outs. package drawing shown Figure 3-2.
DSP56366 Advance Information
Packaging Pin-out Package Information
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
MISO/SDA MOSI/HA0 SDO4_1/SDI1_1 MODA/IRQA# MODB/IRQB# MODCIRQC# MODD/IRQD# GNDD VCCD GNDQ VCCQL GNDD VCCD GNDD VCCD
GNDD VCCD GNDA VCCQH VCCQL GNDQ GNDA VCCA GNDA VCCA GNDA VCCA
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# VCCC GNDC
Figure 144-pin package
DSP56366 Advance Information
Packaging Pin-out Package Information
Table Signal Identification Name
Signal Name
CAS#
Signal Name
Signal Name
GNDS GNDS HA8/HA1 HA9/HA2 HACK/HRRQ HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HA0 HCKR HCKT HCS/HA10 HDS/HWR HOREQ/HTRQ HREQ# HRW/HRD MODA/IRQA# MODB/IRQB# MODC/IRQC# MODD/IRQD# MISO/SDA MOSI/HA0 PCAP PINIT/NMI# RESET# SCK/SCL SCKR SCKR_1 SCKT SCKT_1
Signal Name
SDO0/SDO0_1 SDO1/SDO1_1
SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 SDO4/SDI1 SDO4_1/SDI1_1 SDO5/SDI0 SDO5_1/SDI0_1 SS#/HA2 TIO0 VCCA VCCA VCCA VCCC VCCC VCCD VCCD VCCD VCCD VCCH VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL VCCP VCCS VCCS
EXTAL FSR_1 FST_1 GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD GNDD GNDD GNDH GNDP GNDQ GNDQ GNDQ GNDQ
Table
Signal Identification Number
Signal Name
VCCA GNDA
Signal Name
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1
Signal Name
Signal Name
HAD4 VCCH GNDH HAD3
VCCD GNDD
DSP56366 Advance Information
Packaging Pin-out Package Information
Table
SDO1/SDO1_1 SDO2/SDI3/SDO2_1/ SDI3_1 SDO3/SDI2/SDO3_1/ SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
Signal Identification Number (Continued)
HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# VCCC GNDC VCCA GNDA VCCA GNDA GNDQ VCCQL VCCQH GNDA VCCD GNDD VCCD GNDD VCCQL GNDQ VCCD GNDD MODD/IRQD# MODC/IRQC# MODB/IRQB# MODA/IRQA# SDO4_1/SDI1_1 MOSI/HA0 MISO/SDA
DSP56366 Advance Information
Packaging Pin-out Package Information
TQFP Package Mechanical Drawing
Figure DSP56366 144-pin TQFP Package
DSP56366 Advance Information
Packaging Ordering Drawings
ORDERING DRAWINGS
detailed package drawing available Motorola page package 918-03 search.
DSP56366 Advance Information
SECTION DESIGN CONSIDERATIONS
THERMAL DESIGN CONSIDERATIONS
estimation chip junction temperature, obtained from following equation:
Where:
ambient temperature RqJA package junction-to-ambient thermal resistance °C/W power dissipation package
Historically, thermal resistance been expressed junction-to-case thermal resistance case-to-ambient thermal resistance.
Where:
package junction-to-ambient thermal resistance °C/W package junction-to-case thermal resistance °C/W package case-to-ambient thermal resistance °C/W
device-related cannot influenced user. user controls thermal environment change case-to-ambient thermal resistance, RCA. example, user change flow around device, heat sink, change mounting arrangement printed circuit board (PCB), otherwise change thermal dissipation capability area surrounding device PCB. This model most useful ceramic packages with heat sinks; some heat flow dissipated through case heat sink ambient environment. ceramic packages, situations where heat flow split between path case alternate path through PCB, analysis device thermal performance need additional modeling capability system level thermal simulation tool. thermal performance plastic packages more dependent temperature which package mounted. Again, estimations obtained from satisfactorily answer whether thermal performance adequate, system level model appropriate. complicating factor existence three common ways determining junction-to-case thermal resistance plastic packages.
DSP56366 Advance Information
Design Considerations Electrical Design Considerations
minimize temperature variation across surface, thermal resistance measured from junction outside surface package (case) closest chip mounting area when that surface proper heat sink. define value approximately equal junction-to-board thermal resistance, thermal resistance measured from junction where leads attached case. temperature package case (TT) determined thermocouple, thermal resistance computed using value obtained equation TT)/PD.
noted above, junction-to-case thermal resistances quoted this data sheet determined using first definition. From practical standpoint, that value also suitable determining junction temperature from case thermocouple reading forced convection environments. natural convection, using junction-to-case thermal resistance estimate junction temperature from thermocouple reading case package will estimate junction temperature slightly hotter than actual temperature. Hence, thermal metric, thermal characterization parameter been defined TT)/PD. This value gives better estimate junction temperature natural convection when using surface temperature package. Remember that surface temperature readings packages subject significant errors caused inadequate attachment sensor surface errors caused heat loss sensor. recommended technique attach 40-gauge thermocouple wire bea
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