3-State Inverting Outputs Drive Lines Directly Full Parallel Access Lo

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3-State Inverting Outputs Drive Lines Directly Full Parallel Access Lo

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SN54AC563, SN74AC563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
3-State Inverting Outputs Drive Lines Directly Full Parallel Access Loading Flow-Through Architecture Optimize Layout EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Chip Carriers (FK) Flatpacks (W), Standard Plastic Ceramic DIPs
SN54AC563 PACKAGE SN74AC563 PACKAGE (TOP VIEW)
description
'AC563 octal D-type transparent latches with 3-state outputs. When latch-enable (LE) input high, outputs follow complements data inputs. When taken low, outputs latched inverse logic levels inputs. buffered output-enable (OE) input used place eight outputs either normal logic state (high logic levels) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components.
SN54AC563 PACKAGE (TOP VIEW)
does affect internal operations latches. data retained data entered while outputs high-impedance state. SN54AC563 characterized operation over full military temperature range 55°C 125°C. SN74AC563 characterized operation from -40°C 85°C.
FUNCTION TABLE (each latch) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademark Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 1996, Texas Instruments Incorporated
DALLAS, TEXAS 75265
SN54AC563, SN74AC563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
logic symbol
logic diagram (positive logic)
Seven Other Channels
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range, (see Note -0.5 Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through ±200 Maximum power dissipation 55°C still air) (see Note package package package package Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC563, SN74AC563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
SN54AC563 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise fall rate 3.15 3.85 1.35 1.65 SN74AC563 3.15 3.85 1.35 1.65 ns/V UNIT
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, ±0.1 ±0.5 0.002 0.001 0.001 0.36 0.36 0.36 2.99 4.49 5.49 2.56 3.86 4.86 25°C SN54AC563 2.48 3.85 1.65 SN74AC563 2.46 3.76 4.76 3.85 0.44 0.44 0.44 1.65 UNIT
more than output should tested time, duration test should exceed
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC563, SN74AC563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Setup time, data before Hold time, data after SN54AC563 SN74AC563 UNIT
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Setup time, data before Hold time, data after SN54AC563 SN74AC563 UNIT
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT)
free-air
temperature
SN74AC563 12.5 13.5 10.5
range,
UNIT
25°C 12.5
SN54AC563 16.5 15.5 16.5 15.5 13.5
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT)
free-air
temperature
SN74AC563 11.5
range,
UNIT
25°C
SN54AC563 12.5 12.5 11.5 11.5 13.5 10.5
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC563, SN74AC563 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
LOAD CIRCUIT Timing Input Input VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS Data Input
Input tPLH In-Phase Output tPHL Out-of-Phase Output tPHL tPLH
Output Control (low-level enabling) Output Waveform (see Note Output Waveform Open (see Note
tPZL tPLZ tPHZ
tPZH
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated

3-State Inverting Outputs Drive Lines Directly Full Parallel Access Lo

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