4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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SH66P12
4-bit Microcontroller with Driver
SH6610C-based single-chip 4-bit microcontroller with driver ROM: 2048 bits RAM: bits (Data memory) Operation voltage: 2.5V 5.4V CMOS pins CMOS Open Drain (code option) level subroutine nesting (including interrupts) 8-bit timer/counter with pre-divider circuit Oscillator warm-up timer priority interrupt sources: External interrupt (falling edge) Timer0 interrupt Timer1 interrupt PortB interrupt (falling edge) Oscillator 32.768KHz crystal 262K (code option) Instruction cycle time: 4/32.768KHz 122µs) 32.768KHz clock 4/262KHz 15µs) 262KHz clock driver: (1/4 duty, bias duty, bias) power operation modes: HALT STOP mode Built-in alarm generator carrier frequency: 2KHz 4KHz (code option) power consumption (Iop 30µA, 32.768KHz, Bonding option multi-code software Available CHIP FORM
General Description
SH66P12 single-chip microcontroller integrated with SH6610C 4-bit core, SRAM, timer, alarm generator, driver, port, program ROM.
Configuration
SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
COM3 COM4 OSCI OSCO PORTD3 PORTD2 PORTD1 PORTD0 PORTC3 PORTC2 PORTC1 PORTC0 PORTB3
SH66P12
V2.0
SH66P12
Block Diagram
(2048
TEST OSCI
DATA (256 OSCO 8-Bit TIMER PORTB, PORTC PORTS (3*4) CORE PORTA EXTEMAL PORTA.0 (INT) PORTA.1(BD) PORTA.2 (BD) PORTA.3 COMMON DRIVERS COM1 COM4 PORTD
RESET ALARM GENERATOR
SEGMENT DRIVERS
SEG1 SEG26
OPERATING VOLTAGE VOLTAGE DIVIDER
Description
Designation SEG1 TEST RESET Description Segment signal output display. Seg1 output ports Test internally pull-down.(No connect user) reset input Power Share with Bonding option, internally pull-low programmable PA.0 could external interrupt input PA.1, PA.2 could buzzer output PA.1 (BD), PA.2 program mode, PA.1 shared with DATA, shared with PINPGMB, shared with PINOE Total pads. PORTB0 PORTC0 PORTD0 OSCO OSCI COM1 programmable I/O, vector interrupts (active falling edge) programmable programmable Ground Share with Bonding option, internally pull-high Oscillator output pin, connected crystal oscillator Oscillator input pin, connected crystal external resistor Common signal output display
PORTA0
SH66P12
Functional Description
contains following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, DPL), Stack. (Program Counter) Program Counter used address program ROM. consists 12-bits: Page Register (PC11), Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). program counter normally increases (+1) with every execution instruction except following cases: When executing jump instruction (such JMP, BA0, BAC); When executing subroutine call instruction (CALL); When interrupt occurs; When chip INITIAL RESET mode. program counter loaded with data corresponding each instruction. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment addition/subtraction (DAA, DAS) Logic operations (AND, EOR, ANDIM, EORIM, ORIM) address 2048 words bits program area from $000 $7FF. Vector Address Area ($000 $004) program sequentially executed. There area address $000 through $004 that reserved special interrupt service routine such starting vector address. Address $000H $001H $002H $003H $004H Instruction instruction instruction instruction instruction instruction Function Jump RESET service routine Jump External interrupt service routine Jump TIMER0 service routine Jump TIMER1 service routine Jump service routine (PORTB) Decision (BA0, BA1, BA2, BA3, BAZ, Logic Shift (SHR) Carry Flag (CY) holds overflow, which arithmetic operation generates. During interrupt service call instruction, carry flag pushed into stack restored back from stack RTNI instruction. unaffected RTNW instruction. Accumulator Accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transferred between accumulator system register, RAM, data memory performed. Stack group registers used save contents (10-0) sequentially with each subroutine call interrupt. organized bits levels. saved levels maximum allowed subroutine calls interrupts. contents stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds bottom stack will shifted out.
Table Data Reference Table Data stored program memory referenced using Table Branch (TJMP) Return Constant (RTNW) instructions. Table Branch Register (TBR) Accumulator (AC) placed offset address program ROM. TJMP instruction branch into address ((PC11 PC8) (28) (TBR, AC)). address determined RTNW return look-up value into (TBR, AC). code bit7-bit4 placed into bit3-bit0 into
SH66P12
Built-in contains general-purpose data memory, RAM, system register. Data memory, RAM, system register direct accessed instruction cycle. Because static nature, keep data after enters STOP HALT. Data memory, RAM, System register following memory allocation map: $000 $01F: System register $020 $11F: Data memory (256 bits divided into banks) $300 $319: space bits) Configuration System Register Address IRQX T0L.3 T0H.3 T1L.3 T1H.3 PA.3 PB.3 PC.3 PD.3 LPD3 TBR.3 INX.3 DPL.3 IET0 IRQT0 T0M.2 T1M.2 T0L.2 T0H.2 T1L.2 T1H.2 PA.2 PB.2 PC.2 PD.2 LPD2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 LCDOFF IET1 IRQT1 T0M.1 T1M.1 T0L.1 T0H.1 T1L.1 T1H.1 PA.1 PB.1 PC.1 PD.1 LPD1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 IRQP T0M.0 T1M.0 T0L.0 T0H.0 T1L.0 T1H.0 PA.0 PB.0 PC.0 PD.0 LPD0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 Description Interrupt enable flags Interrupt request flags Bit0-2: Timer0 Mode register Bit0-2: Timer1 Mode register Timer0 load/counter register nibble Timer0 load/counter register high nibble Timer1 load/counter register nibble Timer1 load/counter register high nibble PORTA PORTB PORTC PORTD Enable Control (LPD3 0101: Enable (Default); 1010: Disable Bonding option Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit0: PA.1, PA.2 Alarm output Bit1: HEAVY LOAD Mode Bit2: Bit3: segment output Alarm Envelope Control Bit0: change duty duty, bias Reserved Data Pointer Data Pointer indirectly address data memory. Pointer address located register (3-bits) (4-bits). addressing range have locations. Pseudo index address (INX) used read write Data memory, then address bit9-bit0 comes from DPH, DPL.
AEC3
AEC2
AEC1
AEC0 DUTY
SH66P12
System Register $0D: Address bond bond bond bond Remarks Bit0: Bonding option internal weak drive Bit1: Bonding option internal weak drive Power-on Pull Pull high
SH66P12 Bonding Option different bonding options possible user's needs. chip's program different program flows that will vary depending which bonding option used. readable contents will differ depending bonding.
SH66P12
System Register $13: Address Remarks Bit0: PA.1, PA.2 ALARM output Bit1: HEAVY LOAD Mode Bit2: Power Control Bit3: seg1 output ports PORTA.1, PORTA.2 port PORTA.1, PORTA.2 ALARM output Heavy Load HEAVY LOAD mode Seg1 output Seg1 output ports Power
LCDOFF
HEAVY LOAD Mode (HLM): This mode designed 32KHz crystal oscillator, that oscillation maintained noisy power environment. power might drop suddenly when ALARM driving speaker. designed control this power variation. consumption power will increase during mode, will affect oscillator. Note: needs about instruction cycles set-up oscillation 32.768KHz crystal oscillator. System Register (AEC): Address AEC3 AEC2 AEC1 AEC0 envelope envelope envelope envelope envelope Remarks ALARM envelope control Power
Default carrier frequency 4KHz. selected 2KHz code option. WRITE mode: controls envelope selection. READ mode read current envelope waveforms. Below ALARM functional block equivalent circuit diagram. activate ALARM function, first switch ALARM OUTPUT mode. After setting equal then proper envelope. When data writes into AEC, envelope counter will synchronized same time. programmer read back envelope from register make pattern changes needed programmer. Read operation will affect alarm output waveform.
Sound Mixer 16Hz
Option setting 4KHz 2KHz OSCI OSCO Option setting 32KHz 262KHz
SH66P12
programming alarm waveform shown below:
16Hz
OUTPUT
System Register $15: Address Driver driver contains controller, voltage generator, common signal pins, segment driver pins. There different driving modes that programmable, duty bias, other duty bias. Driving mode controlled register $15H power-on status duty, bias. controller consists display data duty generator. data dual port that transfers data segment pins automatically without program control. segment also used output ports, selected bit3 system register $13H. When segments output ports, data written same address (300H 303H). used data memory needed. When "STOP" instruction executed, will turned off, data same before executing "STOP" instruction. Configuration area: When segments used output ports: Address COM4 300H 301H 302H 303H COM3 COM2 COM1 DATA_BIT DATA_BIT DATA_BIT DATA_BIT DUTY Description Bit0: duty control. driver duty, bias driver duty, bias Power
SH66P12
When segments used segment outputs: Address COM4 300H 301H 302H 303H Segments Address COM4 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM3 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM2 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM1 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG1 SEG2 SEG3 SEG4 COM3 SEG1 SEG2 SEG3 SEG4 COM2 SEG1 SEG2 SEG3 SEG4 COM1 SEG1 SEG2 SEG3 SEG4
SH66P12
PORT SH66P12 pins. Each pins programmable. pins CMOS (Default) Open Drain code option. PORTA, PORTB, PORTC PORTD Each these ports contains pins. Port mapping address shown follows: Address Bit3 PORT PORT PORT PORT Bit2 PORT PORT PORT PORT Bit1 PORT PORT PORT PORT Bit0 PORT PORT PORT PORT
ports pull-high internally, weak drive. equivalent circuit below:
Timer SH66P12 8-bit timers. timer/counter following features: 8-bit up-counting timer/counter. Automatic re-loads counter. 8-bit prescaler. Interrupt overflow from $00. following simplified timer block diagram.
Fosc/4 PRE-SCALER Tosc SYNC 8-BIT COUNTER
Timer Load Register: Since register controls physical READ WRITE operations. Please follow these steps: Write Operation: nibble first; High nibble update counter Read Operation: High Nibble first; nibble followed.
(T1M)
Timer0 Timer1 Configuration Operation Both Timer0 Timer1 consist 8-bit write-only timer load register (TL0L, TL0H; TL1L, TL1H) 8-bit read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each them order digits high order digits. Writing data into timer load register (TL0L, TL0H; TL1L, TL1H) initialize timer counter. low-order digit should written first, then high-order digit. timer counter automatically loaded with contents load register when high order digit written counter counts overflow from $00.
Load Reg.
Load Reg.
8-bit timer counter Latch Reg.
SH66P12
Timer0 Interrupt timer overflow will generate internal interrupt request, when counter counts overflow from $00. interrupt enable flag enabled, then timer interrupt service routine will start. This also used wake from HALT mode. Timer mode register timer programmed several different prescaler ratios setting Timer Mode register (TM0, TM1). 8-bit counter prescaler output pulses. Timer Mode registers (TM0, TM1) 3-bit registers used timer control shown Table1 Table These mode registers select input pulse sources into timer. Table Timer0 Mode Register ($02) TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio
Clock Source System clock System clock System clock System clock System clock System clock System clock System clock
Table Timer1 Mode Register ($03) TM1.2 TM1.1 TM1.0 Prescaler Divide Ratio /211
Clock Source System clock System clock System clock System clock System clock System clock System clock System clock
SH66P12
Interrupt Four interrupt sources available SH66P12: External interrupt share with PA.0) Timer0 interrupt Timer1 interrupt Port's falling edge detection interrupt Interrupt Control Bits Interrupt Service: interrupt control flags mapped system register. They accessed tested program. Those flags cleared initialization chip reset. Address Bit3 IRQX Bit2 IET0 IRQT0 Bit1 IET1 IRQT1 Bit0 IRQP Remarks interrupt enable flags interrupt request flags
When interrupt request generated (IRQx interrupt will activated vector address will generated from priority corresponding interrupt sources. When interrupt occurs, flag will saved into stack memory jump interrupt service vector address. After interrupt occurs, interrupt enable flags (IEx) reset automatically, when IRQx again, interrupt will activated vector address will generated from priority corresponding interrupt sources. Interrupt Servicing Sequence Diagram:
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
Interrupt Nesting: During SH6610C interrupt service, user enable INTERRUPT enable flag before returning from interrupt. servicing sequence diagram shows next interrupt next nesting interrupt occurrences. interrupt request ready instruction execution enable, then interrupt will start immediately after next instruction executions. However, instruction instruction disables interrupt request enable flag, then interrupt service will terminated. External Interrupt External interrupt shared with bit0 PORTA. When bit3 system register (IEX) external interrupt will enabled, falling edge signal PA.0 will generate external interrupt. (Note: while external interrupt enabled, writing bit0 PORTA will generate external interrupt). System Clock SH66P12 clock source. 32.768KHz crystal 262KHz determined code option. generates basic clock pulses that provide system clock supply on-chip peripherals (TIMER0, TIMER1, LCD).
SH66P12
Initial State
There types system reset. Hardware reset input Power reset Power Detection reset Hardware Program counter Data memory Timer counter Timer load register Interrupt Enable Flags Interrupt Request Flags [3:0] After power-on reset $000 Undefined Undefined Undefined 0101
Code option
Oscillator Type: 32.768KHz crystal (Default) 262KHz Alarm Carrier Frequency: 4KHz (Default) 2KHz Reset Pull-up Resistor: Disable Pull-up resistance (Default) Enable Pull-up resistance SH6612/UM6410 Body Option: SH6612 Body (Default) UM6410 Body Port Type: CMOS (Default) PMOS
SH66P12
Instructions
instructions cycle one-word instructions. characteristics memory-oriented operation. Arithmetic Logical Instruction Accumulator Type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx Function Flag Change Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
[3]; shift right
assembler ASM66 V1.0, EORIM mnemonic EORI. However, EORI same operation identical with EORIM. true ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function Decimal adjust Decimal adjust Flag Change
SH66P12
Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx Function Flag Change
Control Instruction Mnemonic CALL RTNW RTNI HALT STOP TJMP Where, Program counter Accumulator Complement accumulator Carry flag Data memory page Stack Table Branch Register Immediate data Logical exclusive Logical Logical bank Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-PC8) (TBR) Function (Not include hhhh; llll Flag Change
CY;PC
Operation
SH66P12
Absolute Maximum Rating*
Supply Voltage -0.3V 7.0V Input Voltage -0.3V VDD+ 0.3V Operating Ambient Temperature -10°C 60°C Storage Temperature -55°C 125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device under these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 3.0V, 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Standby Current Standby Current Input High Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Lighting Symbol ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 ILCD Min. Typ. Max. Unit output pins unload execute instruction output pins unload (HALT mode) exclude current output pins unload (STOP mode) exclude current PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC (IOH 15µA) PORTA, PORTB, PORTC (IOL 300µA) (set PA.1and PA.2 ALARM output (set PA.1and PA.2 ALARM output SEGx, 3µA, SEG1 output port (for reference only) SEGx, 3µA, SEG1 output port (for reference only) COMx, (for reference only) COMx, (for reference only) HALT mode Conditions
SH66P12
Electrical Characteristics (VDD 5.0V, 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Standby Current Standby Current Input High Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Lighting Note: Operation frequency ISB1 ISB1X (Frequency/32.768KHz) ISB1 Operation frequency IOPX (Frequency/32.768KHz) IOP, ISB1 ISB2 IOPX ISB1X ISB1 ISB2X ISB1 Symbol ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 ILCD 19.5 23.0 Min. Typ. Max. Unit output pins unload execute instruction output pins unload (HALT mode) exclude current output pins unload (STOP mode) exclude current PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC (IOH 15µA) PORTA, PORTB, PORTC (IOL 300µA) (set PA.1and PA.2 ALARM output (set PA.1and PA.2 ALARM output SEGx, 3µA, SEG1 output port (for reference only) SEGx, 3µA, SEG1 output port (for reference only) COMx, (for reference only) COMx, (for reference only) HALT mode Conditions
SH66P12
Circuitry (GND 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter LPD-detected Voltage Symbol VLPD Min. Typ. Max. Unit Condition
Characteristics (VDD 3.0V, 25°C, FOSC 32.768KHz unless otherwise specified)
Parameter Oscillation Start Time Halt Time Stop Time Frequency Stability Frequency Variation Symbol TSTT THTT TSPT Min. Typ. Max. Unit reduces Isb1 after instruction executing reduces Isb2 after instruction executing |F(3.0)-F(2.4)|/F(3.0), crystal oscillator (for reference only) (for reference only) Conditions
Characteristics (VDD 3.0V, 25°C, FOSC= 262KHz, unless otherwise specified)
Parameter Oscillation Start Time Halt Time Stop Time Frequency Stability Frequency Variation Symbol TSTT THTT TSPT Min. Typ. Max. Unit reduces Isb1 after instruction executing reduces Isb3 after instruction executing F(3.0)-F(2.4)/F(3.0), oscillator (for reference only) variation caused process variation (for reference only) Conditions
Typical oscillator Resistor Frequency: (for reference only)
1600 1400 1200 1000
3.0V 5.0V
(KHz)
SH66P12
Timing Waveform
duty, bias waveform
Select Unselect Light Unlight
COMX
SEGX
15.625ms COM4 VDD3 COM3 COM1 VDD2 VDD1 VDD3 COM2 COM1 COM2 VDD2 VDD1 VDD3 COM3 VDD2 VDD1 VDD3 COM4 VDD2 VDD1 SEGn+1 SEGn SEGn VDD3 VDD2 VDD1 SEGn+1 VDD3 VDD2 VDD1 VDD3 VDD2 VDD1 -VDD1 -VDD2 -VDD3 3.9ms
COM4 SEGn
SH66P12
duty, bias waveform
Select Unselect Light Unlight
11.7ms 3.9ms COM3 COM2 COM1 COM2 VDD2 COM1 VDD1 VDD2 VDD1 SEGn+2 VDD2 VDD1 SEGn+1 COM4 SEGn SEGn VDD2 VDD1 VDD2 VDD1
COM3
SEGn+1
VDD2 VDD1
COM1 SEGn
VDD2 VDD1 -VDD2 -VDD2
waveform
Heavy load
more
SH66P12
Application Circuits (for reference only)
SH66P12 chip substrate connects system ground. OSC: 262K (code option) LCD: duty, bias PORTA
bias
RESET
SH66P12
OSCI PORTA TEST
OSC: 32.768KHz crystal (code option) LCD: duty, bias PORTB PORTA.0: external interrupt PORTA.1, PORTA.2: ALARM output (carrier frequency: 2KHz 4KHz code option)
bias
RESET PORTA.0 PORTA.1 PORTA.2 OSCI
SH66P12
OSCO TEST
32768Hz
BUZZER
SH66P12
Application Circuits (continued)
OSC: 32.768KHz crystal (code option) LCD: duty, bias PORTB.1 Output When higher than VLCD, reducing VDD1 regulate voltage.
bias
VDD1 RESET OSCI
SH66P12
PORTB.1 TEST OSCO
32768Hz
VDD1
SH66P12
Bonding Diagram
SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 COM3 COM4 OSCI OSCO PORTD3 PORTD2 PORTD1 PORTD0 PORTC3 PORTC2 PORTC1 PORTC0 PORTB3 1970µm
SH66P12
1890µm
Substrate connects GND. bonding wire with diameter 1.0mil recommended. Unit: Designation SEG2 SEG1 TEST RESET PORTA0 PORTA1 PORTA2 PORTA3 PORTB0 PORTB1 PORTB2 PORTB3 PORTC0 PORTC1 PORTC2 PORTC3 PORTD0 PORTD1 PORTD2 PORTD3 OSCO OSCI COM4 -679.50 -563.75 -425.25 -286.75 -164.05 -164.05 -27.00 93.00 213.00 333.00 453.00 573.00 693.00 818.75 818.75 818.75 818.75 818.75 818.75 818.75 818.75 818.75 713.75 818.75 818.75 818.75 818.75 -852.50 -852.50 -852.50 -852.50 -747.50 -852.50 -852.50 -852.50 -852.50 -852.50 -852.50 -852.50 -852.50 -852.50 -722.50 -597.50 -477.55 -357.55 -237.55 -117.55 2.45 122.45 259.90 259.90 379.90 499.90 629.90 Designation COM3 COM2 COM1 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 818.75 688.75 563.75 438.75 313.75 188.75 63.75 -61.25 -186.25 -311.25 -436.25 -561.25 -686.25 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 -818.75 759.05 857.50 857.50 857.50 857.50 857.50 857.50 857.50 857.50 857.50 857.50 857.50 857.50 747.50 617.50 492.50 370.00 250.00 130.00 10.00 -110.00 -230.00 -350.00 -470.00 -592.50 -722.50 -854.10
SH66P12
Ordering Information
Part SH66P12H Package CHIP FORM

4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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