4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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SH66L10
4-bit Microcontroller with Driver
SH6610C-based single-chip 4-bit microcontroller with driver ROM: 2048 bits RAM: bits (data memory) Operation Voltage Range: 1.2V 1.7V CMOS pins (PORTC, switch segment) level subroutine nesting (including interrupts) 8-bit timers with pre-divider circuit Oscillator warm-up timer priority interrupt sources: External interrupt (falling edge) Timer0 interrupt Timer1 interrupt PortB PortC interrupt (falling edge) Clock source: 32.768KHz crystal 131K (type selected code option) Instruction cycle time: 4/32.768KHz 122µs) 32.768KHz crystal 4/131KHz 31µs) 131KHz driver: (1/4 duty, bias duty, bias, segment shared with PORTC, Built-in voltage doubler tripler charge pump circuit Built-in alarm generator (carrier frequency: 2KHz 4KHz. Selected code option) power operation modes HALT STOP mode power consumption Bonding option multi-code software Available CHIP FORM
General Description
SH66L10 single-chip microcontroller integrated with SH6610C core, SRAM, timer, alarm generator, driver, port, voltage pump program ROM.
Configuration
SEG25 SEG26 PORTC0/SEG27 PORTC1/SEG28 PORTC2/SEG29 PORTC3/SEG30 PORTD0/SEG31 PORTD1/SEG32 PORTD2/SEG33 PORTD3/SEG34 PORTA0 PORTA1 PORTA2 PORTA3 PORTB0 PORTB1
SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM4 COM3 COM2 COM1
SH66L10
V2.0
SH66L10
Block Diagram
(2048
TEST OSCI
(256
OSCO
8-BIT TIMER PORTB.0 PORTC (SEG27-30) PORTD (SEG31-34) PORTA.0 (INT) PORTA.1(BD) PORTA.2 (BD) PORTA.3
CORE
PORTS (3*4)
PORTA EXTERNAL
RESET
COMMON DRIVERS
COM1 COM4
ALARM GENERATOR
SEGMENT DRIVERS
SEG1 SEG26
VOLTAGE DOUBLER CHARGE BUMP CIRCUIT
CUP1 CUP2
Description (Total pads mask type)
56,1 Designation SEG1 COM1 VP1, CUP1 TEST RESET OSCO OSCI PORTA0 PORTB0 PORTC0 PORTD0 Description Segment signal output display Common signal output display Power supply driver Connection voltage doubler capacitor Test internally pull-down. connect user) reset input Power supply Bonding option, internally pull-low Bonding option, internally pull-high Ground Oscillator output pin, connected crystal oscillator Oscillator input pin, connected crystal external resistor programmable I/O, PA.0 could external interrupt input PA.1, PA.2 could buzzer output PA.1 (BD), PA.2 programmable I/O, vector interrupt (active falling edge) programmable I/O, Vector interrupt (active falling edge) Shared with SEG27 programmable I/O. shared with SEG31
SH66L10
Functional Description
contains following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, DPL), Stack. 1.1. (Program Counter) Program Counter used address program ROM. consists 11-bits: Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). program counter normally increases (+1) with every execution instruction except following cases: When executing jump instruction (such JMP, BA0, BNC), When executing subroutine call instruction (CALL), When interrupt occurs, When chip INITIAL RESET mode. program counter loaded with data corresponding each instruction. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment addition/subtraction (DAA, DAS) Logic operations (AND, EOR, ANDIM, EORIM, ORIM) address 2048 words bits program area from $000 $7FF. There area from address through that reserved special interrupt service routines, such starting vector address. Address 000H 001H 002H 003H 004H Instruction Instruction Instruction Instruction Instruction Instruction Remarks Jump RESET service routine Jump External interrupt service routine Jump TIMER0 service routine Jump TIMER1 service routine Jump service routine (PORTB) Decision (BA0, BA1, BA2, BA3, BNZ, BNC) Logic Shift (SHR) Carry Flag (CY) holds overflow which arithmetic operation generates. During interrupt servicing call instruction, carry flag pushed into stack retrieved back from stack RTNI instruction. unaffected RTNW instruction. 1.3. Accumulator Accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transfer between accumulator system register data memory performed. 1.4. Stack group registers used save contents (10-0) sequentially with each subroutine call interrupt. organized into bits levels. saved levels maximum allowed subroutine calls interrupts. contents Stack returned sequentially with return instructions (RTNI/RTNW). stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceed bottom stack will shifted out.
*JMP instruction replaced instruction. Built-in contains general-purpose data memory, RAM, system register. following memory allocation map: $000 $01F: System register $020 $11F: Data memory (256 bits, divided into banks) $300 $321: space bits)
SH66L10
Configuration System Register: Address IRQX T0L.3 T0H.3 T1L.3 T1H.3 PA.3 PB.3 PC.3 PD.3 TBR.3 INX.3 DPL.3 AEC3 PPULL PACR.3 PBCR.3 PCCR.3 PDCR.3 IET0 IRQT0 T0M.2 T1M.2 T0L.2 T0H.2 T1L.2 T1H.2 PA.2 PB.2 PC.2 PD.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 LCDOFF AEC2 O/S2 PACR.2 PBCR.2 PCCR.2 PDCR.2 IET1 IRQT1 T0M.1 T1M.1 T0L.1 T0H.1 T1L.1 T1H.1 PA.1 PB.1 PC.1 PD.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 AEC1 O/S1 PACR.1 PBCR.1 PCCR.1 PDCR.1 IRQP T0M.0 T1M.0 T0L.0 T0H.0 T1L.0 T1H.0 PA.0 PB.0 PC.0 PD.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 AEC0 PACR.0 PBCR.0 PCCR.0 PDCR.0 Remarks Interrupt enable flags Interrupt request flags Bit0-2: Timer0 Mode register Bit0-2: Timer1 Mode register Timer0 load counter register nibble Timer0 load counter register high nibble Timer1 load counter register nibble Timer1 load counter register high nibble PORTA PORTB PORTC PORTD Reserved Bit0, Bonding option Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit0: PA.1, PA.2 Alarm Bit1: HEAVY LOAD Mode Bit2: Alarm Envelope Control Bit1: PORTC segment output Bit2: PORTD segment output Bit3: Port pull-up control Reserved Reserved Reserved Reserved Reserved PORTA output port PORTB output port PORTC output port PORTD output port Reserved Power 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
SH66L10
System Register Address $0DH bond bond bond bond Remarks Bit0: Bonding option internal weak drive Bit1: Bonding option internal weak drive Power-on Pull Pull high
SH66L10 Bonding Option different bonding options possible user's needs. chip's program different program flows that will vary depending which bonding option used. readable contents will differ depending bonding.
SH66L10
System Register Address LCDOFF Remarks Bit0: PA.1, PA.2 ALARM output Bit1: heavy load mode Bit2: Power Control PORTA.1, PORTA.2 port PORTA.1, PORTA.2 ALARM output heavy load HEAVY LOAD mode signal pump signal Power
HEAVY LOAD Mode (HLM): This mode designed 32KHz crystal oscillator, that oscillation maintained noisy power environment. power might drop suddenly when ALARM driving speaker. designed control this power variation. consumption power will increase during mode, will affect oscillator. Notice: LCDOFF (system register bit2) will when reset, display will disabled. pump circuit after power reset. When LCDOFF (system register bit2) cleared pump circuit will turn will turns only after receiving "STOP" instruction. LCDOFF disables display output only, won't turn pump circuit. When SH66L10 runs into STOP mode, pump circuit turns automatically. user should turn pump (set LCDOFF after next wake Example:
Power pump Display (sets LCDOFF sets bias
Starts pump circuit turns display. Save total current when only solar battery. also canceled when system back-up battery.
HALT pump starts Wakes after least 50ms Sets Display sets LCDOFF pump (whatever display off) Sets Display sets LCDOFF
pump Wake RESET other INT)
sets LCDOFF only disable display, won't turn pump.
STOP (Pump turns automatically)
SH66L10
System Register Address AEC3 AEC2 AEC1 AEC0 Remarks ALARM envelope control envelope envelope envelope envelope envelope Power
Default carrier frequency 4KHz. selected 2KHz code option. WRITE mode: controls envelope selection. READ mode read current envelope waveforms. Below ALARM functional block equivalent circuit diagram. activate ALARM function, first switch ALARM OUTPUT mode. After setting then proper envelope. When data writes AEC, envelope counter will synchronized. programmer read back envelope from register make pattern changes needed programmer. Read operation will affect alarm output waveform.
Sound Mixer 16Hz
code option OSCI OSCO code option 131K
programming alarm waveform shown below:
16Hz
OUTPUT
SH66L10
System Register Address PPULL Driver driver contains controller, voltage generator, common signal pins, segment driver pins. There different driving modes. duty bias, other duty bias (COM4 same COM1). Driving mode selected code option, controller consists display data duty generator. data dual port that transfers data segment pins automatically without program control. Configuration Area: (Segments duty) Address COM4 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Address COM4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 PORTC, PORTD used SEG27 selected bit2 bit1 system register When used ports, data does affect input output data. Also, when used output, data won't affect output. used data memory needed. When "STOP" instruction executed, display output pump circuit turned off, data same before executing "STOP" instruction. When off, both COMMON SEGMENT output low. O/S2 O/S1 PORTC port PORTC segment27 PORTD ports PORTD segment31 Description Power 0000
SH66L10
Configuration Area: (Segments duty) Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Address COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
Connection Diagram
VDD=1.5V, 4.5V LCD, duty, 1/3bias
CUP1 CUP2 0.1uF 0.1uF 0.1uF VDD=1.5V
VDD=1.5V, LCD, duty, 1/2bias
CUP1 CUP2 0.1uF VDD=1.5V
0.1uF (3V) (3V)
LOGIC CIRCUIT
(3V) (4.5V)
LOGIC CIRCUIT
Notice: pump circuit frequency 4KHz, 2KHz (selected code option). When using small panel, user select 2KHz pump frequency save power. When using large panel, user select 4KHz pump frequency have more power supply ability use. duty bias selected code option.
SH66L10
duty, bias Waveform (VDD 1.5V, 4.5V,
Select COMX SEGX Select Light SEGX Unselect Unlight Unlight Unlight Unselect
15.625ms COM4 COM1 COM3 COM2 COM2 COM1 COM3 COM4 SEGn+1 SEGn SEGn 3.9ms
SEGn+1 COM4 SEGn -VDD -VP2 -VP1
SH66L10
duty, bias Waveform (VDD 1.5V,
Select Unselect
COMX
SEGX Select Light SEGX Unselect Unlight Unlight Unlight
11.7ms 3.9ms COM3 COM1 COM2 COM2 COM1 SEGn+2 COM3 COM4 SEGn+1 SEGn SEGn
SEGn+1
COM1 SEGn -VDD -VP2
SH66L10
Port SH66L10 CMOS ports: PORTA, PORTB, PORTC PORTD. Each pins contains pull-up which controlled program. PORT control register (PACR, PBCR, PCCR, PDCR) controls ON/OFF buffer output buffer. These ports accessed through read/write system register. user output value port time. PORTA,
register PULL PULL PMOS PULL PULL PMOS
PORT CONTROL REGISTER PORTA1, PORT DATA REGISTER
PORT CONTROL REGISTER PORTA0, PORT DATA REGISTER
DATA INPUT
RD-INPUT
DATA INPUT
RD-INPUT
ALARM OUTPUT PORTA1, (for reference only) PORTA0, (for reference only)
O/S2 register O/S1 register PULL PULL PMOS PULL PULL PMOS
PORT CONTROL REGISTER PORTB PORT DATA REGISTER
PORT CONTROL REGISTER PORT DATA REGISTER
PORTD,
DATA INPUT
RD-INPUT
DATA INPUT SEGMENT DRIVER
RD-INPUT
PORTB (for reference only)
PORTC, (for reference only)
When (system register bit0), PA.1 PA.2 used alarm output. When O/S1 (system register bit1) O/S2 (system register bit2) PORTC PORTD used SEGMENT outputs, writing data PC.X (system register 0AH), PD.X (system register 0BH) won't affect output data. Controlling Pull-up These ports contain pull-up controlled program. System register bit3 (PPULL) simultaneously controls ON/OFF pull-up MOS. Pull also controlled port data registers (PA, each port. (Write could turn pull-up MOS.) Thus pull-up turned ON/OFF individually. Port Interrupt PORTB, PORTC interrupt (falling edge) controlled Port register. This means that interrupt request (IEx port from high low) been touched that condition other port bits high level whenever port output input. When PORTC used outputs (O/S1 PORTC interrupt disabled. External PortA.0 shared external interrupts (active low).
SH66L10
Timer SH66L10 8-bit timers. Their operation counts timers consist 8-bit counter 8-bit preload register.
Fosc/4 PRE-SCALER Tosc SYNC 8-BIT COUNTER
low-order digit should written first, then high-order digit. timer counter automatically loaded with contents load register when high order digit written count overflow occurs. timer overflow will generate interrupt interrupt enable flag set. timer programmed several different system clock sources setting Timer Mode register (TM0,TM1). Timer Load Register: Since register controls physical READ WRITE operations, please follow these steps: Write Operation: nibble first; High nibble update counter Read Operation: High Nibble first; nibble followed.
timers provide following functions: Programmable interval timer function. Reading counter value.
Timer0 Timer1 Configuration Operation Both Timer0 Timer1 consists 8-bit write-only timer load register (TL0L, TL0H; TL1L, TL1H), 8-bit read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each them order digits high order digits. timer counter initialized writing data into timer load register (TL0L, TL0H; TL1L, TL1H).
Timer Mode Register
Load Reg.
Load Reg.
8-bit timer counter
Latch Reg.
8-bit counter counts prescaler overflow output pulses. Timer Mode registers (TM0, TM1) 4-bit registers used timer control shown table1 table These mode registers input pulse sources into timer. Table Timer0 Mode Register ($02) TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio
Table Timer1 Mode Register ($03) Clock Source Fosc Fosc Fosc Fosc Fosc Fosc Fosc Fosc TM1.2 TM1.1 TM1.0 Prescaler Divide Ratio
Clock Source Fosc Fosc Fosc Fosc Fosc Fosc Fosc Fosc
SH66L10
Interrupt Four interrupt sources available SH66L10: External interrupt share with PA.0) Timer0 interrupt Timer1 interrupt Port's falling edge detection interrupt
Configuration System Register $00: Address IET0 IET1 Remark Interrupt enable flags
External Interrupt External interrupt shared with bit0 PORTA. When bit3 system register (IEX) external interrupt will enabled, falling edge signal PA.0 will generate external interrupt. (Note: while external interrupt enabled, writing bit0 PORTA will generate external interrupt) Timer0, Timer1 Interrupt, Port Interrupt Ports input clock Timer0 Timer1 based clock. programming Timer interrupt, Port interrupts ports refer SH6610C SPEC Interrupt Servicing Sequence Diagram:
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
Interrupt Nesting: During SH6610C interrupt service, user enable INTERRUPT enable flag before returning from interrupt. servicing sequence diagram shows next interrupt next nesting interrupt occurrences. interrupt request ready instruction execution enabled, then interrupt will start immediately after next instruction executions. However, instruction instruction disables interrupt request enable flag, then interrupt service will terminated. System Clock SH66L10 clock source. OSCI 32.768KHz crystal 131KHz determined code option. generates basic clock pulses that provide system clock on-chip peripherals (TIMER0, TIMER1, LCD).
SH66L10
Instructions
instructions cycle one-word instructions. Their characteristics memory-oriented operation. Arithmetic Logical Instruction Accumulator Type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx Function Flag Change Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
AC[3]; AC[0] shift right
assembler ASM66 V1.0, EORIM memonic EORI. However, EORI identical operation EORIM. same true ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function AC;Mx Decimal adjust add. AC;Mx Decimal adjust sub. Flag Change
SH66L10
Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx Function Flag Change
Control Instruction Mnemonic CALL RTNW RTNI HALT STOP TJMP Where, Program counter Accumulator Complement accumulator Carry flag Data memory page Stack Table Branch Register (bbb) Immediate data Logical exclusive Logical Logical bank Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-PC8) (TBR) (AC) Function AC(0) AC(1) AC(2) AC(3) (Not include hhhh; llll Flag Change
Operation
SH66L10
Absolute Maximum Ratings*
Supply Voltage -0.3V +3.0V Input Voltage. -0.3V 0.3V Operating Ambient Temperature +70°C Storage Temperature -55°C +125°C
*Comments
Stresses levels above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 1.5V, 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Standby Current Standby Current Input High Voltage Input High Voltage Input Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Pull-up Resistor Lighting Symbol ISB1 ISB2 VIH1 VIH2 VIL1 VIL2 VOH1 VOL1 VOH2 VOL2 VOH4 VOL4 VOH5 VOL5 ILCD 0.85 Min. Typ. Max. 0.15 Unit output pins unload execute instruction, exclude Alarm current output pins unload (HALT mode), exclude current. (Not heavy load mode) output pins unload (STOP mode), PORTA, PORTB, PORTC, PORTD OSCI (Driven external clock)
RESET TEST (schmitt trigger input)
Conditions
PORTA, PORTB, PORTC, PORTD OSCI (Driven external clock)
RESET TEST (schmitt trigger input)
PORTB, PORTA.0, (IOH -8µA) PORTB, PORTA.0, (IOL= 0.3mA) (PA.1, PA.2), -0.3mA (PA.1, PA.2 0.3mA SEGx, -3µA SEGx, COMx, -8µA COMx, PULL-UP resistor (VOH -10µA) panel loaded. pump frequency
SH66L10
Electrical Characteristics (VDD 1.5V, 25°C, FOSC 131KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Standby Current Standby Current Reset Current Input High Voltage Input High Voltage Input Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Pull-up Resistor Lighting Symbol ISB1 ISB2 IREST VIH1 VIH2 VIL1 VIL2 VOH1 VOL1 VOH2 VOL2 VOH4 VOL4 VOH5 VOL5 ILCD 0.85 Min. Typ. Max. 0.15 Unit output pins unload execute instruction, exclude Alarm current output pins unload (HALT mode) exclude current. (Not heavy load mode) output pins unload (STOP mode), off, current Reset current PORTA, PORTB, PORTC, PORTD OSCI (Driven external clock)
RESET TEST (schmitt trigger input)
Conditions
PORTA, PORTB, PORTC, PORTD, OSCI (Driven external clock)
RESET TEST (schmitt trigger input)
PORTB, PORTA.0, (IOH -8µA) PORTB, PORTA.0, (IOL= 0.3mA) (PA.1, PA.2), -0.3mA (PA.1, PA.2 0.3mA SEGx, -3µA SEGx, COMx, -8µA COMx, PULL-UP resistor (VOH -10µA) panel loaded. pump frequency
Characteristics (VDD 1.5V, 25°C, unless otherwise specified) Parameter Oscillation Start Time (Crystal) Frequency Variation(RC) Symbol TSTT Min. Typ. Max. Unit Fosc 32.768KHz Include supply voltage chip chip variation 131K Conditions
SH66L10
Application Circuits (for reference only)
SH66L10 chip substrate connects system ground. AP1: 1.5V OSC: 131K (code option) LCD: duty, bias, PORTD used segment. PORTA
Solar Battery
2200pF 0.1uF 0.1uF PORTA CUP1,
OSCI 500K 1.4M
SH66L10
PORTB,
RESET TEST
Code Option:
Addresses: $800 Body data: 0110 1010 0001 0000 (66L10) Addresses: $801 Data: CAPF 1D00 0000 0000 (Clock source) 32768 Crystal (default) 131K (Alarm carrier frequency) 4KHz (default) 2KHz (LCD Pump circuit frequency) 2KHz 4KHz (default) (Duty bias option) duty, bias (default) duty, bias
SH66L10
Bonding Diagram
SEG25 SEG26 PORTC0/SEG27 PORTC1/SEG28 PORTC2/SEG29 PORTC3/SEG30 PORTD0/SEG31 PORTD1/SEG32 PORTD2/SEG33 PORTD3/SEG34 PORTA0 PORTA1 PORTA2 PORTA3 PORTB0 PORTB1 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM4 COM3 COM2 COM1 2050µm
SH66L10
1770µm
Substrate connects Bonding wire with 1.0mil diameter recommended.
Location
Designation SEG25 SEG26 PORTC0 PORTC1 PORTC2 PORTC3 PORTD0 PORTD1 PORTD2 PORTD3 PORTA0 PORTA1 PORTA2 PORTA3 PORTB0 PORTB1 PORTB2 PORTB3 OSCO OSCI -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -760 -637.5 -517.5 -402.5 -402.5 -287.5 -172.5 -57.5 -57.5 757.5 637.5 517.5 402.5 287.5 172.5 57.5 -57.5 -172.5 -287.5 -402.5 -517.5 -637.5 -757.5 -900 -900 -900 -808 -900 -900 -900 -808 -900 Designation
RESET
unit: 57.5 172.5 287.5 402.5 517.5 637.5 637.5 517.5 -900 -900 -900 -900 -900 -900 -900 -757.5 -637.5 -517.5 -402.5 -287.5 -172.5 -57.5 57.5 172.5 287.5 402.5 517.5 637.5 757.5
TEST CUP1 CUP2 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14
SH66L10
Location (continued)
Designation SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 402.5 287.5 172.5 57.5 -57.5 -172.5 Designation SEG21 SEG22 SEG23 SEG24 -287.5 -402.5 -517.5 -637.5
SH66L10
Ordering Information
Part SH66L10H Package CHIP FORM
SH66L10
SPEC Change History:
Change code option $801 cancel invert selection 32kHz-oscillator source. (Page

4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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