COP8SBR9/COP8SCR9/COP8SDR9 8-Bit CMOS Flash Based Microcontroller with
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COP8SBR9/COP8SCR9/COP8SDR9 8-Bit CMOS Flash Based Microcontroller with Memory, Virtual EEPROM Brownout
COP8SBR9/COP8SCR9/COP8SDR9 8-Bit CMOS Flash Based Microcontroller with Memory, Virtual EEPROM Brownout
COP8SBR9/SCR9/SDR9 Flash based microcontrollers highly integrated COP8Feature core devices, with Flash memory advanced features including Virtual EEPROM, High Speed Timers, USART, Brownout Reset. This single-chip CMOS device suited applications requiring full featured, in-system reprogrammable controller with large memory EMI. same device used development, pre-production volume production with range COP8 software hardware development tools. Family features include 8-bit memory mapped architecture, in-system programmability (ISP), clock-doubled Devices included this datasheet: Device COP8SBR9 COP8SCR9 COP8SDR9 Flash Program Memory (bytes) (bytes) Brownout Voltage 2.7V 2.9V 4.17V 4.5V Brownout Pins Packages 44/68 PLCC 44/68 PLCC 44/68 PLCC Temperature -40°C +85°C -40°C +85°C -40°C +85°C operation with instruction cycle, dual clock operation reduced power consumption, Virtual EEPROM using Flash Memory store data, three multi-function 16-bit timer/counters (two with resolution), programmable idle timer with MIWU, USART with on-chip Baud Rate Generator, MICROWIRE/PLUSserial I/O, power saving HALT/IDLE modes, Schmitt trigger inputs, software selectable options, WATCHDOGtimer Clock Monitor, 2.7V-5.5V operation with Brownout Reset, 44/68 packages.
Features
kbytes Flash Program Memory with Security Feature Virtual EEPROM using Flash Program Memory kbyte volatile USART In-System Programmability Flash Memory Dual Clock Operation providing Enhanced Power Save Modes Thirteen multi-source vectored interrupts servicing: External Interrupt USART Idle Timer Three Timers (each with interrupts) MICROWIRE/PLUS Serial peripheral interface Multi-Input Wake Software Trap Idle Timer with programmable interrupt interval 8-bit Stack Pointer (stack RAM) 8-bit Register Indirect Data Memory Pointers True manipulation WATCHDOG Clock Monitor logic Software selectable options TRI-STATE Output/High Impedance Input Push-Pull Output Weak Pull Input Schmitt trigger inputs ports High Current I/Os Temperature range: -40°C +85°C Packaging: PLCC True In-System, Real time emulation full program debug offered MetaLink's Development Systems
Other Features
Three 16-bit timers: Timers operate high speed resolution) Processor Independent mode External Event counter mode Input Capture mode Brown-out Reset (COP8SBR9/SCR) Single supply operation: 2.7V-5.5V Quiet Design (low radiated emissions) Multi-Input Wake-up with optional interrupts MICROWIRE/PLUS (Serial Peripheral Interface Compatible) Clock Doubler operation from Oscillator
COP8is trademark National Semiconductor Corporation.
2000 National Semiconductor Corporation
DS101389
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COP8SBR9/COP8SCR9/COP8SDR9
Block Diagram
DS101389-1
Connection Diagrams
Plastic Chip Carrier
DS101389-3
DS101389-2
View Plastic Chip Package Package Number V68A
View Plastic Chip Package Package Number V44A
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COP8SBR9/COP8SCR9/COP8SDR9
Connection Diagrams
(Continued)
Pinouts 68-Pin Packages Port Type
Alt. MIWU Speed MIWU Speed MIWU MIWU MIWU MIWU MIWU MIWU WDOUT
System Emulation Mode
44-Pin PLCC
68-Pin PLCC
Input POUT Output Clock
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COP8SBR9/COP8SCR9/COP8SDR9
Connection Diagrams
Port RESET Type
(Continued)
Pinouts 68-Pin Packages (Continued) Alt. System Emulation Mode 44-Pin PLCC 68-Pin PLCC RESET
operation WDOUT controlled Option Register
Ordering Information
DS101389-4
FIGURE Part Numbering Scheme
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COP8SBR9/COP8SCR9/COP8SDR9
REDUCTION COP8SBR9/SCR9/SDR9 devices incorporate circuitry that guards against electromagnetic interference increasing problem today's microcontroller board designs. National's patented reduction technology offers clock circuitry, gradual turn-on output drivers (GTOs) internal smoothing filters, help circumvent many issues influencing embedded control designs. National achieved dB-20 reduction transmissions when designs have incorporated patented reducing circuitry. IN-SYSTEM PROGRAMMING VIRTUAL EEPROM device includes program boot that provides capability, through MICROWIRE/PLUS serial interface, erase, program read contents Flash memory. Additional routines included boot ROM, which called user program, enable user customize system software update capability MICROWIRE/ PLUS desired. Additional functions will copy blocks data between Flash Memory. These functions provide virtual EEPROM capability allowing user emulate variable amount EEPROM initializing nonvolatile variables from Flash Memory occasionally restoring these variables Flash Memory. contents boot have been defined National. Execution code from boot dependent state FLEX Option Register exit from RESET. FLEX zero, Flash Memory assumed empty execution from boot begins. further information FLEX bit, refer Section 4.5, Option Register. DUAL CLOCK CLOCK DOUBLER device includes versatile clocking system oscillator circuits designed drive crystal ceramic resonator. primary oscillator operates high speed MHz. secondary oscillator optimized operation 32.768 kHz. user can, through specified transition sequences (please refer Power Saving Features), switch execution between high speed speed oscillators. unused oscillator then turned minimize power dissipation. speed oscillator used, pins available general purpose bidirectional ports. operation will clock twice frequency selected oscillator high speed operation 65.536 speed operation). This doubled clock will referred this document `MCLK'. frequency selected oscillator will referred CKI. Instruction execution occurs tenth selected MCLK rate. TRUE IN-SYSTEM EMULATION On-chip emulation capability been added which allows user perform true in-system emulation using final production boards devices. This simplifies testing evaluation software real environmental conditions. user, merely providing standard connector which
bypassed jumpers final application board, provide software hardware debugging using actual production units. ARCHITECTURE COP8 family based modified Harvard architecture, which allows data tables accessed directly from program memory. This very important with modern microcontroller-based applications, since program memory usually EPROM, while data memory usually RAM. Consequently constant data tables need contained non-volatile memory, they lost when microcontroller powered down. modified Harvard architecture, instruction fetch memory data transfers overlapped with stage pipeline, which allows next instruction fetched from program memory while current instruction being executed using data memory. This possible with Neumann single-address architecture. COP8 family supports software stack scheme that allows user incorporate many subroutine calls. This capability important when using High Level Languages. With hardware stack, user limited small fixed number stack levels. INSTRUCTION today's 8-bit microcontroller application arena cost/ performance, flexibility time market several issues that system designers face attempting build well-engineered products that compete marketplace. Many these issues addressed through manner which microcontroller's instruction handles processing tasks. that's COP8 family offers unique code-efficient instruction that provides flexibility, functionality, reduced costs faster time market that today's microcontroller based products require. Code efficiency important because enables designers pack more on-chip functionality into less program memory space (ROM, Flash). Selecting microcontroller with less program memory size translates into lower system costs, added security knowing that more code packed into available program memory space. 1.6.1 Instruction Features COP8 family incorporates unique combination instruction features, which provide designers with optimum code efficiency program memory utilization. 1.6.2 Single Byte/Single Cycle Code Execution efficiency fact that majority instructions single byte variety, resulting minimum program space. Because compact code does occupy substantial amount program memory space, designers integrate additional features functionality into microcontroller program memory space. Also, majority instructions executed device single cycle, resulting minimum program execution time. fact, instructions single byte single cycle, providing greater code efficiency, faster code execution. 1.6.3 Many Single-Byte, Multi-Function Instructions COP8 instruction utilizes many single-byte, multifunction instructions. This enables single instruction accomplish multiple functions, such DRSZ, DCOR, JID, (Load) (Exchange) instructions with postincrementing post-decrementing, name just
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COP8SBR9/COP8SCR9/COP8SDR9
(Continued)
examples. many cases, instruction simultaneously execute many three functions with same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes external events jumps corresponding service routines (analogous CASE" statements higher level languages). LAID: (Load Accumulator-Indirect); Single byte look table instruction provides efficient data path from program memory CPU. This instruction used table lookup read entire program memory checksum calculations. RETSK: (Return Skip); Single byte instruction allows return from subroutine skips next instruction. Decision branch made subroutine itself, saving code. AUTOINC/DEC: These instructions memory pointers efficiently process block data (simplifying "FOR NEXT" other loop structures higher level languages). 1.6.4 Bit-Level Control Bit-level control over many microcontroller's ports provides flexible means ease layout concerns save board space. members COP8 family provide ability set, reset test individual data memory address space, including memory-mapped ports associated registers. 1.6.5 Register Three memory-mapped pointers handle register indirect addressing software stack pointer functions. memory data pointers allow option post-incrementing postdecrementing with data movement instructions (LOAD/ EXCHANGE). memory-mapped registers allow designers optimize precise implementation certain specific instructions. PACKAGING/PIN EFFICIENCY Real estate board configuration considerations demand maximum space efficiency, particularly given today's high integration small product form factors. Microcontroller users avoid using large packages needed. Large packages take valuable board space increases device cost, trade-offs that microcontroller designs afford. COP8 family offers wide range packages waste pins: 90.9% pins 44-pin package) devoted useful I/O.
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COP8SBR9/COP8SCR9/COP8SDR9
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage Total Current into (Source) -0.3V +0.3V
Total Current (Sink) Storage Temperature Range Protection Level
-65°C +140°C (Human Body Model)
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics
TABLE Electrical Characteristics (-40°C +85°C) Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note Supply Current (Note High Speed Mode 3.33 Dual Clock Mode MHz, Speed 3.33 MHz, Speed Speed Mode Speed HALT Current with Disabled (Note High Speed Mode Dual Clock Mode Speed Mode Idle Current (Note High Speed Mode 3.33 Dual Clock Mode MHz, Speed 3.33 MHz, Speed Speed Mode Speed Supply Current Feature High Brownout Trip Level (BOR Enabled) Brownout Trip Level (BOR Enabled) Input Levels (VIH, VIL) Logic High Logic Internal Bias Resistor Crystal/Resonator Oscillator Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis 5.5V 5.5V, 0.16 0.25 -210 5.5V 5.5V 4.17 4.28 2.78 5.5V, 4.5V, 5.5V, 4.5V, 5.5V, 5.5V, MHz, Speed 5.5V, MHz, Speed 5.5V 5.5V, 4.5V, 14.7 5.5V, 4.5V, 14.7 Peak-to-Peak Conditions Units
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COP8SBR9/COP8SCR9/COP8SDR9
Electrical Characteristics
Parameter Output Current Levels Outputs Source Sink (Note Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) (Note TRI-STATE Leakage Allowable Sink Current (Note Maximum Input Current without Latchup (Note Retention Voltage, HALT Mode) Input Capacitance Load Capacitance Voltage Force Execution from Boot Input Current when Input (Note Flash Memory Data Retention (Note Flash Memory Number Erase/Write Cycles (Note
(Continued)
TABLE Electrical Characteristics (-40°C +85°C) (Continued) Conditions Units
4.5V, 3.8V 2.7V, 1.8V 4.5V, 1.0V 2.7V, 0.4V 4.5V, 3.8V 2.7V, 1.8V 4.5V, 3.8V 2.7V, 1.8V 4.5V, 1.0V 2.7V, 0.4V 5.5V
1000 cycles
(Note (Note 11V, 5.5V 25°C Table Typical Flash Memory Endurance
TABLE Electrical Characteristics (-40°C +85°C) Parameter Instruction Cycle Time (tC) Crystal/Resonator Output Propagation Delay (Note Flash Memory Page Erase Time 4.5V 5.5V 2.7V 0.35 Conditions Units
4.5V
2.2k, 4.5V 5.5V 2.7V 4.5V Table Typical Flash Memory Endurance
Flash Memory Mass Erase Time Frequency MICROWIRE/PLUS Slave Mode MICROWIRE/PLUS Setup Time (tUWS) (Note MICROWIRE/PLUS Hold Time (tUWH) (Note MICROWIRE/PLUS Output Propagation Delay (tUPD) Input Pulse Width (Note Interrupt Input High Time Interrupt Input Time
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COP8SBR9/COP8SCR9/COP8SDR9
Electrical Characteristics
Parameter Timer Input High Time Timer Input Time Timer Input High Time (Note Timer Input Time (Note Output Pulse Width Timer Output High Time Timer Output Time USART Time when using External USART Frequency when being Driven Internal Baud Rate Generator Reset Pulse Width
instruction cycle time. Note Maximum rate voltage change must
(Continued)
TABLE Electrical Characteristics (-40°C +85°C) (Continued) Conditions periods
V/ms.
Units MCLK MCLK
Note Supply IDLE currents measured with driven with square wave Oscillator, driven 180° phase with CKI, inputs connected outputs driven connected load. Note HALT mode will stop from oscillating. Measurement HALT done with device neither sourcing sinking current; with G2-G5 programmed outputs driving load; outputs programmed driving load; inputs tied VCC; converter clock monitor disabled. Parameter refers HALT mode entered setting Port data register. Note Pins RESET designed with high voltage input network. These pins allow input voltages pins will have sink current when biased voltages (the pins have source current when biased voltage below VCC). These pins will latch voltage pins must limited 14V. WARNING: Voltages excess will cause damage pins. This warning excludes transients. Note output propagation delay referenced instruction cycle where output change occurs. Note Parameter characterized tested. Note Reserved. Note timer high speed mode, minimum time MCLK. timer high speed mode, minimum time Note Absolute Maximum Ratings should exceeded.
DS101389-5
FIGURE MICROWIRE/PLUS Timing
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COP8SBR9/COP8SCR9/COP8SDR9
Descriptions
COP8SBR9/SCR9/SDR9 structure enables designers reconfigure microcontroller's functions with single instruction. Each individual independently configured output low, output high, input with high impedance input with weak pull-up device. typical example pins keyboard matrix input lines. input lines programmed with internal weak pull-ups that input lines read logic high when keys open. With closure, corresponding input line will read logic zero since weak pull-up easily overdriven. When released, internal weak pull-up will pull input line back logic high. This eliminates need external pull-up resistors. high current options available driving LEDs, motors speakers. This flexibility helps ensure cleaner design, with less external components lower costs. Below general description available pins. power supply pins. pins must connected. clock input. This connected conjunction with CKO) external crystal circuit form crystal oscillator. Oscillator Description section. RESET master reset input. Reset description section. AVCC Analog Supply converter. should connected externally. This also resistor ladder converter used within converter. AGND ground converter. should connected externally. This also bottom resistor ladder converter used within converter. device contains bidirectional 8-bit ports 4-bit port (F), where each individual independently configured input (Schmitt trigger inputs ports output TRISTATE under program control. Three data memory address locations allocated each these ports. Each port three associated 8-bit memory mapped registers, CONFIGURATION register, output DATA register input register. (See memory various addresses associated with ports.) Figure shows port configurations. DATA CONFIGURATION registers allow each port individually configured under software control shown below:
CONFIGURATION Register DATA Register Port Set-Up Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output
Port 8-bit port. 44-pin device does offer Port unavailable pins terminated. read operation these unterminated pins will return unpredictable values. this device, associated Port Data Configuration registers should used. pins have Schmitt triggers inputs. Port draws power when unbonded. Port 8-bit Port. 44-pin device does offer Port unavailable pins terminated. read operation these unterminated pins will return unpredictable values. this device, associated Port Data Configuration registers should used. pins have Schmitt triggers inputs. Port draws power when unbonded. Port 4-bit Port. pins have Schmitt triggers inputs. 68-pin package fewer than eight Port pins, contains unbonded, floating pads internally chip. binary values read from these bits undetermined. application software should mask these unknown bits when reading Port register, only bit-access program instructions when accessing Port unconnected bits draw power only when they addressed (i.e., brief spikes). Port 8-bit port. G2-G5 bi-directional ports. always general purpose Hi-Z input. pins have Schmitt Triggers their inputs. serves dedicated WATCHDOG output with weak pull-up WATCHDOG feature selected Option register. general purpose WATCHDOG feature selected. WATCHDOG feature selected, Port configuration data register does have effect setup. serves dedicated output clock output. Since input only dedicated clock output pin, associated bits data configuration registers used special purpose functions outlined below. Reading data bits will return zeros. device will placed HALT mode writing Port Data Register. Similarly device will placed IDLE mode writing Port Data Register. Writing Port Configuration Register enables MICROWIRE/PLUS operate with alternate phase clock. configuration bit, high, enables clock start delay after HALT when clock configuration used. Config. Reg. Port CLKDLY Alternate Data Reg. HALT IDLE
Port 8-bit port. pins have Schmitt triggers inputs. 44-pin package does have full 8-bit port contains some unbonded, floating pads internally chip. binary value read from these bits undetermined. application software should mask these unknown bits when reading Port register, only bit-access program instructions when accessing Port These unconnected bits draw power only when they addressed (i.e., brief spikes). Port 8-bit port. pins have Schmitt triggers inputs.
following alternate features: Oscillator dedicated output (MICROWIRE/PLUS Serial Data Input) (MICROWIRE/PLUS Serial Clock) (MICROWIRE/PLUS Serial Data Output) (Timer I/O) (Timer Capture Input) WDOUT WATCHDOG and/or Clock Monitor WATCHDOG enabled, otherwise general purpose INTR (External Interrupt Input) through also used In-System Emulation.
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COP8SBR9/COP8SCR9/COP8SDR9
Descriptions
(Continued)
Port 8-bit port. L-pins have Schmitt triggers inputs. Port supports Multi-Input Wake feature eight pins. Port following alternate functions: Multi-input Walk-up (Timer Input) Multi-input Walk-up (Timer Input) Multi-input Walk-up (Timer Input) Multi-input Walk-up (Timer Input) Multi-input Walk-up and/or (USART Receive) Multi-input Walk-up (USART Transmit) Multi-input Walk-up and/or (USART Clock) (Low Speed Oscillator Output) Multi-input Walk-up (Low Speed Oscillator Input) Port 8-bit output port that preset high when RESET goes low. user more port outputs (except together order higher drive. Note: Care must exercised with operation. RESET, external loads this must ensure that output voltages stay above prevent chip from entering special modes. Also keep external loading less than 1000
DS101389-8
FIGURE Port Configurations Input Mode EMULATION CONNECTION Connection emulation system made connector which interrupts continuity RESET, signals between COP8 device rest target system shown Figure This connector designed into production board replaced jumpers signal traces when emulation longer necessary. emulator will replicate functions RESET. proper operation, connection should made device side emulator connector.
DS101389-6
FIGURE Port Configurations
DS101389-9
FIGURE Emulation Connection
DS101389-7
FIGURE Port Configurations Output Mode
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COP8SBR9/COP8SCR9/COP8SDR9
Functional Description
architecture device modified Harvard architecture. With Harvard architecture, program memory (Flash) separate from data store memory (RAM). Both Program Memory Data Memory have their separate addressing space with separate address buses. architecture, though based Harvard architecture, permits transfer data from Flash Memory RAM. REGISTERS 8-bit addition, subtraction, logical shift operation instruction (tC) cycle time. There registers: 8-bit Accumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer, which optionally post auto incremented decremented. 8-bit alternate address pointer, which optionally post auto incremented decremented. 8-bit Data Segment Address Register used extend lower half address range into data segments bytes each. 8-bit stack pointer, which points subroutine/ interrupt stack RAM). With reset initialized address Hex. decremented items pushed onto stack. points next available location stack. registers memory mapped with exception Accumulator Program Counter (PC). PROGRAM MEMORY program memory consists 32,768 bytes Flash Memory. These bytes hold program instructions constant data (data tables LAID instruction, jump vectors instruction, interrupt vectors instruction). program memory addressed 15-bit program counter (PC). interrupts device vector program memory location 00FF Hex. contents program memory read erased state. Program execution starts location after RESET. Return instruction executed when contains (hex), instruction execution will continue from Program Memory location 7FFF (hex). location 7FFF accessed instruction fetch, Flash Memory will return value This opcode INTR instruction will cause Software Trap. purpose erasing rewriting Flash Memory, organized pages bytes. DATA MEMORY data memory address space includes on-chip data registers, registers (Configuration, Data Pin), control registers, MICROWIRE/PLUS shift register, various registers, counters associated with timers USART (with exception IDLE timer). Data memory addressed directly instruction indirectly pointers. data memory consists 1024 bytes RAM. Sixteen bytes mapped "registers" addresses
Hex. These registers loaded immediately, also decremented tested with DRSZ (decrement register skip zero) instruction. memory pointer registers memory mapped into this space address locations respectively, with other registers being available general usage. instruction permits memory set, reset tested. registers (except memory mapped; therefore, bits register bits directly individually set, reset tested. accumulator bits also directly individually tested. Note: contents undefined upon power-up. DATA MEMORY SEGMENT EXTENSION Data memory address used memory mapped location Data Segment Address Register (S). data store memory either addressed directly single byte address within instruction, indirectly relative reference pointers (each contains single-byte address). This single-byte address allows addressing range locations from hex. upper this single-byte address divides data store memory into separate sections outlined previously. With exception register memory from address locations 00F0 00FF, memory memory mapped with upper single-byte address being equal zero. This allows upper single-byte address determine whether base address range (from 0000 00FF) extended. this upper equals (representing address range 0080 00FF), then address extension does take place. Alternatively, this upper equals zero, then data segment extension register used extend base address range (from 0000 007F) from XX00 XX7F, where represents bits from register. Thus 128-byte data segment extensions located from addresses 0100 017F data segment 0200 027F data segment etc., FF00 FF7F data segment 255. base address range from 0000 007F represents data segment
Figure illustrates register data memory extension used extending lower half base address range hex) into data segments bytes each, with total addressing range kbytes from XX00 XX7F. This organization allows total data segments bytes each with additional upper base segment bytes. Furthermore, addressing modes available data segments. register must changed under program control move from data segment (128 bytes) another. However, upper base segment (containing memory registers, registers, control registers, etc.) always available regardless contents register, since upper base segment (address range 0080 00FF) independent data segment extension. instructions that utilize stack pointer (SP) always reference stack part base segment (Segment regardless contents register. register changed these instructions. Consequently, stack (used with subroutine linkage interrupts) always located base segment. stack pointer will initialized point data memory location 006F result reset.
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COP8SBR9/COP8SCR9/COP8SDR9
Functional Description
(Continued)
DS101389-10
FIGURE Organization bytes contained base segment split between lower upper base segments. first bytes resident from address 0000 006F lower base segment, while remaining bytes represent data memory registers located addresses 00F0 00FF upper base segment. located upper sixteen addresses (0070 007F) lower base segment. Additional beyond these initial bytes, however, will always memory mapped groups bytes less) data segment address extensions (XX00 XX7F) lower base segment. additional bytes this device memory mapped address locations 0100 017F through 0700 077F hex. 4.4.1 Virtual EEPROM Flash memory User functions (see Section 5.7), provide user with capability flash program memory back user defined sections RAM. This effectively provides user with same nonvolatile data storage EEPROM. Management, even amount memory used, responsibility user, however flash memory read write functions have been provided boot ROM. typical method using Virtual EEPROM feature would user copy data during system initialization, periodically, necessary, erase page Flash copy contents back Flash. OPTION REGISTER Option register, located address 0x7FFF Flash Program Memory, used configure user selectable security, WATCHDOG, HALT options. register programmed only external Flash Memory programming Programming modes. Therefore, register must programmed same time program memory. contents Option register shipped from factory read Hex. format Option register follows:
SECURITY WATCH HALT FLEX
Reserved
Reserved
Bits These bits reserved must Security enabled. Flash Memory read write allowed except User ISP/Virtual commands. Mass Erase allowed. Security disabled. Flash Memory read write allowed. Bits These bits reserved must WATCHDOG feature disabled. general purpose I/O. WATCHDOG feature enabled. WATCHDOG output with weak pullup. HALT mode disabled. HALT mode enabled. Execution following RESET will from Flash Memory. Flash Memory erased. Execution following RESET will from Boot with MICROWIRE/PLUS routines. COP8 assembler defines special section type, CONF, into which Option Register data coded. Option Register programmed automatically programmers that certified National.
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COP8SBR9/COP8SCR9/COP8SDR9
Functional Description
(Continued)
user needs ensure that FLEX will when device programmed. following examples illustrate declaration Option Register. Syntax: [label:].sect
DS101389-11
config, conf value byte, ;configures ;options .endsect Example: following sets value Option Register User Identification COP8SBR944V7. Option Register values shown select options: Security disabled, WATCHDOG enabled HALT mode enabled execution will commence from Flash Memory. .chip 8SBR .sect option, conf 0x01 ;wd, halt, flex .endsect .end start Note: programmers certified programming this family parts will support programming Option Register. Please contact National your device programmer supplier more information. SECURITY device security feature which, when enabled, prevents external reading Flash program memory. security Option Register determines, whether security enabled disabled. security feature disabled, contents internal Flash Memory read external programmers built MICROWIRE/PLUS serial interface ISP. Security must enforced user when contents Flash Memory accessed user Virtual EEPROM capability. security feature enabled, then attempt externally read contents Flash Memory will result value (hex) being read from program locations (except Option Register). addition, with security feature enabled, write operation Flash program memory Option Register inhibited. Page Erases also inhibited when security feature enabled. Option Register readable regardless state security accessing location FFFF (hex). Mass Erase Operations possible regardless state security bit. Note: actual memory address Option Register 7FFF (hex), however MICROWIRE/PLUS routines require address FFFF (hex) used read Option Register when Flash Memory secured. entire Option Register must programmed time cannot rewritten without first erasing entire last page Flash Memory. RESET device initialized when RESET pulled On-chip Brownout Reset activated. Brownout Reset feature available COP8SDR9.
FIGURE Reset Logic following occurs upon initialization: Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input) Port HIGH Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input) Port TRI-STATE (High Impedance Input). Exceptions: Watchdog enabled, then Watchdog output. have their weak pull-up enabled during RESET. Port TRI-STATE (High Impedance Input) CLEARED 0000 PSW, CNTRL ICNTRL registers: CLEARED SIOR: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on T2CNTRL: CLEARED T3CNTRL: CLEARED HSTCR: CLEARED ITMR: Cleared except (HSON) Accumulator, Timer Timer Timer Accumulator, Timer Timer Timer RANDOM after RESET with crystal clock option (power already applied) UNAFFECTED after RESET with clock option (power already applied) RANDOM after RESET power-on WKEN, WKEDG: CLEARED WKPND: RANDOM (Stack Pointer): Initialized address Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on Register: CLEARED RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET power-on USART: PSR, ENU, ENUR, ENUI: Cleared except TBMT which one. CONTROL: ISPADLO: CLEARED ISPADHI: CLEARED PGMTIM: PRESET VALUE WATCHDOG enabled): device comes reset with both WATCHDOG
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COP8SBR9/COP8SCR9/COP8SDR9
Functional Description
(Continued)
logic Clock Monitor detector armed, with WATCHDOG service window bits Clock Monitor set. WATCHDOG Clock Monitor circuits inhibited during reset. WATCHDOG service window bits being initialized high default maximum WATCHDOG service window clock cycles. Clock Monitor being initialized high will cause Clock Monitor error following reset clock reached minimum specified frequency termination reset. Clock Monitor error will cause active error output This error output will continue until 16-32 clock cycles following clock frequency reaching minimum specified value, which time output will high. 4.7.1 External Reset RESET input when pulled initializes device. RESET must held minimum instruction cycle guarantee valid reset. During Power-Up initialization, user must ensure that RESET device without Brownout Reset feature held until device within specified voltage. circuit RESET with delay times (5x) greater than power supply rise time recommended. Reset should also wide enough ensure crystal start-up upon Power-Up. RESET also used cause exit from HALT mode. recommended reset circuit this device shown Figure
DS101389-12
FIGURE Reset Circuit Using External Reset 4.7.2 On-Chip Brownout Reset When enabled, device generates internal reset rises. While less than specified brownout voltage (Vbor), device held reset condition Idle Timer preset with 00Fx (240-256 tC). When reaches value greater than Vbor, Idle Timer starts counting down. Upon underflow Idle Timer, internal reset released device will start executing instructions. This internal reset will perform same functions external reset. Once above Vbor this initial Idle Timer time-out takes place, instruction execution begins Idle Timer used normally. however, drops below selected Vbor, internal reset generated, Idle Timer preset with 00Fx. device waits until greater than Vbor countdown starts over. When enabled, functional operation device guaranteed down Vbor level. exception above that brownout circuit will insert delay approximately power time drops below voltage about 1.8V. device will held Reset duration this delay before Idle Timer starts counting This delay starts soon rises above trigger voltage (approximately 1.8V). This behavior shown Figure
DS101389-13
FIGURE Brownout Reset Operation
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COP8SBR9/COP8SCR9/COP8SDR9
Functional Description
(Continued)
Case rises from on-chip RESET undefined until supply greater than approximately 1.0V. this time brownout circuit becomes active holds device RESET. supply passes level about 1.8V, delay about (td) started Idle Timer preset value between 00F0 00FF (hex). Once greater than Vbor expired, Idle Timer allowed count down (tid). Case shows subsequent supply voltage which goes below approximate 1.8V level. drops below Vbor, internal RESET signal asserted. When rises back above 1.8V level, started. Since power supply rise time longer this case, expired before rises above Vbor starts immediately when greater than Vbor. Case shows supply where drops below Vbor, below 1.8V. On-chip RESET asserted when goes below Vbor starts soon supply goes back above Vbor. Brownout Reset feature enabled, internal reset will turned until Idle Timer underflows. internal reset will perform same functions external reset. device guaranteed operate specified frequency down specified brownout voltage. After underflow, logic designed such that additional internal resets occur long remains above brownout voltage. device relatively immune short duration negativegoing transients (glitches). essential that good filtering done ensure that brownout feature works correctly. Power supply decoupling vital even battery powered systems. There optional brownout voltages. part numbers three versions this device are: COP8SBR9, Vbor voltage range COP8SCR9, Vbor high voltage range COP8SDR9, disabled. Refer device specifications actual Vbor voltages. Under circumstances should RESET allowed float. on-chip Brownout Reset feature being used, RESET should connected directly VCC. RESET input also connected external pull-up resistor other external circuitry. output brownout reset detector will always preset Idle Timer value between 00F0 00FF (240 tC). this time, internal reset will generated. feature disabled, then internal resets generated Idle Timer will power-up with unknown value. this case, external RESET must used. When disabled, this on-chip circuitry disabled draws current. contents data registers unknown following on-chip reset.
DS101389-14
FIGURE Reset Circuit Using Power-On Reset OSCILLATOR CIRCUITS device crystal oscillators facilitate power operation while maintaining throughput when required. Further information oscillators found Section Power Saving Features. speed oscillator utilizes port pins. References following text will also apply references G7/CKO will also apply 4.8.1 Oscillator clock input while G7/CKO clock generator output crystal. on-chip bias resistor connected between provided reduce system part count. value resistor range 0.5M (typically 1.0M). Table shows component values required various standard crystal values. Resistor on-chip, high speed oscillator, shown reference. Figure shows crystal oscillator connection diagram. ceramic resonator required frequency used place crystal accuracy requirements quite strict. TABLE Crystal Oscillator Configuration, 25°C,
Chip Chip Chip Chip (pF) 18-36
(pF) 18-36 100-156
Freq. (MHz) 0.455 32.768 kHz*
*Applies connection speed oscillator port pins only. **See Note below.
crystal other oscillator components should placed close proximity pins minimize printed circuit trace length. values external capacitors should chosen obtain manufacturer's specified load capacitance crystal when combined with parasitic capacitance trace, socket, package (which vary from pF). guideline choosing these capacitors Manufacturer's specified load Cparasitic trimmed obtain desired frequency. should less than equal Note: power design speed oscillator makes extremely sensitive board layout load capacitance. user should place crystal load capacitors within 1cm. device must ensure that
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Functional Description
(Continued) 4.8.2 Clock Doubler This device contains frequency doubler that doubles frequency oscillator selected operate main microcontroller core. details select either high speed oscillator speed oscillator described Power Saving Features. When high speed oscillator connected operates MHz, internal clock frequency MHz, resulting instruction cycle time When oscillator connected selected, internal clock frequency kHz, resulting instruction cycle 152.6 output clock doubler called MCLK referenced many places within this document.
above equation load capacitance strictly followed. these conditions met, application have problems with startup speed oscillator. TABLE Startup Times Frequency 3.33 (low speed oscillator) Startup Time 1-10 3-10 3-20 10-30
High Speed Oscillator
Speed Oscillator
DS101389-16 DS101389-15
FIGURE Crystal Oscillator CONTROL REGISTERS CNTRL Register (Address X'00EE)
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
Timer1 (T1) MICROWIRE/PLUS control register contains following bits: T1C3 Timer mode control T1C2 Timer mode control T1C1 Timer mode control T1C0 Timer Start/Stop control timer modes Underflow Interrupt Pending Flag timer mode MSEL Selects MICROWIRE/PLUS signals respectively IEDG External interrupt edge polarity select Rising edge, Falling edge) Select MICROWIRE/PLUS clock divide Register (Address X'00EF)
T1PNDA T1ENA EXPND BUSY EXEN
T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode T1ENA Timer Interrupt Enable Timer Underflow Input capture edge EXPND External interrupt pending BUSY MICROWIRE/PLUS busy shifting flag EXEN Enable external interrupt Global interrupt enable (enables interrupts) Half-Carry flag also affected instructions that affect Carry flag. (Set Carry) (Reset Carry) instructions will respectively clear both carry flags. addition instructions, ADC, SUBC, instructions affect Carry Half Carry flags. ICNTRL Register (Address X'00E8)
Unused LPEN T0PND T0EN µWPND µWEN T1PNDB T1ENB
register contains following select bits: Half Carry Flag Carry Flag
ICNTRL register contains following bits: LPEN Port Interrupt Enable (Multi-Input Wake-up/ Interrupt) T0PND Timer Interrupt pending T0EN Timer Interrupt Enable (Bit toggle) µWPND MICROWIRE/PLUS interrupt pending µWEN Enable MICROWIRE/PLUS interrupt T1PNDB Timer Interrupt Pending Flag capture edge
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Functional Description
T1ENB
(Continued)
DCEN
Selects high speed oscillator speed oscillator Idle Timer Clock.
Timer Interrupt Enable Input capture edge
CCKSEL Selects high speed oscillator speed oscillator primary clock. RSVD ITSEL2 This reserved must Idle Timer period select bit. Idle Timer period select bit. Idle Timer period select bit.
T2CNTRL Register (Address X'00C6)
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
T2CNTRL register contains following bits: T2C3 Timer mode control T2C2 Timer mode control T2C1 Timer mode control T2C0 Timer Start/Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T2PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode T2ENA Timer Interrupt Enable Timer Underflow Input capture edge T2PNDB Timer Interrupt Pending Flag capture edge T2ENB Timer Interrupt Enable Input capture edge T3CNTRL Register (Address X'00B6)
T3C3 T3C2 T3C1 T3C0 T3PNDA T3ENA T3PNDB T3ENB
ITSEL1 ITSEL0
T3CNTRL register contains following bits: T3C3 Timer mode control T3C2 Timer mode control T3C1 Timer mode control T3C0 Timer Start/Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T3PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode T3ENA Timer Interrupt Enable Timer Underflow Input capture edge T3PNDB Timer Interrupt Pending Flag capture edge T3ENB Timer Interrupt Enable Input capture edge HSTCR Register (Address X'00AF)
Reserved T3HS T2HS
HSTCR register contains following bits: T3HS Places Timer High Speed Mode. T2HS Places Timer High Speed Mode. ITMR Register (Address X'00CF)
LSON HSON DCEN CCKS RSVD ITSEL2 ITSEL1 ITSEL0
ITMR register contains following bits: LSON Turns speed oscillator off. HSON Turns high speed oscillator off.
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In-System Programming
INTRODUCTION This device provides capability program program memory while installed application board. This feature called System Programming (ISP). provides means using MICROWIRE/PLUS, user provide own, customized routine. factory installed uses MICROWIRE/PLUS port. user provide routine that uses capabilities device, such USART, parallel port, etc.
FUNCTIONAL DESCRIPTION organization feature consists user flash program memory, factory boot ROM, some registers dedicated performing function. Figure simplified block diagram. factory installed that uses MICROWIRE/PLUS located Boot ROM. size Boot bytes also contains code facilitate system emulation capability. user chooses write routine, must located flash program memory.
DS101389-17
FIGURE Block Diagram described OPTION REGISTER, there bit, FLEX, that controls whether device exits RESET executing from flash memory Boot ROM. user must program FLEX appropriate application. erased state, FLEX device will power-up executing from Boot ROM. When FLEX this assumes that either MICROWIRE/PLUS routine external programming being used program device. using MICROWIRE/PLUS routine, software boot will monitor MICROWIRE/PLUS commands program flash memory. When programming flash program memory complete, FLEX will have programmed device will have reset, either pulling external Reset ground MICROWIRE/PLUS EXIT command, before execution from flash program memory will occur. FLEX upon exiting Reset, device will begin executing from location 0000 flash program memory. assumption, here, that either application using ISP, using MICROWIRE/PLUS jumping within application code, using customized routine. customized routine being used, then must programmed into flash memory means MICROWIRE/PLUS external programming described preceding paragraph. REGISTERS There registers required support ISP: Address Register byte (ISPADHI), Address Register byte (ISPADLO), Read Data Register (ISPRD), Write Data Register (ISPWR), Write Timing Register (PGMTIM), Control Register (ISPCNTRL). ISPCNTRL Register available user. 5.3.1 Address Registers address registers (ISPADHI ISPADLO) used specify address byte data being written read. page erase operations, address beginning page should loaded. mass erase operations, 0000 must placed into address registers. When reading Option register, FFFF (hex) should placed into address registers. Registers ISPADHI ISPADLO cleared Reset. These registers loaded from either flash program memory Boot must maintained entire duration operation. Note: actual memory address Option Register 7FFF (hex), however MICROWIRE/PLUS routines require address FFFF (hex) used read Option Register when Flash Memory secured. TABLE High Byte Address
ISPADHI Addr15 Addr14 Addr Addr12 Addr11 Addr10 Addr9 Addr8
TABLE Byte Address
ISPADLO Addr7 Addr6 Addr5 Addr4 Addr3 Addr2 Addr1 Addr0
5.3.2 Read Data Register Read Data Register (ISPRD) contains value read back from read operation. This register accessed from either flash program memory Boot ROM. This register undefined Reset.
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In-System Programming
(Continued) TABLE Read Data Register
ISPRD Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
5.3.4 Write Timing Register Write Timing Register (PGMTIM) used control width timing pulses write erase operations. value written into this register dependent frequency shown Table This register must written before write erase operation take place. only needs loaded once, each value frequency. This register loaded from either flash program memory Boot must maintained entire duration operation. MICROWIRE/PLUS routine that resident boot requires that this Register defined prior access Flash memory. Refer MICROWIRE/PLUS more information available commands. Reset, PGMTIM register loaded with value that corresponds frequency CKI.
5.3.3 Write Data Register Write Data Register (ISPWR) contains data written into specified address. This register undetermined Reset. This register accessed from either flash program memory Boot ROM. Write Data register must maintained entire duration operation. TABLE Write Data Register
ISPWR Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TABLE PGMTIM Register Format PGMTIM Register kHz-33.3 37.5 kHz-50 kHz-66.67 62.5 kHz-83.3 kHz-100 kHz-133 112.5 kHz-150 kHz-200 kHz-266.67 kHz-300 kHz-400 kHz-500 kHz-666.67 kHz-800 kHz-1.067 MHz-1.33 1.125 MHz-1.5 MHz-2 MHz-2.67 2.625 MHz-3.5 MHz-4.67 MHz-6 MHz-8 MHz-10 Frequency Range
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In-System Programming
(Continued) MANEUVERING BACK FORTH BETWEEN FLASH MEMORY BOOT When using ISP, some point, will necessary maneuver between flash program memory Boot ROM, even when using customized routines. This because it's possible execute from flash program memory while it's being programmed. instructions available perform jumping back forth: Jump Boot (JSRB) Return Flash (RETF). JSRB instruction used jump from flash memory Boot ROM, RETF used return from Boot back flash program memory. 13.0 Instruction specific details operation these instructions. JSRB instruction must used conjunction with register. This prevent jumping Boot event run-away software. JSRB instruction actually jump Boot ROM, must set. This done writing value shown Table register. matches, will instruction cycles. JSRB instruction must executed while set. does match, then will JSRB will jump specified location flash memory. emulation mode, breakpoint encountered while set, counter that counts instruction cycles will frozen until breakpoint condition cleared. register memory mapped register. format when writing shown Table normal operation, necessary test before using JSRB instruction. additional instructions required test cause time-out before JSRB executed. TABLE Register Write Format
When Writing
While high voltage, Load Clock will output onto which will look like clock MICROWIRE/PLUS routine executing slave mode. However, when high voltage, input will also look like logic MICROWIRE/PLUS routine Boot monitors input, waits low, debounces then enables routine. CAUTION: Load clock could conflict with user's external user resolve this conflict, this condition considered minor issue that's only encountered during software development. user should also cautious high voltage applied pin. This high voltage could damage other circuitry connected (e.g. parallel port PC). user wish disconnect other circuitry while connected high voltage. RETURN FLASH MEMORY WITHOUT HARDWARE RESET After programming entire program memory, including options, necessary exit Boot return flash program memory program execution. Upon receipt completion EXIT command through MICROWIRE/PLUS ISP, code will reset part begin execution from flash program memory described Reset section. This assumes that FLEX Option register programmed MICROWIRE/PLUS National Semiconductor provides program, which available from site www.national.com/cop8, that capable programming device from parallel port software accepts manually input commands capable downloading standard Intel Format files. Users wish write their MICROWIRE/PLUS host software should refer COP8 FLASH User Manual, available from same site. This document includes details command format delays necessary between command bytes. MICROWIRE/PLUS supports following features commands:
Bits 7-2: value that must written bit. Bits 1-0: Don't care. FORCED EXECUTION FROM BOOT When user developing customized routine, code lockups software errors encountered. There hardware method these lockups force execution from Boot MICROWIRE/PLUS routine, that customer erase Flash Memory code start over. method force this condition drive high voltage VCC) activate Reset. high voltage condition must held least instruction cycles longer than Reset active. This special condition will start execution from location 0000 Boot where user input appropriate commands, using MICROWIRE/PLUS, erase flash program memory reprogram
Write value Write Timing Register. NOTE: This must first command after entering MICROWIRE/PLUS mode.
Erase entire flash program memory (mass erase). Erase page specified address. Read Option register. Read byte from specified address. Write byte specified address. Read multiple bytes starting specified address. Write multiple bytes starting specified address. Exit return execution flash program memory. following table lists MICROWIRE/PLUS commands provides information required parameters return values.
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In-System Programming
(Continued)
TABLE MICROWIRE/PLUS Commands Command PGMTIM_SET PAGE_ERASE MASS_ERASE READ_BYTE Function Write Pulse Timing Register Page Erase Mass Erase Read Byte Command Value (Hex) 0x3B 0xB3 0xBF 0x1D Value Starting Address Page Confirmation Code Address High, Address Parameters (The entire Flash Memory will erased) Data Byte Security set. 0xFF Security set. Option Register address 0xFFFF, regardless Security Data Bytes Security set. Bytes 0xFF Security set. Return Data
BLOCKR
Block Read
0xA3
Address High, Address Low, Byte Count High, Byte Count 32767 Address High, Address Low, Data Byte Address High, Address Low, Byte Count 16), Data Bytes other invalid command will ignored
WRITE_BYTE BLOCKW
Write Byte Block Write
0x71 0x8F
EXIT INVALID
EXIT
0xD3
(Device will Reset)
Note: user must ensure that Block Writes cross byte boundary within operation.
USER VIRTUAL following commands will support transferring blocks data from flash program memory, vice-versa. user expected enforce application security this case.
Erase entire flash program memory (mass erase). NOTE: Execution this command will force device into MICROWIRE/PLUS mode. Erase page flash memory specified address. Read byte from specified address. Write byte specified address. Copy block data from into flash program memory.
Copy block data from program flash memory RAM. following table lists User ISP/Virtual commands, required parameters return data, applicable. command entry point used argument JSRB instruction. Table lists locations Peripheral Registers, used User Virtual their expected contents. Please refer COP8 FLASH User Manual additional information programming examples User Virtual
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In-System Programming
Command/ Label cpgerase Command Entry Point 0x17
(Continued)
TABLE User ISP/Virtual Entry Points Function Page Erase Parameters Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Accumulator contains confirmation 0x55. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. pointer contains beginning address where result(s) will returned. Register BYTECOUNTLO contains number bytes read 255). user setup segment register. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Register ISPWR contains Data Byte written. Register ISPADHI loaded user with high byte address. Register ISPADLO loaded user with byte address. Register BYTECOUNTLO contains number bytes write 16). combination BYTECOUNTLO ISPADLO registers must such that operation will cross byte boundary. pointer contains beginning address data written. user setup segment register. Return Data page memory beginning ISPADHI, ISPADLO will erased)
cmserase creadbf
Mass Erase Read Byte
0x1A 0x11
(The entire Flash Memory will erased) Data Byte Register ISPRD.
cblockr
Block Read
0x26
Data Bytes, Data will returned beginning location pointed address
cwritebf
Write Byte
0x14
cblockw
Block Write
0x23
exit
EXIT
0x62
(Device will Reset)
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In-System Programming
Register Name ISPADHI ISPADLO ISPWR ISPRD ISPKEY BYTECOUNTLO PGMTIM
(Continued)
TABLE Register Name Definitions Purpose High byte Flash Memory Address byte Flash Memory Address user must store byte written into this register before jumping into write byte routine. Data will returned this register after read byte routine execution. ISPKEY Register required validate JSRB instruction must loaded within instruction cycles before JSRB. Holds count number bytes read written block operations. Write Timing Register. This register must loaded, user, with proper value before execution USER Write Erase operation. Refer Table correct value. user must place this code accumulator before execution Flash Memory Mass Erase command. Must transferred ISPKEY register before execution JSRB instruction. Location 0xA9 0xA8 0xAB 0xAA 0xE2 0xF1 0xE1
Confirmation Code
0x98
RESTRICTIONS SOFTWARE WHEN CALLING ROUTINES BOOT hardware will disable interrupts from occurring. hardware will leave current state, set, hardware interrupts will occur when execution returned Flash Memory. Subsequent interrupts, during operation, from same interrupt source will lost. security feature MICROWIRE/PLUS guaranteed software hardware. When executing MICROWIRE/PLUS routine, security checked prior performing instructions. Only mass erase command, write PGMTIM register, reading Option register permitted within MICROWIRE/PLUS routine. When user performing ISP, commands permitted. entry points from user's code check security. burden user guarantee security. Security description OPTION REGISTER more details security. When using functions Boot ROM, routines will service WATCHDOG within selected upper window. Upon return flash memory, WATCHDOG serviced, lower window enabled, user service WATCHDOG anytime following exit from Boot ROM, must service within selected upper window avoid WATCHDOG error. Block Writes start anywhere page Flash memory, cannot cross half page full page boundaries. user must ensure that page erase mass erase executed between consecutive writes same location Flash memory. writes same location without intervening erase will produce unpredicatable results including possible disturbance unassociated locations.
5.10 FLASH MEMORY DURABILITY CONSIDERATIONS endurance Flash Memory (number possible Erase/Write cycles) function erase time lowest temperature which erasure occurs. device used temperature, additional erase operations used extend erase time. user determine many times erase page based what endurance desired application (e.g. four page erase cycles, each time page erase done, required achieve typical 100k Erase/Write cycles application which operating down 0°C). Also, customer verify that entire page erased, with software, request additional erase operations desired. TABLE Typical Flash Memory Endurance Operating Temp Range Erase Time -40°C 100k -20°C 100k 100k 100k 100k 100k 100k 25°C 100k 100k 100k 100k 100k 100k 100k 100k
25°C
100k 100k 100k 100k 100k 100k 100k 100k
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COP8SBR9/COP8SCR9/COP8SDR9
Timers
device contains very versatile timers (T0, T3). Timers associated autoreload/ capture registers power containing random data. TIMER (IDLE TIMER) device supports applications that require maintaining real time power with IDLE mode. This IDLE mode support furnished IDLE Timer which 16-bit timer. user cannot read write IDLE Timer which count down timer. described Power Saving Features, clock IDLE Timer depends which mode device device High Speed mode, clock IDLE Timer instruction cycle clock (one-fifth frequency). device Dual Clock mode Speed mode, clock IDLE Timer clock. remainder this section, term "selected clock" will refer clock selected Power Save mode device. During Dual Clock Speed modes, divide that creates instruction cycle clock disabled, minimize power consumption. addition time base function, Timer supports following functions:
Exit Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description) Start delay HALT mode Start delay from Figure functional block diagram showing structure IDLE Timer associated interrupt logic. Bits through ITMR register selected triggering IDLE Timer interrupt. Each time selected underflows (every 16k, selected clocks), IDLE Timer interrupt pending T0PND set, thus generating interrupt enabled), Port data register reset, thus causing exit from IDLE mode device that mode. order interrupt generated, IDLE Timer interrupt enable T0EN must set, (Global Interrupt Enable) must also set. T0PND flag T0EN bits ICNTRL register, respectively. interrupt used purpose. Typically, used perform task upon exit from IDLE mode. more information IDLE mode, refer Power Saving Features. Idle Timer period selected bits ITMR register ITMR Register reserved should used software flag. Bits through ITMR Register used dual clock described Power Saving Features.
DS101389-18
FIGURE Functional Block Diagram Idle Timer TABLE Idle Timer Window Length
Idle Timer Period ITSEL2 ITSEL1 ITSEL0 High Speed Mode 4,096 inst. cycles 8,192 inst. cycles 16,384 inst. cycles 32,768 inst. cycles 65,536 inst. cycles Dual Clock Speed Mode 0.125 seconds 0.25 seconds seconds second seconds
ITMR Register
LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0
Reserved Undefined Reserved Undefined Reserved Undefined
ITSEL bits ITMR register cleared Reset Idle Timer period reset 4,096 instruction cycles.
Bits 7-4: Described Power Saving Features. Note: Documentation previous COP8 devices, which included Programmable Idle Timer, recommended user write zero high order bits ITMR Register. existing programs updated this device, writing zero these bits will cause device reset (see Power Saving Features). RSVD: This reserved must ITSEL2:0: Selects Idle Timer period described Table Idle Timer Window Length. time IDLE Timer period changed there possibility generating spurious IDLE Timer interrupt setting T0PND bit. user advised disable IDLE
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Timers
(Continued)
Timer interrupts prior changing value ITSEL bits ITMR Register then clear T0PND before attempting synchronize operation IDLE Timer. TIMER TIMER TIMER device three powerful timer/counter blocks, Since identical, except high speed operation comments equally applicable three timer blocks which will referred Differences between timers will specifically noted. Each timer block consists 16-bit timer, supporting 16-bit autoreload/capture registers, RxB. Each timer block pins associated with TxB. supports required timer block, while input timer block. timer block three operating modes: Processor Independent mode, External Event Counter mode, Input Capture mode. control bits TxC3, TxC2, TxC1 allow selection different modes operation. 6.2.1 Timer Operating Speeds Each timers, except have ability operate either instruction cycle frequency (low speed) internal clock frequency (MCLK). CKI, instruction cycle frequency internal clock frequency MHz. This feature controlled High Speed Timer Control Register, HSTCR. format shown below. place timer, high speed mode, appropriate TxHS speed operation, clear appropriate TxHS This register cleared Reset.
HSTCR T3HS T2HS
every underflow timer alternately reloaded with contents supporting registers, RxB. very first underflow timer causes timer reload from register RxA. Subsequent underflows cause timer reloaded from registers alternately beginning with register RxB. Figure shows block diagram timer mode. underflows programmed toggle output pin. underflows also programmed generate interrupts. Underflows from timer alternately latched into pending flags, TxPNDA TxPNDB. user must reset these pending flags under software control. control enable flags, TxENA TxENB, allow interrupts from timer underflow enabled disabled. Setting timer enable flag TxENA will cause interrupt when timer underflow causes register reloaded into timer. Setting timer enable flag TxENB will cause interrupt when timer underflow causes register reloaded into timer. Resetting timer enable flags will disable associated interrupts. Either both timer underflow interrupts enabled. This gives user flexibility interrupting once period either rising falling edge output. Alternatively, user choose interrupt both edges output.
6.2.2 Mode Processor Independent Mode timer's operating modes Processor Independent mode. this mode, timers generate "Processor Independent" signal because once timer more action required from which translates less software overhead greater throughput. user software services timer block only when parameters require updating. This capability provided fact that timer separate 16-bit reload registers. reload registers contains "ON" time while other holds "OFF" time. contrast, microcontroller that only single reload register requires additional software update reload value (alternate between on-time/off-time). timer generate output with width duty cycle controlled values stored reload registers. reload registers control countdown values reload values automatically written into timer when counts down through generating interrupt each reload. Under software control with minimal overhead, outputs useful controlling motors, triacs, intensity displays, providing inputs data acquisition sine wave generators. this mode, timer counts down fixed rate selected operate from MCLK). Upon
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DS101389-19
FIGURE Timer Mode 6.2.3 Mode External Event Counter Mode This mode quite similar processor independent mode described above. main difference that timer, clocked input signal from after synchronization appropriate internal clock MCLK). timer control bits, TxC3, TxC2 TxC1 allow timer clocked either positive negative edge from pin. Underflows from timer latched into TxPNDA pending flag. Setting TxENA control flag will cause interrupt when timer underflows. this mode input used independent positive edge sensitive interrupt input TxENB control flag set. occurrence positive edge input latched into TxPNDB flag.
Figure shows block diagram timer External Event Counter mode. Note: output available this mode since being used counter input clock.
COP8SBR9/COP8SCR9/COP8SDR9
Timers
(Continued)
Input Capture mode. timer underflow interrupt enabled with TxENA control flag. When interrupt occurs Input Capture mode, user must check both TxPNDA TxC0 pending flags order determine whether input capture timer underflow both) caused interrupt.
Figure shows block diagram timer Input Capture mode. identical
DS101389-20
FIGURE Timer External Event Counter Mode 6.2.4 Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block, input capture mode. this mode, reload registers serve independent capture registers, capturing contents timer when external event occurs (transition timer input pin). capture registers read while maintaining count, feature that lets user measure elapsed time time between events. saving timer value when external event occurs, time external event recorded. Most microcontrollers have latency time because they cannot determine timer value when external event occurs. capture register eliminates latency time, thereby allowing applications program retrieve timer value stored capture register. this mode, timer constantly running fixed MCLK rate. registers, RxB, capture registers. Each register also acts conjunction with pin. register acts conjunction with register acts conjunction with pin. timer value gets copied over into register when trigger event occurs corresponding after synchronization appropriate internal clock MCLK). Control bits, TxC3, TxC2 TxC1, allow trigger events specified either positive negative edge. trigger condition each input specified independently. trigger conditions also programmed generate interrupts. occurrence specified trigger condition pins will respectively latched into pending flags, TxPNDA TxPNDB. control flag TxENA allows interrupt either enabled disabled. Setting TxENA flag enables interrupts generated when selected trigger condition occurs pin. Similarly, flag TxENB controls interrupts from pin. Underflows from timer also programmed generate interrupts. Underflows latched into timer TxC0 pending flag (the TxC0 control serves timer underflow interrupt pending flag Input Capture mode). Consequently, TxC0 control should reset when enter-
DS101389-21
FIGURE Timer Input Capture Mode TIMER CONTROL FLAGS control bits their functions summarized below. TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control TxC0 Timer Start/Stop control Modes (Processor Independent External Event Counter), where Start, Stop Timer Underflow Interrupt Pending Flag Mode (Input Capture) TxPNDA Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled TxPNDB Timer Interrupt Pending Flag TxENB Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled timer mode control bits (TxC3, TxC2 TxC1) detailed Table Timer Operating Modes. When high speed timers counting high speed mode, directly altering contents timer upper lower registers, reload registers recommended. operations particularly problematic. Since these registers change many times single instruction cycle, performing SBIT RBIT operation with timer running produce unpredictable results. recommended procedure stop timer, perform changes timer reload register values, then re-start timer. This warning does apply timer control register. type read/write operation, including SBIT RBIT performed this register operating mode.
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Timers
(Continued) TABLE Timer Operating Modes
Mode
TxC3
TxC2
TxC1
Description PWM: Toggle PWM: Toggle External Event Counter External Event Counter Captures: Pos. Edge Pos. Edge
Interrupt Source Autoreload Autoreload Timer Underflow Timer Underflow Pos. Edge Timer Underflow Pos. Edge Timer Underflow Neg. Edge Timer Underflow Neg. Edge Timer Underflow
Interrupt Source Autoreload Autoreload Pos. Edge Pos. Edge Pos. Edge
Timer Counts MCLK MCLK Pos. Edge Neg. Edge MCLK
Captures: Pos. Edge Neg. Edge
Neg. Edge Pos. Edge Neg. Edge
MCLK
Captures: Neg. Edge Pos. Edge
MCLK
Captures: Neg. Edge Neg. Edge
MCLK
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Power Saving Features
Today, proliferation battery-operated applications placed demands designers drive power consumption down. Battery operated systems only type applications demanding power. power budget constraints also imposed those consumer/industrial applications where well regulated expensive power supply costs cannot tolerated. Such applications rely cost power supply voltage derived directly from "mains" using voltage rectifier passive components. power demanded even automotive applications, increased vehicle electronics content. This required ease burden from battery. power 8-bit microcontrollers supply smarts control batteryoperated, consumer/industrial, automotive applications. device offers system designers variety low-power consumption features that enable them meet demanding requirements today's increasing range low-power applications. These features include voltage operation, current drain, power saving features such HALT, IDLE, Multi-Input walk-up (MIWU). This device supports three operating modes, each which have power save modes operation. three operat-
modes are: High Speed, Dual Clock, Speed. Within each operating mode, power save modes are: HALT IDLE. HALT mode operation, microcontroller activities stopped power consumption reduced very level. this device, HALT mode enabled disabled Option register. IDLE mode similar HALT mode, except that certain sections device continue operate, such on-board oscillator, IDLE Timer (Timer T0), Clock Monitor. This allows real time maintained. During power save modes operation, board RAM, registers, states timers (with exception unaltered. oscillators used support three different operating modes. high speed oscillator refers oscillator connected speed oscillator refers oscillator connected pins When using speed oscillator, user must ensure that pins configured hi-Z input, using USART, Multi-Input-Walk-up these pins disabled. diagram three modes shown Figure
DS101389-22
FIGURE Diagram Power Save Modes POWER SAVE MODE CONTROL REGISTER ITMR control register allows navigation between three different modes operation. also used Idle Timer. register assignments shown below. This register cleared (hex) Reset shown below.
LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0
DCEN:
LSON:
HSON:
This used turn-on low-speed oscillator. When LSON speed oscillator off. When LSON speed oscillator There startup time associated with this oscillator. Oscillator Circuits section. This used turn-on high speed oscillator. When HSON high speed oscillator
CCKSEL:
off. When HSON high speed oscillator There startup time associated with this oscillator. startup time table Oscillator Circuits section. This selects clock source Idle Timer. this then high speed clock clock source Idle Timer. this then speed clock clock source Idle Timer. speed oscillator must started stabilized before setting this This selects whether high speed clock speed clock gated microcontroller core. When this Core clock will high speed clock. When this then
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Power Saving Features
(Continued)
7.3.1 High Speed Halt Mode fully static architecture this device allows state microcontroller frozen. This accomplished stopping internal clock device during HALT mode. controller also stops from oscillating during HALT mode. processor forced exit HALT mode resume normal operation time. During normal operation, actual power consumption depends heavily clock speed operating voltage used application shown Electrical Specifications. HALT mode, device only draws small leakage current, plus current feature enabled), plus current necessary driving outputs. Since total power consumption affected amount current required drive outputs, I/Os should configured draw minimal current prior entering HALT mode, possible. order reduce power consumption even further, power supply (VCC) reduced very level during HALT mode, just high enough guarantee retention data stored RAM. allowed lower voltage level (VR) specified Electrical Specs section. Entering High Speed Halt Mode device enters HALT mode under software control when Port data register processor action stops middle next instruction cycle, power consumption reduced very level. Exiting High Speed Halt Mode There choice methods exiting HALT mode: chip Reset using RESET Multi-Input Walk-up. HALT Exit Using Reset device Reset, which invoked low-level signal RESET input pin, takes device HALT mode starts execution from address 0000H. initialization software should determine what special action needed, any, upon start-up device from HALT. initialization registers following RESET exit from HALT described Reset section this manual. HALT Exit Using Multi-Input Walk-up device brought HALT mode transition received available Walk-up pins. pins used types transitions sensed Multiinput pins software programmable. information programming using Multi-Input Wake-up feature, refer Multi-Input Wake-up section. start-up delay required between device wakeup execution program instructions, depending type chip clock. start-up delay mandatory, implemented whether CLKDLY set. This because crystal oscillators resonators require some time reach stable frequency full operating amplitude. IDLE Timer (Timer provides fixed delay from time clock enabled time program execution begins. Upon exit from HALT mode, IDLE Timer enabled with starting value decremented with each instruction cycle. (The instruction clock runs one-fifth frequency high speed oscillator.) internal Schmitt trigger connected on-chip inverter ensures that IDLE Timer clocked only when oscillator large enough amplitude. (The Schmitt trigger part oscillator closed loop.) When IDLE Timer
Core clock will speed clock. Before switching this either state, appropriate clock should turned stabilized. DCEN CCKSEL High Speed Mode. Core Idle Timer Clock High Speed Dual Clock Mode. Core clock High Speed; Idle Timer Speed Speed Mode. Core Idle Timer Clock Speed
Invalid. this detected, Speed Mode will forced. RSVD: This reserved must Bits 2-0: These bits used control Idle Timer. TIMER (IDLE TIMER) description these bits.
Table lists valid contents four most significant bits ITMR Register. other value illegal will result unrecoverable loss clock core. prevent this condition, device will automatically reset illegal value detected.
TABLE Valid Contents Dual Clock Control Bits LSON HSON DCEN CCKSEL Mode High Speed High Speed/Dual Clock Transition Dual Clock Dual Clock/Low Speed Transition Speed
This internal reset presets Idle Timer 00Fx which results internal reset This delay independent oscillator type state enable. OSCILLATOR STABILIZATION Both high speed oscillator speed oscillator have startup delay associated with them. When switching between modes, software must ensure that appropriate oscillator started stabilized before switching mode. Table Startup Times startup times both oscillators. HIGH SPEED MODE OPERATION This mode operation allows high speed operation both main Core clock also Idle Timer. This default mode device will always entered upon Reset conditions described Reset section. also entered from Dual Clock mode. cannot directly entered from Speed mode without passing through Dual Clock mode first. enter from Dual Clock mode, following sequence must followed using separate instructions: Software clears DCEN Software clears LSON
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Power Saving Features
(Continued)
underflows, clock signals enabled chip, allowing program execution proceed. Thus, delay equal instruction cycles. Note: ensure accurate operation upon start-up device using Multi-input Wakeup, instruction application program used entering HALT mode should followed consecutive (no-operation) instructions. Options This device options associated with HALT mode. first option enables HALT mode feature, while second option disables HALT mode operation. Selecting
disable HALT mode option will cause microcontroller ignore attempts HALT device under software control. Note that this device still placed HALT mode stopping clock input microcontroller, program memory masked ROM. Option section more details this option bit.
DS101389-23
FIGURE Wakeup from HALT 7.3.2 High Speed Idle Mode IDLE mode, program execution stops power consumption reduced very level with HALT mode. However, high speed oscillator, IDLE Timer (Timer T0), Clock Monitor continue operate, allowing real time maintained. device remains idle selected amount time 65,536 instruction cycles, 32.768 milliseconds with instruction clock frequency, then automatically exits IDLE mode returns normal program execution. device placed IDLE mode under software control setting IDLE (bit Port data register). IDLE Timer window selectable from five values, 16k, instruction cycles. Selection this value made through ITMR register. IDLE mode uses on-chip IDLE Timer (Timer keep track elapsed time IDLE state. IDLE Timer runs continuously instruction clock rate, whether device IDLE mode. Each time timer associated with selected window toggles, T0PND set, interrupt generated enabled), device exits IDLE mode that mode. IDLE Timer interrupt enabled, interrupt serviced before execution main program resumes. (However, instruction which started part entered IDLE mode completed before interrupt serviced. This instruction should which should follow enter IDLE instruction.) user must reset IDLE Timer pending flag (T0PND) before entering IDLE mode.
with HALT mode, this device also returned normal operation with reset, with Multi-Input Wakeup input. Upon reset ITMR register cleared ITMR register selects 4,096 instruction cycle Idle Timer. IDLE Timer cannot started stopped under software control, memory mapped, cannot read written software. state upon Reset unknown. Therefore, device into IDLE mode arbitrary time, will stay IDLE mode somewhere between selected number instruction cycles. order precisely time duration IDLE state, entry into IDLE mode must synchronized state IDLE Timer. best this IDLE Timer interrupt, which occurs every underflow IDLE Timer which associated with selected window. Another method poll state IDLE Timer pending T0PND, which same occurrence. Idle Timer interrupt enabled setting T0EN ICNTRL register. time IDLE Timer window length changed there possibility generating spurious IDLE Timer interrupt setting T0PND bit. user advised disable IDLE Timer interrupts prior changing value ITSEL bits ITMR Register then clear TOPND before attempting synchronize operation IDLE Timer. Note: with HALT mode, necessary program NOP's allow clock resynchronization upon return from
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Power Saving Features
(Continued)
HALT Exit Using Multi-Input Wakeup device brought HALT mode transition received available Wakeup pins. pins used types transitions sensed Multiinput pins software programmable. information programming using Multi-Input Wakeup feature, refer MULTI-INPUT WAKEUP. start-up delay required between device wakeup execution program instructions. start-up delay mandatory, implemented whether CLKDLY set. This because crystal oscillators resonators require some time reach stable frequency full operating amplitude. start-up delay used, IDLE Timer (Timer provides fixed delay from time clock enabled time program execution begins. Upon exit from HALT mode, IDLE Timer enabled with starting value decremented with each instruction cycle using high speed clock. (The instruction clock runs one-fifth frequency high speed oscillatory.) internal Schmitt trigger connected on-chip inverter ensures that IDLE Timer clocked only when high speed oscillator large enough amplitude. (The Schmitt trigger part oscillator closed loop.) When IDLE Timer underflows, clock signals enabled chip, allowing program execution proceed. Thus, delay equal instruction cycles. After exiting HALT, Idle Timer will return being clocked speed clock. Note: ensure accurate operation upon start-up device using Multi-input Wakeup, instruction application program used entering HALT mode should followed consecutive (no-operation) instructions. Options This device options associated with HALT mode. first option enables HALT mode feature, while second option disables HALT mode operation. Selecting disable HALT mode option will cause microcontroller ignore attempts HALT device under software control. OPTION REGISTER more details this option bit. 7.4.2 Dual Clock Idle Mode IDLE mode, program execution stops power consumption reduced very level with HALT mode. However, both oscillators, IDLE Timer (Timer T0), Clock Monitor continue operate, allowing real time maintained. Idle Timer clocked speed clock. device remains idle selected amount time second, then automatically exits IDLE mode returns normal program execution using high speed clock. device placed IDLE mode under software control setting IDLE (bit Port data register). IDLE Timer window selectable from five values, 0.125 seconds, 0.25 seconds, seconds, second seconds. Selection this value made through ITMR register. IDLE mode uses on-chip IDLE Timer (Timer keep track elapsed time IDLE state. IDLE Timer runs continuously speed clock rate, whether device IDLE mode. Each time timer associated with selected window toggles, T0PND
IDLE mode. NOP's placed either beginning IDLE Timer interrupt routine immediately following "enter IDLE mode" instruction. more information IDLE Timer associated interrupt, description Timers section. DUAL CLOCK MODE OPERATION This mode operation allows high speed operation Core clock speed operation Idle Timer. This mode entered from either High Speed mode Speed mode. enter from High Speed mode, following sequence must followed: Software sets LSON Software waits until speed oscillator stabilized. Table Software sets DCEN enter from Speed mode, following sequence must followed: Software sets HSON Software waits until high speed oscillator stabilized. Table Startup Times. Software clears CCKSEL
7.4.1 Dual Clock HALT Mode fully static architecture this device allows state microcontroller frozen. This accomplished stopping high speed clock device during HALT mode. processor forced exit HALT mode resume normal operation time. speed clock remains during HALT Dual Clock mode. During normal operation, actual power consumption depends heavily clock speed operating voltage used application shown Electrical Specifications. HALT mode, device only draws small leakage current, plus current feature enabled), plus oscillator current, plus current necessary driving outputs. Since total power consumption affected amount current required drive outputs, I/Os should configured draw minimal current prior entering HALT mode, possible. Entering Dual Clock Halt Mode device enters HALT mode under software control when Port data register processor action stops middle next instruction cycle, power consumption reduced very level. order expedite exit from HALT, speed oscillator left running when device Halted Dual Clock mode. However, Idle Timer will clocked. Exiting Dual Clock Halt Mode When HALT mode entered setting Port data register, there choice methods exiting HALT mode: chip Reset using RESET MultiInput Wakeup. Reset method Multi-Input Wakeup method used with clock option. HALT Exit Using Reset device Reset, which invoked low-level signal RESET input pin, takes device Dual Clock mode puts into High Speed mode.
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Power Saving Features
(Continued)
HALT. processor forced exit HALT mode resume normal operation time. During normal operation, actual power consumption depends heavily clock speed operating voltage used application shown Electrical Specifications. HALT mode, device only draws small leakage current, plus current feature enabled), plus oscillator current, plus current necessary driving outputs. Since total power consumption affected amount current required drive outputs, I/Os should configured draw minimal current prior entering HALT mode, possible. Entering Speed Halt Mode device enters HALT mode under software control when Port data register processor action stops middle next instruction cycle, power consumption reduced very level. order expedite exit from HALT, speed oscillator left running when device Halted Speed mode. However, Idle Timer will clocked. Exiting Speed Halt Mode When HALT mode entered setting Port data register, there choice methods exiting HALT mode: chip Reset using RESET MultiInput Wakeup. Reset method Multi-Input Wakeup method used with clock option, availability input dependent clock option. HALT Exit Using Reset device Reset, which invoked low-level signal RESET input pin, takes device Speed mode puts into High Speed mode. HALT Exit Using Multi-Input Wakeup device brought HALT mode transition received available Wakeup pins. pins used types transitions sensed Multiinput pins software programmable. information programming using Multi-Input Wakeup feature, refer Multi-Input Wakeup section. speed oscillator left running, there start delay when exiting speed halt mode, regardless state CLKDLY bit. Note: ensure accurate operation upon start-up device using Multi-input Wakeup, instruction application program used entering HALT mode should followed consecutive (no-operation) instructions. Options This device options associated with HALT mode. first option enables HALT mode feature, while second option disables HALT mode operation. Selecting disable HALT mode option will cause microcontroller ignore attempts HALT device under software control. Option section more details this option bit. 7.5.2 Speed Idle Mode IDLE mode, program execution stops power consumption reduced very level with HALT mode. However, speed oscillator, IDLE Timer (Timer T0), Clock Monitor continue operate, allowing real
set, interrupt generated enabled), device exits IDLE mode that mode. IDLE Timer interrupt enabled, interrupt serviced before execution main program resumes. (However, instruction which started part entered IDLE mode completed before interrupt serviced. This instruction should which should follow enter IDLE instruction.) user must reset IDLE Timer pending flag (T0PND) before entering IDLE mode. with HALT mode, this device also returned normal operation with Multi-Input Wakeup input. IDLE Timer cannot started stopped under software control, memory mapped, cannot read written software. state upon Reset unknown. Therefore, device into IDLE mode arbitrary time, will stay IDLE mode somewhere between selected time period. order precisely time duration IDLE state, entry into IDLE mode must "synchronized state IDLE Timer. best this IDLE Timer interrupt, which occurs every underflow IDLE Timer which associated with selected window. Another method poll state IDLE Timer pending T0PND, which same occurrence. Idle Timer interrupt enabled setting T0EN ICNTRL register. time IDLE Timer window length changed there possibility generating spurious IDLE Timer interrupt setting T0PND bit. user advised disable IDLE Timer interrupts prior changing value ITSEL bits ITMR Register then clear T0PND before attempting synchronize operation IDLE Timer. Note: with HALT mode, necessary program NOP's allow clock resynchronization upon return from IDLE mode. NOP's placed either beginning IDLE Timer interrupt routine immediately following "enter IDLE mode" instruction. more information IDLE Timer associated interrupt, description Timers section. SPEED MODE OPERATION This mode operation allows speed operation core clock speed operation Idle Timer. Because speed oscillator draws very little operating current, also expedite restarting from HALT mode, speed oscillator left times this mode, including HALT mode. This lowest power mode operation device. This mode only entered from Dual Clock mode. enter Speed mode, following sequence must followed using separate instructions: Software sets CCKSEL Software clears HSON Since speed oscillator already running, there clock startup delay. 7.5.1 Speed HALT Mode fully static architecture this device allows state microcontroller frozen. Because speed oscillator draws very minimal operating current, will left running speed halt mode. However, Idle Timer will running. This also allows faster exit from
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Power Saving Features
(Continued)
time maintained. device remains idle selected amount time seconds, then automatically exits IDLE mode returns normal program execution using speed clock. device placed IDLE mode under software control setting IDLE (bit Port data register). IDLE Timer window selectable from five values, 0.125 seconds, 0.25 seconds, seconds, second, seconds. Selection this value made through ITMR register. IDLE mode uses on-chip IDLE Timer (Timer keep track elapsed time IDLE state. IDLE Timer runs continuously speed clock rate, whether device IDLE mode. Each time timer associated with selected window toggles, T0PND set, interrupt generated enabled), device exits IDLE mode that mode. IDLE Timer interrupt enabled, interrupt serviced before execution main program resumes. (However, instruction which started part entered IDLE mode completed before interrupt serviced. This instruction should which should follow enter IDLE instruction.) user must reset IDLE Timer pending flag (T0PND) before entering IDLE mode. with HALT mode, this device also returned normal operation with Multi-Input Wakeup input. IDLE Timer cannot started stopped under software control, memory mapped, cannot read written software. state upon Reset unknown. Therefore, device into IDLE mode arbitrary time, will stay IDLE mode somewhere between selected time period. order precisely time duration IDLE state, entry into IDLE mode must synchronized state
IDLE Timer. best this IDLE Timer interrupt, which occurs every underflow IDLE Timer which associated with selected window. Another method poll state IDLE Timer pending T0PND, which same occurrence. Idle Timer interrupt enabled setting T0EN ICNTRL register. time IDLE Timer window length changed there possibility generating spurious IDLE Timer interrupt setting T0PND bit. user advised disable IDLE Timer interrupts prior changing value ITSEL bits ITMR Register then clear T0PND before attempting synchronize operation IDLE Timer. with HALT mode, necessary program NOP's allow clock resynchronization upon return from IDLE mode. NOP's placed either beginning IDLE Timer interrupt routine immediately following "enter IDLE mode" instruction. more information IDLE Timer associated interrupt, description Section 6.1, Timer (IDLE Timer). MULTI-INPUT WAKEUP Multi-Input Wakeup feature used return (wakeup) device from either HALT IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature also used generate edge selectable external interrupts.
Figure shows Multi-Input Wakeup logic. Multi-Input Wakeup feature utilizes Port. user selects which particular port combination Port bits) will cause device exit HALT IDLE modes. selection done through register WKEN. register WKEN 8-bit read/write register, which contains control every port bit. Setting particular WKEN enables Wakeup from associated port pin.
DS101389-24
FIGURE Multi-Input Wake Logic
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Power Saving Features
(Continued) port bits have been used outputs then changed inputs with Multi-Input Wakeup/Interrupt, safety procedure should also followed avoid wakeup conditions. After selected port bits have been changed from output input before associated WKEN bits enabled, associated edge select bits WKEDG should reset desired edge selects, followed associated WKPND bits being cleared. This same procedure should used following reset, since port inputs left floating result reset. occurrence selected trigger condition MultiInput Wakeup latched into pending register called WKPND. respective bits WKPND register will occurrence selected trigger edge corresponding Port pin. user responsibility clearing these pending flags. Since WKPND pending register occurrence selected wakeup conditions, device will enter HALT mode Wakeup both enabled pending. Consequently, user must clear pending flags before attempting enter HALT mode. WKEN WKEDG read/write registers, cleared reset. WKPND register contains random value after reset.
user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition). This selection made register WKEDG, which 8-bit control register with assigned each Port pin. Setting control will select trigger condition negative edge that particular Port pin. Resetting selects trigger condition positive edge. Changing edge select entails several steps order avoid Wakeup condition result edge change. First, associated WKEN should reset, followed edge select change WKEDG. Next, associated WKPND should cleared, followed associated WKEN being re-enabled. example serve clarify this procedure. Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt. program would follows: RBIT WKEN Disable MIWU SBIT WKEDG Change edge polarity RBIT WKPND Reset pending flag SBIT WKEN Enable MIWU
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USART
device contains full-duplex software programmable USART. USART (Figure consists transmit shift register, receive shift register seven addressable registers, follows: transmit buffer register (TBUF), receiver buffer register (RBUF), USART control status register (ENU), USART receive control status register (ENUR), USART interrupt clock source register (ENUI), prescaler select register (PSR) baud (BAUD) register. register contains flags transmit receive functions; this register also determines length data frame bits), value ninth transmission, parity selection bits. ENUR register flags framing, data overrun, parity errors line breaks while USART receiving.
Other functions ENUR register include saving ninth received data frame, enabling disabling USART's attention mode operation providing additional receiver/transmitter status information RCVG XMTG bits. determination internal external clock source done ENUI register, well selecting number stop bits enabling disabling transmit receive interrupts. control flag this register also select USART mode operation: asynchronous synchronous.
DS101389-25
FIGURE USART Block Diagram
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USART
(Continued)
Indicates occurrence Data Overrun Error.
USART CONTROL STATUS REGISTERS operation USART programmed through three registers: ENU, ENUR ENUI. DESCRIPTION USART REGISTER BITS USART CONTROL STATUS REGISTER (Address 0BA)
PSEL1 XBIT9/ PSEL0 CHL1 CHL0 RBFL TBMT
Flags Framing Error. Read only, cleared read, cleared reset. Indicates Framing Error been detected since last time ENUR register read.
PEN: This enables/disables Parity 8-bit modes only). Read/Write, cleared reset. Parity disabled. Parity enabled. PSEL1, PSEL0: Parity select bits. Read/Write, cleared reset. PSEL1 PSEL0 Parity Parity enabled) PSEL1 PSEL1 Even Parity Parity enabled) PSEL1 PSEL0 Mark(1) Parity enabled) PSEL1 PSEL1 Space(0) Parity enabled) XBIT9/PSEL0: Programs ninth transmission when USART operating with nine data bits frame. seven eight data bits frame, this conjunction with PSEL1 selects parity. Read/Write, cleared reset. CHL1, CHL0: These bits select character frame format. Parity included generated/verified hardware. Read/Write, cleared reset. CHL1 CHL0 frame contains eight data bits. CHL1 CHL0 frame contains seven data bits. CHL1 CHL0 frame contains nine data bits. CHL1 CHL0 Loopback Mode selected. Transmitter output internally looped back receiver input. Nine framing format used. ERR: This global USART error flag which gets combination errors (DOE, occur. Read only; cannot written software, cleared reset. RBFL: This when USART received complete character copied into RBUF register. automatically reset when software reads character from RBUF. Read only; cannot written software, cleared reset. TBMT: This when USART transfers byte data from TBUF register into TSFT register transmission. automatically reset when software writes into TBUF register. Read only, "one" reset; cannot written software. ENUR USART RECEIVE CONTROL STATUS REGISTER (Address 0BB)
RBIT9 ATTN XMTG RCVG
Indicates occurrence Framing Error. Flags Parity Error. Read only, cleared read, cleared reset. Indicates Parity Error been detected since last time ENUR register read. Indicates occurrence Parity Error. Flags line break. Indicates Line Break been detected since last time ENUR register read. Indicates occurrence Line Break. RBIT9: Contains ninth data received when USART operating with nine data bits frame. Read only, cleared reset. ATTN: ATTENTION Mode enabled while this set. This cleared automatically receiving character with data nine set. Read/Write, cleared reset. XMTG: This indicate that USART transmitting. gets reset last frame (end last Stop bit). Read only, cleared reset. RCVG: This high whenever framing error occurs goes when goes high. Read only, cleared reset. ENUI USART INTERRUPT CLOCK SOURCE REGISTER (Address 0BC)
STP2 ETDX SSEL XRCLK XTCLK
DOE: Flags Data Overrun Error. Read only, cleared read, cleared reset. Indicates Data Overrun Error been detected since last time ENUR register read.
STP2: This programs number Stop bits transmitted. Read/Write, cleared reset. STP2 Stop transmitted. STP2 Stop bits transmitted. BRK: Holds (USART Transmit Pin) generate Line Break. Timing Line Break under software control. ETDX: (USART Transmit Pin) alternate function assigned Port selected setting ETDX bit. SSEL: USART mode select. Read only, cleared reset. SSEL Asynchronous Mode. SSEL Synchronous Mode. XRCLK: This selects clock source receiver section. Read/Write, cleared reset. XRCLK clock source selected through BAUD registers. XRCLK Signal (L1) used clock. XTCLK: This selects clock source transmitter section. Read/Write, cleared reset. XTCLK clock source selected through BAUD registers. XTCLK Signal (L1) used clock. ERI: This enables/disables interrupt from receiver section. Read/Write, cleared reset. Interrupt from receiver disabled. Interrupt from receiver enabled.
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USART
(Continued)
8.4.2 Synchronous Mode this mode data transferred synchronously with clock. Data transmitted rising edge received falling edge synchronous clock. This mode selected setting SSEL ENUI register. input frequency USART same baud rate. When external clock input selected pin, data transmit receive performed synchronously with this clock through TDX/RDX pins. data transmit receive selected with clock output, device generates synchronous clock output pin. internal baud rate generator used produce synchronous clock. Data transmit receive performed synchronously with this clock. FRAMING FORMATS USART supports several serial framing formats (Figure 22). format selected using control bits ENU, ENUR ENUI registers. first format data transmission (CHL0 CHL1 consists Start bit, seven Data bits (excluding parity) Stop bits. applications using parity, parity generated verified hardware. second format (CHL0 CHL1 consists Start bit, eight Data bits (excluding parity) 7/8, Stop bits. Parity generated verified hardware. third format transmission (CHL0 CHL1 consists Start bit, nine Data bits Stop bits. This format also supports USART "ATTENTION" feature. When operating this format, eight bits TBUF RBUF used data. ninth data transmitted received using bits ENUR registers, called XBIT9 RBIT9. RBIT9 read only bit. Parity generated verified this mode. parity enabled/disabled located register. Parity selected 8-bit modes only. parity enabled (PEN parity selection then performed PSEL0 PSEL1 bits located register. Note that XBIT9/PSEL0 located register serves mutually exclusive functions. This programs ninth transmission when USART operating with nine data bits frame. There parity selection this framing format. other framing formats XBIT9 needed PSEL0 used conjunction with PSEL1 select parity. frame formats receiver differ from transmitter number Stop bits required. receiver only requires Stop frame, regardless setting Stop selection bits control register. Note that implicit assumption made full duplex USART operation that framing formats same transmitter receiver.
ETI: This enables/disables interrupt from transmitter section. Read/Write, cleared reset. Interrupt from transmitter disabled. Interrupt from transmitter enabled.
ASSOCIATED PINS Data transmitted received pin. alternate function assigned Port selected setting ETDX ENUI register) one. inherent function Port requiring setup. Port must configured output Port Configuration Register order used pin. baud rate clock USART generated onchip, taken from external source. Port (CKX) external clock pin. either input output, determined Port Configuration Data registers (Bit input, accepts clock signal which selected drive transmitter and/or receiver. output, presents internal Baud Rate Generator output. Note: unavailable Port used Speed Oscillator. USART OPERATION USART modes operation: asynchronous mode synchronous mode. 8.4.1 Asynchronous Mode This mode selected resetting SSEL ENUI register) zero. input frequency USART times baud rate. TSFT TBUF registers double-buffer data transmission. While TSFT shifting current character pin, TBUF register loaded software with next byte transmitted. When TSFT finishes transmitting current character contents TBUF transferred TSFT register Transmit Buffer Empty Flag (TBMT register) set. TBMT flag automatically reset USART when software loads character into TBUF register. There also XMTG which indicate that USART transmitting. This gets reset last frame (end last Stop bit). TBUF read/write register. RSFT RBUF registers double-buffer data being received. USART receiver continually monitors signal level detect beginning Start bit. Upon sensing this level, waits half time samples again. still low, receiver considers this valid Start bit, remaining bits character frame each sampled three times around center time. Serial data input shifted into RSFT register. Upon receiving complete character, contents RSFT register copied into RBUF register Received Buffer Full Flag (RBFL) set. RBFL automatically reset when software reads character from RBUF register. RBUF read only register. There also RCVG which high when framing error occurs goes once goes high.
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USART
(Continued)
DS101389-26
FIGURE Framing Formats USART INTERRUPTS USART capable generating interrupts. Interrupts generated Receive Buffer Full Transmit Buffer Empty. Both interrupts have individual interrupt vectors. bytes program memory space reserved each interrupt vector. vectors located addresses 0xEC 0xEF program memory space. interrupts individually enabled disabled using Enable Transmit Interrupt (ETI) Enable Receive Interrupt (ERI) bits ENUI register. interrupt from Transmitter pending, remains pending, long both TBMT bits set. remove this interrupt, software must either clear write TBUF register (thus clearing TBMT bit). interrupt from receiver pending, remains pending, long both RBFL bits set. remove this interrupt, software must either clear read from RBUF register (thus clearing RBFL bit). BAUD CLOCK GENERATION clock inputs transmitter receiver sections USART individually selected come either from external source (port from source selected BAUD registers. Internally, basic baud clock created from MCLK through two-stage divider chain consisting 1-16 (increments 0.5) prescaler 11-bit binary counter (Figure 23). divide factors specified through read/write registers shown Figure Note that 11-bit Baud Rate Divisor spills over into Prescaler Select Register (PSR). cleared upon reset. shown Table Prescaler Factor corresponds CLOCK. This condition USART power down mode where USART clock turned power saving purpose. user must also turn USART clock when different baud rate chosen. correspondences between 5-bit Prescaler Select Prescaler factors shown Table There many ways calculate divisor factors, particularly effective method would achieve 1.8432 frequency coming first stage. 1.8432
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USART
(Continued)
Prescaler Select 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
Prescaler Factor 10.5 11.5 12.5 13.5 14.5 15.5
prescaler output then used drive software programmable baud rate counter create clock following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 38400 (Table 18). Other baud rates created using appropriate divisors. clock then divided provide rate serial shift registers transmitter receiver. TABLE Baud Rate Divisors (1.8432 Prescaler Output) Baud Rate (110.03) 134.5 (134.58) 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor (N-1) 1046
Note: entries Table assume prescaler output 1.8432 MHz. asynchronous mode baud rate could high 625k.
DS101389-27
FIGURE USART BAUD Clock Generation
example, considering Asynchronous Mode crystal frequency 4.608 MHz, prescaler factor selected (4.608 2)/1.8432 entry available Table 1.8432 prescaler output then used with proper Baud Rate Divisor (Table obtain different baud rates. baud rate 19200 e.g., entry Table value from Table Baud Rate Divisor) Baud Rate 1.8432 MHz/(16 19200 divide performed because asynchronous mode, input frequency USART times baud rate. equation calculate baud rates given below. actual Baud Rate found from: 2)/(16 Where: Baud Rate crystal frequency Baud Rate Divisor (Table Prescaler Divide Factor selected value Prescaler Select Register (Table Note: Synchronous Mode, divisor replaced two. Example: Asynchronous Mode: Crystal Frequency Desired baud rate 19200 Using above equation calculated first. 2)/(16 19200) 32.552 32.552 divided each Prescaler Factor (Table obtain value closest integer. This factor happens 6.5).
TABLE Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 Prescaler Factor CLOCK
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USART
(Continued)
32.552/6.5 5.008 programmed value (from Table should
Using above values calculated 2)/(16 6.5) 19230.769 error (19230.769 19200) 100/19200 0.16%
DS101389-28
FIGURE USART BAUD Clock Divisor Registers EFFECT HALT/IDLE USART logic reinitialized when either HALT IDLE modes entered. This reinitialization sets TBMT flag resets read only bits USART control status registers. Read/Write bits remain unchanged. Transmit Buffer (TBUF) affected, Transmit Shift register (TSFT) bits one. receiver registers RBUF RSFT affected. device will exit from HALT/IDLE modes when Start character detected (L3) pin. This feature obtained using Multi-Input Wakeup scheme provided device. Before entering HALT IDLE modes user program must select Wakeup source pin. This selection done setting WKEN (Wakeup Enable) register. Wakeup trigger condition then selected high transition. This done WKEDG register (Bit one). device halted crystal oscillator used, Wakeup signal will start chip running immediately because finite start time requirement crystal oscillator. idle timer (T0) generates fixed (256 delay ensure that oscillator indeed stabilized before allowing device execute code. user consider this delay when data transfer expected immediately after exiting HALT mode. DIAGNOSTIC Bits CHL0 CHL1 register provide loopback feature diagnostic testing USART. When both bits one, following occurs: receiver input (RDX) internally connected transmitter output (TDX); output Transmitter Shift Register "looped back" into Receive Shift Register input. this mode, data that transmitted immediately received. This feature allows processor verify transmit recei
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