4-Bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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4-Bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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SH6614
4-Bit Microcontroller with Driver
SH6610C-based single-chip 4-bit microcontroller ROM: 4096 bits RAM: bits Operation voltage: 2.4V 6.0V CMOS bi-directional pins 4-Level subroutine nesting (include interrupts) 8-bit auto re-load timer/counter Wem-up timer power-on reset Powerful interrupt sources: External interrupts INT0 Internal interrupt (Timer0) Internal interrupt (Base Timer) Port's falling edge interrupt: PORTB INT1 8-bit Base timer driver: dots (1/8 duty bias) dots (1/4 duty bias) used scan output Built-in dual tone with noise generator Clock sources OSC: (code option select crystal type) Crystal oscillator 32.768K oscillator: 262K OSCX: (system register selected ceramic type) Ceramic oscillator 455K oscillator 1.8M Instruction cycle time: 122.07µs 32.768 crystal 15.27µs 8.79µs 455KHz ceramic 2.22µs power operation modes: HALT STOP power consumption
General Description
SH6614 single chip microcontroller integrated with SRAM, timer dual-tone PSG, driver, port. This chip builds dual-oscillator enhance total chip performance.
Configuration
QFP64
OSCXI OSCXO OSCO OSCI COM1 COM2 COM3 COM4 COM5 COM6 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
SH6614
V2.1
SH6614
QFP100
COM8 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18
RESET TEST SEG1 SEG2
SH6614
Configuration
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4
COM6/SEG33 COM5/SEG34 COM4 COM3 COM2 COM1 OSCI OSCO PC.0 OSCXO OSCXI PA.0 PA.1 PA.2
SH6614
SH6614
Block Diagram
(4096 (512 SH6610C CORE OSCS 8-BIT TIMER0 PORTB
OSCI OSCO OSCXI OSCXO PORTB [0:3] PA.1 (PSG) PA.0 (INT0 PA.2 (PSG) PA.3 [1:8]
PORTA EXTERNAL
RESET
COMMON DRIVER SEGMENT
DRIVER SCAN REGISTER
[1:34]
OPERATING VOLTAGE VOLTAGE GENERATOR
SH6614
Description (QFP64)
Designation SEG30 SEG25 SEG24 SEG1 TEST RESET Port Port Port Port OSCXI OSCXO OSCO OSCI COM1 COM4 COM5 COM8 Description Segment signal output display; shared with scan output Segment signal output display; shared with scan output Connected with external divided resistance Test (Internal pull-low). connect user Reset input internal pull-up) Power supply programmable ,Vector interrupt INT1 programmable I/O,PA.0 shared with INT0 PA.1 PA.2 shared with output Oscillator input Oscillator output Ground Oscillator output Oscillator input Common signal output display Common/segment signal output display
Description (QFP100)
Designation SEG17 SEG1 SEG30 SEG18 TEST RESET Port Port Port Port OSCXI OSCXO OSCO OSCI COM1 COM4 COM5 COM8/SEG34 SEG31 Description Segment signal output display; shared with scan output Segment signal output display; shared with scan output Connected with external divided resistance Test (Internal pull-low). connect user Reset input internal pull-up) Power supply programmable ,Vector interrupt INT1 programmable I/O,PA.0 shared with INT0 PA.1 PA.2 shared with output Oscillator input Oscillator output Ground Oscillator output Oscillator input Common signal output display Common/segment signal output display
SH6614
Description
Designation SEG1 SEG30 TEST RESET Port Port Port Port OSCXI OSCXO OSCO OSCI COM1 COM4 COM5 COM8/SEG34 SEG31 Description Segment signal output display; share with scan output Connected with external divided resistance Test (Internal pull-low). connection user Reset input internal pull-up) Power supply programmable I/O, Vector interrupt INT1 programmable I/O, PA.0 shared with INT0 PA.1, PA.2shared with output Oscillator input Oscillator output Ground Oscillator output Oscillator input Common signal output display Common/segment signal output display
SH6614
Functional Description
core contains following function blocks: Program Counter, ALU, Carry Flag, Accumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPL), Stack. 1.1. (Program Counter) used addressing consisting 12-bits: Page Register (PC11), Ripple Carry Counter (PC10 PC0). program counter normally increases (+1) with each execution instruction except following cases: When executing jump instruction (such JMP, BA0, BC), When executing subroutine call instruction (CALL), When interrupt occurs, When chip INITIAL RESET. program counter loaded with data corresponding each instruction. unconditional jump instruction (JMP) 1-bit page register higher than Program Counter only address program ROM. 1.2. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) SH6614 address 4096 program area $000 $FFF. There area from addresses $000 through $004 that reserved special interrupts service routines such starting vector address. Address 000H 001H 002H 003H 004H Instruction Instruction Instruction Instruction Instruction Instruction Function Jump RESET service routine Jump INT0 service routine Jump Timer0 service routine Jump Base Timer service routine Jump INT1 service routine Decimal adjustment addition/subtraction (DAA, DAS), Logic operations (AND, EOR, ANDI, EORI, ORI) Decision (BA0, BA1, BA2, BA3, BAZ, Carry Flag (CY) holds arithmetic operation overflow. During interrupt call instruction, carry pushed into stack restored from stack RTNI. unaffected RTNW instruction. 1.3. Accumulator accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transfers between accumulator system register, RAM, data memory performed. 1.4. Stack This group registers used save contents sequentially with each subroutine call interrupt. organized bits levels. saved Four levels maximum allowed subroutine calls interrupts. contents Stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds where then bottom stack will shifted out.
SH6614
Built-in SRAM contains general-purpose data memory, RAM, system registers. They accessed direct addressing instruction. following memory allocation map: $000 $01F: System register I/O; $020 $1FF: Data memory (480 4bits, partitioned into banks). $300 $321, $328 $345, $350 $36D: space bits bits). configuration system register Address Bit3 IRQX TM0.3 BTM.3 T0L.3 T0H.3 PA.3 PB.3 PACR.3 PBCR.3 TBR.3 INX.3 DPL3 PPULL LPS1 C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 SEL1 Bit2 IET0 IRQT0 TM0.2 BTM.2 T0L.2 T0H.2 PA.2 PB.2 PACR.2 PBCR.2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 PAM2 LPS0 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 SEL0 Bit1 IEBT IRQBT TM0.1 BTM.1 T0L.1 T0H.1 PA.1 PB.1 PC.1 PACR.1 PBCR.1 TBR.1 INX1 DPL1 DPM.1 DPH.1 PAM1 LCDOFF C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN Bit0 IRQP TM0.0 BTM.0 T0L.0 T0H.0 PA.0 PB.0 PC.0 PACR.0 PBCR.0 TBR.0 INX.0 DPL0 DPM.0 DPH.0 OXON DUTY C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN Function Interrupt enable flags Interrupt request flags Timer0 mode register Base timer mode register Timer0 load/counter nibble Timer0 load/counter high nibble Reserved PORTA PORTB Bonding option PORTA output port PORTB output port Reserved Table branch register Index register (INX) Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit1, 2:PA.1 PA.2 output PORT Bit0: Heavy load mode Bit3: Port pull-up control Bit0: Turn OSCX oscillator Bit1: clocks select (1:OSC /0:OSC) Bit3: OSCX type selection Bit0: Slect DUTY (1/8 1/4) Bit1: Bit2, 3:LCD frequency control Bit2: segment output Bit3: Power degrade channel nibble channel 1high nibble Bit3: channel octave shift control channel nibble alarm output channel nibble channel nibble channel nibble Bit3: channel octave shift control Bit0, Bit1: Channel enable Bit2, Bit3: volume control Bit0, PSG1, PSG2 mode control Bit2, PSG1, PSG2 clock source selection Reserved Initial Value 0000 0000 0000 0000 0000 0000 0000 0000 (default) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
System Register $12. (Please refer SH6610C User's manual)
SH6614
Data memory general purpose data memory organized bits. Because static feature, retain data after enters STOP HALT mode. Oscillator circuit 5.1. Circuit Configuration SH6614 on-chip oscillation circuits OSCX. frequency crystal (Typ. 32.768KHz) (Typ.262KHz) determined code option. This designed frequency operation. OSCX also types: ceramic (Typ.455KHz) (1.8M 2MHz) determined software option. designed high frequency operation. possible select high speed processing high frequency clock select power operation operation clock. start reset initialization, starts oscillation OSCX turned off. Immediatly after reset initialization, clock automatically selected system clock input source.
Oscillator Block Diagram
OSCI OSCO Frequency Clock Oscillator System clock Source Selector OSCXI OSCXO High Frequency Clock Oscillator
Switching control System clock
Base Timer
Generator
Clock
Timing System Clock Switching
SH6614
5.2. oscillation generates basic clock pulses that provides peripherals (Timer0, LCD) with operating clock. Crystal oscillator type
STOP OSCI 32768Hz OSCO 5-6p
oscillator type
RBIAS
OSCI
STOP
Ring Oscllator
OSCO
5.3. OSCX oscillation OSCX clock oscillators. software options selects ceramic CPU's subclock. OSCX ceramic oscillator type
CPUSTOP
OSCXI
455KHz Ceramic OSCXO
OSCX oscillator type
OSCX used, must masked ceramic resonator OSCXI must connected GND.
RBIAS CPUSTOP
OSCI
Ring Oscllator
OSCO
SH6614
5.4. Control oscillator oscillator control register configuration shown follows: Address Bit3 Bit2 Bit1 Bit0 OXON
OXON: OSCX oscillation on/off. Turn-off OSCX oscillation OXM: switching system clock. select system clock OXS: OSCX oscillator type selection OSCX ceramic oscillator 5.5. Programming notes
Turn-on OSCX oscillation select OSCX system clock OSCX oscillator
takes least OSCX oscillation circuit turn until oscillation stabilizes. When switching system clock from OSCX, user must wait minimum since OSCX oscillation running. However, start time varies with respect oscillator characteristics condition use. Thus wait time depends application. When switching from OSCX OSC, turning OSCX instruction. OSCX turn control will delayed instruction cycle automatically prevent operation error. System clock system clock varies clock source changes. following table shows instruction execution time according each frequency system clock source. 32.768 Xtal (OSC Cycle time PORTs provides 8bi-directional pins. Each contains pull-up controllable through programming. When every used input, PORT control register (PACR, PBCR) controls ON/OFF output buffer. 7.1. PORTA These ports contain 8bi-directional ports. circuit configuration PORTA shown
PULLUP PULL_UP PMOS
262K (OSC 17.778
455K ceramic Xtal (OSCX) 8.79
1.8M (OSCX) 2.22
RC(OSCX)
122.07
PORT CONTROL REGISTER PORTX PORT DATA REGISTER
DATAINPUT RD_INPUT
ports SH6614 accessed read/write system register. User output value port time. Memory addresses listed follows: Address Bit3 PORTA.3 PORTB.3 Bit2 PORTA.2 PORTB.2 Bit1 PORTA.1 PORTB.1 Bit0 PORTA.0 PORTB.0
SH6614
7.2. Controlling pull-up PORTA, PORTB contain pull-up controlled program. Bit3 PMOD register controls on/off pull-up simultaneously. Pull-up also controlled port data registers (PA, each port well. Thus pull-up turned on/off. 7.3. Port Interrupt PORTB interrupt (falling edge) controlled Port register. This means that interrupt request (IEx port high goes low) been touched therefore condition other port bits high level whenever port output input. 7.4. External INT0 PortA.0 shared external interrupts (active low). 7.5. Port control register: Address Bit3 PACR.3 PBCR.3 Bit2 PACR.2 PBCR.2 Bit1 PACR.1 PBCR.1 Bit0 PACR.0 PBCR.0
control register: PACR.X, PBCR.X output buffer. input buffer (initial power-on). 7.6. Port mode register (PMOD) Address PAM1, PAM2: HLM: PPULL: Bit3 PPULL Bit2 PAM2 Bit1 PAM1 Bit0 Function Bit1, 2:Select PA.1, PA.2 port output Bit0:Hevey load mode Bit3:Port pull-up control Enable Enable pull-up
Please Enable heavy load mode Disable Port pull-up Disable pull-up
7.7. Heavy load mode (HLM) heavy load protection circuit when battery load becomes heavy, such when external buzzer sounds external speaker turned this mode, crystal oscillator circuit been backup high gain. When setup this mode, more power would provided oscillator circuit. Unless nessary, careful this mode with software since mode enter would delay instruction. Please activate heavy load driving only after setting least instruction wait cycle through software. following shows programming setting. HLM: Heavy load protection mode released Heavy load protection mode set.
HEAVYLOAD
Instruction Cycle Time
SH6614
Programmable sound generator (PSG) channel1 channel2. function block diagram shown follows:
CHANNEL1 OSCX CHANNEL2 MIXER
function provides four subfunctions wide applications. Programmable sound Program sound created channels. Every channel programmed follows: Enable/Disable every channel sounds. Select every channel sound frequency. channel sounds mixed into output. output controlled volume levels. Fine noise provide wide-band noise. wide-band noise volume controlled volume levels. Alarm provide many alarm functions software. alarm carrier frequency programmed individually. alarm volume controlled volume levels. Remote control remote control only expandable application sound. Since remote control frequency 56.13KHz 37.92KHz, software select sound frequency. 8.1. subblock diagram block diagram
SEL0 SEL1
CLK-SLECTOR
OSCX
SEL1
SEL0
source OSC/2 OSCX OSCX/16
32.768K 262K 32.768K 262K OSCX 1.8M OSCX 455K OSCX 1.8M OSCX 455K
32.768K 262K 16.384K 131K 1.8M 455K 112.5K 28.4K
block selects clock sources that provides channel sources.
SH6614
Channel
CH1EN
OCT1
REGISTER C1.6 C1.0
SELECTOR
DIVIDER
OCT1 Channel
Scaling ratio
Channel constructed 7-bit pseudo random counter. Channel enabled/disabled CH1EN. creates either sound frequency alarm carrier frequency remote carrier frequency.
CH2EN OCT2 NOISE GENERATOR
C2.14 C2.0
SELECTOR
SELECTOR
REGISTER C2.14 C2.0
C2.14 C2.8
DIVIDER
C2.3 C2.0
32Hz ENEVLOP ENEVLOP
OCT2
Scaling ratio
Channel constructed 15-bit pseudo random counter. Channel enabled/disabled CH2EN 15-bit wide-band noise generator 7-bit sound generator. also create alarm envelope signal.
Sound generator. Sound generator. Sound generator.
Function Sound generator. Noise generator. Alarm mode register.
SH6614
Mixer
TIME SLOT VOL0 VOL1 PA.1 TIME SLOT CONTROL PA.2 PAM2 SELECTOR2 PA.2 SELECTOR1 PA.1
PAM1
MIXER mixes CH1-OUT CH2-OUT into tone output PA.1 PA.2, when PAM1 1PAM2 Then tone output controlled volume control into volume levels outputted PSG. PA.1 PA.2 controlled PAM1 PAM2 PAM2 PAM1 PA.1:I/O PORT PA.1:PSG output PA.1:I/O PORT PA.1:PSG output Function PA.2: PORT PA.2: PORT PA.2: output PA.2: output
SEL1
SEL0
Vol. control
VOL1
VOL0
Vol. Level
Note: user should enable channels together produce tone, otherwise will produce some unpredictable errors. necessary channels together (ie: play channel melody), allow score always same tones, then unpredicted errors will occur will ignored user.
SH6614
value divider1 corresponding C1.6 C1.0 C2.14 C2.8 shown following table: LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8)
SH6614
8.2. Function description sound generator programmable sound working modes. software designer select clock sourcees clk. then select frequency divided value that controlled value C1.6 C1.0 C2.14 C2.8.The user select volume level controlled VOL0, VOL1. music tone output both user also control OCT1, OCT2 that shifts music tone octaves. Example CH1EN CH2EN OSCX 1.8M, SEL0 SEL1 112kHz; Switch 28kHz Vol. 112kHz Example CH1EN CH2EN OSCX 1.8M, SEL0 SEL1 112kHz; Switch 28kHz; Vol. 112kHz
Example CH1EN CH2EN 32k, SEL0 SEL1 32kHz; Switch 32kHz vol. control, level hardware, software should VOL0 VOL1
Note: 32KHz operations, volume control cannot used, since multiplexing frequency high enough switch sound! user wants turn completely, software must disable both channels. user should turn zero wave from output. Both CH1EN CH2EN should power operation mode. Example software designer wants create (Channel mixed with (Channel sound (For sound frequency please refer Music Table Music Table level 3.Then user select suggestion follows: user first selects CH1EN CH2EN user select OSCX 1.8M SEL0 SEL1 112.5KHz. Then user select OCT1 value channel LSFR (C1.6 C1.0) 108. Please Music Table 1.So channel sound frequency 112.5Khz/8/ 108) 64.10Hz sound frequency. Then user select OCT1 value channel LSFR (C1.6 C1.0) Please refer Music Table 1.So channel sound frequency 112.5Khz/1/ 694.4Hz sound frequency Lastly, user should select VOL1 VOL0 level
SH6614
Note: designer provides crossing tables appendix since designer prefers 32.768K 112.5K. noise generator Fine noise created CH2. user wants create single noise, then make music tone output. Otherwise, user wide-band noise music tone into output through MIXER. Lastly, user select volume levels controlled VOL0, VOL1. alarm generator When alarm mode, provides alarm carrier frequency provides alarm envelope signal. Lastly user select volume levels controlled VOL0, VOL1. channel nibble C2.0 C2.3 will alarm control register. Channel output would modulate with ALARM envelope control 32KHz 262KHz. carrier frequency programmed channel 1.In reading this alarm control register, user read corresponding output envelope frequency (the 1Hz, 4Hz, 8Hz, 32Hz). Alarm control register (OSC 32KHz 262KHz) C2.3 C2.2 C2.1 C2.0 Alarm output control envelop output output output 32Hz output
Figture: Alarm modulation output 32.768KHz 262KHz.
remote control remote control only expandable application sound. user select tone output will create alarm frequency envelope signal. When channel programmed ALARM mode, programmer ALARM mode register "0000B". Program adequate frequency output output. Then PAM1 PAM2 control envelope code. this way, remote control function implemented easily. remote frequency 56.73KHz 37.92KHz. software should select OSCX 455KHz, SEL0 that 455KHz. Then select channel alarm mode (C1M OCT1 C2.0 C2.3 00H. VOL1, VOL2 Then select C1.6 C1.0 that output frequency 455KHz/1/ 37.92KHz. select C1.6 C1.0 that output frequency 455KHz/1/ 56.87KHz.
SH6614
Timer SH6614 8-bit timer. timer consists 8-bit counter 8-bit preload register. timers provide following functions: Programmable internal timer function Read counter values 9.1. Timer configuration operation timer consists 8-bit write-only timer load register (TL0L, TL0H) 8-bit read-only timer counter (TC0L, TC0H). Each order digits high order digits. timer counter initialized writing data into timer load register (TL0L, TL0H). Write low-order digit first then high-order digit. timer counter loaded with content load register automatically when high order digit written counts overflow happens. timer overflow will generate interrupt, interrupt enable flag set. timer programmed several different system clock sources setting Timer Mode register (TM0). Timer reads writes operations follow these rules: Write Operation nibble first High nibble update counter 9.2. Timer0 mode register (TM0) 8-bit counter counts prescaler overflow output pulses. 4-bit registers used timer control shown Table register selects input clock sources timer. Table Timer0 Mode registers ($02) TM0.3 TM0.3 control function: without Auto-Reload function 9.3. Warm-up counter mode, warm-up counter prescaler divided (128). CRYSTAL mode, warm-up counter prescaler divided (65536).
Read Operation High nibble first nibble follows
TM0.2
TM0.1
TM0.0
Prescaler /2048 /512 /128 External
Clock Source System clock System clock System clock System clock System clock System clock System clock INT0
Auto-Reload function
SH6614
Base Timer base timer that shared with warm-up timer clock source (Low frequency oscillation: X'Tal 32.768KHz 262KHz). After reset, counts every clock-input signal. When counts $FF, right after next clock input, counter counts generates overflow This causes interrupt base timer interrupt request flag 1.Therefore, base timer function interval timer periodically, generating overflow output every 256th clock signal output. timer accepts 4096Hz 32KHz clock, base timer generates accurate timing interrupt. This base time prescaler reset program accurate timing. This clock-input source selected Bregister. Address Bit3 BTM.3 Bit2 BTM.2 Bit1 BTM.1 Bit0 BTM.0 Function Base timer mode register
BTM.3 Disable base timer BTM.2 reset base timer BTM.1 BTM.0
BTM.3 Enable base timer BTM.2 reset base timer Prescaler Ratio Clock source 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz
B[3]
base timer counter reset
262k
4096/32K
4Bit Scaler
B[2]
SH6614
Driver driver contains controller, voltage generator, common signal pins segment driver pins. There different driving modes programmable: duty bias, other duty bias. driving mode controlled system register power-on initialization status duty, bias. When duty bias mode used, COM5 used SEG34 SEG1 also used output port, selected system register $16. When SEG1 output port, data must written same addresses (350H-36DH). could used data memory needed. When "STOP" instruction executed, will turned off, data keeps same value before executing "STOP" instruction. 11.1. Control Register Add. LPS1 LPS0 LCDOFF DUTY
LCDOFF: on/off switch. off. DUTY: duty control duty, bias duty, bias LPS1, LPS0: clock frequency control 0,0: LCDCLK OSC/64 0,1: LCDCLK OSC/512 1,0: LCDCLK System clock/512 1,1: LCDCLK System clock/4096 *System clock Instruction cycle time Frame frequency LCDCLK/16 Frame frequency duty; duty same frequency cycle. Frequency 32kHz 32kHz, 32kHz 32kHz, 32kHz 32kHz, 262kHz 262kHz, 262kHz 262kHz, 262kHz 262kHz, OSCX 455kHz OSCX 455kHz OSCX 1.8MHz OSCX 1.8MHz OSCX 2MHz OSCX 2MHz OSCX 455kHz OSCX 455kHz OSCX 1.8MHz OSCX 1.8MHz OSCX 2MHz OSCX 2MHz LPS1, LPS0 32Hz 32Hz 32Hz 32Hz 32Hz 32Hz 256Hz 256Hz 256Hz 256Hz 256Hz 256Hz 32Hz 32Hz 32Hz 32Hz 32Hz 32Hz 14Hz 55Hz 61Hz 14Hz 55Hz 61Hz 1/8Hz 1.7Hz 1/8Hz 6.9Hz 1/8Hz 7.6Hz 1.7Hz 6.9Hz 7.6Hz
before selected system clk. Frame frequency LCDCLK/16 (32Hz) When SCAN OUT, COMx pulled high. easy implement keyboard scan. When STOP mode, COMx SEGx pulled low. easily woken keyboard scan (Port interrupt). When HALT mode, COMx SEGx normal. easily woken base timertimer0 port interrupt.
SH6614
11.2. power
LCDOFF Power Switch Power Supply Control Circuit seg1 segment driver scan output seg34 common driver com1 com8
LPS0 SYSCLK/512 LPS1 OSC/64
DUTY LCDCLK Scaler
Built-in special power control power modulation. Address
O/S: segment/common segment output output ports segment output output ports. When voltage power will degraded about 0.5V, depending level. designed reduce extra contrast control output pins. Then fitted automatically different voltage levels software. 11.3. Configuration duty, bias (COM1 SEG1 Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Address 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Bit3 COM4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit2 COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit1 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit0 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SH6614
duty, bias (COM1 SEG1 Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Address 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
SEG1-30 used scan output port. Address 350H 351H 352H 353H 354H 355H 356H 357H Bit0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 Address 358H 359H 35AH 35BH 35CH 35DH 35EH 35FH Bit0 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 Address 360H 361H 362H 363H 364H 365H 366H 367H Bit0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 Address 368H 369H 36AH 36BH 36CH 36DH Bit0 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
SH6614
11.4. waveform
DUTY BIAS SELECT UNSELECT SELECT UNSELECT SELECT UNSELECT
DUTY BIAS SELECT UNSELECT
Example Duty Bias
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG1 SEG30 FRAME CYCLE
This example
SEG1 SEG30 COM1, COM3, COM5, COM7 lighting. SEG1 SEG30 COM2, COM4, COM6, COM8 lighting.
SH6614
Interrupt interrupt sources available SH6614: External interrupt INT0 Timer0 interrupt Base timer interrupt Port's falling edge detection interrupt INT1 configuration system register Address IRQX IET0 IRQT0 IEBT IRQBT IRQP Function Enable Disable Request request
12.1. External Interrupt INT0 External interrupt shared with PA.0, falling edge active. When register (IEX) external interrupt enabled, writing PA.0 will generate external interrupt. 12.2. Timer interrupt, Base timer interrupt, Port interrupt INT1 then valid interrupt requests will cause interrupt. overflow timer will create interrupt timer 0.The overflow Base timer will create interrupt Base timer. falling edge every port PORTB will create INT1 interrupt (The condition that other port must input/output high level). 12.3. Enable flags Request flags Both Enable flags Request flags read written software. Request flags will hardware interrupt Enable flags will reset hardware when interrupt service routine entered. 12.4. Interrupt Servicing Sequence Diagram: SH6610C interrupt services routine, user enable interrupt enable flag before returning from interrupt. frequently asked question when next interrupt would serviced? Will nesting interrupt happen? From servicing sequence timing diagram, interrupt request ready instruction execution enable. Then interrupt start right after next instructions: instruction disable interrupt request enable flag, then interrupt service sequence would terminated.
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
SH6614
Options Bonding options System register reserved user. available system developer select bonding options, selecting subprogram programmed user. $0A.1 (PC.1) $0A.0 (PC.0) goto subroutine goto subroutine Default goto subroutine goto subroutine
PC.0 PC.1 PC.0
PC.1
PC.0
PC.1
PC.0 PC.1
PC.0 PC.1 PC.0
PC.1
PC.0
PC.1
PC.0 PC.1
SH6614 Bonding Option STOP/HALT mode STOP/HALT mode STOP (STOP instruction) Oscillator OSCX Stop HALT (HALT instruction) OSCX live Hold Hold INT0 INT1 INT0 INT1 T0INT BTINT core Wake Executing after wake signal valid, system will reset. INT0 INT1 signal valid, system will enter interrupt subroutine, then execute main program continue. signal valid, system will reset. INT0 INT1 T0INT BTINT signal valid, system will enter interrupt subroutine first, then execute main program continue.
SH6614
Instruction instructions cycle word instructions. characteristic memory-oriented operation. Arithmetic Logical Instruction Accumulator type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 xxxx 01001 xxxx 01010 xxxx 01011 xxxx 01100 xxxx 01101 xxxx 01110 xxxx Function Flag Change Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
shift right
assembler ASM66 V1.0, EORIM memonic EORI. However, EORI same operation identical with EORIM. Same ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function Decimal adjust add. Decimal adjust sub. Flag Change
SH6614
Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 xxxx Function Flag Change
Control Instruction Mnemonic CALL RTNW RTNI HALT STOP TJMP Where Program counter Accumulator Complement accumulator Carry flag Data memory Immediate data Logical exclusive Logical Logical bank page Stack Table Branch Register Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-C8) (TBR) (AC) Function Flag Change
(Not include
hhhh;
Operation
SH6614
Absolute Maximum Rating*
Supply Voltage -0.3V 7.0V Input Voltage -0.3V 0.3V Operating Ambient Temperature Storage Temperature
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrocal Characteristics
(VDD 3.0V, FOSC 32.768KHz, FOSCX used, unless otherwise specified) Parameter Operating Voltage Operating Current Voltage Divider Resistor Standby Current Standby Current Input High Voltage Input Voltage Drive-high Resistance Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Lighting Symbol RLCD ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 ILCD Min. 0.85 -0.3 Typ. Max. 0.15 Unit output pins unload (HALT mode) excluding bias current output pins unload (STOP mode), PORTA, PORTB INT0 RESET PORTA, PORTB INT0 RESET PORTA, PORTB (IOH -10µA, PORTA.0, PORTA.3, PORTB (IOH -2mA) PORTA.0, PORTA.3, PORTB (IOL 2mA) PORTA.1, PORTA.2 output, -5mA PORTA.1, PORTA.2 output, SEGx, 50P, rise time 1000ns SEGx SEG1 30to output port, -1mA SEG1 30to output port, COMx, -1mA COMx, excluding core operation current output pins unload execute instruction excluding bias current Conditions
Operation frequency ISB1 ISB1X (Frequency/32.768KHz) ISB1 0.8, (VDD 3.0V). Operation frequency IOPX (Frequency/32.768KHz) 0.8, (VDD 3.0V). IOP, ISB1 ISB2 IOPX ISB2X ISB2
SH6614
Electrocal Characteristics
(VDD 5.0V, FOSC 32.768KHz, FOSCX used, unless otherwise specified) Parameter Operating Voltage Operating Current Voltage Divider Resistor Standby Current Standby Current Input High Voltage Input Voltage Drive-high Resistance Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Lighting Symbol RLCD ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 ILCD Min. 0.85 -0.3 Typ. Max. 0.15 Unit output pins unload (HALT mode) excluding bias current output pins unload (STOP mode), PORTA, PORTB INT0 RESET PORTA, PORTB INT0 RESET PORTA, PORTB (IOH -10µA, PORTA.0, PORTA.3, PORTB (IOH -3mA) PORTA.0, PORTA.3, PORTB (IOL 3mA) PORTA.1, PORTA.2 output, -7mA PORTA.1, PORTA.2 output, SEGx, 50P, rise time 1000ns SEGx SEG1-30to output port, =-1mA SEG1-30to output port, =1mA COMx, -1mA COMx, 5.0V, excluding core operation current output pins unload execute instruction excluding bias current Conditions
Operation frequency ISB1 ISB1X (Frequency/32.768KHz) ISB1 0.8, (VDD 5.0V). Operation frequency IOPX (Frequency/32.768KHz) 0.8, (VDD 5.0V). IOP, ISB1 ISB2 IOPX ISB2X ISB2
SH6614
Characteristics (VDD 3.0V, FOSC 32.768KHz, unless otherwise specified)
Parameter Oscillation Start Time Frequency Stability Symbol tSTT |F|/F Min. Typ. Max. Unit [F(3.0)-F(2.5)] (3.0), crystal oscillator Conditions
Characteristics (VDD 5.0V, FOSC 32.768KHz, unless otherwise specified)
Parameter Oscillation Start Time Frequency Stability Symbol tSTT |F|/F Min. Typ. Max. Unit [F(5.0)-F(4.5)] (5.0), crystal oscillator Conditions
Characteristics (VDD 3.0V, FOSC 262KHz, FOSCX stop, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |F|/F Min. Typ. Max. Unit [F(3.0)-F(2.5)] (3.0), Bias resistance accuracy within Conditions
Characteristics (VDD 4.5V, FOSC 262KHz, FOSCX stop, unless otherwise specified)
Parameter Frequency Stability Symbol |F|/F Min. Typ. Max. Unit Conditions [F(4.5)-F(3.6)] (4.5), Bias resistance accuracy within
SH6614
Typical Oscillator Resistor VDD:
(Reference only)
Typical Oscillator Frequency VDD:
(Reference only)
262KHz
(Volts)
919K
(KHz)
(Volts)
1.8MHz
2100 (KHz) 1900 1700 1500 1300
(Volts)
(Volts)
108K
2.0MHz
(Volts)
2300 (KHz) 2100 1900 1700
(Volts)
SH6614
Application Circuit (for reference only)
AP1: OSC: Crystal oscillator 32.768KHz (mask option) OSCX: Ceramic oscillator 455KHz PORTB: PORTA.1, PORTA.2: ALARM output LCD: Internal duty, bias
duty bias
OSCXI 455KHz OSCXO
RESET
SH6614
PORTB OSCO
PORTA.1
BUZZER
32768Hz OSCI TEST PORTA.2
AP2: OSC: oscillator 262KHz (mask option) LCD: Internal duty, bias PORTA, PORTB: PORTA.0: External interrupt
duty bias
OSCXI OSCXO
RESET PORTA PORTB OSCO 930K OSCI TEST
SH6614
PORTA.0
Ext.int
SH6614
AP3: OSC: Crystal oscillator 32.768KHz (mask option) OSCX: oscillator 1.8MHz PORTB: PORTA.1: output PORTA.2: output
RESET
OSCXI OSCXO
120K (VDD
SPEAKETR
PORTB OSCO
SH6614
PORTA.1
8050
32768Hz OSCI TEST
PORTA.2
AP4: Internal bias.1/8 DUTY bias
COM1 COM8 SEG30
PANNEL
BOARD
SEG1 SEG4 SCAN outport
SH6614
SEG4 SEG3 SEG2 SEG1 PORTB0 PORTB1 PORTB2 PORTB3
SH6614
AP5: Large pannel: External bias
Bias Bias Normal pannel Bias Large pannel Ext.R SH6614 SH6614 Ext.R Ext.R Ext.R SH6614 Ext.R Bias Large pannel Ext.R
floating
SH6614
Music Table
Following music scale reference table channel channel under OSCX 1.8MHz. octaves possible) Music scale data 1.8M OSCX SEL0 SEL1 Note Ideal freq. 61.73 65.10 69.29 73.42 77.78 82.41 87.31 92.50 98.00 110.00 123.47 130.81 146.83 164.81 174.61 184.99 196.00 220.00 246.94 261.63 293.66 329.63 349.23 369.99 392.00 440.00 493.88 LSFR OCT1 Real (C1.6~C1.0) freq. Error% Note /OCT2 (C2.14~C2.8) 61.68 -0.08 65.10 69.62 73.24 78.13 82.72 86.81 92.52 97.66 103.40 109.86 117.19 123.36 130.21 137.87 146.48 156.25 163.52 175.78 185.03 195.31 206.80 219.73 234.38 251.12 260.42 281.25 292.97 305.71 334.82 351.56 370.07 390.63 413.60 439.45 468.75 502.23 0.01 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.40 -0.13 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.79 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 Ideal freq. 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 1046.48 1108.71 1174.63 1244.48 1318.48 1396.88 1479.95 1567.95 1661.18 1759.96 1864.62 1975.49 2092.96 2217.41 2349.27 2488.96 2636.96 2793.77 2959.89 3135.90 3322.37 3519.93 3729.23 3950.98 LSFR OCT1/ Real Error% (C1.6~C1.0) OCT2 freq. (C2.14~C2.8) 493.42 -0.09 520.83 556.93 585.94 625.00 661.77 694.44 740.13 781.25 827.21 878.91 937.50 986.84 1041.67 1102.94 1171.88 1250.00 1308.14 1406.25 1480.26 1562.50 1654.41 1757.81 1875.00 2008.93 2083.33 2250.00 2343.75 2445.65 2678.57 2812.50 2960.53 3125.00 3308.82 3515.63 3750.00 4017.86 -0.46 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.41 -0.12 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.78 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69
103.82 116.54
138.59 155.56
207.65 233.08
277.18 311.12
415.30 466.15
SH6614
Music Table
Following music scale reference table channel channel under 32.768KHz. octaves possible) Music scale data SEL0 SEL1 Note Ideal freq. 55.00 58.27 61.73 65.41 69.29 73.42 77.78 82.41 87.31 92.50 98.00 LSFR OCT1 (C1.6~C1.0) /OCT2 (C2.14~C2.8) Real freq. 55.35 58.51 62.06 66.07 68.27 73.14 78.77 81.92 89.04 93.09 97.52 102.40 107.79 113.78 120.47 128.00 136.53 146.29 156.04 165.50 174.30 184.09 195.05 207.39 221.41 234.06 248.24 Error% Note 0.64 0.42 0.54 1.00 -1.48 -0.38 1.27 -0.60 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37 0.31 0.42 -0.18 -0.49 -0.49 -0.12 0.64 0.42 0.53 Ideal freq. 261.63 277.18 293.66 311.12 329.63 349.23 369.99 392.00 415.30 440.00 466.15 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 LSFR OCT1 Real Error% (C1.6~C1.0) /OCT2 freq. (C2.14~C2.8) 260.06 -0.60 277.70 292.57 309.13 327.68 348.60 372.36 390.10 420.10 442.81 468.11 496.49 528.52 546.13 585.14 630.15 655.36 712.35 744.73 780.19 819.20 862.32 910.22 963.77 1024.00 1092.27 1170.29 0.19 -0.37 -0.64 -0.59 -0.18 0.64 -0.49 1.16 0.64 0.42 0.53 1.01 -1.48 -0.37 1.27 -0.59 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37
103.82 110.00
116.54 123.47 130.81
138.59 146.83 155.56 164.81 174.61 184.99 196.00 207.65 220.00 233.08 246.94
1046.48
1108.71 1174.63
SH6614
Bonding Diagram
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 (0,0)
COM7/SEG32 COM6/SEG33 COM5/SEG34 COM4 COM3 COM2 COM1 OSCI OSCO PC.0
SH6614
1680µm
SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
OSCXO OSCXI PA.0 PA.1 PA.2
1800µm
Substrate connect bonding option bonding option Designation TEST RESET PORTC PORTB.3 PORTB.2 PORTB.1 PORTB.0 PORTA.3 PORTA.2 PORTA.1 PORTA.0 OSCXI OSCXO PORTC OSCO OSCI (µm) -770.00 -640.00 -520.00 -405.00 -290.00 -175.00 -60.00 55.00 180.00 175.95 295.00 410.00 525.00 640.00 770.00 900.00 900.00 900.05 900.00 900.00 806.05 907.60 900.00 900.00 900.00 900.00 900.00 900.00 900.00 900.00 (µm) -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -746.00 -848.90 -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -710.00 -590.00 -470.00 -355.00 -240.00 -248.05 -120.00 0.00 120.00 240.00 355.00 470.00 590.00 710.00 Designation [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] (µm) 900.00 770.00 640.00 520.00 405.00 290.00 175.00 60.00 -60.00 -175.00 -290.00 -405.00 -520.00 -640.00 -770.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 (µm) 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 710.00 590.00 470.00 355.00 240.00 120.00 0.00 -120.00 -240.00 -355.00 -470.00 -590.00 -710.00 -840.00
SH6614
Ordering Informations
Part SH6614H SH6614F SH6614F_64 Packages CHIP FORM
SH6614
Package Informations Outline Dimensions
unit: inches/mm
Detail Seating Plane
Detail
Symbol
Dimensions inches 0.130 Max. 0.004 Min. 0.112 0.005 0.016 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.039 0.006 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max.
Dimensions 3.30 Max. 0.10 Min. 2.85 0.13 0.40 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 1.00 0.15 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max.
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
SH6614
100L Outline Dimensions
unit: inches/mm
Detail Seating Plane
Detail
Symbol
Dimensions inches 0.130 Max. 0.004 Min. 0.112 0.005 0.012 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.026 0.006 0.742 NOM. 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max.
Dimensions 3.30 Max. 0.10 Min. 2.85 0.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 0.65 0.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max.
Notes: 1.Dimensions include resin fins. 2.Dimensions Board surface mount pitch design reference only.

4-Bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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