4-Bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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4-Bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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SH6613 SH6613B SH6613C
4-Bit Microcontroller with Driver
SH6610C-based single-chip 4-bit micro-controller ROM: bits RAM: bits Operation voltage: 2.4V 6.0V CMOS bi-directional pins 4-Level subroutine nesting (include interrupts) 8-bit auto re-load timer/counter Warm-up timer power-on reset Powerful interrupt sources: External interrupts INT0 Internal interrupt (Timer0). Internal interrupt (Base Timer). Port's falling edge interrupt: PORTB INT1 8-bit Base timer driver: dots(1/4 duty bias) used scan output
Built-in dual tone with noise generator Clock source OSC: (code option select crystal type) Crystal oscillator 32.768K oscillator: 262K OSCX: (system register select ceramic type) Ceramic oscillator 455K oscillator 1.8M Instruction cycle time: 122.07µs 32.768 crystal 15.27µs 8.79µs 455KHz ceramic 2.22µs power operation mode: HALT STOP power consumption
General Description
SH6613 (SH6613B, SH6613C) single chip microcontroller integrated with SRAM, timer dual-tone PSG, driver port. This chip builds dual-oscillator enhance total chip performance.
Diagram
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG33 SEG34 COM4 COM3 COM2 COM1 OSCI OSCO PC.0 OSCXO OSCXI PA.0 PA.1 PA.2
SH6613 SH6613B SH6613C
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Block Diagram
(4096X16) RAM(512X4) NT6610C CORE OSCS 8-BIT TIMER0 PORTB
OSCI OSCO OSCXI OSCXO PORTB[0:3] PA.1(PSG) PA.0(INT0 PA.2(PSG) PA.3 COM[1:4]
PORTA External
RESET
COMMON DRIVER SEGMENT
DRIVER SCAN REGISTER
SEG[1:34]
OPERATING VOLTAGE VOLTAGE GENERATOR
Description
Designation
Description
Segment signal output display; Share with scans output. Connect with external divided resistance Test (Internal pull-low). connect user. Reset input(No internal pull-up) Power supply. programmable ,Vector interrupt( INT1
1,2,27~58 SEG1~SEG34 10~13 VLCD,V1,V2,V3 TEST RESET Port B.3~Port
14~17 23~26
Port A.3~Port OSCXI OSCXO OSCO OSCI COM1~COM4
programmable I/O,PA.0 shared with INT0 PA.1 PA.2shared with output Oscillator input Oscillator output Ground Oscillator output Oscillator input Common signal output display
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SH6613/B/C
Functional Description
core contains following function blocks: Program Counter, ALU, Carry Flag, Accumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPL), Stack.
(Program Counter) used addressing consisting 12-bits: Page Register (PC11), Ripple Carry Counter (PC10 -PC0). program counter normally increases (+1) with each execution instruction except following cases: When executing jump instruction (such JMP, BA0, BAC), When executing subroutine call instruction (CALL), When interrupt occurs, When chip INITIAL RESET. program counter loaded with data corresponding each instruction. unconditional jump instruction (JMP) 1-bit page register higher than Program Counter only address program ROM. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
Decimal adjustment addition/subtraction (DAA, DAS), Logic operations (AND, EOR, ANDI, EORI, ORI) Decision (BA0, BA1, BA2, BA3, BAZ, BAC) Carry Flag (CY) holds arithmetic operation overflow. During interrupt call instruction, carry pushed into stack restored from stack RTNI. unaffected RTNW instruction.
Accumulator Accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transfers between accumulator system register, RAM, data memory performed. Stack group registers used save contents (11-0) sequentially with each subroutine call interrupt. organized bits levels. saved levels maximum allowed subroutine calls interrupts.
contents Stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds bottom stack will shifted out.
SH6613/B/C address program area $000 $FFF. There area from addresses $000 through $004 that reserved special interrupts service routines starting vector address.
Address Instruction Function
000H 001H 002H 003H 004H
Instruction Instruction Instruction Instruction Instruction
Jump RESET service routine Jump INT0 service routine Jump Timer0 service routine Jump Base Timer service routine Jump INT1 service routine
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Built-in SRAM contains general-purpose data memory, RAM, system registers. They accessed direct addressing instruction. following memory allocation map: $000~$01F: System register I/O; $020~$1FF: Data memory into banks). $300~$321, $350~$36D: space bits). configuration system register Address Bit3 Bit2 Bit1 Bit0 Initial Value Interrupt enable flags 0000 Interrupt request flags 0000 Timer0 mode register 0000 Base timer mode register 0000 Timer0 load/counter nibble 0000 Timer0 load/counter high nibble 0000 Reserved PORTA 0000 PORTB 0000 Bonding option 01(default) PORTA output port 0000 PORTB output port 0000 Reserved Table branch register 0000 Index register(INX) 0000 Data pointer nibble 0000 Data pointer middle nibble 0000 Data pointer high nibble 0000 Bit1,2:PA.1 PA.2 output PORT 0000 Bit0:Heavy load mode Bit3:Port pull-up control Bit0:Turn OSCX oscillator 0000 Bit1:CPU clocks select (1:OSCX/0:OSC) Bit3:OSCX type selection 0000 Bit0:Programmer should Bit1:LCD Bit2,3:LCD frequency control Bit2:Set segment output 0000 Bit3:LCD Power degrade channel nibble 0000 channel 1high nibble 0000 Bit3:channel octave shift control channel nibble alarm output 0000 channel nibble 0000 channel nibble 0000 channel nibble 0000 Bit3:channel octave shift control Bit0,Bit1:Channel enable 0000 Bit2,Bit3:volume control Bit0,1:PSG1,PSG2 mode control 0000 Bit2,3:PSG1,PSG2 clock source selection Reserved Function
$06~$07
IRQX TM0.3 BTM.3 T0L.3 T0H.3 PA.3 PB.3 PACR.3 PBCR.3 TBR.3 INX.3 DPL3 PPULL
IET0 IRQT0 TM0.2 BTM.2 T0L.2 T0H.2 PA.2 PB.2 PACR.2 PBCR.2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 PAM2
IEBT IRQBT TM0.1 BTM.1 T0L.1 T0H.1 PA.1 PB.1 PC.1 PACR.1 PBCR.1 TBR.1 INX1 DPL1 DPM.1 DPH.1 PAM1
IRQP TM0.0 BTM.0 T0L.0 T0H.0 PA.0 PB.0 PC.0 PACR.0 PBCR.0 TBR.0 INX.0 DPL0 DPM.0 DPH.0
OXON
LPS1
LPS0
LCDOFF
C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 SEL1
C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 SEL0
C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN
Should
C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN
*System Register $00~$12 refer "SH6610C User manual".
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Data memory general-purpose data memory organized 512*4 bits. Because static feature. maintain data after enters STOP HALT mode. Oscillator circuit Circuit Configuration
SH6613/B/C on-chip oscillation circuits OSCX. frequency crystal (Typ. 32.768KHz) (Typ.262KHz) determined code option. This designed frequency operation. OSCX also types: ceramic (Typ.455KHz) (1.8M 2MHz) determine software option. designed high frequency operation. possible select high speed processing high frequency clock select power operation operation clock. starting reset initialization, starts oscillation OSCX turned off. Immediate after reset initialization, clock automatically selected system clock input source. Oscillator Block Diagram
OSCI Frequency OSCO Clock Oscillator System clock Source Selector OSCXI OSCXO High Frequency Clock Oscillator Switching control System clock Generator Clock Base Timer
Timing system Clock Switching
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oscillation generates basic clock pulses that provide peripherals (Timer0, LCD) with operating clock. Crystal oscillator type
STOP OSCI
32768Hz OSCO
5-6p
oscillator type
RBIAS STOP
OSCI
Ring Oscllator
OSCO
OSCX oscillation OSCX clock oscillators. software options select ceramic CPU's subclock. OSCX Ceramic oscillator type
CPUSTOP
OSCXI
455KHz Ceramic OSCXO
OSCX oscillator type OSCX used, must masked Ceramic resonator OSCXI must connected GND.
RBIAS CPUSTOP
OSCI
Ring Oscllator
OSCO
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Control oscillator oscillator control register configuration shown blow. Add. Bit3 Bit2 Bit1 Bit0 OXON
OXON: OSCX oscillation on/off. 0:Turn OSCX oscillation OXM: switching system clock. 0:select system clock OXS: OSCX oscillator type selection 0:OSCX ceramic oscillator
1:Turn OSCX oscillation 1:select OSCX system clock 1:OSCX oscillator
Programming notes takes least OSCX oscillation circuit until oscillation stabilizes. When switching system clock from OSCX, must wait minimum since OSCX oscillation goes. However, start time varies with respect oscillator characteristics condition use. waiting time depends applications. When switching from OSCX OSC, turn OSCX instruction. OSCX turn control would delayed instruction cycle automatically prevent operation error. System clock system clock varies clock source changes. following table shows instruction execution time according each frequency system clock source.
32.768 Xtal(OSC
Cycle time PORTs
262K RC(OSC 17.778
455K ceramic Xtal(OSCX) 8.79
1.8M RC(OSCX) 2.22
RC(OSCX)
122.07
provides 8-bidirectional pins. Each contains pull-up controllable program. When every used input, PORT control register (PACR, PBCR) controls ON/OFF output buffer.
PORTA~B These ports contain 8-bidirectional ports. circuit configuration PORTA~B below.
PULLUP PULL_UP PMOS
PORT CONTROL REGISTER PORTX PORT DATA REGISTER
DATAINPUT RD_INPUT
ports SH6613/B/C accessed read/write system register. User output value port time. Memory addresses listed follow:
Address Bit3 PORTA.3 PORTB.3 Bit2 PORTA.2 PORTB.2 Bit1 PORTA.1 PORTB.1 Bit0 PORTA.0 PORTB.0
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Controlling pull-up These ports contain pull-up controlled program. Bit3 PMOD register controls On/Off pull-up simultaneously. Pull-up also controlled port data registers (PA, each port also. pull-up turned On/Off. Port Interrupt
PORTB interrupt (falling edge) controlled Port register. means that interrupt requestIEx port high lowis been touched that condition other port bits high level whenever port output input.
External PortA.0 shared external interrupts (active low). Port control register:
Address
Bit3 PACR.3 PBCR.3
Bit2 PACR.2 PBCR.2
Bit1 PACR.1 PBCR.1
Bit0 PACR.0 PBCR.0
control register: PACR.X, PBCR.X (X=0,1,2,3) output buffer. input buffer (Power initial).
Port mode register (PMOD)
Bit3 PPULL
Bit2 PAM2
Bit1 PAM1
Bit0
Function Bit1,2:Select PA.1,PA.2 port output Bit0:Hevey load mode Bit3:Port pull-up control 1:Enable 1:Enable pull-up
PAM1, PAM2: HLM: PPULL:
Please sees Enable heavy load mode Port pull-up
0:Disable 0:Disable pull-up
Heavy load mode (HLM) heavy load protection circuit when battery load becomes heavy. examples, when external buzzer sound external speaker turned this mode, crystal oscillator circuit been backup high gain. When setup this mode, more power would provided oscillator circuit. Unless necessary, careful this mode with software. Since mode enter would delay instruction. Please activate heavy load driving only after setting least instruction wait cycle through software. Following shows programming setting.
HLM: 0=Heavy load protection mode released 1=Heavy load protection mode set.
HEAVYLOAD
Instruction Cycle Time
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Programmable sound generator(PSG)
channel1 channel2. function block diagram follows.
CHANNEL1 OSCX CHANNEL2 MIXER
function provides four subfunctions wide application.
Programmable sound Program sound created channels. Every channel programmed follows. Enable/Disable every channel sounds. Select every channel sound frequency. channel sounds mixed into output. output controlled volume levels. Fine noise provide wide-band noise. wide-band noise volume controlled volume levels. Alarm provide many alarm functions software. alarm carrier frequency programmed individual. alarm volume controlled volume levels. Remote control remote control only expandable application sound. Since remote control frequency 56.13KHz 37.92KHz, software could select sound frequency. subblock diagram
block diagram
SEL0 SEL1
CLK-SLECTOR
OSCX
SEL1
SEL0
source
OSC/2 OSCX OSCX/16
OSC=32.768K OSC=262K OSC=32.768K OSC=262K OSCX=1.8M OSCX=455K OSCX=1.8M OSCX=455K
32.768K 262K 16.384K 131K 1.8M 455K 112.5K 28.4K
block selects clock sources that provides channel sources.
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SH6613/B/C
Channel
CH1EN
OCT1
REGISTER C1.6~C1.0
SELECTOR
DIVIDER
OCT1
Scaling ratio
Channel
Channel constructed 7-bit pseudo random counter. Channel enabled/disabled CH1EN. creates either sound frequency alarm carrier frequency remote carrier frequency.
CH2EN OCT2 NOISE GENERATOR C2.14~C2.0 SELECTOR REGISTER C2.14~C2.0 C2.14~C2.8 DIVIDER SELECTOR
C2.3~C2.0 32Hz ENEVLOP ENEVLOP
OCT2
Scaling ratio
Channel constructed 15-bit pseudo random counter. Channel enabled/disabled CH2EN 15-bit wide-band noise generator 7-bit sound generator. also create alarm envelope signal.
Function
Sound generator. Sound generator. Sound generator.
Sound generator. Noise generator. Alarm mode register.
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Mixer
TIME SLOT VOL0 VOL1 PA.1 TIME SLOT CONTROL PA.2 PAM2 SELECTOR2 PA.2 SELECTOR1 PA.1
PAM1
MIXER mixes CH1-OUT CH2-OUT into tone output PA.1 PA.2, when PAM1=1PAM2=1. Then tone output controlled volume control into volume levels outputted PSG. PA.1 PA.2 controlled PAM1 PAM2
PAM2 PAM1 Function
PA.1:I/O PORT PA.1:PSG output PA.1:I/O PORT PA.1:PSG output
PA.2:I/O PORT PA.2:I/O PORT PA.2: output PA.2: output
SEL1
SEL0
Vol. control
VOL1
VOL0
Vol. Level
Note: Don't enable channels together produce tone, will produce some unpredicted errors. necessary channels together (EX. play channel melody), don't score always same tones then unpredicted errors will occur will ignore through user hearing.
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value divider1 corresponding C1.6~C1.0 C2.14~C2.8 shown following table:
LSFR (C1.6~C1.0) (C2.14~C2.8) LSFR (C1.6~C1.0) (C2.14~C2.8) LSFR (C1.6~C1.0) (C2.14~C2.8) LSFR (C1.6~C1.0) (C2.14~C2.8)
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Function description sound generator programmable sound working modes. software designer select clock sources clk. then select frequency divided value that controlled value C1.6~C1.0 C2.14~C2.8.In
select volume level controlled VOL0, VOL1. music tone output both also control OCT1, OCT2 that shifts music tone octaves. Example1:CH1EN=CH2EN=1 Example2:CH1EN=0;CH2EN=1 OSCX=1.8M,SEL0=SEL1=1 OSCX=1.8M,SEL0=SEL1=1 =112kHz;Switch clk=28kHz =112kHz;Switch clk=28kHz; Vol. clk=112kHz Vol. clk=112kHz
Example3: CH1EN=CH2EN=1 OSC=32k,SEL0=SEL1=0 32kHz; Switch 32kHz vol. control, level hardware, software should VOL0=VOL1=1.
Note: 32KHz operations, volume control cannot used, because multiplexing frequency high enough switch sound! user want turn completely, software must disable both channels. User should turn zero wave from output. Both CH1EN CH2EN should power operation mode. Example
software designer wants create (channel mixed with (channel sound (the sound frequency please Music table1 Music table2), level=3.He select suggestion follows. first selects CH1EN=CH2EN=1,C1M=C2M=0. select OSCX=1.8M SEL0=SEL1=1, CLK=112.5KHz. Then select OCT1=1 value channel LSFR (C1.6~C1.0)=23,so =108. Please Music table1. channel sound sound frequency. Then select OCT1=0 value channel LSFR (C1.6~C1.0)=4F,so =81. Please Music table1. channel sound sound frequency Lastly, should select VOL1=1 VOL0=0, level=3.
Note:
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designer provides crossing tables appendix that what designer prefers clk=32.768K clk=112.5K. noise generator fine noise created CH2. want create single noise, make music tone output. Otherwise wide-band noise music tone into output through MIXER. Lastly select volume levels controlled VOL0, VOL1.
alarm generator When alarm mode, provides alarm carrier frequency provides alarm envelope signal. Lastly select volume levels controlled VOL0, VOL1. channel nibble C2.0~C2.3 will alarm control register. Channel output would modulate with ALARM envelope control 32KHz 262KHz. carrier frequency programmed channel 1.In reading this alarm control register, read corresponding output envelope frequency (the 1Hz, 4Hz, 8Hz, 32Hz). Alarm control register (OSC=32KHz 262KHz) C2.3 C2.2 C2.1 C2.0 Alarm output control envelop output output output 32Hz output
Figure: Alarm modulation output OSC=32.768KHz OSC=262KHz.
remote control remote control only expandable application sound. select tone output will create alarm frequency envelope signal. When channel programmed ALARM mode. Programmer ALARM mode register "0000B". Program adequate frequency output output. Then PAM1 PAM2 control envelope code. this way, remote control function implemented easily. remote frequency =56.73KHz 37.92KHz. software should select OSCX=455KHz, SEL=1 SEL0=0, that CLK=455KHz. Then select channel alarm mode (C1M=1), OCT1=0,C2.0~C2.3 00H. VOL1, VOL2=1,1. Then select C1.6~C1.0=7E, that output select C1.6~C1.0=78,so that output
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SH6613/B/C
Timer
SH6613/B/C 8-bit timer. timer consists 8-bit counter 8-bit preload register. timers provide following functions: internal timer function counter values
Timer configuration operation timer consists 8-bit write-only timer load register (TL0L, TL0H) 8-bit read-only timer counter (TC0L, TC0H). Each them order digits high order digits. timer counter initialized writing data into timer load register (TL0L, TL0H). Write low-order digit first then high-order digit. timer counter loaded with content load register automatically when high order digit written counts overflow happens. timer overflow will generate interrupt, interrupt enable flag set. timer programmed several different system clock sources setting Timer Mode register (TM0). Timer reads writes operations follow these rules: Write Operation: Read Operation
nibble first High nibble update counter
Timer0 mode register (TM0)
High nibble first nibble follows
8-bit counter counts prescaler overflow output pulses. 4-bit registers used timer control shown Table1. register selects input clock sources timer.
Table1: Timer0 Mode registers ($02)
TM0.3
TM0.2
TM0.1
TM0.0
Prescaler /2048 /512 /128 External
Clock Source System clock System clock System clock System clock System clock System clock System clock INT0
TM0.3 control function: without Auto-Reload function Auto-Reload function
Warm-up counter mode, warm-up counter prescaler divided (128). Crystal mode, warm-up counter prescaler divided (65536).
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SH6613/B/C
Base Timer
base timer that shared with warm-up timer clock source (Low frequency oscillation: X'tal 32.768KHz 262KHz). After reset, counts every clock-input signal. When counts $FF, right after next clock input, counter counts generates overflow This causes interrupt base timer interrupt request flag 1.Therefor, base timer function interval timer periodically, generating overflow output every 256th clock signal output. timer accepts 4096Hz 32KHz clock, base timer generates accurate timing interrupt. This base time prescaler reset program accurate timing. This clock-input source sleeted Bregister.
Address Bit3 Bit2 Bit1 Bit0 Function
BTM.3
BTM.2
BTM.1
BTM.0
Base timer mode register
BTM.3=0: Disable base timer BTM.2=0: reset base timer
BTM.1 BTM.0
BTM.3=1: Enable base timer BTM.2=1: reset base timer
Prescaler Ratio Clock source
4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz
BTM[3]
base timer counter reset
262k
4096/32K
4Bit Scaler
BTM[2]
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SH6613/B/C
Driver
driver contains controller, voltage generator, common signal pins segment driver pins, duty bias. SEG1~30 also used output port, selected system register $16. When SEG1~30 output port, write data same addresses (350H-36DH). could used data memory need. When "STOP" instruction executed, will turned off, data keeps same value before executing "STOP" instruction.
11.1 Control Register
Add.
LPS1
LPS0
LCDOFF
Should
LCDOFF: on/off switch. off. LPS1, LPS0: clock frequency control 0,0: LCDCLK OSC/64 0,1: LCDCLK OSC/512 1,0: LCDCLK System clock/512 1,1: LCDCLK System clock/4096 *System clock= Instruction cycle time Frame frequency=LCDCLK/16 Frame frequency duty; duty same frequency cycle. Frequency OSC=32kHz (#), OSC=32kHz, OSC=32kHz (#), OSC=32kHz, OSC=32kHz(#), OSC=32kHz, OSC=262kHz (#), OSC=262kHz, OSC=262kHz (#), OSC=262kHz OSC=262kHz OSC=262kHz (#), OSCX=455kHz OSCX=455kHz OSCX=1.8MHz OSCX=1.8MHz OSCX=2MHz OSCX=2MHz OSCX=455kHz OSCX=455kHz OSCX=1.8MHz OSCX=1.8MHz OSCX=2MHz OSCX=2MHz LPS1, LPS0 32Hz 32Hz 32Hz 32Hz 32Hz 32Hz 256Hz 256Hz 256Hz 256Hz 256Hz 256Hz 32Hz 32Hz 32Hz 32Hz 32Hz 32Hz 14Hz 55Hz 61Hz 14Hz 55Hz 61Hz 1/8Hz 1.7Hz 1/8Hz 6.9Hz 1/8Hz 7.6Hz 1.7Hz 6.9Hz 7.6Hz
before sleeted system clk. Frame frequency=LCDCLK/16 (32Hz) When SCAN OUT, COMx pulled high. easy implement keyboard scan. When STOP mode, COMx SEGx pulled low. easily waken keyboard scan (Port interrupt). When HALT mode, COMx SEGx normal. easily waken base timertimer0 port interrupt.
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block diagram reference only. 11.2 power
LCDOFF Power Switch com1 common driver com4
Power Supply Control Circuit
LPS0 SYSCLK/512 LPS1 OSC/64
LCDCLK Scaler
DUTY
seg1 segment driver scan output seg34
Build-in special power control power modulation. Add. output ports.
O/S: segment/common segment output output ports segment output When voltage power would degraded about 0.5V, depending level. designed reduce extra contrast control output pins. Then fitted automatically different voltage levels software.
11.3 Configuration
duty, bias (COM1~4,SEG1~34)
Address Bit3 COM4 Bit2 COM3 Bit1 COM2 Bit0 COM1 Address Bit3 COM4 Bit2 COM3 Bit1 COM2 Bit0 COM1
300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H
SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
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SEG1-30 used scan output port.
Address Bit0 Address Bit0 Address Bit0 Address Bit0
350H 351H 352H 353H 354H 355H 356H 357H
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8
358H 359H 35AH 35BH 35CH 35DH 35EH 35FH
SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16
360H 361H 362H 363H 364H 365H 366H 367H
SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
368H 369H 36AH 36BH 36CH 36DH
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
11.4 waveform
DUTY BIAS SELECT UNSELECT
SELECT
UNSELECT
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SH6613/B/C
Interrupt interrupt sources available SH6613/B/C: interrupt INT0 interrupt timer interrupt falling edge detection interrupt( INT1
configuration system register
Function
IRQX
IET0 IRQT0
IEBT IRQBT
IRQP
1:Enable 0:Disable 1:Request 0:No request
12.1 External Interrupt INT0
External interrupt shared with PA.0, falling edge active. When register (IEX) external interrupt enabled, writing PA.0 will generate external interrupt.
12.2 Timer interrupt, Base timer interrupt, Port interrupt INT1
IEx=1 then valid interrupt requests will cause interrupt. overflow timer will create interrupt timer 0.The overflow Base timer will create interrupt Base timer. falling edge every port PORTB will create INT1 interrupt (The condition that other port must input/output high level).
12.3 Enable flags Request flags
Both Enable flags Request flags read written software. Request flags will hardware interrupt, Enable flags will reset hardware when interrupt service routine entered.
12.4 Interrupt Servicing Sequence Diagram:
SH6610C interrupt services routine, user enable interrupt enable flag before returning from interrupt. frequently asked question when next interrupt would serviced? Will nesting interrupt happen? From servicing sequence timing diagram, interrupt request ready instruction execution enable. Then interrupt start right after next instructions: instruction disable interrupt request enable flag, then interrupt service sequence would terminated.
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
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Options
Bonding options System register reserved user opened system developer select these bonding options, selecting subprogram that programmed user. $0A.1 (PC.1) $0A.0 (PC.0) subroutine subroutine Default subroutine subroutine
PC.0 PC.1 PC.0
PC.1
PC.0
PC.1
PC.0 PC.1
PC.0 PC.1 PC.0
PC.1
PC.0
PC.1
PC.0
PC.1
NT6614 Bonding Option
STOP/HALT mode STOP/HALT mode Oscillator core Wake Executing after wake
STOP (STOP instruction)
OSCX Stop
Hold
INT0 INT1
signal valid, system will reset. INT0 INT1 signal valid, system will enter interrupt subroutine, then execute main program continue. signal valid, system will reset. INT0 INT1 T0INT BTINT signal valid, system will enter interrupt subroutine first, then execute main program continue.
HALT (HALT instruction)
OSCX live
Hold
INT0
INT1 ,T0INT
BTINT
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SH6613/B/C
Instruction
instructions cycle word instruction. characteristic memory-oriented operation. Arithmetic Logical Instruction Accumulator type
Mnemonic Instruction Code Function Flag Change
ADCM ADDM SBCM SUBM EORM ANDM
00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000
AC[3] AC[0] shift right
Immediate Type
Mnemonic Instruction Code Function Flag Change
ADIM SBIM EORIM ORIM ANDIM
01000 xxxx 01001 xxxx 01010 xxxx 01011 xxxx 01100 xxxx 01101 xxxx 01110 xxxx
assembler ASM66 V1.0, EORIM mnemonic EORI. However, EORI same operation identical with EORIM. Same ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust
Mnemonic Instruction Code Function Flag Change
11001 0110 xxxx 11001 1010 xxxx
Decimal adjust add. Decimal adjust sub.
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SH6613/B/C
Transfer Instruction
Mnemonic Instruction Code Function Flag Change
00111 0bbb xxxx 00111 1bbb xxxx 01111 xxxx
Control Instruction
Mnemonic Instruction Code Function Flag Change
CALL
10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx
AC=0 CY=1 AC(0)=1 AC(1)=1 AC(2)=1 AC(3)=1
PC+1 (Not include
RTNW RTNI HALT STOP TJMP
11010 000h 11010 1000 0000 11011 0000 0000 11011 1000 0000
hhhh;
1110p xxxx xxxx 11110 1111 1111 11111 1111 1111
(Include (PC11-C8)(TBR)(AC)
Operation
Where, Program counter Accumulator Complement accumulator Carry flag Data memory
Immediate data Logical exclusive Logical Logical bank=000
page Stack Table Branch Register
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SH6613/B/C
Absolute Maximum Rating
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Supple Voltage -0.3V +7.0V Input Voltage -0.3V VDD+0.3V Operating Ambient Temperature Storage Temperature +125
Electrical Characteristics
(VDD=3.0V, GND=0V, TA=25, FOSC=32.768KHz, FOSCX used, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Conditions
Operating Voltage Operating Current voltage divider resistor Standby Current Standby Current Input High Voltage Input Voltage Drive-high resistance Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage lighting
RLCD ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 ILCD
-0.3 VDD-0.6 VDD-1.0
VDD+0.3 VDD+0.3
output pins unload execute instruction exclude bias current
output pins unload (HALT mode) exclude bias current output pins unload (STOP mode), PORTA, PORTB INT0, RESET PORTA, PORTB INT0, RESET PORTA, PORTB (IOH -10µA, PORTA.0, PORTA.3, PORTB (IOH -2mA). PORTA.0, PORTA.3, PORTB (IOL 2mA). PORTA.1, PORTA.2 output, -5mA. PORTA.1, PORTA.2 output, 5mA. SEGx, C=50P, rise time<1000ns SEGx SEG1 30to output port, =-1mA SEG1 30to output port, =1mA COMx, -1mA. COMx, 1mA. VDD=3V, exclude core operation current
Operation frequency ISB1 ISB1X (VDD 3.0V). Operation frequency IOPX (VDD 3.0V). IOP, ISB1 ISB2 IOPX ISB2X
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SH6613/B/C
Characteristics (VDD=3.0V, GND=0V, TA=25, FOSC=32.768KHz,unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Conditions
Oscillation Start Time Frequency Stability
tSTT |F|/F
[F(3.0)-F(2.5)]/F(3.0), crystal oscillator
Characteristics (VDD=3.0V, GND=0V, TA=25, FOSC=262KHz, FOSCX stop, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Conditions
Oscillation Start Time Frequency Stability
tSTT |F|/F
[F(3.0)-F(2.5)]/F(3.0), Bias resistance accuracy within
Characteristics (VDD=4.5V,GND=0V, TA=25, FOSC=262KHz, FOSCX stop, unless otherwise specified)
Parameter Symbol Min. Typ. Max. Unit Conditions
Frequency Stability
|F|/F
[F(4.5)-F(3.6)]/F(4.5), Bias resistance accuracy within
25/33
V1.2
SH6613/B/C
Typical oscillator Resistor VDD: (Reference only) Typical oscillator Frequency VDD: (Reference only)
F=262KHz R(K)
R=919K
VDD(Volts)
F(KHz)
VDD(Volts)
F=1.8MHz
2100 F(KHz) 1900 1700 1500 1300 VDD(Volts)
R(K)
VDD(Volts)
R=108K
F=2.0MHz VDD(Volts) R(K)
F(KHz)
2300 2100 1900 1700 R=91K
VDD(Volts)
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SH6613/B/C
Application Circuit (for reference only)
AP1:
OSC: Crystal oscillator 32.768KHz(mask option) OSCX: Ceramic oscillator 455KHz PORTB: PORTA.1, PORTA.2: ALARM output LCD: Internal duty, bias
duty 1/3bias RESET OSCXO PORTA.1 BUZZER OSCXI 455KHz
SH6613/B/C
PORTB OSCO
32768Hz OSCI TEST
PORTA.2
AP2:
OSC: oscillator 262KHz(mask option) LCD: Internal duty, bias PORTA, PORTB: PORTA.0: External interrupt
duty bias
RESET
OSCXI OSCXO
PORTA PORTB OSCO 930K OSCI
SH6613/B/C
PORTA.0
Ext.int
TEST
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V1.2
SH6613/B/C
AP3:
OSC: Crystal oscillator 32.768KHz(mask option) OSCX: oscillator 1.8MHz PORTB: PORTA.1: output PORTA.2: output
RESET
OSCXI
100~120K (VDD=3~5v)
SPEAKETR
OSCXO
SH6613/B/C
PORTB OSCO
PORTA.1
8050
32768Hz OSCI TEST
PORTA.2
AP4:
Internal bias.1/4 DUTY 1/3bias
COM1 COM4 SEG34
PANNEL
BOARD
SEG1~SEG4 SCAN outpost
SH6613/B/
SEG4 SEG3 SEG2 SEG1 PORTB0 PORTB1 PORTB2 PORTB3
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V1.2
SH6613/B/C
AP5:
Large panel: External bias
Bias Normal pannel VLCD
Bias Large pannel VLCD Ext.R
SH6613/B/C
SH6613/B/C Ext.R Ext.R
VCC,V1,V2,V3 floating
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SH6613/B/C
Music Table1
Following music scale reference table channel 1(or channel under OSCX=1.8MHz. octave possible. Music scale data 1.8M OSCX SEL0=SEL1=1
Ideal freq. OCT1 /OCT2 LSFR (C1.6~C1.0) (C2.14~C2.8) Real freq. Ideal freq. OCT1 /OCT2 LSFR (C1.6~C1.0) (C2.14~C2.8) Real freq.
Note
Error% Note
Error%
61.74 65.41 73.42 82.41 87.31 98.00 110.00 123.47 130.81 146.83 164.81 174.61 196.00 220.00 246.94 261.63 293.66 329.63 349.23 392.00 440.00 493.88
61.75 65.19 73.33 82.82 86.91 97.78 110.00 123.51
0.03% -0.34% -0.11% 0.51% -0.45% -0.23% 0.00% 0.03%
493.88 523.25 587.33 659.26 698.46 783.99 880.00 987.77 1046.50 1174.66 1318.51 1396.91 1567.98 1760.00 1975.53 2093.00 2349.32 2637.02 2793.83 3135.96 3520.00 3951.07
494.04 521.48 586.67 662.59 695.31 782.22 880.00 988.07 1042.96 1173.33 1309.77 1408.00 1564.44 1760.00 1942.07 2085.93 2346.67 2681.90 2816.00 3128.89 3520.00 4022.86
0.03% -0.34% -0.11% 0.51% -0.45% -0.23% 0.00% 0.03% -0.34% -0.11% -0.66% 0.79% -0.23% 0.00% -1.69% -0.34% -0.11% 1.70% 0.79% -0.23% 0.00% 1.82%
130.37 -0.34% 146.67 -0.11% 163.72 -0.66% 176.00 0.79%
195.56 -0.23% 220.00 0.00%
242.76 -1.69% 260.74 -0.34% 293.33 -0.11% 335.24 352.00 1.70% 0.79%
391.11 -0.23% 440.00 502.86 0.00% 1.82%
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SH6613/B/C
Music Table2
Following music scale reference table channel 1(or channel under OSC=32.768KHz. 4-octave possible. Music scale data SEL0=SEL1=0
Ideal freq. OCT1 /OCT2 LSFR (C1.6~C1.0) (C2.14~C2.8) Real freq. Ideal freq. OCT1 /OCT2 LSFR (C1.6~C1.0) (C2.14~C2.8) Real freq.
Note
Error% Note
Error%
55.00 61.74 65.41 73.42 82.41 87.31 98.00 110.00 123.47 130.81 146.83 164.81 174.61 196.00 220.00 246.94
55.35 62.06 66.06 73.14 81.92 89.04 97.52
0.64% 0.53% 1.01% -0.37% -0.59% 1.99% -0.48%
261.63 293.66 329.63 349.23 392.00 440.00 493.88 523.25 587.33 659.26 698.46 783.99 880.00 987.77 1046.50 1174.66
260.06 292.57 327.68 348.60 390.10 442.81 496.48 528.52 585.14 655.36 712.35 780.19 862.32 963.76
-0.60% -0.37% -0.59% -0.18% -0.48% 0.64% 0.53% 1.01% -0.37% -0.59% 1.99% -0.48% -2.01% -2.43%
107.79 -2.01% 120.47 -2.43% 131.07 0.20%
146.29 -0.37% 165.49 0.41%
174.30 -0.18% 195.05 -0.48% 221.41 248.24 0.64% 0.53%
1024.00 -2.15% 1170.29 -0.37%
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Bonding diagram
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG32 SEG33 SEG34 COM4 COM3 COM2 COM1 OSCI OSCO PC.0 OSCXO OSCXI PA.0 PA.1 PA.2
SH6613 SH6613B SH6613C
(0,0)
1680µm
SEG3
1800µm
Substrate connect Designation X(µm) Y(µm) Designation X(µm) Y(µm)
bonding option bonding option
SEG[2] SEG[1] VLCD TEST RESET PORTC[1] PORTB.3 PORTB.2 PORTB.1 PORTB.0 PORTA.3 PORTA.2 PORTA.1 PORTA.0 OSCXI OSCXO PORTC[0] OSCO OSCI COM[1] COM[2] COM[3] COM[4] SEG[34] SEG[33]
-770.00 -640.00 -520.00 -405.00 -290.00 -175.00 -60.00 55.00 180.00 175.95 295.00 410.00 525.00 640.00 770.00 900.00 900.00 900.05 900.00 900.00 806.05 907.60 900.00 900.00 900.00 900.00 900.00 900.00 900.00 900.00
-840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -746.00 -848.90 -840.00 -840.00 -840.00 -840.00 -840.00 -840.00 -710.00 -590.00 -470.00 -355.00 -240.00 -248.05 -120.00 0.00 120.00 240.00 355.00 470.00 590.00 710.00 32/33
SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3]
900.00 770.00 640.00 520.00 405.00 290.00 175.00 60.00 -60.00 -175.00 -290.00 -405.00 -520.00 -640.00 -770.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00 -900.00
840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 840.00 710.00 590.00 470.00 355.00 240.00 120.00 0.00 -120.00 -240.00 -355.00 -470.00 -590.00 -710.00 -840.00
V1.2
SH6613/B/C
Ordering Information
Part Package
SH6613H SH6613BH SH6613CH
CHIP FORM CHIP FORM CHIP FORM
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V1.2

4-Bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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