4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit
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SH6612A
4-bit Microcontroller with Driver
SH6610C-based single-chip 4-bit microcontroller with driver ROM: 2048 bits RAM: bits (data memory) Operation Voltage Range: 2.2V 5.4V typically) CMOS pins (PORTA CMOS Open Drain code option level subroutine nesting (including interrupts) 8-bit timers with pre-divider circuit Oscillator warm-up timer priority interrupt sources: External interrupt (falling edge) Timer0 interrupt Timer1 interrupt PortB interrupt (falling edge) Clock source: 32.768KHz crystal 262K (code option) Instruction cycle time: 4/32.768KHz 122µs) 32.768KHz crystal 4/262KHz 15µs) 262KHz driver: (1/4 duty bias duty bias) power operation modes HALT STOP mode Built-in alarm generator (carrier frequency: 2KHz 4KHz code option) power consumption (Iop 10µA, 32.768KHz, Bonding option multi-code software Available CHIP FORM
General Description
SH6612A single-chip microcontroller integrated with SH6610C core, SRAM, timer, alarm generator, driver, port, program ROM.
Configuration
SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
COM3 COM4 OSCI OSCO PORTD3 PORTD2 PORTD1 PORTD0 PORTC3 PORTC2 PORTC1 PORTC0 PORTB3
SH6612A
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SH6612A
Block Diagram
(2048
TEST
OSCI (256 OSCO 8-Bit TIMER PORTB, PORTC PORTS (3*4) CORE PORTA extemal PORTA.0 (INT) PORTA.1(BD) PORTA.2 (BD) PORTA.3 COMMON DRIVERS COM1 COM4 PORTD
RESET ALARM GENERATOR
SEGMENT DRIVERS
SEG1 SEG26
OPERATING VOLTAGE VOLTAGE DIVIDER
Description
Designation SEG1 TEST RESET PORTA0 Description Segment signal output display. Seg1 output Test internally pull-down connect user) reset input Power Bonding option, internally pull-low programmable PA.0 could external interrupt input( PA.1, PA.2 could buzzer output PA.1 (BD), PA.2 programmable I/O, vector interrupt (active falling edge) programmable programmable Ground Bonding option, internally pull-high Oscillator output pin, connected crystal oscillator Oscillator input pin, connected crystal external resistor Common signal output display
PORTB0 PORTC0 PORTD0 OSCO OSCI COM1
Total pads mask type.
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SH6612A
Functional Description
contains following function blocks: Program Counter (PC), Arithmetic Logic Unit (ALU), Carry Flag (CY), Accumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPM, DPL), Stacks. (Program Counter) restored back from stack RTNI instruction. used address Programmable ROM. unaffected RTNW instruction. consists 12-bits: Accumulator Page Register (PC11), Ripple Carry Counter (PC10 Accumulator 4-bit register holding results PC0). arithmetic logic unit. conjunction with ALU, data program counter normally increases (+1) with transfers between accumulator system register every execution instruction except following data memory performed. cases: Data Pointer When executing jump instruction (such JMP, BA0, Data Pointer indirectly address data memory. BC); Pointer address located register (3-bits), When executing subroutine call instruction (CALL); (3-bits) (4-bits). addressing range have When interrupt occurs; 3FFH locations. Pseudo index address (INX) used When chip INITIAL RESET mode. read write Data memory, then address bit9 bit0 comes from DPH, DPL. program counter loaded with data corresponding each instruction. Stack This group registers used save contents (11-0) sequentially with each subroutine call performs arithmetic logic operations. interrupt. organized bits levels. provides following functions: saved levels maximum allowed total Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, subroutine calls interrupts. SBI) Note: Decimal adjustment addition/subtraction (DAA, DAS) contents Stack returned sequentially Logic operations (AND, EOR, ANDIM, EORIM, ORIM) with return instructions (RTNI/RTNW). Stack Decision (BA0, BA1, BA2, BA3, BAZ, operated first-in, last-out basis. This 4-level nesting Logic Shift (SHR) includes both subroutine calls interrupts requests. Carry Flag (CY) holds overflow, which Note that program execution enter abnormal state arithmetic operation generates. During interrupt service number calls interrupts requests exceeds call instruction, carry flag pushed into stack then bottom stack will shifted out.
SH6612A address words program area from $000 $7FF. SPACE system 2048 bits. Vector Address Area ($000 $004) program sequentially executed. There area address $000 through $004 that reserved special interrupt service routine such starting vector address.
Address 000H 001H 002H 003H 004H
Instruction instruction instruction instruction instruction instruction
Remarks Jump RESET service routine Jump External interrupt service routine Jump TIMER0 service routine Jump TIMER1 service routine Jump service routine (PORTB)
*JMP instruction replaced instruction. Table Data Reference Table Data stored program memory referenced using Table Branch (TJMP) Return Constant (RTNW) instructions. Table Branch Register (TBR) Accumulator placed offset address program ROM. TJMP instruction branch into address ((PC11 PC8) (28) (TBR, A)). address determined RTNW return look-up value into (TBR, code bit7-bit4 placed into bit3-bit0 into
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SH6612A
Built-in SRAM contains general-purpose data memory, system register. Addressing Data memory system register accessed instruction direct addressing. following memory allocation map: $000 $01F: System register $020 $11F: Data memory (256 bits, divided into banks). $300 $319: space bits). Data Memory Data memory organized bits ($020 $11F). Because static nature, keep data after enters STOP HALT. configuration system register: IRQX T0L.3 T0H.3 T1L.3 T1H.3 PA.3 PB.3 PC.3 PD.3 TBR.3 INX.3 DPL.3 IET0 IRQT0 T0M.2 T1M.2 T0L.2 T0H.2 T1L.2 T1H.2 PA.2 PB.2 PC.2 PD.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 LCDOFF IET1 IRQT1 T0M.1 T1M.1 T0L.1 T0H.1 T1L.1 T1H.1 PA.1 PB.1 PC.1 PD.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 IRQP T0M.0 T1M.0 T0L.0 T0H.0 T1L.0 T1H.0 PA.0 PB.0 PC.0 PD.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 Remarks Interrupt enable flags Interrupt request flags Bit0-2: Timer0 Mode register Bit0-2: Timer1 Mode register Timer0 load/counter register nibble Timer0 load/counter register high nibble Timer1 load/counter register nibble Timer1 load/counter register high nibble PORTA PORTB PORTC PORTD Reserved Bonding option Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit0: PA.1, PA.2 Alarm Bit1: HEAVY LOAD Mode Bit2: Bit3: segment outport Alarm Envelope Control Bit0: change duty duty, bias Reserved
AEC3
AEC2
AEC1
AEC0 DUTY
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SH6612A
System Clock Oscillator SH6612A clock source. Oscillator determined code option. oscillator generates basic clock pulses that provide system clock supply on-chip peripherals. System clock FOSC/4. Instruction cycle time: 4/32768Hz (122.1µs) 32768Hz oscillator. 4/262KHz (15µs) 262KHz oscillator. Oscillator type Crystal oscillator: 32768Hz
OSCI 20pF 32768Hz 20pF OSCO
oscillator: 262KHz
750K OSCI
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SH6612A
low-order digit should written first, then high-order digit. timer counter automatically loaded with contents load register when high order digit written counter counts overflow from $00. Timer Load Register: Since register controls physical READ WRITE operations. Please follow these steps: Write Operation: nibble first High nibble update counter Read Operation: High Nibble first nibble followed.
Timer0 Timer1 SH6612A 8-bit timers. timer counter following features: 8-bit up-counting timer/counter. Automatic re-loads counter. 8-level prescaler. Interrupt overflow from $00. following simplified timer block diagram.
Tosc Fosc/4 PRESCALER SYNC 8-BIT COUNTER
TM.2 TM.1 TM.0
timers provide following functions: Programmable interval timer function. Read counter value. Timer0 Timer1 Configuration Operation Both Timer0 Timer1 consist 8-bit write-only timer load register (TL0L, TL0H; TL1L, TL1H) 8-bit read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each them order digits high order digits. Writing data into timer load register (TL0L, TL0H; TL1L, TL1H) initialize timer counter. Timer Mode Register
Load Reg.
Load Reg.
8-bit timer counter Latch Reg.
timer programmed several different prescaler ratios setting Timer Mode register (TM0, TM1). 8-bit counter prescaler overflow output pulses. Timer Mode registers (TM0, TM1) 3-bit registers used timer control shown Table Table These mode registers select input pulse sources into timer. Table Timer0 Mode Register ($02) TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio /211
Table Timer1 Mode Register ($03) Clock Source System clock System clock System clock System clock System clock System clock System clock System clock TM1.2 TM1.1 TM1.0 Prescaler Divide Ratio /211
Clock Source System clock System clock System clock System clock System clock System clock System clock System clock
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SH6612A
Port SH6612A CMOS quasi-I/O ports, PORTA, PORTB, PORTC, PORTD. ports programmable. PORTA,B,C,D pull-high internally, weak drive. equivalent circuit below:
Data-Out
Data-In
Port Data Register: (PDR) Address Bit3 PORT PORT PORT PORT Bit2 PORT PORT PORT PORT Bit1 PORT PORT PORT PORT Bit0 PORT PORT PORT PORT
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SH6612A
7.Interrupt Four interrupt sources available SH6612A: External interrupt shared with PA.0) Timer0 interrupt Timer1 interrupt PortB interrupts (falling edge)
Interrupt Control Bits Interrupt Service interrupt control flags mapped system register. They accessed tested program. Those flags cleared initialization chip reset. Address IRQX IET0 IRQT0 IET1 IRQT1 IRQP Remark Interrupt enable flags Interrupt request flags
When interrupt request generated (IRQx interrupt will activated vector address will generated from priority corresponding interrupt sources. When interrupt occurs, flag will saved into stack memory jump interrupt service vector address. After interrupt occurs, interrupt enable flags (IEx) reset automatically, when IRQx again, interrupt will activated vector address will generated from priority corresponding interrupt sources. External Interrupt External interrupt shared with bit0 PORTA. When bit3 system register (IEX) external interrupt will enabled, falling edge signal PA.0 will generate external interrupt. (Note: while external interrupt enabled, writing bit0 PORTA will generate external interrupt). Port falling edge Interrupt PortB used port interrupt sources. PortB transitions from would generate interrupt request (IRQP=1). Further falling edge transition would able make interrupt request until input pins have returned VDD. Port Interrupt used wake from HALT STOP mode. Timer Interrupt input clock Timer0 Timer1 based system clock. timer overflow from will generate internal interrupt request (IRQT0 IRQT1=1), interrupt enable flag enabled (IET0 IET1=1), timer interrupt service routine will start. Timer interrupt also used wake from HALT mode. Interrupt Nesting: During SH6610C interrupt service, user enable INTERRUPT enable flag before returning from interrupt. servicing sequence diagram shows next interrupt next nesting interrupt occurrences. interrupt request ready instruction execution enable, then interrupt will start immediately after next instruction executions. However, instruction instruction disables interrupt request enable flag, then interrupt service will terminated. Interrupt Servicing Sequence Diagram:
Inst.cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
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SH6612A
Driver driver contains controller, voltage generator, common signal pins segment driver pins. There different driving modes programmable: duty bias, other duty bias. driving mode controlled system register power initialization status duty, bias. controller consists display data duty generator. data dual port that transfers data segment pins automatically without program control. SEG1 also used output port, selected system register $13. When SEG1 output ports, data written same addresses (300H-303H). could used data memory needed. When "STOP" instruction executed, will turned off, data keeps same value before executing "STOP" instruction. Control Register System Register LCDOFF Description Bit0: PA.1, PA.2 Alarm Bit1: HEAVY LOAD Mode Bit2: Bit3: segment outport
PAM:
PORTA Mode control: PORTA.1, PORTA.2 port PORTA.1, PORTA.2 ALARM output HLM: Heavy load mode control: heavy load HEAVY LOAD mode LCDOFF: Power control: signal signal O/S: Seg1 control: Seg1 output Seg1 output ports
System Register DUTY: DUTY duty, bias Description duty control
duty control duty, bias
divider resistance control (code option) Driving Capability Total Internal divider resistance 1.44M Normal Driving Capability Total Internal divider resistance 360K High Driving Capability Total Internal divider resistance 165K Higher Driving Capability Total Internal divider resistance 120K When large panel used, user select smaller divider resistance through code option increase bias current better performance. will cost more power, when smaller divider resistance used. Configuration area When segments used output ports: Address COM4 300H 301H 302H 303H COM3 COM2 COM1 DATA_BIT DATA_BIT DATA_BIT DATA_BIT
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SH6612A
When segments used segment outputs: Address COM4 300H 301H 302H 303H SEG1 SEG2 SEG3 SEG4 COM3 SEG1 SEG2 SEG3 SEG4 COM2 SEG1 SEG2 SEG3 SEG4 COM1 SEG1 SEG2 SEG3 SEG4
Segments Address COM4 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H Address COM4 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM2 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 COM1 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26
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SH6612A
Timing Waveforms
duty, bias waveform
Select Unselect Light Unlight
COMX
SEGX
15.625ms COM4 VDD3 COM1 COM3 VDD1 VDD3 COM2 COM2 VDD2 VDD1 COM1 VDD3 COM3 VDD2 VDD1 VDD3 COM4 VDD2 VDD1 SEGn+1 SEGn VDD3 VDD2 VDD1 VDD2 3.9ms
SEGn
SEGn+1
VDD3 VDD2 VDD1 VDD3 VDD2 VDD1 -VDD1 -VDD2 -VDD3
COM4 SEGn
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SH6612A
duty, bias waveform
Select Unselect Light Unlight
11.7ms 3.9ms COM3 VDD2 VDD1
COM1
COM2 COM1 SEGn+2 COM2
VDD2 VDD1
COM3
VDD2 VDD1
SEGn+1 SEGn COM4 VDD2 VDD1
SEGn
VDD2 VDD1
SEGn+1
VDD2 VDD1
COM1 SEGn
VDD2 VDD1 -VDD1 -VDD2
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SH6612A
HEAVY LOAD Mode(HLM) When more current will provide oscillator circuit avoid supply current drop that usually takes place heavy output load. Perform heavy load driving only after setting least wait time through software, after switching heavy load mode. This mode designed 32KHz crystal oscillator, that oscillation maintained noisy power environment. power might drop suddenly when ALARM driving speaker. designed control this power variation. consumption power will increase during mode, will affect oscillator. Note: needs about instruction cycles set-up oscillation 32.768KHz crystal oscillator. waveform
Heavy load
more
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SH6612A
ALARM envelope control System Register $14: AEC3 AEC2 AEC1 AEC0 Remarks ALARM envelope control envelope envelope envelope envelope envelope Power
Default carrier frequency 4KHz. selected 2KHz code option. WRITE mode: control envelop selection. READ mode read current envelope wave forms. Below ALARM functional block equivalent circuit diagram. activate ALARM function, first switch ALARM OUTPUT mode. After setting equal then proper envelope. When data writes into AEC, envelope counter will synchronized same time. programmer read back envelope from register make pattern changes needed programmer. Read operation will affect alarm output waveform.
Sound Mixer 16Hz
mask option OSCI OSCO mask option 262K
programming alarm waveform shown below (32.768KHz crystal 262K RC):
OUTPUT
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SH6612A
Option Bonding Option System Register (Bonding option) $0DH bond bond bond bond Remarks Bit0: Bonding option internal weak drive Bit1: Bonding option internal weak drive Power-on Pull Pull high
SH6612A Bonding Option different bonding options possible user's needs. chip's program different program flows that will vary depending which bonding option used. readable contents will differ depending bonding. HALT STOP mode After execution HALT instruction, SH6612A will enter halt mode. halt mode, will stop operating. peripheral circuit (Timer, Alarm LCD) will keep operating. After execution STOP instruction, SH6612A will enter stop mode. stop mode, whole chip (including oscillator) will stop operating. HALT mode, SH6612A waked interrupt occurs. STOP mode, SH6612A waked port interrupt occurs external interrupt occurs.
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SH6612A
Instructions instructions cycle word instructions. characteristics memory oriented operation. Arithmetic Logical Instruction Accumulator Type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) X(,B) Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
AC,Mx
AC,Mx
AC,Mx
AC,Mx
AC,Mx
AC,Mx
AC,Mx
AC[3]; AC[0] shift right
Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx Function Flag Change
AC,Mx
AC,Mx AC,Mx AC,Mx AC,Mx
assembler ASM66 V1.0, EORIM memonic EORI. However, EORI same operation identical with EORIM. Same ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function AC;Mx Decimal adjust add. AC;Mx Decimal adjust sub. Flag Change
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SH6612A
Transfer Instruction Mnemonic X(,B) X(,B) Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx Function Flag Change
AC,Mx
Control Instruction Mnemonic CALL Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx RTNW RTNI HALT STOP TJMP Where, Program counter Accumulator Complement accumulator Carry flag Data memory page Stack Table Branch Register Immediate data Logical exclusive Logical Logical bank=000 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 X(Include (PC11-PC8) (TBR) Function AC=0 CY=1 AC(0)=1 AC(1)=1 AC(2)=1 AC(3)=1 X(Not include hhhh; llll Flag Change
CY;PC
Operation
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SH6612A
*Absolute Maximum Ratings
Supply Voltage -0.3V +5.5V Input Voltage. -0.3V DD+0.3V Operating Ambient Temperature -10°C +70°C Storage Temperature -55°C +125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposed absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 3.0V, 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Standby Current Standby Current Input High Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Lighting Symbol ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 ILCD Min. Typ. Max. Unit output pins unload execute instruction output pins unload (HALT mode) exclude current output pins unload (STOP mode) off, current PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD (IOH 15µA) PORTA, PORTB, PORTC, PORTD (IOL= 300µA) (set PA.1and PA.2 ALARM output (set PA.1and PA.2 ALARM output SEGx, SEG1 output port (for reference only) SEGx, SEG1 output port (for reference only) COMx, (for reference only) COMx, (for reference only) HALT mode (normal driving capability) Conditions
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SH6612A
Electrical Characteristics (VDD 5.0V, 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter Operating Voltage Operating Voltage Standby Current Standby Current Input High Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Lighting Note: Operation frequency ISB1 ISB1x (Frequency/32.768KHz) Operation frequency Iopx (Frequency/32.768KHz) Iop, Isb1 Isb2 Iopx ISB1x ISB2x Symbol ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 ILCD 19.5 Min. Typ. Max. Unit output pins unload execute instruction output pins unload (HALT mode) exclude current output pins unload (STOP mode) off, current PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD PORTA, PORTB, PORTC, PORTD (IOH 15µA) PORTA, PORTB, PORTC, PORTD (IOL= 300µA) (set PA.1and PA.2 ALARM output (set PA.1and PA.2 ALARM output SEGx, SEG1 output port (for reference only) SEGx, SEG1 output port (for reference only) COMx, (for reference only) COMx, (for reference only) HALT mode (normal driving capability) Conditions
25°C, unless otherwise specified. Parameter Voltage Symbol VLVR Min. Typ. Max. Unit Condition enable
Note: This function always enable, user can't disable
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SH6612A
Characteristics (VDD 3.0V, 25°C, FOSC 32.768KHz unless otherwise specified)
Parameter Oscillation Start Time Halt Time Stop Time Frequency Stability Frequency Variation Symbol tSTT tHTT tSPT Min. Typ. Max. Unit reduces Isb1 after instruction executing reduces Isb2 after instruction executing (3.0)- (2.4)]/ (3.0), crystal oscillator (for reference only) (for reference only) Conditions
Characteristics (VDD 3.0V, 25°C, FOSC= 262KHz, unless otherwise specified)
Parameter Oscillation Start Time Halt Time Stop Time Frequency Stability Frequency Variation Symbol tSTT tHTT tSPT Min. Typ. Max. Unit reduces Isb1 after instruction executing reduces Isb3 after instruction executing (3.0)- (2.4)/ (3.0), oscillator (for reference only) variation caused process variation (for reference only) Conditions
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SH6612A
Application Circuits (for reference only)
SH6612A chip substrate connects system ground. 262K (code option) Panel: duty, bias; (S/W select duty, auto bias) Panel: duty, bias; (S/W select duty, auto bias; ignore duty segments) PORTA
bias
RESET 0.1uF
SH6612A
OSCI PORTA 750K TEST
OSC: 32.768KHz crystal (code option) LCD: duty, bias PORTB PORTA.0: external interrupt PORTA.1, PORTA.2: ALARM output (carrier frequency: 2KHz 4KHz code option) (code option)
bias
RESET 0.1uF
OSCI
32768Hz
SH6612A
OSCO TEST PORTA.1 PORTA.2 PORTA.0
BUZZER
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SH6612A
Application Circuits (continued)
OSC: 32.768KHz LCD: duty, bias PORTB.1 Output When higher than VLCD, reducing toVDD1 regulate voltage.
bias RESET 0.1uF OSCI 32768Hz OSCO PORTB.1 TEST
SH6612A
VDD1
262K (code option) Panel: duty, bias; (S/W select duty, auto bias) Panel: duty, bias; (S/W select duty, auto bias; ignore duty segments) PORTA Internal pull high resistor RESET (Code Option)
bias
RESET
SH6612A
OSCI PORTA 750K TEST
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SH6612A
Bonding Diagram
SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3
COM3 COM4 OSCI OSCO PORTD3 PORTD2 1658µm PORTD1 PORTD0 PORTC3 PORTC2 PORTC1 PORTC0 PORTB3
SH6612A
1644µm
Substrate connects GND. bonding wire with diameter 1.0mil recommended. Designation SEG2 SEG1 TEST RESET PORTA0 PORTA1 PORTA2 PORTA3 PORTB0 PORTB1 PORTB2 PORTB3 PORTC0 PORTC1 PORTC2 PORTC3 PORTD0 PORTD1 PORTD2 PORTD3 OSCO OSCI COM4 -630 -510 -395 -280 -165 -152.4 390.1 -758.8 -758.8 -758.8 -758.8 -758.8 -662.95 -758.8 -758.8 -758.8 -758.8 -758.8 -758.8 -758.8 -758.8 -638.8 -526.8 -416.8 -308.8 -200.8 -92.8 15.2 123.2 233.65 316.15 413.8 523.8 638.8 Designation COM3 COM2 COM1 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 -165 -275 -390 -510 -630 -752 -752 -752 -752 -752 -752 -752 -752 -752 -752 -752 -752 -752 -752
unit: 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 758.8 633.3 513.3 393.3 278.3 170.3 62.3 -45.7 -153.7 -263.7 -373.7 -488.7 -623.8 -758.8
Notice:
Locations SH6612A different from SH6612. Please attention.
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SH6612A
Ordering Information
Part SH6612AH Package CHIP FORM
Data sheet Version History
SH6612A Specification Revision History Version Content notice location Change LCD&HLM Waveform location double capacitors with 32.768K Crystal oscillator Change description "LCD divider resistor control" "LVR" instead "LPD" Change "Operating Ambient Temperature" location, "O/S" description, PORTD VOH,VOL Description Spec Original Date
Nov.2003
Nov.2003 Octo.2003 Sept.2003
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