Mask 4-Bit Microcontroller with Driver Clock source: 32.768KHz cr

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Mask 4-Bit Microcontroller with Driver Clock source: 32.768KHz cr

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SH6603
Mask 4-Bit Microcontroller with Driver
Clock source: 32.768KHz crystal 131K (type selected mask option) Instruction cycle time: 4/32.768KHz 122µs) 32.768KHz crystal 4/131KHz 31µs) 131KHz driver: (1/4,1/3, duty, 1/3,1/2 bias) Built-in EL-light driver Built-in Resistor Frequency converter circuit Built-in voltage charge pump circuit Built-in channel power operation modes: HALT STOP power consumption (ISB 2µA, 32.768KHz, Bonding option multi-code software Available CHIP FORM
Features
SH6610C-based single-chip 4-bit microcontroller with driver ROM: 2048 bits RAM: bits (data memory) Operation Voltage Range: 2.2V 3.6V (typical 3.0V) CMOS bi-directional pins level subroutine nesting (including interrupts) 8-bit timers with pre-divider circuit Built-in watch timer priority interrupt sources: External interrupt (rising edge) Timer0 interrupt Timer1 interrupt PortB PortC interrupt (rising edge)
General Description
SH6603 single-chip microcontroller integrated with SH6610C core, SRAM, program ROM, programmable driving buffers, 8-bit timer, generator, driver, EL-light driver, Resistor Frequency converter circuit watch timer.
Configuration
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 PORTC0/SEG31 PORTC1/SEG32 PORTC2/SEG33 PORTC3/SEG34 PORTB0/RX1 PORTB1/RX2 PORTB2/RX3 PORTB3/CX
SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM4 COM3 COM2 COM1
SH6603
V0.3
SH6603
Block Diagram
OSCI
OSCILLATOR DRIVERS
OSCO
COM1 SEG1
BITS VOLTAGE PUMP BITS DATA MEMORY
CUP1 CUP2
2048 BITS TIMER
PORTA [3:0]
PORTA [3:0] /Ex.INT INPUT /PSG OUTPUT /EL_LIGHT OUTPUT PORTB [3:0] /PORTB INPUT /RFC PORTC [3:0] /PORTC INPUT /SEG31
PORTB [3:0]
TIMER
PORTC [3:0]
RESET
WATCH TIMER
CHANNEL
TEST
CONVERTER EL_LIGHT DRIVER
SH6603
Description
Designation PORTA0 Description programmable Vector external interrupt. (active rising edge) Shared with output programmable pins Shared with output programmable pins Shared with EL-light output (PA2), (PA3) Test input. (High active with test mode, internal pull down) connect user Power supply 3.6V SH6603 Bonding option, internally pull-low Oscillator output pad, connect crystal oscillator Oscillator input pad, connect crystal external resistor Ground Bonding option, internally pull-high reset input. (Low active, internal pull Connect voltage booster capacitor Connect voltage booster capacitor Power supply driver Common signal output display Segment signal output display programmable pins.(Direct drive analog movement) Vector port interrupt. (active rising edge) Shared with SEG31 programmable pins Vector port interrupt. (active rising edge) PB.0 shared with PB.3 shared with CX.( counter input pin)
PORTA1 PORTA [2:3] TEST OSCO OSCI RESET CUP1 CUP2 COM1 SEG1 PORTC [0:3]
PORTB [0:3]
Total pads
SH6603
Functional Description
contains following functional blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, DPL), Stacks. address 2048 words bits program area from $0000H $07FFH. Vector Address Area ($000 $004) program sequentially executed. There area address $000 through $004 that reserved special interrupt service routine such starting vector address. Address 000H 001H 002H 003H 004H Instruction instruction instruction instruction instruction instruction Remarks Jump RESET service routine Jump External interrupt service routine Jump TIMER0 service routine Jump TIMER1 service routine Jump service routine
*JMP instruction replaced instruction. Table Data Reference Table Data stored program memory referenced using Table Branch (TJMP) Return Constant (RTNW) instructions. Table Branch Register (TBR) Accumulator placed offset address program ROM. TJMP instruction branch into address ((PC11 PC8) (28) (TBR, A)). address determined RTNW return look-up value into (TBR, code bit7-bit4 placed into bit3-bit0 into Built-in contains general-purpose data memory, system register. Addressing Data memory system register accessed instruction direct addressing. following memory allocation map: $000 $01F: System register $020 $09F: Data memory (128 bits, divided into banks). $300 $321: space bits). Data Memory Data memory organized bits ($020 $09F). Because static nature, keep data after enters STOP HALT. Data Pointer Data Pointer indirectly address data memory. Pointer address located register (3-bits), (3-bits) (4-bits). addressing range have 3FFH locations. Pseudo index address (INX) used read write Data memory, then address bit9 bit0 comes from DPH, DPL.
SH6603
Configuration System Register: Address IRQX T0L.3 T0H.3 T1L.3 T1H.3 PA.3 PB.3 PC.3 IET0 IRQT0 T0M.2 T1M.2 T0L.2 T0H.2 T1L.2 T1H.2 PA.2 PB.2 PC.2 IET1 IRQT1 T0M.1 T1M.1 T0L.1 T0H.1 T1L.1 T1H.1 PA.1 PB.1 PC.1 IRQP T0M.0 T1M.0 T0L.0 T0H.0 T1L.0 T1H.0 PA.0 PB.0 PC.0 Interrupt enable flags Interrupt request flags Bit0 Timer0 Mode register Bit0 Timer1 Mode register Timer0 load counter register nibble Timer0 load counter register high nibble Timer1 load counter register nibble Timer1 load counter register high nibble PORTA PORTB PORTC PAM: PORTA1 output S/P: PORTC segment output EL/P: PORTA3 light output RF/P: PORTB converter RX1, 3EN: Enables oscillation RX1, ENX: counter ELON: EL-LIGHT on/off control ELPF: EL-LIGHT driver charge frequency select ELF: EL-LIGHT driver discharge frequency select OSCS: type selection Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bonding option LPS1 frequency control DUTY1 duty BIAS: bias LCDOFF: control PSGEN: enable Prescaler PPULL: Port pull-down control C1.0 1.3: nibble C1.6 1.4: high nibble PORTA input/output control PORTB input/output control PORTC input/output control counter register nibble counter register middle_low nibble counter register middle_high nibble counter register high nibble Bit0 Watch timer control Watchdog timer overflow flag. (Read only) Remarks
RF/P
EL/P
RX3EN
RX2EN
RX1EN
ELON
ELPF
OSCS
TBR.3 INX.3 DPL.3 LPS1 LCDOFF
TBR.2 INX.2 DPL.2 DPM.2 DPH.2 LPS0 BIAS
TBR.1 INX.1 DPL.1 DPM.1 DPH.1
TBR.0 INX.0 DPL.0 DPM.0 DPH.0
DUTY
DUTY0
PPULL C1.3 PACR.3 PBCR.3 PCCR.3 RFL.3 RFML.3 RFMH.3 RFH.3
C1.2 C1.6 PACR.2 PBCR.2 PCCR.2 RFL.2 RFM.2 RFMH.2 RFH.2 WDT.2
C1.1 C1.5 PACR.1 PBCR.1 PCCR.1 RFL.1 RFML.1 RFMH.1 RFH.1 WDT.1
PSGEN C1.0 C1.4 PACR.0 PBCR.0 PCCR.0 RFL.0 RFML.0 RFMH.0 RFH.0 WDT.0
SH6603
System Register $13: (Bonding option) Address LPS1 LPS0 Remarks Bonding option LPS1 frequency control Default bonding option bond bond bond bond System Reset 00XX
SH6603 Bonding Option
different bonding options possible user's needs. chip's program different program flows that will vary depending which bonding option used. readable contents will differ depending bonding.
SH6603
Port provides ports. Each port contains pull-down controllable program. Bit3 PMOD register controls On/Off pull-downs simultaneously. Pull-down controlled port data registers (PDR) each port also (Write could turn pull-down MOS). pull-down turned individually. port control register (PCR) controls ON/OFF output buffer. PortA.0 shared with output PortA.1 shared with output PortA.2&3 shared with light output. PortB.0-3 shared with Resistor Frequency converter circuit I/O. PortC.0-3 shared with segment output. System Register $0B: Address Remarks PAM: PORTA1 output S/P: PORTC segment output EL/P: PORTA3 light output RF/P: PORTB converter PORTA0-1 port PORTA0-1 output PORTC port PORTC segment output PORTA3 port PORTA3 light output PORTB port PORTB port System Reset
RF/P
EL/P
0000
DATA INPUT
RD-INPUT
PORT CONTROL REGISTER PORT
PORT DATA REGISTER
PULL DOWN
Port Data Register: (PDR) Address PA.3 PB.3 PC.3 PA.2 PB.2 PC.2 PA.1 PB.1 PC.1 PA.0 PB.0 PC.0 Remarks PORTA PORTB PORTC System Reset XXXX XXXX XXXX
SH6603
Port Control Register: (PCR) Address Bit3 PACR.3 PBCR.3 PCCR.3 Bit2 PACR.2 PBCR.2 PCCR.2 Bit1 PACR.1 PBCR.1 PCCR.1 Bit0 PACR.0 PBCR.0 PCCR.0 Remarks PORTA input/output control PORTB input/output control PORTC input/output control System Reset 0000 0000 0000
control register: PACR.X, PBCR.X, PCCR.X input buffer. output buffer. Port Function Control: (PMOD) Address PPULL PSGEN Remark PSGEN: enable Prescaler PPULL: Port pull-down control System Reset 0000
PPULL Port Pull-down enables control Disable PORT pull-down Enable PORT pull-down
SH6603
Timer SH6603 8-bit timers. timer counter following features: 8-bit up-counting timer/counter. Automatic re-loads counter. 8-bit prescaler. Interrupt overflow from $00. following simplified timer block diagram.
Fosc/4 PRESCALER Tosc SYNC 8-BIT COUNTER
Timer Load Register: Since register controls physical READ WRITE operations. Please follow these steps: Write Operation: nibble first; High nibble update counter Read Operation: High Nibble first; nibble followed.
TM.2 TM.1 TM.0
timers provide following functions: Programmable interval timer function. Read counter value. Timer0 Timer1 Configuration Operation Both Timer0 Timer1 consist 8-bit write-only timer load register (TL0L, TL0H; TL1L, TL1H) 8-bit read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each them order digits high order digits. Writing data into timer load register (TL0L, TL0H; TL1L, TL1H) initialize timer counter. low-order digit should written first, then high-order digit. timer counter automatically loaded with contents load register when high order digit written counter counts overflow from $00. Timer Mode Register
Load Reg.
Load Reg.
8-bit timer counter Latch Reg.
timer programmed several different prescaler ratios setting Timer Mode register (TM0, TM1). 8-bit counter prescaler overflow output pulses. Timer Mode registers (TM0, TM1) 3-bit registers used timer control shown Table1 Table These mode registers select input pulse sources into timer. Table Timer0 Mode Register ($02) TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio /211 Clock Source System clock System clock System clock System clock System clock System clock System clock System clock Table Timer1 Mode Register ($03) TM1.2 TM1.1 TM1.0 Prescaler Divide Ratio /211 Clock Source System clock System clock System clock System clock System clock System clock System clock System clock
SH6603
System Clock SH6603 clock source. 32.768KHz crystal 131KHz determined mask option. generates basic clock pulses that provide system clock supply on-chip peripherals (TIMER0, TIMER1, LCD, PSG, Watchdog timer). System clock FOSC/4. Instruction cycle time: 4/32.768KHz 122µs) 32.768KHz oscillator. 4/131KHz 31µs) 131KHz oscillator. Oscillator 32.768KHz crystal:
OSCI Setting: (reference only) Crystal 32.768KHz
OSCO
131K
Rosc OSCI
OSCO
System Register (Bit0): Oscillator type select register Address Remarks ELON: EL-LIGHT on/off control ELPF: EL-LIGHT driver charge frequency select ELF: EL-LIGHT driver discharge frequency select OSCS: type selection 131KHz Oscillator 32.768KHz crystal Oscillator System Reset
ELON
ELPF
OSCS
0000
SH6603
Channel provided. 7-bit pseudo random counter. reduce power consumption, disable sound effect generator during both STOP HALT. control register Address PPULL C1.3 C1.2 C1.6 C1.1 C1.5 PSGEN C1.0 C1.4 Remarks PSGEN: enable Prescaler PPULL: Port pull-down control nibble high nibble System Reset 0000 0000 0000
PSGEN: disable, "BD" output enable Prescaler Ratio Clock source 32KHz 32KHz 32KHz 32KHz Actual Clock 131KHz 65.5KHz 32KHz 16KHz
channel
C1.6 C1.0
32.768KHz 131KHz
4-Bit Scaler
actual clock selected changing register $15H, selected, only different tone changing value value created group counters (LSFR). Different initial data written these counters, different created. Actual Clock
output frequency
SH6603
Value corresponding Register $16H $17H (C1.6 C1.0) shown following table LSFR (C1.6 C1.0) LSFR (C1.6 C1.0) LSFR (C1.6 C1.0) LSFR (C1.6 C1.0)
SH6603
Driver driver contains controller, voltage generator, common signal pads, segment driver pads. There bias modes (1/3 bias) three duty mode (1/4, duty) that programmable, data dual port that transfers data segment pads automatically without program control. PORTC SEG31 It's selected bit1 system register $0B. When ports, data won't effect input output data. Also, when output, data won't effect output. used data memory needed. When "STOP" instruction executed, will turned off, data same before execution "STOP" instruction. When off, both COMMON SEGMENT output Control Register Control Register $13: Address LPS1 LPS0 Remarks Bonding option LPS1 frequency control clock frequency fOSC/128 clock frequency fOSC/256 clock frequency fOSC/512 clock frequency fOSC/1024 System Reset 00XX
Frame frequency fFRM LCDCLK/8 @1/4 duty duty Frame frequency fFRM LCDCLK/6 @1/3 duty Control Register $14: Address LCDOFF BIAS DUTY DUTY0 Remarks DUTY1 duty BIAS: bias LCDOFF: control duty duty duty bias bias System Reset 0000
Note: When voltage converts circuit used.
SH6603
Configuration Area Segments 1/4duty Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Address COM4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
Segments 1/3duty Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Address COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SH6603
Segments 1/2duty Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Address COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
Connection Diagram
3.0V, 4.5VLCD, 1/3Bias
3.0V
3.0V, 3.0VLCD, 1/2Bias
3.0V
CUP1 0.1µF CUP2
CUP1 0.1µF CUP2 0.1µF
Voltage Pump Circuit
4.5V 0.1µF 1.5V 0.1µF (0V)
Voltage Pump Circuit
3.0V 0.1µF 1.5V
(0V)
Notice: pump circuit frequency could 8KHz, 4KHz, 2KHz 1KHz (selected mask option). When small panel, user select 1KHz pump frequency save power. when large panel, user select 8KHz pump frequency have more power supply ability use. Default pump circuit frequency 4KHz.
SH6603
Waveform duty, bias (VDD 3.0V, 4.5V, 1.5V,
COM1
COM2
COM3
COM4
COM1- 4-SEG display
COM1-SEG display
COM2-SEG display
COM3-SEG display SEG1 COM4-SEG display
COM1 3-SEG display
COM1 4-SEG display
COM1 4-SEG display Frame frequency
SH6603
duty, bias (VDD 3.0V, 4.5V, 1.5V,
COM1
COM2
COM3
COM4
COM1- 4-SEG display
COM1-SEG display
COM2-SEG display
COM3-SEG display SEG1 COM1 3-SEG display
COM1 3-SEG display Frame frequency
SH6603
duty, bias (VDD 3.0V, 4.5V, 1.5V,
COM1
COM2
COM3
COM4
COM1 2-SEG display
COM1-SEG display SEG1 COM2-SEG display
COM1 2-SEG display Frame frequency
SH6603
duty, bias (VDD 3.0V, 3.0V, 1.5V,
COM1 COM2 COM3 COM4
COM1 4-SEG display COM1-SEG display COM2-SEG display COM3-SEG display COM4-SEG display COM1 3-SEG display COM1 4-SEG display COM1 4-SEG display Frame frequency SEG1
SH6603
duty, bias (VDD 3.0V, 3.0V, N1.5V,
COM1 COM2 COM3 COM4
COM1 3-SEG display COM1-SEG display COM2-SEG display
SEG1 COM3-SEG display COM1 3-SEG display COM1 3-SEG display Frame frequency
duty, bias (VDD 3.0V, 3.0V, 1.5V,
COM1 COM2 COM3 COM4 COM1 2-SEG display COM1-SEG display
SEG1 COM2-SEG display COM1 2-SEG display Frame frequency
SH6603
Interrupt Four interrupt sources available SH6603: External interrupt (share with PA.0) Timer0 interrupt Timer1 interrupt Port's rising edge detection interrupt (PBC) Interrupt Control Bits Interrupt Service interrupt control flags mapped system register. They accessed tested program. Those flags cleared initialization chip reset. Address IET0 IET1 Remarks Interrupt enable flags System Reset 0000
When interrupt request generated (IRQx interrupt will activated vector address will generated from priority corresponding interrupt sources. When interrupt occurs, flag will saved into stack memory jump interrupt service vector address. After interrupt occurs, interrupt enable flags (IEx) reset automatically, when IRQx again, interrupt will activated vector address will generated from priority corresponding interrupt sources. Interrupt Servicing Sequence Diagram:
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
Interrupt Nesting: During SH6610C interrupt service, user enable interrupt enable flag before returning from interrupt. servicing sequence diagram shows next interrupt next nesting interrupt occurrences. interrupt request ready instruction execution enable, then interrupt will start immediately after next instruction executions. However, instruction instruction disables interrupt request enable flag, then interrupt service will terminated. External Interrupt (INT) External interrupt shared with bit0 PORTA. When bit3 system register (IEX) external interrupt will enabled, rising edge signal PA.0 will generate external interrupt. (Note: while external interrupt enabled, writing bit0 PORTA will generate external interrupt.) When PortA.0 shared with output, external disabled even Timer (Timer0,Timer1) Interrupt input clock Timer0 Timer1 based clock. timer overflow will generate internal interrupt request, when counter counts overflow from $00. interrupt enable flag enabled, then timer interrupt service routine will start. This also used wake from HALT mode.
Port Interrupt
PORTB PORTC used port interrupt sources. Since PORT programmable I/O, only input port generate external interrupt. PORTB PORTC input transitions from would generate interrupt request. Further rising edge transition would able make interrupt request until input pins have returned GND. This also used wake from STOP mode.
SH6603
EL-LIGHT System Register (Bit3 ~1): Address Remarks ELON: EL-LIGHT on/off control ELPF: EL-LIGHT driver charge frequency select ELF: EL-LIGHT driver discharge frequency select OSCS: type selection output frequency ELCLK output frequency ELCLK output frequency ELCLK output frequency ELCLK EL-LIGHT driver turn EL-LIGHT driver turn System Reset
ELON
ELPF
OSCS
0000
ELCLK 32KHz @32KHz crystal 131KHz/4 @131KHz oscillator. When EL-LIGHT off, output low. Setup system register select EL-LIGHT driver waveform. ELON will turn EL-LIGHT driver. will output driver waveform automatic diagram blew. With externally transistor, diode, inductance resistor, pump panel 250V.
ELON
Panel
While EL-LIGHT turned will turn before turned When EL-LIGHT turn off, will turn first, then will still work cycle make sure voltage left panel. EL-LIGHT would keep working HALT mode. would turn after executed "STOP" instruction (ELC keep low). Notice: Please turn EL-LIGHT before execute "STOP" instruction.
SH6603
Resistor Frequency Converter System Register $0B, $0C, $1E: Address Remarks System Reset
RF/P
RFL.3
PAM: PORTA1 output S/P: PORTC segment output EL/P EL/P: PORTA3 light output RF/P: PORTB converter RX1, 3EN: Enables oscillation RX1, RX3EN RX2EN RX1EN ENX: counter RFL.2 RFL.1 RFL.0 16-bit counter register nibble
0000
0000 0000 0000 0000 0000
RFML.3 RFM.2 RFML.1 RFML.0 16-bit counter register middle_low nibble RFMH.3 RFMH.2 RFMH.1 RFMH.0 16-bit counter register middle_high nibble RFH.3 RFH.2 RFH.1 RFH.0 16-bit counter register high nibble
When RF/P PortB used converter. oscillation circuit 16-bit counter used calculate relative resistance temperature humidity sensor. diagram shown below:
RF/P RX1EN Controller RX2EN RX3EN Rref 16-BIT Counter
methodologies measuring input count value: RXnEN (Enables oscillation RXn). Using timer1 timer0 interval control (start counter). When timer1 timer0 interrupt happened, 16-bit counter value RXn-F count value. repeat capture different count value Rref. Notice: When RF/P PORTB interrupt disabled. 16-bit counter event counter when using RFC. Max-frequency should less then 2MHz. could keep working HALT mode, would stop automatic when execute "STOP" instruction. (Keep last state RX1-3 ports stop counter) Temperature sensor resistor: @250C (for reference only) Humidity sensor: @250C, 50%RH (for reference only)
SH6603
Watch Timer Watch timer down-count counter, clock source 32768Hz 131/4KHz. watchdog timer automatically generates device reset when overflows. Software enable disable this function. watchdog timer control registers (WDT bit0 selects different overflow frequency. bit3 watchdog timer overflow flag. System Register (WDT) Address Remarks Bit0 Watch timer control Watch timer overflow flag.(Read only) Watchdog timer disable Watchdog timer overflow frequency 0.125Hz Watchdog timer overflow frequency 0.25Hz Watchdog timer overflow frequency 0.5Hz Watchdog timer overflow frequency Watchdog timer overflow frequency Watchdog timer overflow frequency Watchdog timer overflow frequency watchdog timer overflow reset Watchdog timer overflow Power 0000
WDT.2 WDT.1 WDT.0
will reset when watchdog timer overflows. normal operation, read write ($1F), watchdog timer should re-count before overflow happens. HALT STOP Mode After execution HALT instruction, SH6603 will enter halt mode. halt mode, will stop operating. peripheral circuit (Timer0, Timer1, display, RFC, EL-light, watchdog timer) will keep operating. After execution STOP instruction, SH6603 will enter stop mode. stop mode, whole chip (including oscillator, watchdog timer) will stop operating. HALT mode, SH6603 waked interrupt occurs. STOP mode, SH6603 waked external Interrupt port interrupt occurs. Warm-up Timer SH6603 builds oscillator warm-up timer eliminate unstable state initial oscillation when oscillator starts oscillating following conditions: Hardware reset Power reset Wake-up from stop mode Warm-up time interval: mode, warm-up counter prescaler divided (128), warm-up time interval 0.98 Crystal mode, warm-up counter prescaler divided (4096), warm-up time interval
SH6603
Initial State
There types system reset. Hardware reset input Power reset Watchdog timer overflow reset (When watchdog timer enable) Hardware Program Counter Data Memory Timer Counter Timer Mode Register Interrupt Enable Flags Interrupt Request Flags DPH, DPM, Port (Port PPULL driver driver EL-LIGHT driver driver $000 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Input (Disable PORT pull-down MOS) duty, bias 0000B (Hardware reset Power reset) 1000B (Watchdog timer overflow reset) After System Reset
SH6603
Instructions
instructions cycle one-word instructions. characteristic memory-oriented operation. Arithmetic Logical Instruction Accumulator Type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx Function Flag Change Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
[3]; shift right
Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function Decimal adjust add. Decimal adjust sub. Flag Change
SH6603
Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx Function Flag Change
Control Instruction Mnemonic CALL RTNW RTNI HALT STOP TJMP Where, Program counter Accumulator Complement accumulator Carry flag Data memory page Stack Table Branch Register Immediate data Logical exclusive Logical Logical bank 000, Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-PC8) (TBR) (AC) Function (Not include hhhh; llll Flag Change
Operation
SH6603
Absolute Maximum Ratings*
Supply Voltage -0.3V +7.0V Input Voltage. -0.3V 0.3V Operating Ambient Temperature .0°C +70°C Storage Temperature .-55°C +125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposed absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 3.0V, 25°C, FOSC 32.768KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Symbol Min. Typ. Max. Unit Execute instruction, output pads unload Include current (1/4duty, 1/3bias) Exclude current, HALT mode, output pads unload Include current (1/4duty, 1/3bias) Exclude current STOP mode, off, output pads unload PORTA, PORTB, PORTC TEST, Ex.INT, RESET PORTA, PORTB, PORTC TEST, Ex.INT, RESET PORTA, PORTC (IOH -1.0mA) PORTA, PORTC (IOL 2.0mA) (set PA.0, PA.1 output ELC,ELP (set PA.2, PA.3 driver), (IOH -0.3mA) (set PA.0, PA.1 output ELC,ELP (set PA.2, PA.3 driver), (IOL 0.3mA) PORTB (IOH -3.0mA) PORTB (IOL= 3.0mA) SEGx (IOH -3.0µA, 1/3bias) SEGx (IOL 3.0µA, 1/3bias) COMx (IOH -8.0µA, 1/3bias) COMx (IOL -8.0µA, 1/3bias) Pull-down resistor VDD) Conditions
Standby Current Standby Current Input High Voltage Input High Voltage Input Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage
ISB1 ISB2 VIH1 VIH2 VIL1 VIL2 VOH1 VOL1 VOH2
Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Pull-low Resistor
VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5
SH6603
Electrical Characteristics (VDD 3.0V, 25°C, FOSC 131KHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Symbol Min. Typ. Max. Unit Execute instruction, output pads unload Include current (1/4duty, 1/3bias) Exclude current HALT mode, output pads unload Include current (1/4duty, 1/3bias) Exclude current STOP mode, off, output pads unload Conditions
Standby Current Standby Current
ISB1 ISB2
Characteristics (VDD 3.0V, 25°C, unless otherwise specified)
Parameter Oscillation Start Time Frequency stability Frequency Variation Symbol TSTT Min. Typ. Max. Unit Conditions FOSC 32.768KHz Crystal FOSC 131KHz |F(2.4V) F(3.0V)|/F(3.0V) FOSC 131KHz Chip chip variation
Mask Option
Clock Source Select 32768Hz Crystal (default) 131KHz Pump Circuit Frequency Select 1KHz 2KHz 4KHz (default) 8KHz
SH6603
Application Circuit (for reference only)
AP1: (10) (11) (12) Oscillator: 32.768KHz Crystal (mask option system register $0D'bit0=1). PORTA0, output. PORTA2, EL-Light output. PORTB0 (Resistor Frequency Converter). PORTC0 (Input: Output: Direct drive analog movement). driver: Duty, Bias, 4.5V LCD. Temperature Sensor. Humidity Sensor. Rref: Reference Resister. converter capacitor. 3.0V, 32.768KHz Crystal. 12pF, 0.1µF, 100, 10K, IN4148, 3.2mH/15.
4COM 30SEG 1/4Duty 1/3Bias
OSCI OSCO Rref RESET Reset TEST PORTC0 PORTA3 CUP1 CUP2 PORTA2 COM1 SEG1 PORTA0 PORTA1 Panel BUZZER
SH6603
SH6603
AP2: Oscillator: 32.768KHz Crystal (mask option system register $0D'bit0=1). PORTA0, output. PORTA2, EL-Light output. PORTB0 (Input: Output: Direct drive analog movement). PORTC0 Shared with SEG31 driver: Duty, Bias, LCD. 3.0V, 32.768KHz Crystal. 12pF, 0.1µF, 100, 10K, IN4148, 3.2mH/15.
4COM 34SEG 1/4Duty 1/2Bias
CUP1 PORTA1 CUP2 OSCI OSCO RESET Reset TEST PORTB0 PORTA2 Panel BUZZER COM1 SEG1 PORTA0
SH6603
PORTA3
AP3: Oscillator: 131KHz (mask option system register $0D'bit0=0). PORTA, I/O.(40Keys) driver: Duty, Bias, 4.5V LCD. 3.0V, ROSC =1.8M, 0.1µF.
4COM 30SEG 1/4Duty 1/3Bias
Rosc CUP1 CUP2 OSCI OSCO COM1 SEG1 PORTA0 PORTA1 PORTA2 PORTA3 PORTB0 PORTB1 PORTB2 PORTB3 PORTC0 PORTC1 PORTC2 PORTC3 TEST
SH6603
RESET Reset
SH6603
Ordering Information
Part SH6603H Package CHIP FORM
SH6603
Bonding Diagram
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 PORTC0/SEG31 PORTC1/SEG32 PORTC2/SEG33 PORTC3/SEG34 PORTB0/RX1 PORTB1/RX2 PORTB2/RX3 PORTB3/CX
(0,0) SEG10 SEG9 SEG8 SEG7 SEG6 1961µm SEG5 SEG4 SEG3 SEG2 SEG1 COM4 COM3 COM2 COM1
SH6603
1971µm
Substratum connects GND. Unit: Designation PORTA0 PORTA1 PORTA2 PORTA3 TEST OSCO OSCI RESET CUP1 CUP2 COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 -852.00 -720.00 -590.00 -470.00 -350.00 -233.00 -233.00 -115.00 0.00 118.00 118.00 235.00 350.00 470.00 590.00 720.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 852.00 -847.00 -847.00 -847.00 -847.00 -847.00 -755.00 -847.00 -847.00 -847.00 -755.00 -847.00 -847.00 -847.00 -845.00 -847.00 -847.00 -847.00 -715.00 -585.00 -465.00 -345.00 -230.00 -115.00 0.00 115.00 230.00 345.00 465.00 585.00 Designation SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 PORTC0 PORTC1 PORTC2 PORTC3 PORTB0 PORTB1 PORTB2 PORTB3 852.00 852.00 720.00 590.00 470.00 350.00 230.00 115.00 0.00 -115.00 -230.00 -350.00 -470.00 -590.00 -720.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 -852.00 715.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 847.00 845.00 715.00 585.00 465.00 345.00 230.00 115.00 0.00 -115.00 -230.00 -345.00 -465.00 -585.00 -715.00
SH6603
Appendix:
Music Scale Reference Table (for reference only) Table Following music scale reference table under actual clock 32KHz. Note Ideal freq. 130.81 138.59 146.83 155.56 164.81 174.61 185.00 195.99 207.65 220.00 233.08 246.94 261.62 277.18 293.66 311.13 329.62 349.22 369.99 LSFR Real freq. Error (C1.6-C1.0) 131.15 139.13 146.79 155.34 164.95 173.91 186.05 195.12 207.79 219.18 231.88 246.15 262.30 275.86 296.30 313.73 326.53 347.83 372.09 0.26% 0.39% -0.03% -0.14% 0.08% -0.40% 0.57% -0.44% 0.07% -0.37% -0.51% -0.32% 0.26% -0.48% 0.90% 0.84% -0.94% -0.40% 0.57% Note Ideal freq. 392.00 415.31 440.00 466.17 493.85 523.24 554.37 587.32 622.25 659.24 698.44 739.99 783.96 830.60 880.00 932.32 987.76 1046.48 1108.72 LSFR Real freq. Error (C1.6-C1.0) 390.24 410.26 444.44 470.59 500.00 516.13 551.72 592.59 615.38 666.67 695.65 727.27 800.00 842.11 888.89 941.18 1000.00 1066.67 1142.86 -0.44% -1.21% 1.01% 0.95% 1.24% -1.36% -0.48% 0.90% -1.10% 1.13% -0.40% -1.72% 2.04% 1.38% 1.01% 0.95% 1.24% 1.93% 3.08%
SH6603
Table2: Following music scale reference table under actual clock 16KHz. Note Ideal freq. 65.41 69.30 73.42 77.78 82.41 87.31 92.50 98.00 103.83 110.00 116.54 123.47 130.81 138.59 146.83 155.56 164.81 174.61 185.00 LSFR Real freq. Error (C1.6-C1.0) 65.58 69.57 73.40 77.67 82.48 86.96 93.03 97.56 103.90 109.59 115.94 123.08 131.15 137.93 148.15 156.87 163.27 173.92 186.05 0.26% 0.39% -0.03% -0.14% 0.08% -0.40% 0.57% -0.44% 0.07% -0.37% -0.51% -0.32% 0.26% -0.48% 0.90% 0.84% -0.94% -0.40% 0.57% Note Ideal freq. 195.99 207.65 220.00 233.08 246.94 261.62 277.18 293.66 311.13 329.62 349.22 369.99 392.00 415.31 440.00 466.17 493.85 523.24 554.37 LSFR Real freq. Error (C1.6-C1.0) 195.12 205.13 222.22 235.30 250.00 258.07 275.86 296.30 307.69 333.34 347.83 363.64 400.00 421.06 444.45 470.59 500.00 533.34 571.43 -0.44% -1.21% 1.01% 0.95% 1.24% -1.36% -0.48% 0.90% -1.10% 1.13% -0.40% -1.72% 2.04% 1.38% 1.01% 0.95% 1.24% 1.93% 3.08%
SH6603
Table3: Following music scale reference table under actual clock 131KHz. Note Ideal freq. 523.24 554.37 587.32 622.25 659.24 698.44 739.99 783.96 830.60 880.00 932.32 987.76 1046.48 1108.72 1174.64 1244.52 1318.48 1396.88 1479.96 LSFR Real freq. Error (C1.6-C1.0) 524.00 555.08 584.82 623.81 661.62 696.81 735.96 779.76 829.11 885.14 935.71 992.42 1039.68 1110.17 1169.64 1235.85 1310.00 1393.62 1488.64 0.15% 0.13% -0.43% 0.25% 0.36% -0.23% -0.55% -0.54% -0.18% 0.58% 0.36% 0.47% -0.65% 0.13% -0.43% -0.70% -0.64% -0.23% 0.59% Note Ideal freq. 1568.00 1661.24 1760.00 1864.68 1975.40 2092.96 2217.48 2349.28 2489.00 2636.96 2793.76 2959.96 3135.84 3322.40 3520.00 3729.28 3951.04 4185.92 4434.88 LSFR Real freq. Error (C1.6-C1.0) 1559.52 1679.49 1770.27 1871.43 1984.85 2112.90 2183.33 2339.29 2519.23 2620.00 2847.83 2977.27 3119.05 3275.00 3447.37 3638.89 3852.94 4093.75 4366.67 -0.54% 1.10% 0.58% 0.36% 0.48% 0.95% -1.54% -0.43% 1.21% -0.64% 1.94% 0.58% -0.54% -1.43% -2.06% -2.42% -2.48% -2.20% -1.54%
Oscillator Characteristics (for reference only) Typical oscillator Resistor VDD:
131KHz 1.86 1.84 1.82 1.80 1.78 1.76 1.74
SH6603
Typical oscillator Frequency VDD:
1.8M) 135.0 134.0 133.0 (KHz) 132.0 131.0 130.0 129.0 128.0
Typical oscillator Resistor Frequency:
3.0V 2.40 2.20 2.00 1.80 1.60 1.40 1.20 100.0 110.0 120.0 130.0 140.0 150.0 160.0 170.0
(KHz)
SH6603
Data Sheet Version History
Version Content electrical characters change. Functional Description changes. Preliminary SPEC. electrical characters change. Application circuit added. Bonding diagram added. Original Date Jul. 2003 Jan. 2002 May. 2001

Mask 4-Bit Microcontroller with Driver Clock source: 32.768KHz cr

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