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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Latency Frequency
Latency Maximum Operating Frequency (MHz) DDR200 DDR266A DDR333
Double data rate architecture: data transfers clock cycle Bidirectional data strobe (DQS) transmitted received with data, used capturing data receiver edge-aligned with data reads center-aligned with data writes Differential clock inputs Four internal banks concurrent operation Data mask (DM) write data. organi-
zation (LDM, UDM), byte. aligns transitions with transitions Commands entered each positive edge; data data mask referenced both edges Burst Lengths: Latency: 2.5, Auto Precharge option each burst access Auto Refresh Self Refresh Modes 15.6 Maximum Average Periodic Refresh Interval refresh) 2.5V (SSTL_2 compatible) VDDQ 2.5V 0.2V 2.5V 0.2V TSOP66 package
Description
128Mb SDRAM high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. internally configured quad-bank DRAM. 128Mb SDRAM uses double-data-rate architecture achieve high-speed operation. double data rate architecture essentially prefetch architecture with interface designed transfer data words clock cycle pins. single read write access 128Mb SDRAM effectively consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, onehalf-clock-cycle data transfers pins. bidirectional data strobe (DQS) transmitted externally, along with data, data capture receiver. strobe transmitted SDRAM during Reads memory controller during Writes. edge-aligned with data Reads center-aligned with data Writes. 128Mb SDRAM operates from differential clock crossing going HIGH going referred positive edge CK). Commands (address control signals) registered every positive edge Input data registered both edges DQS, output data referenced both edges DQS, well both edges Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed. address bits registered coinci2002-05-06
dent with Read Write command used select bank starting column location burst access. SDRAM provides programmable Read Write burst lengths locations. Auto Precharge function enabled provide self-timed precharge that initiated burst access. with standard SDRAMs, pipelined, multibank architecture SDRAMs allows concurrent operation, thereby providing high effective bandwidth hiding precharge activation time. auto refresh mode provided along with power-saving power-down mode. inputs compatible with JEDEC Standard SSTL_2. outputs SSTL_2, Class compatible. Note: functionality described timing specifications included this data sheet Enabled mode operation.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Ordering Information
Part Number HYB25D128400AT(L)-8 HYB25D128800AT(L)-8 HYB25D128160AT(L)-8 DDR200 Latency Clock (MHz) Latency Clock (MHz) Speed Org. Package
HYB25D128400AT(L)-7 HYB25D128800AT(L)-7 HYB25D128160AT(L)-7 DDR266A
TSOP-II
HYB25D128400AT(L)-6 HYB25D128800AT(L)-6 HYB25D128160AT(L)-6 DDR333
Power Versions have partnumber, f.e. HYB25D128400ATL-8. These components specifically selected IDD6 Self Refresh currents.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Configuration
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VDDQ VSSQ VDDQ VSSQ VDDQ A10/AP
VDDQ VSSQ VDDQ VSSQ LDQS A10/AP
16Mb 32Mb
DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ VSSQ UDQS VREF
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
VSSQ VDDQ VSSQ VDDQ VSSQ VREF
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Input/Output Functional Description
Symbol Type Input Function Clock: differential clock inputs. address control input signals sampled crossing positive edge negative edge Output (read) data referenced crossings (both directions crossing). Clock Enable: HIGH activates, deactivates, internal clock signals device input buffers output drivers. Taking provides Precharge Power-Down Self Refresh operation (all banks idle), Active Power-Down (row Active bank). synchronous power down entry exit, self refresh entry. asynchronous self refresh exit. must maintained high throughout read write accesses. Input buffers, excluding disabled during power-down. Input buffers, excluding CKE, disabled during self refresh. Chip Select: commands masked when registered HIGH. provides external bank selection systems with multiple banks. considered part command code. standard pinout includes pin. Command Inputs: RAS, (along with define command being entered. Input Data Mask: input mask signal write data. Input data masked when sampled HIGH coincident with that input data during Write access. sampled both edges DQS. Although pins input only, loading matches loading. x16, corresponds data DQ0-DQ7; corresponds data DQ8-DQ15. Bank Address Inputs: define which bank Active, Read, Write Precharge command being applied. also determines mode register extended mode register accessed during EMRS cycle. Address Inputs: Provide address Active commands, column address Auto Precharge Read/Write commands, select location memory array respective bank. sampled during Precharge command determine whether Precharge applies bank (A10 LOW) banks (A10 HIGH). only bank precharged, bank selected BA0, BA1. address inputs also provide op-code during Mode Register command. Data Input/Output: Data bus. Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered write data. Used capture write data.For x16, LDQS corresponds data DQ0-DQ7; UDQS corresponds data DQ8-DQ15. Connect: internal electrical connection present. Supply Supply Supply Supply Supply Power Supply: 2.5V 0.2V. Ground Power Supply: 2.5V 0.2V. Ground SSTL_2 reference voltage: (VDDQ
Input
RAS, CAS,
Input Input
UDM,
Input
BA0,
Input
Input
UDQS,LDQS VDDQ VSSQ VREF
Input/Output Input/Output
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Block Diagram (32Mb
Control Logic
Command Decode
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
4096
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (4096 1024
Data
Address Register
A0-A11, BA0,
Gating Mask Logic 1024 (x8) Column Decoder
COL0 Write FIFO Drivers
Input Register Mask
Receivers
DQ0-DQ3,
Data COL0
Column-Address Counter/Latch
COL0
Note: This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. Note: unidirectional signal (input only), internally loaded match load bidirectional signals.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Block Diagram (16Mb
Control Logic
Command Decode
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
4096
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (4096
Data
Address Register
A0-A11, BA0,
Gating Mask Logic
(x16)
COL0 Write FIFO Drivers
Input Register Mask
Receivers
DQ0-DQ7,
Column Decoder Column-Address Counter/Latch COL0
Data COL0
Note: This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. Note: unidirectional signal (input only), internally loaded match load bidirectional signals.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Block Diagram (8Mb
Command Decode
Control Logic
Bank1 Row-Address Bank0 Row-Address Latch Decoder
Bank2
Bank3
Mode Registers
4096
Read Latch
Refresh Counter
Generator
Sense Amplifiers Bank Control Logic
8192
Drivers
Bank0 Memory Array (4096 256x
Data
Address Register
A0-A11, BA0,
Gating Mask Logic
(x32)
COL0 Write FIFO Drivers
Input Register Mask
Receivers
DQ0-DQ15, LDQS, UDQS
Column Decoder Column-Address Counter/Latch COL0
Data COL0
Note: This Functional Block Diagram intended facilitate user understanding operation device; does represent actual circuit implementation. Note: unidirectional signals (input only), internally loaded match load bidirectional UDQS LDQS signals.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Functional Description
128Mb SDRAM high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. 128Mb SDRAM internally configured quad-bank DRAM. 128Mb SDRAM uses double-data-rate architecture achieve high-speed operation. doubledata-rate architecture essentially prefetch architecture, with interface designed transfer data words clock cycle pins. single read write access 128Mb SDRAM consists single 2n-bit wide, clock cycle data transfer internal DRAM core corresponding n-bit wide, one-half clock cycle data transfers pins. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration Active command, which then followed Read Write command. address bits registered coincident with Active command used select bank accessed (BA0, select bank; A0-A11 select row). address bits registered coincident with Read Write command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. following criteria must met: power sequencing specified during power power down given following criteria: VDDQ driven from single power converter output meets specification minimum resistance ohms limits input current from supply into VREF tracks VDDQ/2 following relationship must followed: VDDQ driven after with such that VDDQ driven after with VDDQ such that VDDQ 0.3V VREF driven after with VDDQ such that VREF VDDQ 0.3V outputs High-Z state, where they remain until driven normal operation read access). After power supply reference voltages stable, clock stable, SDRAM requires 200µs delay prior applying executable command. Once 200µs delay been satisfied, Deselect command should applied, should brought HIGH. Following command, Precharge command should applied. Next Mode Register command should issued Extended Mode Register, enable DLL, then Mode Register command should issued Mode Register, reset DLL, program operating parameters. clock cycles required between reset executable command. During cycles clock locking, Deselect command must applied. After clock cycles, Precharge command should applied, placing device "all banks idle" state. Once idle state, AUTO REFRESH cycles must performed. Additionally, Mode Register command Mode Register, with reset deactivated (i.e. program operating parameters without resetting DLL) must performed. Following these cycles, SDRAM ready normal operation.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Register Definition
Mode Register Mode Register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode. Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power (except which self-clearing). Mode Register bits A0-A2 specify burst length, specifies type burst (sequential interleaved), A4-A6 specify latency, A7-A11 specify operating mode. Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements results unspecified operation. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable. burst length determines maximum number column locations that accessed given Read Write command. Burst lengths locations available both sequential interleaved burst types. Reserved states should used, unknown operation incompatibility with future versions result. When Read Write command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst wraps within block boundary reached. block uniquely selected A1-Ai when burst length two, A2-Ai when burst length four A3-Ai when burst length eight (where most significant column address given configuration). remaining (least significant) address bit(s) (are) used select starting location within block. programmed burst length applies both Read Write bursts.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Mode Register Operation
Address Mode Register
Operating Mode
Latency
Burst Length
Valid Valid
Operating Mode Normal operation reset Normal operation Reset Test Mode Reserved Burst Type Sequential Interleave
Latency
Latency Reserved Reserved (optional) Reserved Reserved (1.5**) Reserved
Burst Length
Burst Length Reserved Reserved Reserved Reserved Reserved
must select Mode Register (vs. Extended Mode Register). will supported future versions this product
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Burst Definition
Starting Column Address Burst Length Type Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Order Accesses Within Burst
Notes: burst length two, A1-Ai selects two-data-element block; selects first access within block. burst length four, A2-Ai selects four-data-element block; A0-A1 selects first access within block. burst length eight, A3-Ai selects eight-data- element block; A0-A2 selects first access within block. Whenever boundary block reached within given sequence above, following access wraps within block. Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition page Read Latency Read latency, latency, delay, clock cycles, between registration Read command availability first burst output data. latency programmed clocks. Read command registered clock edge latency clocks, data available nominally coincident with clock edge Reserved states should used unknown operation incompatibility with future versions result.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Operating Mode normal operating mode selected issuing Mode Register Command with bits A7-A11 zero, bits A0-A6 desired values. reset initiated issuing Mode Register command with bits A9-A11 each zero, one, bits A0-A6 desired values. Mode Register command issued reset should always followed Mode Register command select normal operating mode. other combinations values A7-A11 reserved future and/or test modes. Test modes reserved states should used unknown operation incompatibility with future versions result.
Required Latencies
Latency
Command Read CL=2
Latency 2.5,
Command Read CL=2.5
Shown with nominal tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Extended Mode Register
Extended Mode Register controls functions beyond those controlled Mode Register; these additional functions include enable/disable, output drive strength selection (optional). These functions controlled bits shown Extended Mode Register Definition. Extended Mode Register programmed Mode Register command (with retains stored information until programmed again device loses power. Extended Mode Register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements result unspecified operation. Enable/Disable must enabled normal operation. enable required during power initialization, upon returning normal operation after having disabled purpose debug evaluation. automatically disabled when entering self refresh operation automatically re-enabled upon exit self refresh operation. time enabled, clock cycles must occur before Read command issued. This reason clock cycles must occur before issuing Read Write command upon exit self refresh operation. Output Drive Strength normal drive strength outputs specified SSTL_2, Class curves normal drive strength included this document. addition this design version supports weak driver mode lighter load and/or point-to-point environments which activated during mode register set. curves weak driver mode will included this document later.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Extended Mode Register Definition
Address Extended Mode Register
Operating Mode
Drive Strength
Valid Operating Mode Normal Operation other states Reserved Normal Weak Drive Strength
must must select Extended Mode Register (vs. base Mode Register) Enable Disable
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Commands
Deselect Deselect function prevents commands from being executed SDRAM. SDRAM effectively deselected. Operations already progress affected. Operation (NOP) Operation (NOP) command used perform SDRAM. This prevents unwanted commands from being registered during idle wait states. Operations already progress affected. Mode Register mode registers loaded inputs A0-A11, BA1. mode register descriptions Register Definition section. Mode Register command only issued when banks idle bursts progress. subsequent executable command cannot issued until tMRD met. Active Active command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A11 selects row. This remains active open) accesses until Precharge Read Write with Auto Precharge) issued that bank. Precharge Read Write with Auto Precharge) command must issued completed before opening different same bank. Read Read command used initiate burst read access active (open) row. value BA0, inputs selects bank, address provided inputs A0-Ai, (where don't care] x16, don't care] selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Read burst; Auto Precharge selected, remains open subsequent accesses. Write Write command used initiate burst write access active (open) row. value BA0, inputs selects bank, address provided inputs A0-Ai, (where don't care] where selects starting column location. value input determines whether Auto Precharge used. Auto Precharge selected, being accessed precharged Write burst; Auto Precharge selected, remains open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered low, corresponding data written memory; signal registered high, corresponding data inputs ignored, Write executed that byte/column location. Precharge Precharge command used deactivate (close) open particular bank open row(s) banks. bank(s) will available subsequent access specified time after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. Otherwise BA0, treated
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
"Don't Care." Once bank been precharged, idle state must activated prior Read Write commands being issued that bank. precharge command treated there open that bank, previously open already process precharging. Auto Precharge Auto Precharge feature which performs same individual-bank precharge functions described above, without requiring explicit command. This accomplished using enable Auto Precharge conjunction with specific Read Write command. precharge bank/row that addressed with Read Write command automatically performed upon completion Read Write burst. Auto Precharge nonpersistent that either enabled disabled each individual Read Write command. Auto Precharge ensures that precharge initiated earliest valid stage within burst. user must issue another command same bank until precharge (tRP) completed. This determined explicit Precharge command issued earliest possible time, described each burst type Operation section this data sheet. Burst Terminate Burst Terminate command used truncate read bursts (with Auto Precharge disabled). most recently registered Read command prior Burst Terminate command truncated, shown Operation section this data sheet. Auto Refresh Auto Refresh used during normal operation SDRAM analogous Before (CBR) Refresh previous DRAM types. This command nonpersistent, must issued each time refresh required. refresh addressing generated internal refresh controller. This makes address bits "Don't Care" during Auto Refresh command. 128Mb SDRAM requires Auto Refresh cycles average periodic interval 15.6 (maximum). allow improved efficiency scheduling switching between tasks, some flexibility absolute refresh interval provided. maximum eight Auto Refresh commands posted system, meaning that maximum absolute interval between Auto Refresh command next Auto Refresh command 15.6 This maximum absolute interval short enough allow updates internal SDRAM restricted Auto Refresh cycles, without allowing much drift between updates. Self Refresh Self Refresh command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. Self Refresh command initiated Auto Refresh command coincident with transitioning low. automatically disabled upon entering Self Refresh, automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before Read command issued). Input signals except (low) "Don't Care" during Self Refresh operation. procedure exiting self refresh requires sequence commands. (and must stable prior returning high. Once high, SDRAM must have commands issued tXSNR because time required completion internal refresh progress. simple algorithm meeting both refresh requirements apply NOPs clock cycles before applying other command.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Truth Table Commands
Name (Function) Deselect (Nop) Operation (Nop) Active (Select Bank Activate Row) Read (Select Bank Column, Start Read Burst) Write (Select Bank Column, Start Write Burst) Burst Terminate Precharge (Deactivate Bank Banks) Auto Refresh Self Refresh (Enter Self Refresh Mode) Mode Register Address Bank/Row Bank/Col Bank/Col Code Op-Code Read Write Notes
HIGH commands shown except Self Refresh. BA0, select either Base Extended Mode Register (BA0 selects Mode Register; selects Extended Mode Register; other combinations BA0-BA1 reserved; A0-A11 provide op-code written selected Mode Register.) BA0-BA1 provide bank address A0-A11 provide address. BA0, provide bank address; A0-Ai provide column address (where x16, x4); HIGH enables Auto Precharge feature (nonpersistent), disables Auto Precharge feature. LOW: BA0, determine which bank precharged. HIGH: banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH; Self Refresh LOW. Internal refresh counter controls bank addressing; inputs I/Os "Don't Care" except CKE. Applies only read bursts with Auto Precharge disabled; this command undefined (and should used) read bursts with Auto Precharge enabled write bursts Deselect functionally interchangeable.
Truth Table Operation
Name (Function) Write Enable Write Inhibit Used mask write data; provided coincident with corresponding data. Valid Notes
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Operations
Bank/Row Activation Before Read Write commands issued bank within SDRAM, that bank must "opened" (activated). This accomplished Active command addresses A0-A11, (see Activating Specific Specific Bank), which decode select both bank activated. After opening (issuing Active command), Read Write command issued that row, subject tRCD specification. subsequent Active command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive Active commands same bank defined tRC. subsequent Active command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive Active commands different banks defined tRRD.
Activating Specific Specific Bank
A0-A11 BA0, address. bank address. Don't Care HIGH
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
tRCD tRRD Definition
Command A0-A11 BA0,
RD/WR
tRRD
tRCD
Don't Care
Reads Subsequent programming mode register with latency, burst type, burst length, Read bursts initiated with Read command, shown Read Command page starting column bank addresses provided with Read command Auto Precharge either enabled disabled that burst access. Auto Precharge enabled, that accessed starts precharge completion burst, provided tRAS been satisfied. generic Read commands used following illustrations, Auto Precharge disabled. During Read bursts, valid data-out element from starting column address available following latency after Read command. Each subsequent data-out element valid nominally next positive negative clock edge (i.e. next crossing CK). Page Read Burst: Latencies (Burst Length page shows general timing each supported latency setting. driven SDRAM along with output data. initial state known read preamble; state coincident with last data-out element known read postamble. Upon completion burst, assuming other commands have been initiated, goes High-Z. Data from Read burst concatenated with truncated with data from subsequent Read command. either case, continuous flow data maintained. first data element from burst follows either last element completed burst last desired data element longer burst which being truncated. Read command should issued cycles after first Read command, where equals number desired data element pairs (pairs required prefetch architecture). This shown Consecutive Read Bursts: Latencies (Burst Length page Read command initiated clock cycle following previous Read command. Nonconsecutive Read data illustrated Non-Consecutive Read Bursts: Latencies (Burst Length page Full-speed Random Read Accesses: Latencies (Burst Length within page pages) performed shown page
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Read Command
A0-A9, A0-A9 x16: A0-A8 BA0, column address bank address enable Auto Precharge disable Auto Precharge Don't Care HIGH
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Read Burst: Latencies (Burst Length
Latency
Command Address
Read
a,COL
CL=2
DOa-n
Latency
Command Address
Read a,COL
CL=2.5
DOa-n
data from bank column subsequent elements data appear programmed order following a-n. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Consecutive Read Bursts: Latencies (Burst Length
Latency
Command Address
Read Read
BAa,
BAa,
CL=2
DOa-n DOa-b
Latency
Command Address
Read
BAa,
Read
BAa,COL
CL=2.5
DOa- DOa-
a-b) data from bank column bank column When burst length bursts concatenated. When burst length second burst interrupts first. subsequent elements data appear programmed order following a-n. subsequent elements data appear programmed order following a-b. Shown with nominal tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Non-Consecutive Read Bursts: Latencies (Burst Length
Latency
Command Address
Read
BAa,
Read
BAa,
CL=2
DOa-
Latency
Command Address
Read
BAa,
Read
BAa,
CL=2.5
DOa-
a-b) data from bank column bank column subsequent elements data appear programmed order following (and following a-b). Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Random Read Accesses: Latencies (Burst Length
Latency
Command Address
Read
BAa,
Read
BAa,
Read
BAa,
Read
BAa,
CL=2
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b' DOa-g
Latency
Command Address
Read Read Read Read
BAa,
BAa,
BAa,
BAa,
CL=2.5
DOa-n DOa-n' DOa-x DOa-x' DOa-b DOa-b'
a-n, etc. data from bank column etc. etc. even complement etc. (i.e., column address inverted). Reads active rows banks. Shown with nominal tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Data from Read burst truncated with Burst Terminate command, shown Terminating Read Burst: Latencies (Burst Length page Burst Terminate latency equal read (CAS) latency, i.e. Burst Terminate command should issued cycles after Read command, where equals number desired data element pairs. Data from Read burst must completed truncated before subsequent Write command issued. truncation necessary, Burst Terminate command must used, shown Read Write: Latencies (Burst Length page example shown tDQSS(min). tDQSS(max) case, shown here, longer idle time. DQSS(min) tDQSS(max) defined section Writes. Read burst followed truncated with, Precharge command same bank (provided that Auto Precharge activated). Precharge command should issued cycles after Read command, where equals number desired data element pairs (pairs required prefetch architecture). This shown Read Precharge: Latencies (Burst Length page Read latencies 2.5. Following Precharge command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data elements. case Read being executed completion, Precharge command issued optimum time described above) provides same operation that would result from same Read burst with Auto Precharge enabled. disadvantage Precharge command that requires that command address busses available appropriate time issue command. advantage Precharge command that used truncate bursts.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Terminating Read Burst: Latencies (Burst Length
Latency
Command Address
Read
BAa,
CL=2
DOa-n
further output data after this point. tristated. Latency
Command Address
Read
BAa,
CL=2.5
DOa-n
further output data after this point. tristated.
data from bank column Cases shown bursts terminated after data elements. subsequent elements data appear programmed order following a-n. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Read Write: Latencies (Burst Length
Latency
Command Address
Read
BAa,
Write
BAa,
CL=2
DOa-n
tDQSS (min)
Latency
Command Address
Read
BAa,
Write
BAa,
CL=2.5
DOa-n
tDQSS (min)
Dla-b
data from bank column data bank column subsequent elements data appear programmed order following a-n. Data elements applied following programmed order, according burst length. Shown with nominal tAC, tDQSCK, tDQSQ.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Read Precharge: Latencies (Burst Length
Latency
Command
Read
Address
CL=2
DOa-n
Latency
Command
Read
Address
CL=2.5
DOa-n
data from bank column Cases shown either uninterrupted bursts interrupted bursts subsequent elements data appear programmed order following a-n. Shown with nominal tDQSCK, tDQSQ
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Writes Write bursts initiated with Write command, shown Write Command page starting column bank addresses provided with Write command, Auto Precharge either enabled disabled that access. Auto Precharge enabled, being accessed precharged completion burst. generic Write commands used following illustrations, Auto Precharge disabled. During Write bursts, first valid data-in element registered first rising edge following write command, subsequent data elements registered successive edges DQS. state between Write command first rising edge known write preamble; state following last data-in element known write postamble. time between Write command first corresponding rising edge DQSS) specified with relatively wide range (from 125% clock cycle), most Write diagrams that follow drawn extreme cases (i.e. tDQSS(min) tDQSS(max)). Write Burst (Burst Length page shows extremes tDQSS burst four. Upon completion burst, assuming other commands have been initiated, enters High-Z additional input data ignored. Data Write burst concatenated with truncated with subsequent Write command. either case, continuous flow input data maintained. Write command issued positive edge clock following previous Write command. first data element from burst applied after either last element completed burst last desired data element longer burst which being truncated. Write command should issued cycles after first Write command, where equals number desired data element pairs (pairs required prefetch architecture). Write Write (Burst Length page shows concatenated bursts example non-consecutive Writes shown Write Write: DQSS, Non-Consecutive (Burst Length page Full-speed random write accesses within page pages performed shown Random Write Cycles (Burst Length page Data Write burst followed subsequent Read command. follow Write without truncating write burst, tWTR (Write Read) should shown Write Read: NonInterrupting (CAS Latency Burst Length page Data Write burst truncated subsequent Read command, shown figures Write Read: Interrupting (CAS Latency Burst Length page Write Read: Nominal DQSS, Interrupting (CAS Latency Burst Length page Note that only data-in pairs that registered prior period written internal array, subsequent data-in must masked with shown diagrams noted previously. Data Write burst followed subsequent Precharge command. follow Write without truncating write burst, should shown Write Precharge: Non-Interrupting (Burst Length page Data Write burst truncated subsequent Precharge command, shown figures Write Precharge: Interrupting (Burst Length page Write Precharge: Nominal DQSS Write), Interrupting (Burst Length page Note that only data-in pairs that registered prior period written internal array, subsequent data should masked with Following Precharge command, subsequent command same bank cannot issued until met. case Write burst being executed completion, Precharge command issued optimum time described above) provides same operation that would result from same burst with Auto Precharge. disadvantage Precharge command that requires that command address busses available appropriate time issue command. advantage Precharge command that used truncate bursts.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Command
A0-A9, A0-A9 x16: A0-A8 BA0, column address bank address enable Auto Precharge disable Auto Precharge Don't Care HIGH
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Burst (Burst Length
Maximum DQSS
Command Address
Write
tDQSS (max)
Dla-b
Minimum DQSS
Command Address
Write
tDQSS (min)
Dla-b
data bank column subsequent elements data applied programmed order following a-b. non-interrupted burst shown. with Write command (Auto Precharge disabled).
Don't Care
2002-05-06
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Write (Burst Length
Maximum DQSS
Command Address
Write Write
BAa,
BAa,
tDQSS (max)
Minimum DQSS
Command Address
Write
Write
tDQSS (min)
data bank column etc. subsequent elements data applied programmed order following a-b. subsequent elements data applied programmed order following a-n. non-interrupted burst shown. Each Write command bank.
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Write: DQSS, Non-Consecutive (Burst Length
Command Address
Write
Write
BAa,
BAa,
tDQSS (max)
a-b, etc. data bank column etc. subsequent elements data applied programmed order following a-b. subsequent elements data applied programmed order following a-n. non-interrupted burst shown. Each Write command bank.
Don't Care
2002-05-06
Page
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Random Write Cycles (Burst Length
Maximum DQSS
Command Address
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
tDQSS (max)
a-b' a-x' a-n' a-a'
Minimum DQSS
Command Address
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
Write
BAa,
tDQSS (min)
a-b' a-x' a-n' a-a'
a-b, etc. data bank column etc. etc. even complement etc. (i.e., column address inverted). Each Write command bank.
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Read: Non-Interrupting (CAS Latency Burst Length
Maximum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (max)
Minimum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (min)
data bank column subsequent elements data applied programmed order following a-b. non-interrupted burst shown. tWTR referenced from first positive edge after last data pair. with Write command (Auto Precharge disabled). Read Write commands bank.
Don't Care
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Read: Interrupting (CAS Latency Burst Length
Maximum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (max)
DIa-
Minimum DQSS
Command
Write Read
tWTR Address
BAa, BAa,
tDQSS (min)
data bank column interrupted burst shown, data elements written. subsequent elements data applied programmed order following a-b. tWTR referenced from first positive edge after last data pair. Read command masks last data elements burst. with Write command (Auto Precharge disabled). Read Write commands necessarily same bank. These bits incorrectly written into memory array low.
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Read: Minimum DQSS, Number Data Write), Interrupting (CAS Latency Burst Length
Command
Write
Read
tWTR Address
BAa, BAa,
tDQSS (min)
data bank column interrupted burst shown, data elements written. subsequent elements data applied programmed order following a-b. tWTR referenced from first positive edge after last desired data pair (not last desired data element) Read command masks last data elements burst. with Write command (Auto Precharge disabled). Read Write commands necessarily same bank. This correctly written into memory array low. Don't Care These bits incorrectly written into memory array low.
2002-05-06
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Read: Nominal DQSS, Interrupting (CAS Latency Burst Length
Command
Write
Read
tWTR Address
BAa, BAa,
tDQSS (nom)
data bank column interrupted burst shown, data elements written. subsequent elements data applied programmed order following a-b. tWTR referenced from first positive edge after last desired data pair. Read command masks last data elements burst. with Write command (Auto Precharge disabled). Read Write commands necessarily same bank. These bits incorrectly written into memory array low.
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Precharge: Non-Interrupting (Burst Length
Maximum DQSS
Command
Write
Address
all)
tDQSS (max)
Minimum DQSS
Command
Write
Address
all)
tDQSS (min)
data bank column subsequent elements data applied programmed order following a-b. non-interrupted burst shown. referenced from first positive edge after last data pair. with Write command (Auto Precharge disabled).
Don't Care
2002-05-06
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Precharge: Interrupting (Burst Length
Maximum DQSS
Command
Write
Address
all)
tDQSS (max)
Minimum DQSS
Command
Write
Address
all)
tDQSS (min)
data bank column interrupted burst shown, data elements written. subsequent element data applied programmed order following a-b. referenced from first positive edge after last desired data pair. Precharge command masks last data elements burst, burst length with Write command (Auto Precharge disabled). don't care programmed burst length programmed burst length becomes don't care this point. These bits incorrectly written into memory array low.
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Precharge: Minimum DQSS, Number Data Write), Interrupting (Burst Length
Command
Write
Address
all)
tDQSS (min)
data bank column interrupted burst shown, data element written. referenced from first positive edge after last desired data pair. Precharge command masks last data elements burst. with Write command (Auto Precharge disabled). don't care programmed burst length programmed burst length becomes don't care this point. This correctly written into memory array low. These bits incorrectly written into memory array low.
Don't Care
2002-05-06
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Write Precharge: Nominal DQSS Write), Interrupting (Burst Length
Command
Write
Address
all)
tDQSS (nom)
Data bank column interrupted burst shown, data elements written. subsequent element data applied programmed order following a-b. referenced from first positive edge after last desired data pair. Precharge command masks last data elements burst. with Write command (Auto Precharge disabled). don't care programmed burst length programmed burst length becomes don't care this point. These bits incorrectly written into memory array low.
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Precharge Command
A0-A9, Banks BA0, Bank bank address Low, otherwise Don't Care). Don't Care HIGH
Precharge Precharge command used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after Precharge command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. When banks precharged, inputs BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior Read Write commands being issued that bank.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Power-Down Power-down entered when registered accesses progress). power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE. still running Power Down mode, maximum power savings, user option disabling prior entering Powerdown. that case, must enabled after exiting power-down, clock cycles must occur before Read command issued. power-down mode, stable clock signal must maintained inputs SDRAM, other input signals "Don't Care". However, powerdown duration limited refresh requirements device, most applications, self refresh mode preferred over DLL-disabled power-down mode. power-down state synchronously exited when registered HIGH (along with Deselect command). valid, executable command applied clock cycle later.
Power Down
Command
VALID column access progress
Exit power down mode
VALID
Enter Power Down mode (Burst Read Write operation must progress)
Don't Care
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Truth Table Clock Enable (CKE)
CKEn logic state clock edge state previous clock edge. Current state state SDRAM immediately prior clock edge COMMAND command registered clock edge ACTION result COMMAND states sequences shown illegal reserved.
Current State Previous Cycle CKEn Current Cycle Command Action Notes
Self Refresh Self Refresh Power Down Power Down Banks Idle Banks Idle Bank(s) Active
Deselect Deselect Deselect AUTO REFRESH Deselect "Truth Table Current State Bank Command Bank (Same Bank)" page
Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Precharge Power-Down Entry Self Refresh Entry Active Power-Down Entry
Deselect commands should issued clock edges occurring during Self Refresh Exit (tXSNR) period. minimum clock cycles needed before applying read command allow lock input clock.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Truth Table Current State Bank Command Bank (Same Bank)
Current State Idle Active Read (Auto Precharge Disabled) Command Deselect Operation Active AUTO REFRESH MODE REGISTER Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Select column start Read burst Select column start Write burst Deactivate bank(s) Select column start Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column start Read burst Select column start Write burst Truncate Write burst, start Precharge Action NOP. Continue previous operation NOP. Continue previous operation Select activate Notes 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6, 1-6,
Write (Auto Precharge Disabled)
This table applies when HIGH HIGH (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table bank-specific, except where noted, i.e., current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. following states must interrupted command issued same bank. Precharging:Starts with registration Precharge command ends when met. Once met, bank idle state. Activating:Starts with registration Active command ends when tRCD met. Once tRCD met, bank "row active" state. Read w/Auto Precharge Enabled: Starts with registration Read command with Auto Precharge enabled ends when been met. Once met, bank idle state. Write w/Auto Precharge Enabled: Starts with registration Write command with Auto Precharge enabled ends when been met. Once met, bank idle state. Deselect commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state according Truth Table following states must interrupted executable command; Deselect commands must applied each positive clock edge during these states. Refreshing: Starts with registration Auto Refresh command ends when tRFC met. Once tRFC met, SDRAM "all banks idle" state. Accessing Mode Register: Starts with registration Mode Register command ends when tMRD been met. Once tMRD met, SDRAM "all banks idle" state. Precharging All: Starts with registration Precharge command ends when met. Once met, banks idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; all/any banks precharged, all/any must valid state precharging. bank-specific; BURST TERMINATE affects most recent Read burst, regardless bank. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. 2002-05-06
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Truth Table Current State Bank Command Bank (Different bank)
Current State Idle Activating, Active, Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) Command Deselect Operation Command Otherwise Allowed Bank Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select column start Write burst Select activate Select column start Read burst Select activate Select column start Read burst Select column start Write burst Action NOP/continue previous operation NOP/continue previous operation Notes 1-7,10 1-7,9,10 1-7,10 1-7,10
This table applies when HIGH HIGH (see Truth Table Clock Enable (CKE) after tXSNR tXSRD been previous state self refresh). This table describes alternate bank operation, except where noted, i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: Read burst been initiated, with Auto Precharge disabled, terminated been terminated. Write: Write burst been initiated, with Auto Precharge disabled, terminated been terminated. Read with Auto Precharge Enabled: note Write with Auto Precharge Enabled: note AUTO REFRESH Mode Register commands only issued when banks idle. BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. Reads Writes listed Command/Action column include Reads Writes with Auto Precharge enabled Reads Writes with Auto Precharge disabled. Requires appropriate masking. Write command applied after completion data output. Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When read with auto precharge write with auto precharge enabled command follow other banks long that command does interrupt read write data transfer other limitations apply (e.g. contention between READ data WRITE data must avoided). mimimum delay from read write command with auto precharge enable, command different banks summarized table
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Truth Table Concurrent Auto Precharge
From Command
Command (different bank) Read Read w/AP
Minimum Delay with Concurrent Auto Precharge Support (BL/2) tWTR BL/2 BL/2 (rounded up)+ BL/2
Units
WRITE w/AP
Write Write w/AP Precharge Activate Read Read w/AP
Read w/AP
Write Write w/AP Precharge Activate
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Simplified State Diagram
Power Applied Power
Precharge PREALL
Self Refresh REFS REFSX
EMRS
Idle
REFA
Auto Refresh
CKEL CKEH
Active Power Down CKEH CKEL
Precharge Power Down
Write Write Write
Active
Burst Stop Read
Read Read Read
Write Read Write
Read
Read
Precharge PREALL Automatic Sequence Command Sequence
PREALL Precharge Banks Mode Register EMRS Extended Mode Register REFS Enter Self Refresh REFSX Exit Self Refresh REFA Auto Refresh
CKEL Enter Power Down CKEH Exit Power Down Active Write Write with Autoprecharge Read Read with Autoprecharge Precharge
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Operating Conditions Absolute Maximum Ratings
Symbol VOUT VDDQ TSTG IOUT Parameter Voltage pins relative Voltage Inputs relative Voltage supply relative Voltage supply relative Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating Units
-0.5 VDDQ+ -0.5 +3.6 -0.5 +3.6 -0.5 +3.6
+150
Note: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Input Output Capacitances
Parameter Input Capacitance: Delta Input Capacitance: Input Capacitance: other input-only pins Delta Input Capacitance: other input-only pins Input/Output Capacitance: DQS, Delta Input/Output Capacitance DQS, Symbol CdI1 CdI2 CdIO Min. Max. 0.25 Units Notes
These values guaranteed design tested sample base only. VDDQ 2.5V 0.2V, 100MHz, 25°C, VOUT (DC) VDDQ/2, VOUT (Peak Peak) 0.2V. Unused pins tied groundVOUT (Peak Peak) 0.2V. inputs grouped with pins reflecting fact that they matched loading facilitate trace matching board level.
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
(0°C 70°C; VDDQ 2.5V 0.2V, 2.5V 0.2V)
Symbol VSS, VSSQ VIH(DC) VIL(DC) VIN(DC) VID(DC) VIRatio Supply Voltage Supply Voltage Supply Voltage Supply Voltage Reference Voltage Termination Voltage (System) Input High (Logic1) Voltage Input (Logic0) Voltage Input Voltage Level, Inputs Input Differential Voltage, Inputs VI-Matching Pullup Current Pulldown Current Input Leakage Current input (All other pins under test Output Leakage Current (DQs disabled; Vout VDDQ Output High Current, Normal Strength Driver (VOUT Parameter 0.49 VDDQ VREF 0.04 VREF 0.15 0.51 VDDQ VREF 0.04 VDDQ VREF 0.15 VDDQ VDDQ Units Notes
Electrical Operating Conditions
0.36 0.71
1.95
15.2
15.2
Output Current, Normal Strength Driver (VOUT 0.35
Inputs recognized valid until VREF stabilizes. VREF expected equal VDDQ transmitting device, track variations level same. Peak-to-peak noise VREF exceed value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level ration pullup current pulldown current specified same temperature voltage, over entire temperature voltage range, device drain source voltage from 0.25 1.0V. given output, represents maximum difference between pullup pulldown drivers process variation.
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Normal Mode Pulldown Pullup Characteristics
nominal pulldown curve SDRAM devices expected, guaranteed, within inner bounding lines curve. full variation driver pulldown current from minimum maximum process, temperature, voltage within outer bounding lines curve.
Normal Mode Pulldown Characteristics
1OUT (mA) VOUT nominal pullup curve SDRAM devices expected, guaranteed, within inner bounding lines curve. full variation driver pullup current from minimum maximum process, temperature, voltage within outer bounding lines curve. Nominal Minimum Maximum
Nominal High
Normal Mode Pullup Characteristics
1OUT (mA) -100 -120 -140 -160 Maximum VOUT Nominal High Nominal Minimum
full variation ratio maximum minimum pullup pulldown current does exceed 1.7, device drain source voltages from 1.0. full variation ratio nominal pullup pulldown current should unity 10%, device drain source voltages from 1.0V.
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Normal Mode Pulldown Pullup Currents
Pulldown Current (mA) Voltage Nominal 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.9 63.3 63.8 64.1 64.6 64.8 65.0 Nominal High 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Nominal Pullup Current (mA) Nominal High
-6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5
-52.7 -52.8
-7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5
-155.3 -160.1
-4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0
-41.1 -41.2
-10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6
-192.9 -198.2
Evaluation Conditions Driver Characteristics
Nominal Operating Temperature Process Corner 2.5V typical Minimum 2.3V slow-slow Maximum 2.7V fast-fast
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Weak
Mode Pulldown Pullup Characteristics
Weak Strength Pulldown Characteristics
Maximum
Typical high Iout [mA]
Typical
Minimum
Vout
weak pulldown curve SDRAM devices expected, guaranteed, within inner bounding lines curve weak pullup curve SDRAM devices expected, guaranteed, within inner bounding lines curve. full variation driver pullup current from minimum maximum process, temperature, voltage within outer bounding lines curve.
Weak Strength Pullup Characteristics
-10,0 -20,0 -30,0
Minimum
Iout
Typical
-40,0 -50,0 -60,0 -70,0 -80,0
Typical high
Maximum
Vout
full variation ratio maximum minimum pullup pulldown current does exceed 1.7, device drain source voltages from 1.0. full variation ratio nominal pullup pulldown current should unity 10%, device drain source voltages from 1.0V.
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2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Weak Strength Driver Pulldown Pullup Currents
Pulldown Current (mA) Voltage Nominal Nominal High Nominal Pullup Current (mA) Nominal High
10.3 13.6 16.9 19.6 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8
11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6
10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6
14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7
-3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9
-4.3 -8.2 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8
-2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3
-5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Specification Conditions
VDDQ 2.5V 0.2V; 2.5V 0.2V)
Symbol Parameter/Condition
DDR200 typ.
Symbol
Parameter/Condition
Notes DDR333 DDR200 DDR266 Unit Notes DDR266A DDR333 typical typical typical Unit
Operating Current: bank; active precharge; MIN; MIN; IDD0 inputs bank; active precharge; MIN; Operating Current: changing once clock cycle; address control inputs IDD0 changing changing once clock cycle; address MIN; inputs once every clock cycles
max.
typ.
max.
typ.
max.
control inputs changing once every clock cycles
IDD1
Operating Current: bank; read precharge; Burst Operating Current: bank; activeactive/read/precharge; Burst Refer Refer following page detailed test conditions. previous page detailed test conditions.
IDD2P Precharge Power-Down Standby Current: banks idle; power-down mode; mode; MAX; IDD2P MAX;
Precharge Floating Standby Current: banks idle; IDD2F Floating Standby Current: MIN,control inputs changing MIN; Precharge MIN; ,address other banks idle; ,address other changing once IDD2F once clock cycle, Vcontrol inputsDQS clock cycle,
Precharge Power-Down Standby Current: banks idle; power-down
Standby Current: MIN, banks Precharge QuietVIL MAX; VREF idle; IDD2Q MIN; ,address other control inputs stable Active Power-Down Standby Current: bank active; power-down IDD3P MAX; VREF mode; MAX; MIN;V VREF
Active Standby Current: bank active; active precharge;CS
IDD2Q
VREF andStandby Current: Precharge Quiet MIN, banks idle;
MIN; ,address other control inputs stable
tbd.
tbd.
tbd.
IDD3P
Active Power-Down Standby Current: bank active; power-down mode; MIN; tRAS MAX; MIN; MAX; =changing twice VREF control inputs changing DD3N inputs MIN;VIN clock cycle; address
1235
3812
once clock cycle
Operating Current: bank active; active reads; continuous burst; Active Standby Current: bankactive; Burst precharge;CS MIN; MIN; tRAS MAX; changing clock cycle; IDD3N VIHaddress control inputs MIN; onceDM, inputs changing twice IDD4R outputs changing twice clock cycle; DDR200, clock cycle; address control inputs changing once clock cycle
2590 11045
DDR266A, CL=3 DDR333; MIN; IOUT
Operating Current: bank active; Burst reads; continuous burst; address address control inputs changing once clock cycle; IDD4W control inputs changing once clock cycle; data outputs changing every inputs changing twice clock cycle; DDR200, DDR266A, IDD4R clock edge; DDR200, DDR266A, CL=3 DDR333; MIN; IOUT CL=3 DDR333;
Operating Current: bank active; Burst writes; continuous burst;
IDD5
IDD4W
Auto-Refresh Current: tRFC MIN, distributed refresh
Operating Current: bank active; Burst writes; continuous burst; address standard version control inputs changing once clock cycle; data outputs changing every Self-Refresh Current: 0.2V; external IDD6 clock edge; DDR200, DDR266A, CL=3 DDR333; (standard products) clock
tbd.
power version
tbd.
tbd.
tbd.
tbd.
tbd.
IDD5 Auto-Refresh Current: tRFC MIN, distributed refresh
IDD7
IDD6 Self-Refresh Current: 0.2V; external clock
Operating Current: four bank; four bank interleaving with BL=4; Refer previous page detailed test conditions. standard version
power version specifications tested after device properly initialized measured DDR200, DDR266 DDR333 Operating Current: four bank; four bank interleaving with BL=4; IDD7 Input slew rate 1V/ns. Refer following page detailed test conditions. Enables on-chip refresh address counters
specifications tested after device= 2.5V 25oC, test condition maximum values: test limit 2.7V Test condition typical values properly initialized measured DDR200, DDR266 DDR333 10oC Input slew rate 1V/ns. Enables on-chip refresh address counters Test condition typical values 2.5V 25°C, test condition maximum values: test limit 2.7V 10°C
Page
2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Current Measurement Conditions IDD1 Operating current bank operation
Only bank accessed with tRC(min) Burst Mode, Address Control inputs edge changing once clock cycle. lout Timing patterns DDR200 (100Mhz, CL=2) CL=2, BL=4, tRCD tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst DDR266A (133Mhz, CL=2) CL=2, BL=4, tRCD tCK, tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst DDR333 (166Mhz, CL=2.5) CL=2.5, BL=4, tRCD tCK, tCK, tRAS Setup: Read repeat same timing with random address changing data changing every burst 3.Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 Operating current: Four bank operation
Four banks being interleaved with tRC(min) Burst Mode, Address Control inputs edge changing. lout Timing patterns DDR200 (100Mhz, CL=2) CL=2, BL=4, tRRD tCK, tRCD= tCK, Read with autoprecharge Setup: Read repeat same timing with random address changing data changing every burst DDR266A (133Mhz, CL=2) CL=2, BL=4, tRRD tCK, tRCD Setup: Read repeat same timing with random address changing data changing every burst DDR333 (166Mhz, CL=2.5) CL=2.5, BL=4, tRRD tCK, tRCD Setup: Read repeat same timing with random address changing data changing every burst 3.Legend A=Activate, R=Read, W=Write, P=Precharge, N=NOP
2002-05-06
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HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Characteristics
(Notes apply following Tables; Electrical Characteristics Operating Conditions, Operating Conditions, Specifications Conditions, Electrical Characteristics Timing.) voltages referenced VSS. Tests timing, IDD, electrical, characteristics, conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. figure below represents timing reference load used defining relevant timing parameters part. intended either precise representation typical system environment depiction actual load presented production tester. System designers will IBIS other simulation tools correlate timing reference load system environment. Manufacturers will correlate their production test conditions (generally coaxial transmission line terminated tester electronics). timing tests swing 1.5V test environment, input timing still referenced crossing point CK), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e. receiver effectively switches result signal crossing input level, remains that state long signal does ring back above (below) input (HIGH) level) System Characteristics like Setup Holdtime Derating Slew Rate, Delta Rise/Fall Derating,DDR SDRAM Slew Rate Standards, Overshoot Undershoot specification Clamp characteristics latest JEDEC specification components
Output Load Circuit Diagram Timing Reference Load
Output (VOUT) Timing Reference Point
30pF
Operating Conditions
VDDQ 2.5V 0.2V; 2.5V 0.2V)
Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Parameter/Condition Input High (Logic Voltage, DQS, Signals Input (Logic Voltage, DQS, Signals Input Differential Voltage, Inputs Input Closing Point Voltage, Inputs 0.31 VREF 0.31 Unit Notes
0.5*VDDQ 0.5*V
Input slew rate 1V/ns. Inputs recognized valid until VREF stabilizes. magnitude difference between input level input level value expected equal 0.5*VDDQ transmitting device must track variations level same. 2002-05-06
Page
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Electrical Characteristics Timing Absolute Specifications
VDDQ 2.5V 0.2V; 2.5V 0.2V, Characteristics) (Part
DDR200 output access time from CK/CK DDR266A DDR333
Symbol
Parameter
Unit
Notes
0.45 0.45
0.55 0.55
0.75 0.75
0.45 0.45
0.75 0.75
0.55 0.55
0.45 0.45
0.55 0.55
1-4,10 1-4,10 1-4, 1-4, 1-4, 1-4,
tDQSCK output access time from CK/CK tIPW tDIPW tDQSS tDQSQ tQHS input hold time input setup time Control Addr. input pulse width (each input) input pulse width (each input) Data-out high-impedence time from CK/CK Data-out low-impedence time from CK/CK Write command latching transition DQS-DQ skew (DQS associated signals) Data hold skew factor output hold time from Clock cycle time high-level width low-level width Clock Half Period
(tCL
(tCL 1.75
(tCL, 0.45 0.45 1.75
0.75
1.25
0.75 0.75
0.75
0.75 0.75
1.25
0.75
1.25
tHP-tQHS 0.35 0.40 0.25 0.60 tHP-tQHS 0.35 0.40 0.25 0.60 120,000 0.40
0.75 tHP-tQHS 0.35 0.60 0.40 0.25 0.75 0.75 0.60 120,000 0.40
0.45
0.55
tDQSL,H input (high) pulse width (write cycle) tDSS tDSH tMRD falling edge setup time (write cycle) falling edge hold time from (write cycle) Mode register command cycle time
0.60 0.60 70,000
tWPRES Write preamble setup time tWPST tWPRE Write postamble Write preamble Address control input setup time Address control input hold time Read preamble Read postamble Active Precharge command Active Active/Auto-refresh command period fast slew rate slow slew rate fast slew rate slow slew rate
0.40
2-4, 10,11
tRPRE tRPST tRAS
2002-05-06
Page
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Electrical Characteristics Timing Absolute Specifications
VDDQ 2.5V 0.2V; 2.5V 0.2V, Characteristics) (Part
DDR200 tRFC tRCD tRAP tRRD tDAL tWTR tXSNR tXSRD tREFI Auto-refresh Active/Auto-refresh command period Active Read Write delay Precharge command period Active Autoprecharge delay Active bank Active bank command Write recovery time Auto precharge write recovery precharge time Internal write read command delay Exit self-refresh non-read command Exit self-refresh read command Average Periodic Refresh Interval (4096 refresh commands 64ms refresh period) 15.6 DDR266A (twr/tck) (trp/tck) 15.6 15.6 DDR333 1-4,9 1-4,
Symbol
Parameter
Unit
Notes
Input slew rate 1V/ns DDR266 DDR333 1V/ns DDR200. CK/CK input reference level (for timing reference CK/CK) point which cross: input reference level signals other than CK/CK, VREF. CK/CK slew rate V/ns Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (Note VTT. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device operates with greater value this parameter, system performance (bus turnaround) degrades accordingly. specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from Hi-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum eight Autorefresh commands posted given SDRAM device. each terms, already integer, round next highest integer. equal actual system clock cycle time. These parameters guarantee device timing, they necessarily tested each device Fast slew rate V/ns slow slew rate V/ns 1V/ns command/address slew rate >1.0 V/ns, measured between VOH(ac) VOL(ac)
Page
2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Electrical Characteristics Timing DDR266 Applicable Specifications Expressed Clock Cycles VDDQ 2.5V 0.2V; 2.5V 0.2V,
Characteristics)
DD266A CL=2 Symbol tMRD tWPRE tRAS tRFC tRCD tRRD tDAL tWTR tXSNR tXSRD Parameter Mode register command cycle time Write preamble Active Precharge command Active Active/Auto-refresh command period Auto-refresh Active/Auto-refresh command period Active Read Write delay Precharge command period Active bank Active bank command Write recovery time Auto precharge write recovery precharge time Internal write read command delay Exit self-refresh non-read command Exit self-refresh read command 0.25 16000 Units Notes
Input slew rate 1V/ns CK/CK input reference level (for timing reference CK/CK) point which cross: input reference level signals other than CK/CK, VREF. Inputs recognized valid until VREF stabilizes. Output timing reference level, measured timing reference point indicated Characteristics (Note VTT. transitions occur same access time windows valid data transitions. These parameters referred specific voltage level, specify when device longer driving (HZ), begins driving (LZ).
2002-05-06
Page
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Timing Diagrams Data Input (Write)
(Timing Burst Length
tDQSL tDQSH
Data column subsequent elements data applied programmed order following
Don't Care
Data Output (Read)
(Timing Burst Length
tDQSQ
(Data output hold time from DQS) tDQSQ only shown once shown referenced different edges DQS, only clarify illustration. tDQSQ both apply each four relevant edges DQS. tDQSQ max. used determine worst case setup time controller data capture. used determine worst case hold time controller data capture.
Page
2002-05-06
2002-05-06
applied directly device, however tVTD must greater than equal zero avoid device latchup. required before command applied cycles required before Read command applied. Autorefresh commands moved follow first MRS, precede second Precharge command.
tVTD
VDDQ
(System*)
VREF
cycles CK**
tMRD tMRD tRFC tRFC tMRD
200µs
Initialize Mode Register Sets
EMRS
LVCMOS LEVEL
Command
CODE CODE CODE CODE CODE CODE
A0-A9,
BANKS
BA0=H BA1=L
BANKS
BA0,
BA0=L BA1=L
BA0=L BA1=L
High-Z
High-Z
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Page
Power-up: stable
Don't Care
Extended Mode Register
Load Mode Register, Reset
Load Mode Register (with
Page
VALID VALID VALID
Enter Power Down Mode
Power Down Mode
Command
VALID*
ADDR
Exit Power Down Mode
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
column accesses allowed progress time power down entered. this command Precharge device already idle state) then power down mode shown Precharge power down. this command Active least already active), then power down mode shown Active power down.
Don't Care
2002-05-06
2002-05-06
tRFC tRFC
Auto Refresh Mode
VALID VALID
Command
A0-A8
A11,A11
BANKS
BANK
BANK(S)
BA0,
Precharge; Active; address; Bank address; Autorefresh. commands shown ease illustration; other valid commands possible these times. signals don't care/high-Z operations shown.
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Page
Don't Care
Page
Clock must stable before exiting Self Refresh Mode
tRP*
Self Refresh Mode
cycles
tXSRD, tXSRN VALID
Command
VALID
ADDR
Enter Self Refresh Mode
Exit Self Refresh Mode
Device must banks idle state before entering Self Refresh Mode. tXSNR required before non-read command applied, tXSRD (200 cycles CK). required before Read command applied.
Don't Care
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
2002-05-06
2002-05-06
VALID Read VALID VALID
Command
A0-A9, A11,
BANKS
BANK
BA0,
(min) tRPRE
Read without Auto Precharge (Burst Length
(min) tRPST tDQSCK (min) (min)
Case AC/tDQSCK
CL=2
(max) tRPRE
(max) (max) (max) tRPST tDQSCK (max)
Case tAC/tDQSCK
data from column
subsequent elements data provided programmed order following
Don't Care
Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address.
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Page
commands shown ease illustration; other commands valid these times.
Page
VALID VALID VALID
Command
Read
A0-A9, A11,
BA0,
Read with Auto Precharge (Burst Length
(min) tRPRE
(min) (min) tRPST tDQSCK (min) (min)
Case tAC/tDQSCK
CL=2
(max) tRPRE
(max) (max) (max) tRPST tDQSCK (max)
Case tAC/tDQSCK
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
data from column subsequent elements data provided programmed order following enable Auto Precharge. active; address. commands shown ease illustration; other commands valid these times.
Don't Care
2002-05-06
VALID BANKS BANK Read
2002-05-06
Command
A0-A9, A11,
Bank Read Access (Burst Length
BA0,
(min) tRPRE
tRCD tRAS (min) (min) (min) tRPST tDQSCK (min)
Case AC/tDQSCK
CL=2
(max) tRPRE
(max) (max) (max) tDQSCK tRPST (max)
Case tAC/tDQSCK
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
data from column subsequent elements data provided programmed order following disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address. commands shown ease illustration; other commands valid these times.
Page
Don't Care
Page
VALID Write
Command
A0-A9,
BANKS
BANK
tWPRE tWPRES tDQSH tDQSS tWPST tDQSL tDSH
Write without Auto Precharge (Burst Length
BA0,
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
tDQSS min. Data column subsequent elements data applied programmed order following DIn. Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address. commands shown ease illustration; other valid commands possible these times.
Don't Care
2002-05-06
2002-05-06
tDAL VALID VALID VALID Write
Command
A0-A9, A11,
Write with Auto Precharge (Burst Length
BA0,
tDSH tDQSH tDQSL tWPST
tWPRES tDQSS
tWPRE
tDQSS min.
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Page
Data column subsequent elements data applied programmed order following DIn. Enable Auto Precharge. Active; address; Bank address. commands shown ease illustration; other valid commands possible these times.
Don't Care
Page
VALID tRAS Write
Command
Bank Write Access (Burst Length
A0-A9,
BANKS BANK
tRCD tWPRES tDQSH tDQSS tDQSL tWPST tDSH
BA0,
tWPRE
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
tDQSS min. data column subsequent elements data applied programmed order following Disable Auto Precharge. don't care High this point. Precharge; Active; address. commands shown ease illustration; other valid commands possible these times.
Don't Care
2002-05-06
2002-05-06
VALID Write
Command
A0-A9,
Write Operation (Burst Length
BANKS
BANK
BA0,
tWPRES tDQSH tDQSS tDQSL tWPST tDSH
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
data column subsequent elements data applied programmed order following (the second element masked). Disable Auto Precharge. Don't care High this point. Precharge; Active; address; Bank address. commands shown ease illustration; other valid commands possible these times. tDQSS min.
Page
Don't Care
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Package Dimensions
Plastic Package, P-TSOPII-66 (400mil; lead) Thin Small Outline Package
0,05
1,20
0,25 Basic
ting
±0,1
Page
2002-05-06
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
TABLE CONTENT
Features Description Configuration Input/Output Functional Description Block Diagram (32Mb Block Diagram (16Mb Block Diagram (8Mb Functional Description Initialization Register Definition Mode Register Operation Burst Definition Required Latencies Extended Mode Register Extended Mode Register Definition Commands Delesect, Operation Mode Register Active Read Write Precharge Auto Precharge Burst Terminate Auto Refresh Self Refresh Truth Table Commands Truth Table Operation Operations Activating Specific Specific Bank tRCD tRRD Definition Read Command Read Burst Consecutive Read Bursts Non-Consecutive Read Bursts Random Read Accesses Terminating Read Burst Read Write Read Precharge Write Command Write Burst (Burst Length Write Write (Burst Length Write Write Random Write Cycles
2002-05-06
Write Read Write Read Interrupting Write Read: Minimum DQSS Write Read: Nominal DQSS Write Precharge Non-Interrupting Write Precharge Interrupting Write Precharge Minimum DQSS Write Precharge: Nominal DQSS Precharge Power-Down Truth Table Clock Enable (CKE) Truth Table Current State, SameBank Truth Table Current State,Different Bank Truth Table Concurrent Auto Precharge Simplified State Diagram Operating Conditions Absolute Maximum Ratings Input Output Capacitances Electrical Operating Conditions Normal Mode Pulldown Characteristics Normal ModePullup Characteristics Normal ModePulldown Pullup Currents Weak Mode Pulldown Characteristics Weak ModePullup Characteristics Weak ModePulldown Pullup Currents Specifications Conditions Characteristics Output Load Circuit Diagram Operating Conditions Electrical Characteristics Timing Timing Diagrams Data Input (Write) Data Output (Read) Initialize Mode Register Sets Power Down Mode Auto Refresh Mode Self Refresh Mode Read without Auto Precharge Read with Auto Precharge Bank Read Access Write without Auto Precharge. Write with Auto Precharge Bank Write Access Write Operation Package Dimensions Table Content Security Information
Page
HYB25D128400/800/160AT(L) 128-Mbit Double Data Rate SDRAM
Attention please
patents other rights third parties concerned, liability only assumed components, applications, processes circuits implemented within components assemblies. This information describes type components shall considered assured characteristics. Terms delivery rights change design reserved. questions technology, delivery prices please contact INFINEON Technologies Offices Munich INFINEON Technologies Sales Offices Representatives worldwide. technical requirements components contain dangerous substances. information types question please contact your nearest INFINEON Technologies office representative.
Packing Please recycling operators known you. help touch with your nearest sales office. agreement will take packing material back, sorted. must bear costs transport. packing material that returned unsorted which obliged accept, shall have invoice costs incurred. Components used life-support devices systems must expressly authorized such purpose! Critical components1 INFINEON Technologies, only used lifesupport devices systems2 with express written approval INFINEON Technologies. critical component component used life-support device system whose failure reasonably expected cause failure that lifesupport device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain human life. they fail, reasonable assume that health user endangered.
2002-05-06
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