4-Bit Microcontroller with Driver SH6610D-based single-chip 4-bit
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SH69P54
4-Bit Microcontroller with Driver
SH6610D-based single-chip 4-bit microcontroller OTPROM: 4096 bits RAM: 384X4bits System register: 48X4 bits Data RAM: 336X4 bits Operation voltage: fOSC=400KHz 4MHz, VDD=2.4V 6.0V fOSC=4MHz 8MHz, VDD=4.5V 6.0V CMOS bi-directional pins(PORT switch segment) Built pull-up pull-low resistor 8-Level subroutine nesting (include interrupts) 8-bit auto re-load timer/counter Warm-up timer power-on reset Powerful interrupt sources: External rising/falling interrupt Internal interrupt (Timer0) Internal interrupt (Base Timer) Port's rising/falling edge interrupt: PORTBC 8-bit Base timer driver: 8X30 (1/8 duty bias (1/6 duty bias), 5X33 (1/5duty bias) 4X34 dots (1/4 duty bias) used scan output shared matrix Built-in dual tone with noise generator Built-in watch timer level (OTP option) High level: 4.0V level: 2.5V Clock sources OSC: (OTP option select crystal type) Crystal oscillator: 32.768K oscillator: 262K OSCX: (system register selected ceramic type) Ceramic oscillator 400K-8MHz oscillator 2MHz-8MHz Instruction cycle time: 122.07µs 32.768 15.27µs 8.79µs 455KHz 0.5µs User program read data power operation modes: HALT STOP power consumption type
General Description
SH69P54 single chip microcontroller integrated with SRAM, OTPROM,timer,watchdog timer dual-tone PSG, driver,LED Matrix driver port.
V0.4
SH69P54
QFP64 Configuration
SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 RESET TEST OSCO OSCI OSCXO OSCXI
SH69P54
SH69P54
Configuration
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
RESET TEST OSCO OSCI OSCXO
SH69P54
OSCXI
SH69P54
Block Diagram
(4096 (384 OSCS SH6610D CORE PORTA EXTERNAL 8-BIT TIMER0 OSCI OSCO OSCXI OSCXO PA.0 (INT0 PA.1 (PSG) PA.2 (PSG) PA.3 PORTB [0:3] PORTC [0:3] PORTD [0:3] [1:30] (SEG1 shared with PORTC &PORTD) [1:8] (COM5 shared with SEG34
PORT RESET SCAN REGISTER COMMON DRIVER OPERATING VOLTAGE VOLTAGE GENERATOR DRIVER SEGMENT
SH69P54
Description
1,2,3,4 5,6,7,8 9,10,11,12 13,14,15,16 Designation PORTD3 PORTD0 PORTC3 PORTC0 PORT PORTB0 PORTA3 PORTA0 25,26,27,28 29,30,31,32 33,34, 35,36 37-58 OSCXI OSCXO OSCI OSCO TEST RESET COM1 COM4 COM5/SEG34,COM6/SEG33, COM7/SEG32,COM8/SEG31 SEG30-SEG9 Description programmable I/O, shared with Segment programmable I/O, shared with Segment programmable I/O, Vector interrupt programmable I/O, PA.1, PA.2shared with output Ground Bonding option Power supply Bonding option Oscillator input Oscillator output Oscillator input Oscillator output Test must connected GND. Reset input internal pull-up) Connected with external divided resistance Common signal output display Common/segment signal output display Segment signal output display, Shared with scan output
Total: Pads, bonding Pads. Programming Description (OTP program mode) Designation Shared RESET OSCI PORTA0 Description Programming Power supply (+5.5V) Programming high voltage Power supply (+10.5V) Ground Programming Clock input Programming Data
SH69P54
Functional Description
core contains following function blocks: Program Counter, ALU, Carry Flag, Accumulator, Table Branch Register (TBR), Data Pointer (INX, DPH, DPL), Stack. 1.1. (Program Counter) used addressing consisting 12-bits: Page Register (PC11), Ripple Carry Counter (PC10 PC0). program counter normally increases (+1) with each execution instruction except following cases: When executing jump instruction (such JMP, BA0, BC), When executing subroutine call instruction (CALL), When interrupt occurs, When chip INITIAL RESET. program counter loaded with data corresponding each instruction. unconditional jump instruction (JMP) 1-bit page register higher than Program Counter only address program ROM. 1.2. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment addition/subtraction (DAA, DAS), Logic operations (AND, EOR, ANDI, EORI, ORI) Decision (BA0, BA1, BA2, BA3, BAZ, Carry Flag (CY) holds arithmetic operation overflow. During interrupt call instruction, carry pushed into stack restored from stack RTNI. unaffected RTNW instruction. 1.3. Accumulator accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transfers between accumulator system register, RAM, data memory performed. 1.4. Stack This group registers used save contents sequentially with each subroutine call interrupt. organized bits levels. saved Eight levels maximum allowed subroutine calls interrupts. contents Stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 8-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds where then bottom stack will shifted out.
OTPROM SH69P54 address 4096 program area $000 $FFF. There area from addresses $000 through $004 that reserved special interrupts service routines such starting vector address. Address 000H 001H 002H 003H 004H Instruction Instruction Instruction Instruction Instruction Instruction Function Jump RESET service routine Jump External interrupt service routine Jump Timer0 service routine Jump Base Timer service routine Jump PORT service routine
SH69P54
Built-in SRAM contains general-purpose data memory, RAM, system registers. They accessed direct addressing instruction. following memory allocation map: $000 $01F: System register I/O; $300 $348: space $370 $37F: System register (a)The configuration system register Address Bit3 IRQX TM0.3 BTM.3 TL0.3 TH0.3 PA.3 PB.3 PC.3 PD.3 PAM2 TBR.3 INX.3 DPL.3 Bit2 IET0 IRQT0 TM0.2 BTM.2 TL0.2 TH0.2 LCDON PA.2 PB.2 PC.2 PD.2 PAM1 O/S2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 O/S1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 O/S0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 Bit1 IEBT IRQBT TM0.1 BTM.1 TL0.1 TH0.1 RLCD1 PA.1 PB.1 PC.1 PD.1 Bit0 IRQP TM0.0 BTM.0 TL0.0 TH0.0 RLCD0 PA.0 PB.0 PC.0 PD.0 Interrupt enable flags Interrupt request flags Timer0 Mode register (Prescaler) Base timer mode register Timer0 load/counter register digit Timer0 load/counter register high digit Reserverd Bit0,1: Select resistance divider Bit2: on/off PORTA PORTB PORTC PORTD Bit0,1: Bonding option Bit2,3: PA.1&PA.2 output PORT Bit0: PORTC segment Bit1: PORTD segment Bit2: segment output port Bit3: Voltage degrade Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit0:External interrupt(PA.0) rising/falling edge PULLEN PH/PL PBCFR EINFR Bit1:PBC interrupt rising/falling edge Bit2:Port pull-hi/low Bit3: Port pull-up/low enable control Bit0: Turn OSCX oscillator Bit1: clocks select OSCX/0: OSC) Bit3: OSCX type selection Bit0,1: Select DUTY(1/8,1/6,1/5 1/4) Bit2,3: frequency control Remarks $020 $16F: Data memory (336 4bits, partitioned into banks). $358 $36D: Scan output
OXON
LPS1
LPS0
DUTY0
DUTY1
SH69P54
configuration system register (continue) $370 $371 $372 $373 $374 $375 $376 $377 PA3OUT PA2OUT PA1OUT PA0OUT PB3OUT PB2OUT PB1OUT PB0OUT PC3OUT PC2OUT PC1OUT PC0OUT PD3OUT PD2OUT PD1OUT PD0OUT RDT.3 RDT.7 RDT.11 RDT.15 SEL1 C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 RDT.2 RDT.6 RDT.10 RDT.14 WDT.2 SEL0 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 RDT.1 RDT.5 RDT.9 RDT.13 WDT.1 C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN RDT.0 RDT.4 RDT.8 RDT.12 WDT.0 C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN PORTA output port 1,output;0,input PORTB output port 1,output;0,input PORTC output port 1,output;0,input PORTD output port 1,output;0,input Data table address data register Data table address data register Data table address data register Data table address data register Bit0-2: Watch timer control Bit3: Watch timer overflow flag Reserved Bit0, PSG1, PSG2 mode control Bit2, PSG1, PSG2 clock source selection channel nibble channel 1high nibble Bit3: channel octave shift control channel nibble alarm output channel nibble channel nibble channel nibble Bit3: channel octave shift control Bit0, Bit1: Channel enable Bit2, Bit3: volume control
System Register $12. (Please refer SH6610D User's manual) System Register state IRQX T0M.3 BTM.3 T0L.3 T0H.3 PA.3 PB.3 PC.3 PD.3 PAM2 IET0 IRQT0 T0M.2 BTM.2 T0L.2 T0H.2 LCDON PA.2 PB.2 PC.2 PD.2 PAM1 IEBT IRQBT T0M.1 BTM.1 T0L.1 T0H.1 RLCD1 PA.1 PB.1 PC.1 PD.1 IRQP T0M.0 BTM.0 T0L.0 T0H.0 RLCD0 PA.0 PB.0 PC.0 PD.0 Power Reset /Pin Reset Voltage Reset 0000 0000 0000 0000 xxxx xxxx -000 0000 0000 0000 0000 00xx Reset 0000 0000 uuuu uuuu xxxx xxxx -uuu 0000 0000 0000 0000 uuxx
SH69P54
System Register state (continue): $370 $371 $372 $373 $374 $375 $376 $377 TBR.3 INX.3 DPL.3 PULLEN LPS1 PA3OUT PB3OUT PC3OUT PD3OUT RDT.3 RDT.7 RDT.11 RDT.15 SEL1 C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 O/S2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2 PH/PL LPS0 PA2OUT PB2OUT PC2OUT PD2OUT RDT.2 RDT.6 RDT.10 RDT.14 WDT.2 SEL0 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 O/S1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 PBCFR DUTY1 PA1OUT PB1OUT PC1OUT PD1OUT RDT.1 RDT.5 RDT.9 RDT.13 WDT.1 C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN O/S0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0 EINFR OXON DUTY0 PA0OUT PB0OUT PC0OUT PD0OUT RDT.0 RDT.4 RDT.8 RDT.12 WDT.0 C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN Power Reset /Pin Reset Voltage Reset 0000 xxxx xxxx xxxx -xxx -xxx 0100 0-00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Reset uuuu uuuu uuuu uuuu -uuu -uuu 0uuu u-0u uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 1000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu00
Legend: unknown, unchanged, unimplemented read '0'.
SH69P54
Others initial state: Others Program Counter (PC) Accumulator (AC) Data Memory Data memory general-purpose data memory organized bits. Because static feature, retain data after enters STOP HALT mode. Oscillator circuit 5.1. Circuit Configuration SH69P54 on-chip oscillation circuits OSCX. frequency crystal (Typ. 32.768KHz) (Typ.262KHz) determined option. This designed frequency operation. OSCX also types: ceramic (Typ.455KHz) 8MHz) determined software option. designed high frequency operation. possible select high speed processing high frequency clock select power operation operation clock. start Power reset, reset power reset initialization, starts oscillation OSCX turned off. start reset initialization, starts oscillation OSCX remains original state. Immediatly after reset initialization, clock automatically selected system clock input source. After Reset $000 Undefined Undefined Undefined
Oscillator Block Diagram
OSCI OSCO Frequency Clock Oscillator System clock Source Selector OSCXI OSCXO High Frequency Clock Oscillator
Switching control System clock
Base Timer
Generator
Clock
5.2. oscillation generates basic clock pulses that provide peripherals (Timer0, LCD) with operating clock.
Crystal oscillator type
OSCI
32768Hz OSCO
CHIP
oscillator type
RBIAS OSCI
CHIP
OSCO
SH69P54
5.3. OSCX oscillation OSCX clock oscillators. software options selects ceramic CPU's subclock.
OSCX ceramic oscillator type
OSCXI
455KHz Ceramic OSCXO
CHIP
OSCX oscillator type
OSCX used, must masked ceramic resonator OSCXI must connected GND.
RBIAS OSCXI
CHIP
OSCXO
5.4. Control oscillator oscillator control register configuration shown follows: Address Bit3 Bit2 Bit1 Bit0 OXON
OXON: OSCX oscillation on/off. Turn-off OSCX oscillation OXM: switching system clock. select system clock OXS: OSCX oscillator type selection OSCX ceramic oscillator 5.5. Programming notes
Turn-on OSCX oscillation select OSCX system clock OSCX oscillator
takes least OSCX oscillation circuit turn until oscillation stabilizes. When switching system clock from OSCX, user must wait minimum since OSCX oscillation running. However, start time varies with respect oscillator characteristics condition use. Thus wait time depends application. When switching from OSCX OSC, user should switch clock first then turn OSCX. switching from OSCX turning OSCX instruction, OSCX turn control will delayed instruction cycle automatically prevent operation error. Following timing system clock switching.
OSCX turn OSCX turn
OSCXO
OSCO
CLOCK
High frequency operation frequency operation Warm-up time Switch from OSCX Switch from OSCX High frequency operation
Figure Timing system Clock Switching
SH69P54
System clock system clock varies clock source changes. following table shows instruction execution time according each frequency system clock source. 32.768 Xtal (OSC Cycle time 122.07 262K (OSC 17.778 455K ceramic Xtal (OSCX) 8.79 (OSCX) RC(OSCX)
Power Detection (LPD) function monitor supply voltage generate internal reset device. typically used line applications large battery where large loads switched cause device voltage temporarily fall below specified operating minimum. Power supply voltage Operating ambient temperature 7.1. Functions Circuit function selected option. circuit following functions: generates internal reset signal when VLPD tLPD cancels internal reset signal when VLPD VLPD tLPD Here, VDD: power supply voltage, VLPD: detect voltage, There level selected option: level: 2.4~2.6V, typical 2.5V High level: 3.8~4.2V, typical 4.0V tLPD: 100us enabled disabled permanently option.
VLPD 100µs tLPD System reset warm-up count
Internal Reset
Figure voltage reset example
SH69P54
PORTs provides 16bi-directional pins. Each contains pull-up controllable through programming. When every used input, PORT control register (PACR, PBCR,PCCR,PDCR) controls ON/OFF output buffer. Every internal pull pull resister, which controled PULLEN, PH/PL data port. Port mapping address shown follows: Address Bit3 PA.3 PB.3 PC.3 PD.3 Bit2 PA.2 PB.2 PC.2 PD.2 Bit1 PA.1 PB.1 PC.1 PD.1 Bit0 PA.0 PB.0 PC.0 PD.0 PORTA PORTB PORTC PORTD PORTA output port 1,output;0,input PORTB output port 1,output;0,input PORTC output port 1,output;0,input PORTD output port 1,output;0,input Remarks Power 0000 0000 0000 0000 0000 0000 0000 0000
PA3OUT PA2OUT PA1OUT PA0OUT PB3OUT PB2OUT PB1OUT PB0OUT PC3OUT PC2OUT PC1OUT PC0OUT PD3OUT PD2OUT PD1OUT PD0OUT
Equivalent Circuit Single
PULLEN PH/PL CONTROL REGISTER OUTPUT HIGH MOSFET PULL HIGH MOSFET
DATA REGISTER
READ DATA READ
OUTPUT MOSFET PULL MOSFET
System register Address Bit3 Bit2 Bit1 Bit0 Remarks Bit0:External interrupt(PA.0) rising/falling edge PULLEN PH/PL PBCFR EINFR Bit1:PBC interrupt rising failing edge Bit2:Port pull-hi/low Bit3: Port pull-up/low enable control EINFR: External Rising Edge interrupt External Falling Edge interrupt, PBCFR: Rising Edge interrupt Falling Edge interrupt, PH/PL: Port Pull resister Port Pull resister PULLEN: Port Pull /Pull enable, Port Pull /Pull disable turn pull resister,user must PULLEN 1,set PH/PL 1,and write port data register. turn pull resister,user must PULLEN 1,set PH/PL 0,and write port data register. 0100 Power
SH69P54
8.1. PORTB PORTC interrupt PORTB PORTC used port interrupt sources. Following port interrupt function block-diagram.
PBOUT[3] PB[3] PBOUT[2] PB[2] PBOUT[1] PB[1] PBOUT[0] PB[0] PCOUT[3] PC[3] PCOUT[2] PC[2] PCOUT[1] PC[1] PCOUT[0] PC[0] PBCFR PBOUT[3] PB[3] PBOUT[2] PB[2] PBOUT[1] PB[1] PBOUT[0] PB[0] PCOUT[3] PC[3] PCOUT[2] PC[2] PCOUT[1] PC[1] PCOUT[0] PC[0] PORT INTERRUPT DETECT PORTINT
8.2. External INT0 PortA.0 shared external interrupts. External INT0(PA.0) PORT interrupt PROGRAMMING NOTES user wants generate interrupt when rising edge from emerges port, following must executed. 1.Set port input port, fill port data register avoid port floating. 2.Pull port (Use external pull resistance PULLEN 1and PH/PL 3.Set Rising Edge register. (Set PBCFR application. EINFR EXINT application.) further rising edge transition would able make interrupt request until pins return application. user wants generate interrupt when falling edge from emerges port, following must executed. port input port, fill port data register avoid port floating. Pull port (Use external pull resistance PULLEN 1and PH/PL Falling Edge register.(Set PBCFR application.Set EINFR EXINT application.) further falling edge transition would able make interrupt request until pins return application. When PortC shared segment, user only generate interrupt PortB.
SH69P54
Timer SH69P54 8-bit timer. timer consists 8-bit counter 8-bit preload register. timers provide following functions: Programmable internal timer function Read counter values 9.1. Timer configuration operation timer consists 8-bit write-only timer load register (TL0L, TL0H) 8-bit read-only timer counter (TC0L, TC0H). Each order digits high order digits. timer counter initialized writing data into timer load register (TL0L, TL0H). Write low-order digit first then high-order digit. timer counter loaded with content load register automatically when high order digit written counts overflow happens. timer overflow will generate interrupt, interrupt enable flag set. timer programmed several different system clock sources setting Timer Mode register (TM0). Timer reads writes operations follow these rules: Write Operation nibble first High nibble update counter 9.2. Timer0 mode register (TM0) 8-bit counter counts prescaler overflow output pulses. 4-bit registers used timer control shown Table register selects input clock sources timer. Table Timer0 Mode registers ($02) TM0.3 TM0.3 control function: without Auto-Reload function 9.3. Warm-up counter device builds oscillator warm-up timer eliminate unstable state initial oscillation when oscillator starts oscillating following conditions: Hardware reset Power reset voltage reset Wake-up from stop mode Warm-up time interval: oscillator selected system clock, warm-up counter prescaler divided (128). Example: 262K system clock,warm-up time interval x(1/262k)=0.489ms. Crystal/Ceramic oscillator selected system clock,the warm-up counter prescaler divided (4096). Example: Ceramic system clock,warm-up time interval x(1/8M)=0.512ms. warm-up time wake from stop status differen different system clock source. Auto-Reload function TM0.2 TM0.1 TM0.0 Prescaler /2048 /512 /128 External Clock Source System clock System clock System clock System clock System clock System clock System clock INT0 Read Operation High nibble first nibble follows
SH69P54
Base Timer base timer that shared with warm-up timer clock source (Low frequency oscillation: X'Tal 32.768KHz 262KHz). After reset, counts every clock-input signal. When counts $FF, right after next clock input, counter counts generates overflow This causes interrupt base timer interrupt request flag 1.Therefore, base timer function interval timer periodically, generating overflow output every 256th clock signal output. timer accepts 4096Hz 32KHz clock, base timer generates accurate timing interrupt. This base time prescaler reset program accurate timing. This clock-input source selected Bregister. Address Bit3 BTM.3 Bit2 BTM.2 Bit1 BTM.1 Bit0 BTM.0 Function Base timer mode register
BTM.3 Disable base timer BTM.2 reset base timer BTM.1 BTM.0
BTM.3 Enable base timer BTM.2 reset base timer Prescaler Ratio
B[3]
Clock source 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz
base timer counter reset
262k
4096/32K
4Bit Scaler
B[2]
SH69P54
Watch Timer (WDT) Watch timer down-count counter, clock source independent built-in oscillator, that will always even STOP mode enabled). watchdog timer automatically generates device reset when overflows. option enable disable this function. watchdog timer control registers (WDT bit2 select different overflow frequency. bit3 watchdog timer overflow flag. Watchdog timer enabled, will reset when watchdog timer overflows. Repeat reads writes register ($1E), watchdog timer should re-count before overflow happens. System Register $1E: (WDT) WDT.2 WDT.1 WDT.0 Remarks Bit2-0: Watch timer control Bit3: Watchdog timer overflow flag (Read only) Watch timer-out period 4096ms Watch timer-out period 1024ms Watch timer-out period 256ms Watch timer-out period 128ms Watch timer-out period 64ms Watch timer-out period 16ms Watch timer-out period Watch timer-out period watchdog timer overflow reset Watchdog timer overflow, reset happens
Note: Watchdog timer-out period valid will cleared after Power Reset Reset Power Reset.
SH69P54
Driver driver contains controller, voltage generator, common signal pins segment driver pins. There four different driving modes programmable: duty bias,1/6 duty bias,1/5 duty bias bias &1/3bias. driving mode controlled system register power-on initialization status duty, bias. When duty bias mode used, COM7 used SEG32 When duty bias mode used, COM6 used SEG33 When duty bias mode used, COM5 used SEG34 SEG9 also used output port, selected system register $0D. When SEG9 output port, data must written same addresses (358H-36DH). could used data memory needed. When "STOP" instruction executed, will turned off, data keeps same value before executing "STOP" instruction. 12.1. Control Register Add. LPS1 LPS0 DUTY1 DUTY0
DUTY1,0: duty control 0,0: duty, bias 0,1: duty, bias 1,0: duty, bias 1,1: duty, bias LPS1, LPS0: frame frequency control. clock divided from OSC,so frame frequency will change proportion variation frequency. FRAME Frequency (OSC=32768Hz) DUTY MODE DUTY MODE DUTY MODE DUTY MODE LPS1, LPS0 32Hz 34.1Hz 34.1Hz 32Hz 16Hz 17.0Hz 17.0Hz 16Hz 8.5Hz 8.5Hz 4.2Hz 4.2Hz
FRAME Frequency (OSC=262KHz) DUTY MODE DUTY MODE DUTY MODE DUTY MODE
LPS1, LPS0 256Hz 273Hz 273Hz 256Hz 128Hz 136Hz 136Hz 128Hz 64Hz 68Hz 68Hz 64Hz 32Hz 34Hz 34Hz 32Hz
COM1
COM1
FRAME
When STOP mode, COMx SEGx pulled low. easily woken keyboard scan (Port interrupt). When HALT mode, COMx SEGx normal. easily woken base timertimer0 port interrupt.
SH69P54
12.2. power
LCDOFF Power Switch com1 common driver com8
Power Supply Control Circuit
LPS0 SYSCLK/512 LPS1 OSC/64
DUTY LCDCLK Scaler
seg1 segment driver scan output seg34
Built-in special power control power modulation. Address O/S2 O/S1 O/S0
O/S2: segment/common segment output output ports segment output output ports. O/S1: PORTD segment PORT PORT segments. O/S0: PORTC segment PORT PORT segments. When divider resistance 270K, voltage power will degraded about VDD. designed reduce extra contrast control output pins. Then fitted automatically different voltage levels software. 12.3. Select different divider resistance Address LCDON RLCD1 RLCD0
LCDON: on/off switch. off. *When off, output application. shared application, output output GND. RLCD1, RLCD0: divider resistance control 0,0: R1=R2=R3=R4=270K(Default) 0,1: R1=R2=R3=R4=90K 1,0: R1=R2=R3=R4=30K 1,1: R1=R2=R3=R4=10K When large panel used, user value increase bias current better performance. will cost more power, when smaller divider resistances used. User also external parallel connection resistances complex bias current.
LCDON Power Switch
Power Supply Control Circuit
SH69P54
SH69P54
12.4. Configuration duty, bias (COM1 SEG1 Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Address 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Bit3 COM4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit2 COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit1 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit0 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SH69P54
duty, bias (COM1 SEG1 Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H 346H 347H 348H Address Bit3 Bit2 Bit1 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33
SH69P54
duty, bias (COM1 SEG1 Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H 346H 347H Address Bit3 Bit2 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32
SH69P54
duty, bias (COM1 SEG1 Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H Address Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
SEG9-30 used scan output port. Address 358H 359H 35AH 35BH 35CH 35DH Bit0 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Address 35EH 35FH 360H 361H 362H 363H Bit0 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 Address 364H 365H 366H 367H 368H 369H Bit0 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Address 36AH 36BH 36CH 36DH Bit0 SEG27 SEG28 SEG29 SEG30
SH69P54
12.5. waveform
DUTY BIAS SELECT UNSELECT SELECT UNSELECT SELECT UNSELECT DUTY BIAS SELECT UNSELECT
Example output waveform duty bias
COM1
COM2
COM3
SH69P54
Example Duty Bias
COM4 COM1 COM3 COM2 COM2 COM1 COM3 COM4 SEGn+1 SEGn SEGn
SEGn+1 COM4 SEGn
12.6. SHARED APPLICATION User application matrix option configuration same RAM. APPLICATION NOTE seg&com cann't driver matrix directly cause weak driving ability.So Matrix application driving-transistor circuit will used such following. Example Duty Matrix Application Circuit
COM1 COM2 COM3 COM8
COM1' SEG1' SEG2' SEG1 SEG2 SEG29 SEG30 SEG29' SEG30'
COM2'
COM3'
COM8'
Matrix 8X30 dots
SH69P54
12.7. waveform
DUTY UNSELECT
DUTY UNSELECT
SELECT SELECT SELECT SELECT
SELECT SELECT SELECT SELECT
UNSELECT
UNSELECT
UNSELECT
UNSELECT
Example Duty 4X10 Dots
COM1' COM2' COM3' COM4'
COM1 COM2 COM3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
SEG1' SEG2' SEG3' SEG4'SEG5' SEG6'SEG7' SEG8' SEG9' SEG10'
COMx' SEGx'refer driving-amplified output COMx SEGx.
Read DATA Address RDT.3 RDT.7 RDT.11 RDT.15 RDT.2 RDT.6 RDT.10 RDT.14 RDT.1 RDT.5 RDT.9 RDT.13 RDT.0 RDT.4 RDT.8 RDT.12 Remarks Data table address data register Data table address data register Data table address data register Data table address data register Power 0000 0000 0000 0000
register consists 12-bit write-only address load register (RDT.11 RDT.0) 16-bit read-only table data read-out register (RDT.15 RDT.0). read table data, users should write table address register first (high nibble first then nibble), then after instruction, right data will into register automatically (write lowest nibble address into will start data read-out action).
SH69P54
Programmable sound generator (PSG) channel1 channel2. function block diagram shown follows:
CHANNEL1 OSCX CHANNEL2 MIXER
function provides four subfunctions wide applications. Programmable sound Program sound created channels. Every channel programmed follows: Enable/Disable every channel sounds. Select every channel sound frequency. channel sounds mixed into output. output controlled volume levels. Fine noise provide wide-band noise. wide-band noise volume controlled volume levels. Alarm provide many alarm functions software. alarm carrier frequency programmed individually. alarm volume controlled volume levels. Remote control remote control only expandable application sound. Since remote control frequency 56.13KHz 37.92KHz, software select sound frequency. 14.1. subblock diagram block diagram
SEL0 SEL1
CLK-SLECTOR
OSCX
SEL1
SEL0
source OSC/2 OSCX OSCX/16
32.768K 262K 32.768K 262K OSCX 1.8M OSCX 455K OSCX 1.8M OSCX 455K
32.768K 262K 16.384K 131K 1.8M 455K 112.5K 28.4K
block selects clock sources that provides channel sources.
SH69P54
Channel
CH1EN SELECTOR DIVIDER OCT1
REGISTER C1.6 C1.0
OCT1
Scaling ratio
Channel constructed 7-bit pseudo random counter. Channel enabled/disabled CH1EN. creates either sound frequency alarm carrier frequency remote carrier frequency
Channel
CH2EN OCT2 NOISE GENERATOR
C2.14 C2.0
SELECTOR
SELECTOR
REGISTER C2.14 C2.0
C2.14 C2.8
DIVIDER
C2.3 C2.0
32Hz ENEVLOP ENEVLOP
OCT2
Scaling ratio
Channel constructed 15-bit pseudo random counter. Channel enabled/disabled CH2EN 15-bit wide-band noise generator 7-bit sound generator. also create alarm envelope signal.
Sound generator. Sound generator. Sound generator.
Function Sound generator. Noise generator. Alarm mode register.
SH69P54
Mixer
TIME SLOT VOL0 VOL1 PA.1 TIME SLOT CONTROL PA.2 PAM2 SELECTOR2 PA.2 SELECTOR1 PA.1
PAM1
MIXER mixes CH1-OUT CH2-OUT into tone output PA.1 PA.2, when PAM1 1PAM2 Then tone output controlled volume control into volume levels outputted PSG. PA.1 PA.2 controlled PAM1 PAM2 PAM2 PAM1 PA.1:I/O PORT PA.1:PSG output PA.1:I/O PORT PA.1:PSG output Function PA.2: PORT PA.2: PORT PA.2: output PA.2: output
SEL1
SEL0
Vol. control
VOL1
VOL0
Vol. Level
Note: user should enable channels together produce tone, otherwise will produce some unpredictable errors. necessary channels together (ie: play channel melody), allow score always same tones, then unpredicted errors will occur will ignored user.
SH69P54
value divider1 corresponding C1.6 C1.0 C2.14 C2.8 shown following table: LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8)
SH69P54
14.2. Function description sound generator programmable sound working modes. software designer select clock sources clk. then select frequency divided value that controlled value C1.6 C1.0 C2.14 C2.8.The user select volume level controlled VOL0, VOL1. music tone output both user also control OCT1, OCT2 that shifts music tone octaves. Example CH1EN CH2EN OSCX 1.8M, SEL0 SEL1 112kHz; Switch 28kHz Vol. 112kHz Example CH1EN CH2EN OSCX 1.8M, SEL0 SEL1 112kHz; Switch 28kHz; Vol. 112kHz
Example CH1EN CH2EN 32k, SEL0 SEL1 32kHz; Switch 32kHz vol. control, level hardware, software should VOL0 VOL1
Note: 32KHz operations, volume control cannot used, since multiplexing frequency high enough switch sound! user wants turn completely, software must disable both channels. user should turn zero wave from output. Both CH1EN CH2EN should power operation mode. Example software designer wants create (Channel mixed with (Channel sound (For sound frequency please refer Music Table Music Table level 3.Then user select suggestion follows: user first selects CH1EN CH2EN user select OSCX 1.8M SEL0 SEL1 112.5KHz. Then user select OCT1 value channel LSFR (C1.6 C1.0) 108. Please Music Table 1.So channel sound frequency 112.5Khz/8/ 108) 64.10Hz sound frequency. Then user select OCT2 value channel LSFR (C2.8 C2.14) Please refer Music Table 1.So channel sound frequency 112.5Khz/1/ 694.4Hz sound frequency Lastly, user should select VOL1 VOL0 level
SH69P54
Note: designer provides crossing tables appendix since designer prefers 32.768K 112.5K. noise generator Fine noise created CH2. user wants create single noise, then make music tone output. Otherwise, user wide-band noise music tone into output through MIXER. Lastly, user select volume levels controlled VOL0, VOL1. alarm generator When alarm mode, provides alarm carrier frequency provides alarm envelope signal. Lastly user select volume levels controlled VOL0, VOL1. channel nibble C2.0 C2.3 will alarm control register. Channel output would modulate with ALARM envelope control 32KHz 262KHz. carrier frequency programmed channel 1.In reading this alarm control register, user read corresponding output envelope frequency (the 1Hz, 4Hz, 8Hz, 32Hz). Alarm control register (OSC 32KHz 262KHz) $373 C2.3 C2.2 C2.1 C2.0 Alarm output control envelop output output output 32Hz output
Figture: Alarm modulation output 32.768KHz 262KHz.
remote control remote control only expandable application sound. user select tone output will create alarm frequency envelope signal. When channel programmed ALARM mode, programmer ALARM mode register "0000B". Program adequate frequency output output. Then PAM1 PAM2 control envelope code. this way, remote control function implemented easily. remote frequency 56.73KHz 37.92KHz. software should select OSCX 455KHz, SEL1 SEL0 that 455KHz. Then select channel alarm mode (C1M OCT1 C2.0 C2.3 00H. VOL1, VOL2 Then select C1.6 C1.0 that output frequency 455KHz/1/ 37.92KHz. select C1.6 C1.0 that output frequency 455KHz/1/ 56.87KHz.
SH69P54
Interrupt interrupt sources available SH69P54: External interrupt (INT0) Timer0 interrupt Base timer interrupt Port's falling/rising edge detection interrupt (INT1) configuration system register Address IRQX IET0 IRQT0 IEBT IRQBT IRQP Function Enable Disable Request request
15.1. External Interrupt (INT0) External interrupt shared with PA.0, falling/rising edge active. When register (IEX) external interrupt enabled. 15.2. Timer interrupt, Base timer interrupt, Port interrupt (INT1) then valid interrupt requests will cause interrupt. overflow timer will create interrupt timer 0.The overflow Base timer will create interrupt Base timer. falling/rising edge every port PORTB PORTC will create INT1 interrupt (The condition that other port must input high level). 15.3. Enable flags Request flags Both Enable flags Request flags read written software. Request flags will hardware interrupt Enable flags will reset hardware when interrupt service routine entered. 15.4. Interrupt Servicing Sequence Diagram: SH6610D interrupt services routine, user enable interrupt enable flag before returning from interrupt. frequently asked question when next interrupt would serviced? Will nesting interrupt happen? From servicing sequence timing diagram, interrupt request ready instruction execution enable. Then interrupt start right after next instructions: instruction disable interrupt request enable flag, then interrupt service sequence would terminated.
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
HALT STOP Mode After execution HALT instruction, device will enter halt mode. halt mode, will stop operating. peripheral circuit (Timer0, BASETIMER, watchdog timer) will keep operating. After execution STOP instruction, device will enter stop mode. stop mode, whole chip (including oscillator) will stop operating without watchdog timer, enabled. HALT mode, SH69P54 waked interrupt occurs. STOP mode, SH69P54 waked port interrupt occurs Watchdog timer overflow (when enabled).
SH69P54
Options 17.1. Bonding options System register reserved user. available system developer select bonding options, selecting subprogram programmed user. $0C.1 $0C.0
goto subroutine goto subroutine Default goto subroutine goto subroutine
SH69P54 Bonding Option 17.2. option Oscillate type: 32.768K Crystal oscillator (Default) 262K oscillator Oscx range select: 400KHz-2MHz (Default) 2MHz-8MHz Watch timer: Enable (Default) Disable Reset Disable (Default) Enable level High level:4.0V (Default) level:2.5V LCD/LED matrix application (Default) matrix application
SH69P54
Instruction instructions cycle word instructions. characteristic memory-oriented operation. Arithmetic Logical Instruction Accumulator type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 xxxx 01001 xxxx 01010 xxxx 01011 xxxx 01100 xxxx 01101 xxxx 01110 xxxx Function Flag Change Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
shift right
Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function Decimal adjust add. Decimal adjust sub. Flag Change
SH69P54
Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 xxxx Function Flag Change
Control Instruction Mnemonic CALL RTNW RTNI HALT STOP TJMP Where Program counter Accumulator Complement accumulator Carry flag Data memory Immediate data Logical exclusive Logical Logical bank page Stack Table Branch Register Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-C8) (TBR) (AC) Function Flag Change
(Not include
hhhh;
Operation
SH69P54
Absolute Maximum Rating*
Supply Voltage -0.3V 7.0V Input Voltage -0.3V 0.3V Operating Ambient Temperature Storage Temperature
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability
Electrocal Characteristics
(VDD 3.0V ,GND FOSC 32.768KHz, FOSCX used, voltage divider resistor =270K,1/4 bias, unless otherwise specified) Parameter Operating Voltage Operating Current Operating Current Standby Current Standby Current Standby Current Input High Voltage Symbol IOP1 IOP2 ISB1 ISB1H ISB2 Min. -0.3 Typ. Max. Unit output pins unload execute instruction, off, off, output pins unloaded, OSCX system clock, FOSCX=4MHz (Execute instruction) output pins unload (HALT mode), off, off, output pins unload, (HALT mode) OSCX system clock,FOSCX=4MHz off, disable output pins unload (STOP mode), off, PORTA~PORTD INT0, RESET TEST (Schmitt trigger input) PORTA~PORTD RLCD1,RLCD0=0,0 RLCD1,RLCD0=0,1 RLCD1,RLCD0=1,0 RLCD1,RLCD0=1,1 RESET INT0, TEST (Sch mitt trigger input) PORTA.0,PORTA.3,PORTB~D (IOH -2mA PORTA.0, PORTA.3, PORTB~D (IOL PORTA.1~2 Alarm output, -5mA PORTA.1~2 Alarm output, SEGx output port SEGx -1mA SEGx output port SEGx, COMx, -100µA COMx, 2.5mA COMx, SEGx, voltage variation V1,V2,V3,V4 less than 0.2V. PORTA~D, PORTA~D, Conditions
Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Driving resistor Pull-high Resistance Pull-low Resistance Current Lighting voltage divider resistor
VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 IWDT ILCD RLCD
SH69P54
Electrocal Characteristics
(VDD 5.0V,GND= 0V,TA 25,FOSC =32.768KHz,FOSCX used,LCD voltage divider resistor =270K,1/4 bias,unless otherwise specified) Parameter Operating Voltage Operating Current Operating Current Standby Current Standby Current Standby Current Input High Voltage Input Voltage Pull-high Resistance Pull-low Resistance Current Lighting Symbol IOP1 IOP2 ISB1 ISB1H ISB2 IWDT ILCD Min. -0.3 Typ. Max. Unit output pins unload execute instruction, off, output pins unloaded, OSCX system clock, FOSCX=8MHz (Execute instruction) output pins unload (HALT mode), off, output pins unload, (HALT mode), OSCX system clock,FOSCX=8MHz off, disable output pins unload (STOP mode), off, PORTA~PORTD INT0, RESET TEST (Schmitt trigger input) PORTA~PORTD INT0, RESET TEST (Schmitt trigger input) PORTA~D, PORTA~D, Conditions
SH69P54
Characteristics (VDD 3.0V, FOSC 32.768KHz CRYSTAL, unless otherwise specified) Parameter Oscillation Start Time Symbol tSTT Min. Typ. Max. Unit Conditions
Characteristics (GND FOSC 262KHz FOSCX stop, unless otherwise specified) Parameter Frequency Variation Symbol |F|/F Min. Typ. Max. Unit Conditions Include supply voltage chip-to-chip variation
Characteristics (GND FOSCX 8MHz unless otherwise specified) Parameter Frequency Variation Symbol |F|/F Min. Typ. Max. Unit Conditions Include supply voltage chip-to-chip variation
Power Detect Electrical Characteristics 2.4~6V, 25°C, FOSC 8MHz, unless otherwise specified. Parameter Voltage(Low) Voltage(High) Symbol VLPD1 VLPD2 Min. Typ. Max. Unit option=1 option=1 enable VDD<VLPD Condition
power detect ignore time tLPD
Timing Waveform System Clock Timing Waveform
System Oscillator
System Clock
SH69P54
oscillator Characteristics Graphs Typical oscillator Resistor Frequency: (for reference only) Fosc Frequency
5.0V Fosc(kHz) 2000 4000 Rosc(K) 6000 8000
Resistor FOSC, VDD=5.0V
VDD=3.0V Fosc(kHz) 2000 4000 Rosc(K) 6000 8000
Resistor FOSC, VDD=3.0V
SH69P54
Foscx Frequency
VDD=5V 8000 6000 Foscx(kHz) 4000 2000 Roscx(K)
Resistor FOSCX, VDD=5.0V
VDD=3.0V 8000 6000 Foscx(kHz) 4000 2000 Roscx(K)
Resistor FOSCX, VDD=3.0V
SH69P54
System Programming Notice COB(chip Board) assembling mode, System Programming technology valid chip SinoWealth Programming Interface chip must left user's application PCB, users assemble components including chip application before programming chip first. course accessible that bonding chip only first, then programming code, assembling others components last. Because programming timing Programming Interface very sensitive, four jumpers needed (VDD, VPP, SDA, SCK) separate programming pins from application circuit just following diagram.
Application SH69P54 Writer
Application Circuit Jumper
recommended step following these jumpers: jumper Open separate programming pins from application circuit before programming code. Connect programming interface with Writer Begin Programming code. Disconnect writer short these jumpers when programming finished. more detail information please refer writer user manual.
SH69P54
Application Circuit (for reference only)
AP1: OSC: Crystal oscillator 32.768KHz (code option) OSCX: Ceramic oscillator 455KHz PORTB: PORTA.1, PORTA.2: ALARM output LCD: Internal duty, bias
duty bias 100p RESET OSCXO OSCXI 455KHz
SH69P54
32768Hz
PORTB OSCO OSCI
PORTA.1 BUZZER
PORTA.2
TEST
AP2: OSC: oscillator 262KHz (code option) LCD: Internal duty, bias PORTA, PORTB: PORTA.0: External interrupt
duty bias
RESET
OSCXI
OSCXO
SH69P54
930K
PORTA PORTB OSCO OSCI
PORTA.0
Ext.int
TEST
SH69P54
AP3: OSC: Crystal oscillator 32.768KHz (code option) OSCX: oscillator 1.8MHz PORTB,PORTC,PORTD: PORTA.1: output PORTA.2: output
duty bias
RESET PORTB PORTC PORTD OSCO OSCXO OSCXI SPEAKER
SH69P54
PORTA.1
8050
32768Hz OSCI TEST
PORTA.2
AP4: Large panel: internal different bias resistor don't meet request, user External bias
Bias Bias Normal pannel Bias Large pannel Ext.R SH69P54 SH69P54 Ext.R Ext.R internal bias resistors Ext.R SH69P54 Ext.R Bias Large pannel Ext.R
SH69P54
Music Table
Following music scale reference table channel channel under OSCX 1.8MHz. octaves possible) Music scale data 1.8M OSCX SEL0 SEL1 Note Ideal freq. 61.73 65.10 69.29 73.42 77.78 82.41 87.31 92.50 98.00 110.00 123.47 130.81 146.83 164.81 174.61 184.99 196.00 220.00 246.94 261.63 293.66 329.63 349.23 369.99 392.00 440.00 493.88 LSFR Real OCT1 Error% Note (C1.6~C1.0) freq. /OCT2 (C2.14~C2.8) 61.68 -0.08 65.10 69.62 73.24 78.13 82.72 86.81 92.52 97.66 103.40 109.86 117.19 123.36 130.21 137.87 146.48 156.25 163.52 175.78 185.03 195.31 206.80 219.73 234.38 251.12 260.42 281.25 292.97 305.71 334.82 351.56 370.07 390.63 413.60 439.45 468.75 502.23 0.01 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.40 -0.13 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.79 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 Ideal freq. 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 1046.48 1108.71 1174.63 1244.48 1318.48 1396.88 1479.95 1567.95 1661.18 1759.96 1864.62 1975.49 2092.96 2217.41 2349.27 2488.96 2636.96 2793.77 2959.89 3135.90 3322.37 3519.93 3729.23 3950.98 LSFR Real OCT1/ Error% (C1.6~C1.0) freq. OCT2 (C2.14~C2.8) 493.42 -0.09 520.83 556.93 585.94 625.00 661.77 694.44 740.13 781.25 827.21 878.91 937.50 986.84 1041.67 1102.94 1171.88 1250.00 1308.14 1406.25 1480.26 1562.50 1654.41 1757.81 1875.00 2008.93 2083.33 2250.00 2343.75 2445.65 2678.57 2812.50 2960.53 3125.00 3308.82 3515.63 3750.00 4017.86 -0.46 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.41 -0.12 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.78 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69
103.82 116.54
138.59 155.56
207.65 233.08
277.18 311.12
415.30 466.15
SH69P54
Music Table
Following music scale reference table channel channel under 32.768KHz. octaves possible) Music scale data SEL0 SEL1 Note Ideal freq. 55.00 58.27 61.73 65.41 69.29 73.42 77.78 82.41 87.31 92.50 98.00 LSFR OCT1 (C1.6~C1.0) /OCT2 (C2.14~C2.8) Real freq. 55.35 58.51 62.06 66.07 68.27 73.14 78.77 81.92 89.04 93.09 97.52 102.40 107.79 113.78 120.47 128.00 136.53 146.29 156.04 165.50 174.30 184.09 195.05 207.39 221.41 234.06 248.24 Error% Note 0.64 0.42 0.54 1.00 -1.48 -0.38 1.27 -0.60 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37 0.31 0.42 -0.18 -0.49 -0.49 -0.12 0.64 0.42 0.53 Ideal freq. 261.63 277.18 293.66 311.12 329.63 349.23 369.99 392.00 415.30 440.00 466.15 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 1046.48 LSFR Real OCT1 Error% (C1.6~C1.0) freq. /OCT2 (C2.14~C2.8) 260.06 -0.60 277.70 292.57 309.13 327.68 348.60 372.36 390.10 420.10 442.81 468.11 496.49 528.52 546.13 585.14 630.15 655.36 712.35 744.73 780.19 819.20 862.32 910.22 963.77 1024.00 1092.27 1170.29 0.19 -0.37 -0.64 -0.59 -0.18 0.64 -0.49 1.16 0.64 0.42 0.53 1.01 -1.48 -0.37 1.27 -0.59 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37
103.82 110.00
116.54 123.47 130.81
138.59 146.83 155.56 164.81 174.61 184.99 196.00 207.65 220.00 233.08 246.94
1108.71 1174.63
SH69P54
Bonding Diagram
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 RESET TEST OSCO OSCI OSCXO 1956
SH69P54 (0,0)
OSCXI
2162
Substrate connects GND. unit: Designation 3/SEG8 2/SEG7 1/SEG6 0/SEG5 3/SEG4 2/SEG3 1/SEG2 0/SEG1 OSCXI OSCXO OSCI OSCO TEST RESET (µm) -874 -735 -610 -485 -360 -235 -110 1005 1011 1011 1011 1011 1011 1011 1011 1011 1011 1011 (µm) -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -908 -581 -581 -365 -461 -235 -120 Designation COM1 COM2 COM3 COM4 C5/S34 C6/S33 C7/S32 C8/S31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 (µm) -149 -264 -379 -499 -619 -749 -879 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 -1011 (µm) 902.5 772.5 642.5 522.5 402.5 287.5 172.5 57.5 -57.5 -172.5 -287.5 -402.5 -522.5 -642.5 -772.5 -902.5
SH69P54
Package Informations
Outline Dimensions
unit: inches/mm
Detail Seating Plane
Detail
Symbol
Dimensions inches 0.130 Max. 0.004 Min. 0.112 0.005 0.016 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.039 0.006 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max.
Dimensions 3.30 Max. 0.10 Min. 2.85 0.13 0.40 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 1.00 0.15 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max.
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
SH69P54
Ordering Information
Part SH69P54H SH69P54F Package CHIP FORM
Product SPEC. Change Notice
SH69P54 Specification Revision History Version Content Bonding diagram added. Application circuit added. oscillator Characteristics Graphs added. 5-COM 6-COM driving. Oscx 8MHz. Original Date Oct.2003 Mar.2003 Dec.2002
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