4-bit Microcontroller with driver Remote control carrier synthesi
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SH67P51
4-bit Microcontroller with driver
Remote control carrier synthesizer
Features
SH6610C-based single-chip 4-bit micro-controller ROM: 2048 bits RAM: bits Data Operation voltage: 1.8V 3.6V (Typically 3.0V) CMOS bi-directional pins PortA,PortB PortC: shared with SEG1-4 PortD: shared with SEG5-8 PortE: shared with OSCXI, OSCXO 4-level subroutine nesting (including interrupts) 8-bit auto re-load timer/counter 8-bit base timer Warm-up timer power-on reset Powerful interrupt sources: Internal interrupt (Timer0). Internal interrupt (Base Timer) External interrupts: PortB PortC (falling edge). Built-in remote control programmable carrier synthesizer Build voltage regulator Pull-up resistor reset (OTP option) driver: 3X29 dots (1/3 duty bias) 4X28 dots (1/4 duty bias) 5X27 dots (1/5 duty bias) 6X26 dots (1/6 duty bias) Dual Clock Source OSC(OTP option): Crystal oscillator: 32.768 oscillator: OSCX: Ceramic/Crystal oscillator: 400k~4MHz Build (4MHz±2%) Instruction cycle time: 4/4MHz 1µs) 4MHz OSCX clock 4/455kHz(=8.79µs) 455kHz 4/32.768kHz(=122.07µs) 32.768kHz clock 4/131kHz(=30.52µs) 131kHz clock power operation modes: HALT STOP Built-in watchdog timer Built-in Voltage Reset Circuit (1.7±0.1V) Power Detect (2.3±0.1V)
General Description
SH67P51is dedicated infrared remote control transmitter with applications. This chip integrates SH6610C 4-bit core with SRAM, ROM, 8-bit timer, base timer, driver, programmable input/output driving buffers, carrier synthesizer, voltage regulator. This chip builds dual-oscillator enhance total chip performance.
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SH67P51
Configuration
SEG13 SEG12 SEG11 SEG10 SEG9 SEG8/PD3 SEG7/PD2 SEG6/PD1 SEG5/PD0 SEG4/PC3 SEG3/PC2 SEG2/PC1 SEG1/PC0 COM1 VSUB CUP1 CUP2 RESET TEST
SH67P51
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SH67P51
Configuration
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 COM6 SEG28 COM5 COM4 SEG29 COM3
SH67P51
OSCXO OSCXI
OSCO OSCI
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Block Diagram
(2048 Internal (128 8Bit Timer0 &8Bit Base timer PORTS (4*4+2)
TEST
OSCI, OSCO OSCXI,OSCXO PORTE0-1(shared with OSCXI,OSCXO) PORTD (shared with SEG5-8) PORTC (shared with SEG1-4) PORTB PORTA
CORE
REMOTE CONTROL SYNTHESIZER
COMMON DRIVERS
COM1 COM3 COM4, shared with SEG29,28,27
RESET
SEGMENT DRIVERS
SEG1-SEG29
Power control circuit
power
VP1- VP3, VSUB CUP1,CUP2
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SH67P51
Descriptions
5,4,3,1 32,34,35 Designation VP1-VP3 CUP1-2 VSUB RESET TEST OSCI OSCO OSCXI OSCXO SEG1 SEG4 SEG5 SEG8 SEG9 SEG26 SEG27-SEG28 COM6-COM5 COM1-COM3 COM4 SEG29 Power supply LCD, Connection bias capacitor Power supply pin, connected external capacitor Reset input (Optional internal pull-up) Test (Internal pull-low). Carrier synthesizer infrared output pin. Power supply. Oscillator input pin. Oscillator output Oscillator input connected ceramic oscillator. Shared with programmable pin. Oscillator output connected ceramic oscillator. Shared with programmable pin. Ground pin. programmable I/O. programmable pins, Vector Interrupt (Active falling edge). segment 1-4. Shared with programmable pins, Vector Interrupt (Active falling edge), segment 5-8. Shared with programmable pins, Vector Interrupt (Active falling edge), driver Segment driver Segment Shared with driver Common driver Common driver Common Shared with driver Segment Descriptions
Programming Description (OTP program mode)
Symbol Shared TEST OSCI PA[0] Description Programming Power supply (+5.5V) Programming high voltage Power supply (+10.5V) Ground Programming Clock input Programming Data
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Descriptions (Total pad)
Designation VP1-VP3 CUP1-2 VSUB RESET TEST OSCI OSCO OSCXI OSCXO SEG1 SEG4 SEG5 SEG8 SEG9 SEG26 SEG27-SEG28 COM6-COM5 COM1-COM3 COM4 SEG29 Power supply LCD, Connection bias capacitor Power supply pin, connected external capacitor Reset input (Optional internal pull-up) Test (Internal pull-low). Carrier synthesizer infrared output pin. Power supply. Oscillator input pin. Oscillator output Oscillator input connected ceramic oscillator. Shared with programmable pin. Oscillator output connected ceramic oscillator. Shared with programmable pin. Ground pin. programmable programmable pins, Vector Interrupt (Active falling edge). segment 1-4. Shared with programmable pins, Vector Interrupt (Active falling edge), segment 5-8. Shared with programmable pins, Vector Interrupt (Active falling edge), driver Segment driver Segment ,28. Shared with driver Common driver Common driver Common Shared with driver Segment Descriptions
Programming Description (OTP program mode)
Symbol Shared TEST OSCI Description Programming Power supply (+5.5V) Programming high voltage Power supply (+10.5V) Ground Programming Clock input Programming Data
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Functional Description
Decision (BA0, BA1, BA2, BA3, BAZ, Logic Shift (SHR) Carry Flag (CY) holds overflow, which arithmetic operation generates. During interrupt service call instruction, carry flag pushed into stack restored back from stack RTNI instruction. unaffected RTNW instruction. 1.3. Accumulator Accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transferred between accumulator system register, data memory performed. 1.4. Stack group registers used save contents (11-0) sequentially with each subroutine call interrupt. organized bits levels. saved levels maximum allowed subroutine calls interrupts. contents Stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds bottom stack will shifted out. contains following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, DPL), Stack. 1.1. (Program Counter) Program Counter used address program ROM. consists 12-bits: Page Register (PC11), Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC0). program counter normally increases (+1) with every execution instruction except following cases: When executing jump instruction (such JMP, BA0, BC); When executing subroutine call instruction (CALL) When interrupt occurs; When chip INITIAL RESET mode. program counter loaded with data corresponding each instruction. 1.2. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment addition/subtraction (DAA, DAS) Logic operations (AND, EOR, ANDIM, EORIM, ORIM) SH67P51can address 2048 program area from $000 $7FF. Vector Address Area ($000 $004) program sequentially executed. There area address $000 through $004 that reserved special interrupt service routine such starting vector address. Address $000H $001H $002H $003H $004H Instruction Remarks Jump RESET Reserved Jump TIMER0 Jump Base Timer Jump
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Built-in consists general purpose data memory system registers. Direct addressing instruction access data memory system register. following memory allocation map: $000 $027: System register I/O; $028 $0A7: Data memory (128 bits). $300~$33A: RAM; Configuration System Register Address TBR.3 INX.3 DPL.3 PULLEN TBR.2 INX.2 DPL.2 DPM.2 DPH.2 CPS2 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 CPS1 PA.3 PB.3 PC.3 PD.3 LCDON PA.2 PB.2 PC.2 PD.2 PA.1 PB.1 PC.1 PD.1 PE.1 PA.0 PB.0 PC.0 PD.0 PE.0 REMO TBR.0 INX.0 DPL.0 DPM.0 DPH.0 CPS0 OXON Bit3 BTM.3 TL0.3 TH0.3 Bit2 IET0 IRQT0 TM0.2 BTM.2 TL0.2 TH0.2 Bit1 IEBT IRQBT TM0.1 BTM.1 TL0.1 TH0.1 Bit0 IRQP TM0.0 BTM.0 TL0.0 TH0.0 Description Interrupt enable flags Interrupt request flags Timer0 Mode register Base Timer Mode register Timer0 load/counter register digit Timer0 load/counter register high digit Bit0: 2.3v flag Bit2: turn PORTA PORTB PORTC PORTD PORTE Bit0: REMO output data. Bit0: output status. Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit2-0: Carrier counter source pre-divider Bit3: Port pull high enable control Bit0: Turn OSCX oscillator Bit1: clocks select OSCX/0: OSC) Bit3: OSCX type selection Bit0,1: Select DUTY(1/3 1/6) Bit2: PortC Segment1 Bit3: PortD Segment5 Control PORTA~PORTD input output access enable disable. Used matrix's application. Control PORTE input output access enable disable. Used matrix's application. PORTA output port
O/S1
O/S0
DUTY1
DUTY0
PAIN
PBIN
PCIN
PDIN
PA3OUT PA2OUT PA1OUT
PEIN PA0OUT
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configuration system register (continue) Address $24~27 CFL3 CFL7 CFH3 CFH7 CFL2 CFL6 CFH2 CFH6 CFL1 CFL5 CFH1 CFH5 CFL0 CFL4 CFH0 CFH4 WDT.2 WDT.1 WDT.0 Bit3 PB3OUT PC3OUT PD3OUT Bit2 PB2OUT PC2OUT PD2OUT Bit1 PB1OUT PC1OUT PD1OUT PE1OUT Bit0 PB0OUT PC0OUT PD0OUT PE0OUT Description PORTB output port PORTC output port PORTD output port PORTE output port Reserved Bit0 Watch timer control WDF: Watchdog timer overflow flag. Reserved Carrier level timer load data register Carrier level timer load data register Carrier high level timer load data register Carrier high level timer load data register Reserved
(b). system register initial state
Address PA.3 PB.3 PC.3 PD.3 LCDON PA.2 PB.2 PC.2 PD.2 PA.1 PB.1 PC.1 PD.1 PE.1 PA.0 PB.0 PC.0 PD.0 PE.0 BTM.3 TL0.3 TH0.3 IET0 IRQT0 TM0.2 BTM.2 TL0.2 TH0.2 IEBT IRQBT TM0.1 BTM.1 TL0.1 TH0.1 IRQP TM0.0 BTM.0 TL0.0 TH0.0 Power Reset /Pin Reset Voltage Reset -000 -000 -000 0000 xxxx xxxx -0-0000 0000 0000 0000 Reset -000 -000 -uuu uuuu xxxx xxxx -u-0000 0000 0000 0000
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Address CFL3 CFL7 CFH3 CFH7 CFL2 CFL6 CFH2 CFH6 CFL1 CFL5 CFH1 CFH5 CFL0 CFL4 CFH0 CFH4 WDT.2 WDT.1 WDT.0 PA3OUT PB3OUT PC3OUT PD3OUT PA2OUT PB2OUT PC2OUT PD2OUT PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT TBR.3 INX.3 DPL.3 PULLEN O/S1 PAIN O/S0 PBIN TBR.2 INX.2 DPL.2 DPM.2 DPH.2 CPS2 TBR.1 INX.1 DPL.1 DPM.1 DPH.1 CPS1 DUTY1 PCIN TBR.0 INX.0 DPL.0 DPM.0 DPH.0 CPS0 OXON DUTY0 PDIN PEIN PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT Power Reset /Pin Reset Voltage Reset xxxx xxxx xxxx -xxx -xxx 0000 0-00 1100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Reset uuuu uuuu uuuu -uuu -uuu 0uuu u-0u uuuu uuuu 0000 0000 0000 0000 1000 uuuu uuuu uuuu uuuu
Legend: unknown, unchanged, unimplemented.
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Oscillator circuit 4.1. Circuit Configuration SH67P51 on-chip oscillation circuits OSCX. frequency oscillator (32.768kHz crystal 131kHz selected option). This designed frequency operation. OSCX high frequency oscillator (internal oscillator (4MHz external ceramic/crystal oscillator, selected Register OXS). designed high frequency operation. possible select high speed processing high frequency clock select power operation operation clock. When RESET pulled VLVR, OSCX will stop oscillation. after RESET returns high VLVR, will starts oscillation OSCX will turned off. clock automatically selected system clock input source. After reset initialization, starts oscillation OSCX remains original state. clock automatically selected system clock input source.
Oscillator Block Diagram
OSCI OSCO Frequency Clock Oscillator System clock Source Selector OSCXI High Frequency OSCXO Clock Oscillator
Switching control System clock
Base Timer
Generator
Clock
4.2. oscillation generates basic clock pulses that provide peripherals (Base timer, LCD) with operating clock. Crystal oscillator type
OSCI
32768Hz OSCO
CHIP
12pF reference. (Please refer oscillator spec) oscillator type
RBIAS OSCI
CHIP
OSCO
RBIAS: 1.5M reference
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4.3. OSCX oscillation OSCX internal 4MHz external ceramic/crystal oscillator. software options select ceramic internal CPU's clock. Ceramic/Crystal resonator: 400kHz 4MHz.
OSCXI Ceramic OSCXO
20~200pF. (Please refer oscillator spec) Internal oscillator: 4MHz. When internal 4MHz selected, OSCXI OSCXO also PortE0,1. 4.4. Control oscillator oscillator control register configuration shown follows: Address Bit3 Bit2 Bit1 Bit0 OXON
OXON: OSCX oscillation on/off. Turn-off OSCX oscillation OXM: switching system clock. select system clock OXS: OSCX oscillator type selection OSCX ceramic oscillator 4.5. Programming notes
Turn-on OSCX oscillation select OSCX system clock OSCX oscillator, OSCXI/OSCXO PortE
takes least OSCX oscillation circuit turn until oscillation stabilizes. When switching system clock from OSCX, user must wait minimum since OSCX oscillation running. However, start time varies with respect oscillator characteristics condition use. Thus wait time depends application. When switching from OSCX OSC, user should switch clock first then turn OSCX. switching from OSCX turning OSCX instruction, OSCX turn control will delayed instruction cycle automatically prevent operation error. Following timing system clock switching.
OSCX turn OSCX turn
OSCXO
OSCO
CLOCK
High frequency operation frequency operation Warm-up time Switch from OSCX Switch from OSCX High frequency operation
Figure Timing system Clock Switching
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4.6. System clock system clock varies clock source changes. following table shows instruction execution time according each frequency system clock source. 32.768kHz Crystal (OSC) 131kHz (OSC) 455kHz Ceramic (OSCX) Cycle time 122.07 30.52µs 8.79 4MHz (OSCX)
Timer SH6636 8-bit timer. timer/counter following features: 8-bit up-counting timer/counter Automatically re-loads counter 8-bit pre-scaler Interrupt overflow from following simplified timer block diagram. Timer block Diagram
[2:0]
Read Operation: High nibble first, Followed nibble.
Load Reg.
Load Reg.
8-bit timer counter
TIMER0 (8bits)
FOSC/4
Latch Reg.
TIMER0 Load Register
Timer Load register Configure Timer mode register timer programmed several different prescaler ratios setting Timer Mode register (TM0). 8-bit counter prescaler overflow output pulses. timer mode registers (TM0) 3-bit registers used timer control shown Table These mode registers select input pulse sources into timer. Table Timer0 Mode Register TM0.2 TM0.1 TM0.0 Prescaler Divide Ratio /211
Configuration Operation Timer0 consists 8-bit write-only timer load register (TL0L, TL0H), 8-bit read-only timer counter (TC0L, TC0H). Each them order digits high order digits. Writing data into timer load register (TL0L, TL0H) initialize timer counter. Load register programming: Write low-order digit first then high-order digit. timer counter automatically loaded with contents load register when high order digit written counter counts overflow from $00. Timer Load Register: Since register will control physical READ WRITE operations. Follow these steps: Write Operation: nibble first, High nibble update counter
Ratio 2048 (initial)
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5.3. Warm-up counter device builds oscillator warm-up timer eliminate unstable state initial oscillation when oscillator starts oscillating following conditions: After reset/ Power reset voltage reset Watch reset Wake-up from stop mode Warm-up time interval: oscillator (OSC OSCX) selected system clock, warm-up counter pre-scaler (128). Example: 131kHz system clock, warm-up time interval (1/131kHz)=977 Example: 4MHz system clock, warm-up timer interval (1/4MHz)=32µs Crystal/Ceramic oscillator selected system clock, warm-up counter pre-scaler (8192). Example: 32.768kHz crystal system clock, warm-up time interval (1/32.768kHz)=250ms. Example: 455kHz ceramic system clock, warm-up time interval (1/455kHz)=18ms warm-up time wake from stop status different different system clock source. Base Timer base timer that shared with warm-up timer clock source base timer pre-scaler output pulse (scaled from clock, X'Tal 32.768kHz 131kHz). After reset, counts every clock-input signal. When counts $FF, right after next clock input, counter counts generates overflow. This causes interrupt flag base timer Therefore, base timer function interval timer periodically, generating overflow output every clock signal input. timer accepts 4096Hz 16KHz clock, base timer generates accurate timing interrupt. This base time pre-scaler reset program accurate timing. This clock-input source selected Bregister. Address Bit3 BTM.3 Bit2 BTM.2 Bit1 BTM.1 Bit0 BTM.0 Function Base timer mode register
BTM.3 Disable base timer BTM.2 reset base timer BTM.1 BTM.0
BTM.3 Enable base timer BTM.2 reset base timer Prescaler Ratio
B[3]
Clock source Fosc/8 Fosc/32 Fosc/64 Fosc/128
base timer counter reset
32kHz 131kHz
4096/16KHz
4Bit Scaler
B[2]
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PORT SH67P51 provides pins. Each contains pull-high controllable program. Sections below show circuit configuration ports. PORTA, PORTB, PORTC, PORTD, PORTE Each these ports contains bits 2bits pins (PortC,D shared with SEG1~8, PortE shared with OSCXI/OSCXO) port control register control ON/OFF output buffer port. Port mapping address shown follows: Address Bit3 PA.3 PB.3 PC.3 PD.3 Bit2 PA.2 PB.2 PC.2 PD.2 Bit1 PA.1 PB.1 PC.1 PD.1 PE.1 Bit0 PA.0 PB.0 PC.0 PD.0 PE.0 Remarks PORTA PORTB PORTC PORTD PORTE
following sections show circuit configuration ports.
PULL-UP PORT CONTROL REGISTER PORT DATA REGISTER DATA INPUT RD_INPUT PULL-UP PMOS
Figure. Port Configuration Function Block Diagram Port Control Register: Address Bit3 PA3OUT PB3OUT PC3OUT PD3OUT Bit2 PA2OUT PB2OUT PC2OUT PD2OUT Bit1 PA1OUT PB1OUT PC1OUT PD1OUT PE1OUT Bit0 PA0OUT PB0OUT PC0OUT PD0OUT PE0OUT Remarks PORTA output port PORTB output port PORTC output port PORTD output port PORTE output port
control register: PAXOUT, PBXOUT, PCXOUT, PDXOUT, PEXOUT output buffer. input buffer (power-on initial).
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share control register Add. OXON Remark Bit0: Turn OSCX oscillator Bit1: clocks select OSCX/0: OSC) Bit3: OSCX type selection Bit0, Select DUTY (1/3 1/6) Bit2: PortC Segment1 Bit3: PortD Segment5
O/S1
O/S0
DUTY1
DUTY0
OXS:
OSCX ceramic oscillator (Default) OSCX oscillator, OSCXI/OSCXO PortE
O/S0:
select PortC ports select PortC Segment (Default)
O/S1:
select PortD ports select PortD Segment (Default)
default value O/S0, O/S1 "1", after Power reset. means that PortC,D shared Segment output after Power reset. PortC,D shouldn't pulled high external signal source avoid additional leakage current when reset. Controlling pull-high These ports contain pull-high controlled program. PULLEN register controls On/Off pull-high simultaneously. Pull-high controlled port data registers (PA, each port also. Thus, pull-high turned individually. turn pull resister, user must PULLEN 1,and write port data register. Port Function Control below: Address PULLEN PULLEN CPS2 CPS1 CPS0 Remarks Bit2-0: Carrier counter source pre-divider Bit3: Port pull high enable control
Port Pull-low enables control Enable PORT pull-high Disable PORT pull-high (power-on initialization)
Ports matrix SH67P51's make matrix PortC~PortD segment output same time. this application, user should control that scanning matrix share timing display. Only when user scan matrix, Ports used I/O; otherwise PortC,D segment output drive panel. Ports used segment controlled software. scan application, when user doesn't execute operation scan key, Ports which don't share segment output should I/O, disabled it's pull high resistor input/output access write system register ($16H~$1CH)'s corresponding bit. Execute above operation prevent voltage input general Ports Port's pull high output affect segment's waveform. When user wants scan key, ports, which make matrix should used general I/O, ports' pull high resistor input access should enabled clear system register ($16H, $17H)'s corresponding bit.
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matrix's ports control register PAIN PBIN PCIN PDIN Remark Control PORTA~PORTD input output access enable disable. Used matrix's application. Control PORTE input output access enable disable. Used matrix's application.
PEIN
PAIN.PFIN: matrix's application, control PORTA~F input output access. Enable PA~PE pull high resistor access, Ports normal state Disable PA~PE pull high resistor it's access Port Interrupt PORTB PORTC used port interrupt sources. Since PORT programmable I/O, only input port generate external interrupt. PORTB PORTC input transitions from will generate interrupt request Further falling edge transition would able make interrupt request until input pins have returned VDD. following port interrupt function block-diagram.
PORTC.3 PC3OUT PORTC.2 PC2OUT PORTC.1 PC1OUT PORTC.0 PC0OUT PORTB.3 PB3OUT PORTB.2 PB2OUT PORTB.1 PB1OUT PORTB.0 PB0OUT
FALLING EDGE DETECTION
PORT INTERRUPT
Figure. PORT Interrupt Block Diagram
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8.Remote Control Carrier Synthesizer SH67P51 builds-in carrier synthesizer infrared remote control circuits. Address Bit3 PULLEN Bit2 CPS2 Bit1 CPS1 Bit0 CPS0 REMO Remarks Bit2-0: Carrier counter source pre-divider Bit3: Port pull high enable control Bit0: REMO output data. Bit0: output status.
REMO: Remote output data control. output status read instruction. CPS2~0: Carrier counter source pre-divider control Register carrier synthesizer programmed several different pre-scaler ratios setting CPS2~0. Carrier count source pre-divider control Register CPS2 CPS1 CPS0 Pre-scaler Divide Ratio System clock
Ratio 2048
System clock System clock System clock System clock System clock System clock System clock
carrier generating counter count-up counter reload data register. counter load registers both have order digits high order digits. Writing data into timer load registers ($20,$21,$22,$23) initialize counter. After system reset, counter automatically loaded with contents high level timer load data register ($22,$23)and output high level same time. Following when counter counts overflow from $00,the counter automatically loaded with contents level timer load data register ($20,$21) output level same time. When counter counts overflow again from again, counter will loaded with contents high level timer load data register again. above sequences make complete loop. carrier synthesizer output continuous carrier wave certain duties certain period. bit0 $0D(REMO) 1from 0,the carrier counter will initialized load high level timer load data register output high level whatever states counter Load register programming: User modify level timer load data register ($20,$21) change width level. User also modify high level timer load data register ($22,$23)to change width high level. carrier synthesizer output carrier wave different duties different period.
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Carrier load data register Address Bit3 CFL3 CFL7 CFH3 CFH7 Bit2 CFL2 CFL6 CFH2 CFH6 Bit1 CFL1 CFL5 CFH1 CFH5 Bit0 CFL0 CFL4 CFH0 CFH4 Remarks Carrier level timer load data register Carrier level timer load data register Carrier high level timer load data register Carrier high level timer load data register
level timer load data register Carrier output
SYSTEM CLOCK
Prescaler divider
Carrier generating counter
High level timer load data register
REMO
CARRIER SYNTHESIZER
Figure. Remote Control Functional Block Diagram example: System clock 4M/4 4M/4 4M/4 4M/4 480k/4 455k/4 432k/4
CPS2, CPS1, CPS0 1,1,1 1,1,1 1,1,1 1,1,1 1,1,1 1,1,1 1,1,1
Carrier Duty 8/25 9/26 13/27 7/28 =1/4
Carrier Frequency 40.00kHz 38.46kHz 37.04kHz 35.71kHz 40.00kHz 37.92kHz 36.00kHz
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COUNTER SOURCE
RESET SIGNAL
REMO COUNTER OVERFLOW 1:load high level data register
2:High level counter overflow load lowlevel data register 3:Low level counter overflow load high level data register MODIFY HIGH&LOW DATA REGISTER CARRIER OUTPUT
OUTPUT OUTPUT HIGH HIGH LEVEL OUTPUT LEVEL OUTPUT LEVEL LEVEL
(255n1)clock interval (255n2)clock interval carrier wave period
n1Dec=($1E,$1D)Hex n2Dec=($1C,$1B)Hex
Figure.5 CARRIER SYNTHESIZE WAVE
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Driver driver contains controller, voltage regulator generator, common signal pins 26~29 segment driver pins. There seven different driving modes programmable: duty bias, duty bias duty bias duty bias. driving mode controlled system register power-on initialization status duty, bias. When "STOP" instruction executed, will turned off, data keeps same value before executing "STOP" instruction. When off, both COMMON SEGMENT output 9.1. Control Register Add. O/S1 LCDON O/S0 DUTY1 DUTY0 Remark Bit2: turn Bit0, Select DUTY (1/3 1/6) Bit2: PortC Segment1 Bit3: PortD Segment5
Segment: Register bit2,3 control segment number. O/S0: select PortC ports select PortC Segment O/S1: select PortD ports select PortD Segment default value O/S0, O/S1 "1", after Power reset. means that PortC,D shared Segment output after Power reset. PortC,D shouldn't pulled high external signal source avoid additional leakage current when reset. Duty: bit1, 0(DUTY1, DUTY0) control duty DUTY1, duty control duty, bias, Segment29 shared Common duty, bias duty, bias, Segment28, shared Common duty, bias, Segment27, 28,29 shared Common 6,5,4
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clock: LCDCLK OSC/32(32.768k crystal) OSC/128(131k 1024 Frame frequency LCDCLK/(4X8) 32Hz LCDCLK/(4X6) 42.7Hz LCDCLK/(3X10) 34.1Hz LCDCLK/(2X12) 42.7Hz duty duty duty duty
power program turn turn writing bit2. LCDON: on/off switch. off. *When off, output application. SH67P51 build voltage regulator power. When unstable (VDD 2.0~3.6), internal voltage regulator generate stable voltage power.
*The following diagram application diagram power circuit
VDD=2.0-3.6V
Voltage Regulator
LCDON CUP1 CUP2 0.1µF
power supply circuit
2.1+/-0.3 VSUB 0.1µF 0.1µF 0.1µF 0.1µF
Figure.6 power circuit diagram
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SH67P51
9.2. Configuration duty bias (4X28) Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH Address Bit3 COM4 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Bit2 COM3 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Bit1 COM2 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Bit0 COM1 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28
duty bias (3X29) Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH Address Bit3 Bit2 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 Bit1 COM2 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 Bit0 COM1 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29
V0.4
SH67P51
duty bias (5X27) Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 320H 321H 322H 323H 324H 325H 326H 327H 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH Address Bit3 Bit2 Bit1 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27
V0.4
SH67P51
duty bias (6X26) Bit3 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 320H 321H 322H 323H 324H 325H 326H 327H 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H Address Bit3 Bit2 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26
V0.4
SH67P51
Interrupt Three interrupt sources available SH67P51: Timer0 overflow interrupt Base timer overflow interrupt Port's falling edge detection interrupt (PBC) Interrupt Control Bits Interrupt Service interrupt control flags mapped through system register. They accessed tested program. These flags cleared initialization chip reset. Address Bit3 Bit2 IET0 IRQT0 Bit1 IEBT IRQBT Bit0 IRQP Remarks interrupt enable flags interrupt request flags
When interrupt request generated (IRQx interrupt will activated vector address will generated from priority corresponding interrupt sources. When interrupt occurs, flag will saved into stack memory jump interrupt service vector address. After interrupt occurs, interrupt enable flags (IEx) reset automatically, thus, when IRQx again, interrupt will activated vector address will generated from priority corresponding interrupt sources. Interrupt Servicing Sequence Diagram:
Inst. cycle Instruction Execution Instruction Execution Instruction Execution Vector Generated Stacking
Fetch Vector address Reset IE.X
Interrupt Generated
Interrupt Accepted
Start vector address
V0.4
SH67P51
Interrupt Nesting: During SH6610C interrupt service, user enable interrupt enable flag before returning from interrupt. servicing sequence diagram shows next interrupt next nesting interrupt occurrences. interrupt request ready instruction execution enable, then interrupt will start immediately after next instruction executions. However, instruction instruction disables interrupt request enable flag, then interrupt service will terminated. HALT STOP mode After execution HALT instruction, SH67P51 will enter HALT mode. HALT mode, will stop operating; however, peripheral circuit (timer) will keep operating. After execution STOP instruction, SH67P51 will enter STOP mode. STOP mode, entire chip (including oscillator) will stop operating. HALT mode, SH67P51 woken interrupt occurs. STOP mode, SH67P51 woken port interrupt occurs. Power Detect (LPD) function monitors supply voltage battery Address Functions Circuit: circuit following functions: when VLPD 2.3±0.1V) bit=0 when VLPD 2.3±0.1V) Voltage Reset (LVR) function monitors supply voltage applies internal reset micro-controller battery replacement. applied circuit satisfies following conditions, incorporated software control. Functions Circuit: circuit following functions: Generates internal reset signal when VLPD 1.7±0.1V). Bit3 Bit2 Bit1 Bit0 Remarks Bit0: 2.3v flag
V0.4
SH67P51
Watch Timer Watchdog timer down-count counter, clock source clock (32.768k X'tal 131k RC). watchdog timer automatically generates device reset when overflows. option enable disable this function. watchdog timer control registers (WDT bit0 select different overflow frequency. bit3 watchdog timer overflow flag. System Register (WDT) Address example:
When Fosc 32.768kHz Crystal WDT2-0 000, Watch timer-out period /Fosc
Remarks Bit0 Watch timer control WDF: Watchdog timer overflow flag. (Read only)
Watch timer-out period /Fosc
Power 0000
WDT.2 WDT.1 WDT.0
Watch timer-out period /Fosc
Watch timer-out period /Fosc Watch timer-out period /Fosc Watch timer-out period /Fosc Watch timer-out period /Fosc Watch timer-out period /Fosc Watch timer-out period /Fosc
watchdog timer overflow reset Watchdog timer overflow
When Fosc 131kHz WDT2-0 =000, Watch timer-out period 217/Fosc will reset when watchdog timer overflows. read will clear normal operation, read write $1E, watchdog timer should re-count before overflow happens. function disabled option.
V0.4
SH67P51
option (a). Internal pull-up resistor RESET enable (default) disable (b). Watch Timer enable (default) disable (c). type select 32.768kHz crystal 131kHz System Programming Notice (chip Board) assembling mode, System Programming technology valid chip SinoWealth Programming Interface chip must left user's application PCB, users assemble components including chip application before programming chip first. course accessible that bonding chip only first, then programming code, assembling others components last. Because programming timing Programming Interface very sensitive, four jumpers needed (VDD, VPP, SDA, SCK) separate programming pins from application circuit just following diagram.
Application SH6XPXX Writer
Application Circuit Jumper
recommended step following these jumpers: jumper Open separate programming pins from application circuit before programming code. Connect programming interface with Writer Begin Programming code. Disconnect writer short these jumpers when programming finished. more detail information please refer writer user manual.
V0.4
SH67P51
Instruction instructions cycle one-word instructions. characteristics memory-oriented operation. Arithmetic Logical Instructions Accumulator Type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx Function Flag Change (,B) Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function [3]; shift right Flag Change
assembler ASM66 V1.0, EORIM mnemonic EORI. However, EORI same operation identical with EORIM. same true ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust Mnemonic Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx Function Flag Change Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function Decimal adjust add. Decimal adjust sub. Flag Change
V0.4
SH67P51
Control Instruction Mnemonic CALL RTNW RTNI HALT STOP TJMP Where: Program counter Accumulator Complement accumulator Carry flag Data memory page Stack Table Branch Register Immediate data Logical exclusive Logical Logical bank Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-PC8) (TBR) (AC) Operation Function (Not include hhhh; llll Flag Change
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SH67P51
Absolute Maximum Rating*
Supply Voltage .-0.3V +6.0V Input Voltage -0.3V 0.3V Operating Ambient Temperature -10to Storage Temperature -55to +125
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device under these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 3.0V, FOSCX 4MHz, unless otherwise specified)
Parameter Operating Voltage Operating Current Symbol Min. Max. Unit output pins unload, (Execute instruction) Fosc=32.768k crystal, OSCX HALT Current ISB1 without panel output pins unload (HALT mode) STOP Current sink current driving current Input Voltage Input Voltage Input High Voltage Input High Voltage Input Leakage Current Output High Voltage Output High Voltage Output Voltage Output Voltage Pull-up Resistor driving resistor ISB2 IREM1 IREM2 VIL1 VIL2 VIH1 VIH2 VOH1 VOH2 VOL1 VOL2 GND-0.3 GND-0.3 0.85 VDD-0.7 0.15 VDD+0.3 VDD+0.3 STOP output pins unload Condition
VREM1 0.3V VREM2 ports, pins tri-state. RESET TEST, OSCI (Schmitt trigger input) Ports, pins tri-state RESET TEST, OSCI (Schmitt trigger input) Input Pad, =GND PortB-PortE, -0.5mA PortA -5mA PortB-PortE, PortA, 10mA Internal pull-up resistor reset SEG1~29, COM1~6
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SH67P51
Power Detect Circuitry(TA =25, unless otherwise specified)
Parameter Power Detect voltage Voltage Reset voltage Symbol VLPD VLVR Min. Typ. Max. Unit Condition
Voltage Regulator Circuitry(VDD 2.0-3.6V, =5-45, unless otherwise specified)
Parameter Regulator output voltage (VP2 output voltage) Symbol Min. Typ. Max. Unit Condition Connecting 200k resistor between GND. Without panel load
Electrical Characteristics (VDD 3.0V, 25°C, internal oscillator, unless otherwise specified)
Parameter Oscillator Start time Internal Frequency Variation Symbol TOSC FOSCX 3.92 Min. Typ. Max. 4.08 Unit Conditions Oscillator 32.768KHz =2.0-3.6V,
frequency oscillator Resistor Frequency: (VDD reference only)
1000 F(kHz) 1000 2000 3000 4000 5000 6000 7000 R(k) 8000
V0.4
SH67P51
Application Circuit (for reference only) AP1: Remote Control Keys) Oscillator: Internal (OSCXI OSCXO shared PortE0, PortA0-2: Buffers PortB, PortA3 PortE: Input Buffers Internal pull high RESET (10) possible, specification revised reduce power consumption
0.1uF
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
CUP1,2 VSUB
COM1-4 SEG1/PC0 SEG5-28 SEG2/PC1 SEG3/PC2 SEG4/PC3 OSCXI/PE0 SH67P51 OSCXO/PE1
RESET
CE=47uF
32768Hz
OSCI OSCO
Temperature Sensor R1,2: Reference Resister ROP: Option Resister 12pF reference. (Please refer oscillator spec)
V0.4
SH67P51
AP2: Remote Control Keys) (11) Oscillator: 455kHz Ceramic oscillator (12) PortA0-2: Buffers (13) PortB, PortA3: Input Buffers (14) Internal pull high RESET (15) (16) possible, specification revised reduce power consumption
0.1uF
0.1uF 0.1uF 0.1uF 0.1uF
CUP1,2
COM1-4 SEG1/PC0 SEG5-28 SEG2/PC1 SEG3/PC2 SEG4/PC3
0.1uF 0.1uF
VSUB
SH67P51
CE=47uF
RESET 32768Hz OSCI OSCO OSCXI/PE0 455KHz OSCXO/PE1
Temperature Sensor R1,2: Reference Resister ROP: Option Resister 12pF reference. (Please refer oscillator spec) 20~200pF. (Please refer oscillator spec)
V0.4
SH67P51
Bonding Diagram
(0,0)
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 COM6 SEG28 COM5 COM4 SEG29 COM3
SH67P51
2150um
OSCXO OSCXI
OSCO OSCI
2010um
Substratum connects GND.
Location
Designation OSCXO OSCXI OSCO OSCI TEST RESET CUP2 -867.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -878.5 -494.8 -291.1 -174.3 -57.5 57.5 947.5 810.05 690.05 570.05 455.05 340.05 225.05 110.05 -4.95 -119.95 -234.95 -796.3 -911.3 -933.4 -947.4 -947.4 -947.4 -947.4 Designation CUP1 VSUB COM1 COM2 COM3 COM4 SEG29 SEG28 COM5 SEG27 COM6 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 172.5 287.5 402.5 517.5 632.6 747.5 867.5 878.5 878.5 878.5 878.5 878.5 878.5 878.5 878.5 878.5 878.5 878.5
unit:
-947.4 -947.4 -947.4 -947.4 -947.4 -947.4 -947.4 -809.95 -689.95 -574.95 -459.95 -344.95 -229.95 -114.95 0.05 115.05 230.05 345.05
V0.4
SH67P51
Location (continued)
Designation SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 878.5 878.5 878.5 878.5 872.5 747.5 632.5 517.5 402.5 287.5 460.05 575.05 690.05 810.05 947.5 947.5 947.5 947.5 947.5 947.5 Designation SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 172.5 57.5 -57.5 -172.5 -287.5 -402.5 -517.5 -632.5 -747.5 947.5 947.5 947.5 947.5 947.5 947.5 947.5 947.5 947.5
Ordering Information
Part SH67P51H SH67P51F Package Chip form
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SH67P51
Outline Dimensions
unit: inches/mm
Detail Seating Plane
Detail
Symbol
Dimensions inches 0.130 Max. 0.004 Min. 0.112 0.005 0.016 +0.004 -0.002 0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.039 0.006 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max.
Dimensions 3.30 Max. 0.10 Min. 2.85 0.13 0.40 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 1.00 0.15 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max.
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
V0.4
SH67P51
Specification Revision History Version Content information about package description. bonding diagram. frequency Frequency-Resistance diagram. information about programming. Change warm counter. "VSUB" change application current, Change reset value Change address system register RAM, change reset value $1E. Change definition voltage regulator LPD. Original Date
V0.4
2003/12/10
V0.3 V0.2 V0.1
2003/08/06 2003/07/14 2003/06/09
V0.4
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