4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit
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SH67L18A
4-bit Microcontroller with Driver
SH6610C-based single-chip 4-bit microcontroller with driver ROM: bits (bank switched) RAM: 1024 bits (system control register, bank switched data memory RAM) Operation Voltage Range: 1.2V 1.7V CMOS pins level subroutine nesting (including interrupts) 8-bit timer with pre-divider circuit priority interrupt sources: External interrupt (falling edge) Base Timer interrupt Timer0 interrupt Port interrupt (falling edge) System clock source: 32.768KHz crystal selected code option. (Refer CODE OPTION) Instruction cycle time: 4/200KHz (20µs) 200KHz 4/32.768KHz (122µs) 32.768KHz crystal Base timer clock source: 32.768KHz crystal oscillator selected code option. (Refer CODE OPTION) driver: (1/4 duty, bias) segment shared with PORTD, Built-in voltage treble charge pump circuit Built-in alarm generator (carrier frequency: 2KHz 4KHz. selected system register) power operation modes: HALT STOP mode power consumption Bonding option multi-code software Watch timer Available CHIP FORM
General Description
SH67L18A single-chip microcontroller integrated with SH6610C core, SRAM, timer, alarm generator, driver, ports, voltage pump program ROM.
Configuration
SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 PORTD0 SEG42 PORTD1 SEG43 PORTD2 SEG44 PORTD3 SEG45 PORTE0 SEG46 PORTE1
SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM1 COM2 COM3 COM4 PORTF0 PORTF1 PORTF2 PORTF3 CUP1
SH67L18A
V1.0
SH67L18A
Block Diagram
TEST OSCXI OSCI OSCO
8-BIT TIMER PORTB PORTF PORTA.0 (INT) PORTA.1 (BD) PORTA.2 (BD) PORTA.3
CORE
PORTS
PORTA EXTERNAL
RESET1
COMMON DRIVERS
COM1 COM4
SEGMENT DRIVERS ALARM GENERATOR
SEG1 SEG48 (SEG41 shared with PORTD PORTE)
RESET0
VOLTAGE TREBLE CHARGE BUMP CIRCUIT
CUP1 CUP2
Description (Total pads mask type)
40-79,88-93,1,2
Designation SEG1-40, 41-48 COM1 VP1, CUP1, CUP2 TEST
RESET1 RESET0
Description Segment signal output display SEG41 switch ports (PORTD Common signal output display Power supply driver Connection voltage treble capacitor Test internally pull-down connection user)
reset input (level edge triggering selected code option, active falling edge active, internal pull-high) reset input (level edge triggering selected code option, active falling edge active, internal pull-high) Power supply Ground Bonding option (internally pull-low) Bonding option (internally pull-high) 32.768KHz X'tal input 32.768KHz X'tal output 200KHz Oscillator input programmable I/O, PA.0 could external interrupt input PA.1, PA.2 could buzzer output PA.1 (BD), PA.2 programmable Vector interrupt (Active falling edge) connection
3-6,23,24,27 28,30,80-87
OSCI OSCO OSCXI PORTA0 PORTB0
SH67L18A
Functional Description
contains following functional blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, DPL), Stacks. 1.1. (Program Counter) Program Counter used address program ROM. consists 12-bits: Page Register (PC11) Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). program counter normally increases (+1) with every execution instruction except following cases: When executing jump instruction (such JMP, BA0, BAC); When executing subroutine call instruction (CALL); When interrupt occurs; When chip INITIAL RESET. program counter loaded with data corresponding each instruction. unconditional jump instruction (JMP) 1-bit page register higher than 1.2. performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI)
address words bits program area from $0000 $1FFF. Program Counter only address program ROM. address program ROM, bank switch. There area from address $0000 through $0004 that reserved special interrupt service routines, such starting vector address. Decimal adjustment addition/subtraction (DAA, DAS) Logic operations (AND, EOR, ANDIM, EORIM, ORIM) Decision (BA0, BA1, BA2, BA3, BAZ, BAC) Logic Shift (SHR) Carry Flag (CY) holds overflow, which arithmetic operation generates. During interrupt service call instruction, carry flag pushed into stack restored back from stack RTNI instruction. unaffected RTNW instruction.
1.3. Accumulator Accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transfers performed between accumulator system register, RAM, data memory. 1.4. Stack group registers used save contents (10-0) sequentially with each subroutine call interrupt. organized bits levels. saved levels maximum allowed subroutine calls interrupts. contents Stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds bottom stack will shifted out.
Address
0000H 0001H 0002H 0003H 0004H
Instruction
instruction instruction instruction instruction instruction
Remarks
Jump RESET service routine Jump External interrupt service routine Jump TIMER0 service routine Jump Base Timer service routine Jump service routine (PORTB)
*JMP instruction replaced instruction.
SH67L18A
Bank Switch Mapping
Program Counter (PC11 PC0) only address space. Bank switch technique used extend address space. lower addressing space maps lower space (BANK0). upper addressing space maps seven banks (BANK upper ROM. (According Bank Register $1F) bank switch mapping follows:
Address
000-7FF
Space, $1FH
0000 07FF (BANK 0800-0FFF (BANK
Space, $1FH
0000 07FF (BANK 1000 -17FF (BANK
Space, $1FH
0000 07FF (BANK 1800 -1FFF (BANK
Table Data Reference
Table Data stored program memory referenced using Table Branch (TJMP) Return Constant (RTNW) instructions. Table Branch Register (TBR) Accumulator placed offset address program ROM. TJMP instruction branch placed into address ((PC11 PC8) (TBR, A)). address determined RTNW return look-up value into (TBR, code bit7-bit4 placed into bit3-bit0 into
Built-in contains general-purpose data memory, RAM, system register. following memory allocation map: $000 $01F: System register $020 $2FF, $338 $3FF: Data memory (944 bits, divided into banks) $300 $337: space bits) bank table: (RAMB: System Register $14H bit3)
Bank Bank Bank Bank Bank Bank Bank Bank RAMB=0, RAMB=0, RAMB=0, RAMB=0, RAMB=0, RAMB=0, RAMB=0, RAMB=0,
$020 $07F $080 $0FF $100 $17F $180 $1FF $200 $27F $280 $2FF $300 $37F $380 $3FF
bank data instructions.
SH67L18A
Configuration System Register: Address
IRQX TL0.3 TH0.3 BTL.3 BTH.3 PA.3 PB.3 PD.3 PE.3 PF.3 TBR.3 INX.3 DPL.3 PPULL
IET0 IRQT0 TM0.2 BTM.2 TL0.2 TH0.2 BTL.2 BTH.2 PA.2 PB.2 PD.2 PE.2 PF.2 TBR.2 INX.2 DPL.2 DPM.2 DPH.2
IEBT IRQBT TM0.1 BTM.1 TL0.1 TH0.1 BTL.1 BTH.1 PA.1 PB.1 PD.1 PE.1 PF.1 TBR.1 INX.1 DPL.1 DPM.1 DPH.1
IRQP TM0.0 BTM.0 TL0.0 TH0.0 BTL.0 BTH.0 PA.0 PB.0 PD.0 PE.0 PF.0 TBR.0 INX.0 DPL.0 DPM.0 DPH.0
Remarks
Interrupt enable flags Interrupt request flags Timer0 Mode register (TM0) Bit3: RESET0 causes system reset RESET1 causes system reset HVL: Switch Base Timer into heavy load mode Base timer mode register (BTM) Timer0 load/counter register nibble Timer0 load/counter register high nibble Base Timer load/counter register nibble Base Timer load/counter register high nibble PORTA PORTB
Power
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100
Reserved. Always keep User's program. Refer notice.
PORTD PORTE PORTF Table Branch Register Pseudo index register Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit0: PA.1, PA.2 Alarm Bit1: Alarm carrier frequency select Bit2: display Bit3: Port pull-up control Bonding option CS1, CS0: display segment selection Bit2 reserved. Must User's program always kept Bit3 reserved. Always keep User's program. Data table address data register Data table address data register Data table address data register Data table address data register PORTA output PORTB output
RDT.1 RDT.5 RDT.9 RDT.13
RDT.0 RDT.4 RDT.8 RDT.12
0000
RDT.3 RDT.7 RDT.11 RDT.15
RDT.2 RDT.6 RDT.10 RDT.14
PA3OUT PA2OUT PA1OUT PA0OUT PB3OUT PB2OUT PB1OUT PB0OUT AEC3 AEC2 AEC1 AEC0
0000 0000 0000 0000
Reserved. Must User's program always kept Refer notice.
Alarm Envelope Control Reserved
SH67L18A
Configuration System Register (continued): Address
Remarks
Power
PFOUT
PEOUT
PDOUT
PORTD, output Bit3: Watchdog timer reset/flag (write reset WDT) Bit1 Bank register Bit2 reserved. Always keep User's program.
1000
BNK1
BNK0
-000
SH67L18A
System Register $14H Address Remark Power-on
Bit0: Bonding option internal weak drive Bit1: Bonding option internal weak drive Bit2: Reserved Bit3: Reserved bond bond bond bond Select display segments Select display segments segment PORTE Select display segments segment PORTD segment PORTE
Must User's program Always kept User's program
0000
SH67L18A Bonding Option
different bonding options possible user's needs. chip's program different program flows that will vary depending which bonding option used. readable contents will differ depending bonding.
SH67L18A
System Register $13H Address Remark Power
PPULL
Bit0: PA.1, PA.2 ALARM output Bit1: Alarm carrier frequency select Bit2: display Bit3: Port Pull-up Control PORTA.1, PORTA.2 port PORTA.1, PORTA.2 ALARM output Alarm carrier frequency Alarm carrier frequency Control display Control display Port pull-up disable Port pull-up enable
0100
System Register $15H $18H (ROM table register: RDT) Address Remarks Power
RDT.3 RDT.7 RDT.11 RDT.15
RDT.2 RDT.6 RDT.10 RDT.14
RDT.1 RDT.5 RDT.9 RDT.13
RDT.0 RDT.4 RDT.8 RDT.12
Data table address data register Data table address data register Data table address data register Data table address data register
0000 0000 0000 0000
register consists 14-bit write-only address load register (RDT.13 RDT.0) 16-bit read-only table data read-out register (RDT.15 RDT.0). read table data, users should write table address register first (high nibble first then nibble), then after instruction, right data will into register automatically (write lowest nibble address into will start data read-out action). Programmer 16-bit data into address data allocation instruction "DW". (Reference UASM66 Cross Assembler User's guide)
SH67L18A
System Register $1CH: Address Remark Power
AEC3
AEC2
AEC1
AEC0
ALARM envelope control envelope envelope envelope envelope envelope
0000
Default carrier frequency 4KHz. selected 2KHz system register ($13H, bit1) activate ALARM function, first switch ALARM OUTPUT mode select carrier frequency. After setting equal proper envelope. When data writes into AEC, envelope counter will synchronized same time. programmer read back envelope from register make pattern changes needed. Read operation will affect alarm output waveform. programming alarm waveform shown below:
OUTPUT
Notice: Normally, Alarm carrier clock comes from Base Timer clock source condition code option When system clock selected 32.768KHZ(Crystal) code option (10), Alarm carrier clock will selected from system clock. When system clock selected 200KHz (RC) code option (11), Alarm carrier clock will also selected from system clock.
SH67L18A
Driver
driver contains controller, voltage generator, common signal pads, segment driver pads (1/4 duty, bias). controller consists display data duty generator. data dual port that transfers data segment pads automatically without program control. SEG41 also used ports, selected bit1 bit0 system register $14. When SEG41 output port, users output
Configuration Area: (Segments 1/4duty) Address COM4 COM3 COM2 COM1
data writing data PORTD address $0B, $0C. used data memory needed. When "STOP" instruction executed, will turned off, data same before executing "STOP" instruction. When off, both COMMON SEGMENT output low.
Address
COM4
COM3
COM2
COM1
300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24
318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H 322H 323H 324H 325H 326H 327H 330H 331H 332H 333H 334H 335H 336H 337H
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48
SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48
SH67L18A
Connection Diagram:
1.5V
4.5V PANEL DUTY BIAS
CUP1 CUP2
(4.5V)
LOGIC CIRCUITS
(3.0V) (1.5V)
2200pF
0.1µF
Notice: pump circuit frequency 4KHz regardless option system clock. Normally, driver clock comes from Base Timer clock source condition code option 01). Thus display even STOP mode. When system clock selected 32.768KHZ (Crystal) code option (10), driver clock will selected from system clock. this case, will turned while "STOP" instruction executing. When system clock selected 200KHz (RC) code option (11), driver clock will also selected from system clock. this case, will turned while "STOP" instruction executing.
SH67L18A
System Register $13H: Address Remark Power
System Register $14H: Address
Bit2: display
Remark Bit2: Reserved. Must User's program.
Power
-000
Select display segments Select display segments segment PORTE Select display segments segment PORTD segment PORTE
Program Notice: Writing bit2 system register must under condition "LCD OFF". Otherwise will regarded illegal operation. Since pump circuits need more current while starting please confirm before turning Base Timer clock source oscillator condition code option (00). condition code option (01).
SH67L18A
Waveform
output waveform duty bias shown below.
Select COMX SEGX Select Light SEGX Unselect Unlight Unlight Unlight Unselect
Notice: frame frequency 65.1Hz under condition code option (11) because driver clock fetched from system clock (200KHz (FLCD (system clock/6)/512) frame frequency 64Hz under condition code option (10) because driver clock fetched from system clock (32.768KHz Crystal) (FLCD system clock/512) frame frequency 64Hz under condition code option because driver clock fetched from Base Timer clock source (32.768KHz Crystal 32KHz (FLCD Base Timer clock/512)
SH67L18A
Port
SH67L18A CMOS ports: PORTA, PORTB PORTF. Each pins contains pull-up controllable program. PORT control register (PAXOUT PBXOUT) controls ON/OFF buffer output buffer. These ports accessed read/write system register. users output value port time. PORTA,
register PULL PULL PMOS PULL PULL PMOS
PORT CONTROL REGISTER PORTA1, PORT DATA REGISTER
PORT CONTROL REGISTER PORT DATA REGISTER
PORTA0, PORTB
DATA INPUT
RD-INPUT
DATA INPUT
RD-INPUT
ALARM OUTPUT PORTA1, (for reference only) PORTA0, PORTB (for reference only)
When (system register $13H bit0), PA.1 PA.2 used alarm outputs.
CS1,CS0 register PULL PULL PMOS register PULL PULL PMOS
PORT CONTROL REGISTER PORTD, PORT DATA REGISTER
PORT CONTROL REGISTER PORTF PORT DATA REGISTER
DATA INPUT
RD-INPUT
DATA INPUT
RD-INPUT
SEGMENT PORTD, (for reference only)
COMMON PORTF (for reference only)
Since PORTD, shared with segment41 48,individually, when CS1& system register 01H, PD.0 PD.3 used seg41 When CS1& system register 00H, PD.0 PD.3 used seg41 PE.0 PE.3 seg45
Controlling Pull-up
These ports contain pull-up controlled program. System register $13H bit3 (PPULL) controls ON/OFF pull-up simultaneously. These Pull MOSs also controlled port data registers (PA, each port. (Write turn pull-up MOS.) pull-up turned ON/OFF individually.
Port Program Notice: user's program, necessary always keep bits system register "0". user's program, necessary always keep bits system register "1". After SH67L18A powered Reset pressed reset occurred, user's program must follow steps: 0AH, 0000B 1BH, 1111B 14H, 01xxB 1FH, x000B
SH67L18A
Port Interrupts
PORTB interrupts (falling edge) controlled Port register. means that interrupt request (IEx port high low) been touched that condition other input port bits high level.
External
PortA.0 shared external interrupt (active low).
SH67L18A
Timer
SH67L18A 8-bit timer count-up, consisting 8-bit counter 8-bit pre-loaded register. addition, other base timer provides real time clock function timekeeper. Timer0 provides following functions: Programmable interval timer Read counter value Interrupt overflow from Please follow these rules: Write Operation: nibble first High nibble update counter Read Operation: High nibble first nibble followed
Timer0 Configuration Operation: Timer0 consists 8-bit write-only timer load register (TL0L, TL0H), 8-bit read-only timer counter (TC0L, TC0H). counter load register both have order digit high order digit. Writing data into timer load register (TL0L, TL0H) initialize timer counter. Load register programming: low-order digit should written first, then high-order digit. timer counter automatically loaded with contents load register when high order digit written counter counts overflow from $00. Timer Load Register: Since register would control physical READ WRITE operations. Table Timer0 Mode Register ($02) TM0.2
Timer0 Interrupt: timer overflow will generate internal interrupt request, when counter counts overflow from $00. interrupt enable flag enabled, then timer interrupt service routine will start. This also used wake from HALT mode.
Timer0 programmed several different clock sources setting Timer Mode Register (TM0).
Timer0 Mode Register: Timer Mode Registers (TM0) 4-bit registers used timer control shown Table Mode Register selects input pulse sources timer.
TM0.1
TM0.0
Prescaler Divide Ratio
Clock Source
System clock System clock System clock System clock System clock System clock System clock System clock
SH67L18A
Base Timer Configuration Operation:
Base timer generates different frequency interrupts real time clock based value register BTM, shown Table heavy load register, HVL, used switch 32.768K Crystal oscillator into heavy load mode that makes oscillation easier startup period more current needed.
Table Base Timer Mode Register ($03) BTM.2
BTM.1
BTM.0
Interrupt Period
Stop (initial) 0.5Hz 16Hz 32Hz
Clock Source
32KHz 32KHz 32KHz 32KHz 32KHz 32KHz 32KHz 32KHz
achieve above interrupt periods, system register (BTL BTH) must both.
Notice: Please enable 32.768K oscillator before turning since clock comes from Base Timer clock source condition code option (00). condition code option (01).
example using Base Timer:
Initial (stop) (disable) (enable) (0.5 BTH, Warm BInterrupt? Warm Done
(reduce current)
Notice: Normally, condition code option 01), initial value Bregister 00H.It means that Base Timer controlled ON/OFF software writing BTM. Meanwhile, OSCI/OSCO (Crystal oscillator also turned ON/OFF this value. When system clock selected 32.768KHz (Crystal) code option (10), Bregister initial value 00H. means that Base Timer controlled ON/OFF software writing BTM. Bregister written system operation, device will stop 32.768KHz crystal oscillator. this case, clock source Alarm carrier driver will selected from system clock. When system clock selected 200KHz (RC) code option (11), Bregister initial value 00H. means that Base Timer controlled ON/OFF software writing BTM. Bregister written system operation, device will stop 200KHz oscillator. this case, clock source Alarm carrier driver will also selected from system clock.
SH67L18A
Interrupt
Four interrupt sources available SH67L18A:
External interrupt share with PA.0) Base time interrupt Timer0 interrupt Port's falling edge detection interrupt configuration system register $00H $01H: Address
IRQX
IET0 IRQT0
IEBT IRQBT
IRQP
Remarks
Interrupt enable flags Interrupt request flags
Interrupt request begins when IRQx this time, interrupt will activate vector address will commence from priority corresponding interrupt source. When interrupt occurs, flags will saved stack memory jump interrupt service vector address. After interrupt occurs, interrupt enable flags (IEx) automatically reset interrupt disabled. IRQx, which caused interrupt, must reset software interrupt service routine. When again, SH67L18A supply multi-level interrupts.
External Interrupt
External interrupt shared with bit0 PORTA. When bit3 system register (IEX) 1and PA.0 INPUT, external interrupt will enabled, falling edge signal PA.0 will generate external interrupt.
Base time Interrupt, Timer0 Interrupt, Port Interrupts
input clock Timer0 based clock. programming Timer interrupt, Port interrupts refer SH6610C SPEC.
Vector Address Interrupt Priority Priority
(Most) (Least)
Interrupt Source
RESET
TMR0
SH67L18A
Interrupt Servicing Sequence Diagram:
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
Interrupt Nesting: During SH6610C interrupt service, user enable INTERRUPT enabled flag before returning from interrupt. servicing sequence diagram shows next interrupt next nesting interrupt occurrences. interrupt request ready instruction execution enable, then interrupt will start immediately after next instruction executions. However, instruction instruction disables interrupt request enable flag, then interrupt service will terminated. System Clock Oscillation Circuit
system clock generator produces clock pulses supplied on-chip peripherals. Instruction cycle time 200KHz clock 32.768KHz clock
OSCXI 200K OSCI OSCO OSCO 200K OSCI OSCXI
Crystal
CODE OPTION
CODE OPTION
OSCXI
200K
OSCXI
OSCI Crystal OSCO
OSCI
OSCO
CODE OPTION
CODE OPTION
SH67L18A
HALT STOP After execution HALT instruction, SH67L18A will enter HALT mode. HALT mode, will stop operating, peripheral circuit (timer) will keep operating. After execution STOP instruction, SH67L18A will enter STOP mode. STOP mode, entire chip (including system oscillator) will stop operating. HALT mode, SH67L18A will wake interrupt occurs. STOP mode, SH67L18A will wake port interrupt occurs Binterrupt occurs. Notice: Normally, condition code option 01), 32.768KHz clock activated setting BTM.2-BTM.0, Base Timer keeps running even STOP mode. Thus, driver also output waveforms, since clock fetched from Base Timer clock source. condition code option 11), driver output waveforms STOP mode because it's clock source fetched from system clock. Either does Alarm carrier clock. this case, SH67L18A will wake only port interrupt occurs while STOP mode. Warm-up Timer
warm-up timer eliminates initial oscillation instability following cases: Power-on reset; Wake-up from STOP. warm-up timer will count system clock cycles when 32.768KHz crystal oscillator used system clock source. warm-up timer will count system clock cycles when 200KHz oscillator used system clock source. Software warm-up needed Base Timer start
Watch Timer
SH67L18A Watch-Dog-Timer. input clock watchdog timer fetched from system clock. will STOP mode. SH67L18A will generate RESET condition when Watchdog times-out. Watchdog enabled disabled permanently code option. prevent timing generating device RESET condition, users should write bit3 system register before timing-out. time-out period approx. 20ms (VDD 1.5V 200KHz oscillator). longer time-out periods desired, prescaler with division ratio 1:2048 assigned under software controlled writing register ($02).
System Register Address
Remark
Bit3: Watchdog timer reset/flag (write reset WDT)
0.02ms SYSTEM CLOCK 200KHz
Internal
SCALER_1
/1024
Time Period 20ms
PRESCALER
/128
/512
/2048
Final Time period
SH67L18A
Prescaler Divide Ratio: TM0.2
TM0.1
TM0.0
Prescaler divide ratio
1:32 1:128 1:512 1:2048 (Power initial)
Timer-out period
20.48ms 40.96ms 81.92ms 163.84ms 655.36ms 2,621ms 10,484ms 41,936ms
Notice:
enabled, code option, Watchdog Timer will cleared when Power-On initial. must cleared only Watchdog Timer time-out occurred both normal operation mode HALT mode. Watchdog Timer cleared when device wakes from STOP mode, regardless source wake-up.
Status Condition
Power-On reset cause reset during normal operation cause reset HALT mode reset during normal operation HALT mode reset interrupt wake-up STOP mode
Condition
Program Notice: system clock changed code option, time-out period Watchdog Timer (approx. 20ms) will also changed, regardless value prescaler divide ratio. prescaler with division ratio 1:2048 prolong time-out periods writing register. Since register shared with Timer0, same prescaler value Timer0. changed some proper use, WDT's time-out periods will also changed.
SH67L18A
Instructions
instructions cycle one-word instructions. characteristics memory-oriented operation. Arithmetic Logical Instruction
Accumulator Type Mnemonic
ADCM ADDM SBCM SUBM EORM ANDM
Instruction Code
00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000
Function
Flag Change
[3]; shift right
Immediate Type Mnemonic
ADIM SBIM EORIM ORIM ANDIM
Instruction Code
01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx
Function
Flag Change
assembler ASM66 V1.0, EORIM mnemonic EORI. However, EORI same operation identical with EORIM. Same ORIM with respect ORI, ANDIM with respect ANDI.
Decimal Adjust Mnemonic
Instruction Code
11001 0110 xxxx 11001 1010 xxxx
Function
Decimal adjust add. Decimal adjust sub.
Flag Change
SH67L18A
Transfer Instruction Mnemonic
Instruction Code
00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx
Function
Flag Change
Control Instruction Mnemonic
CALL RTNW RTNI HALT STOP TJMP
Instruction Code
10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111
Function (Not include hhhh; llll
Flag Change
(Include (PC11-PC8) (TBR) (AC)
Operation
Where,
Program counter Accumulator Complement accumulator Carry flag Data memory page Stack Table Branch Register Immediate data Logical exclusive Logical Logical bank (bbb: 111)
(bbb)
SH67L18A
Absolute Maximum Ratings*
Supply Voltage -0.3V +3.0V Input Voltage .-0.3V 0.3V Operating Ambient Temperature +70°C Storage Temperature -55°C +125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposed absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 1.5V, 25°C, FOSC 200KHz, unless otherwise specified) Parameter
Operating Voltage Operating Current Standby Current Standby Current Reset Current Lighting Input High Voltage Input High Voltage Input Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Pull-up Resistor RESET Pull-up Resistor RESET Pull-up Resistor
Symbol
ISB1 ISB2 IREST ILCD VIH1 VIH2 VIL1 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4
Min.
Typ.
Max.
Unit
Conditions
output pins unload execute instruction, exclude Basetimer, Alarm current output pins unload (HALT mode) exclude Basetimer, Alarm current output pins unload (STOP mode), off, Alarm off, Basetimer clock Chip current when RESET0 available panel loaded. pump frequency PORTA, PORTB, PORTC OSCI (Driven external clock) (reference only) RESET TEST (schmitt trigger input) PORTA, PORTB, PORTC OSCI (Driven external clock) (reference only) RESET TEST (schmitt trigger input) PORTA, (IOH 0.3mA) PORTA, (IOL 0.3mA) (set PA.1and PA.2 ALARM output), 0.3mA (set PA.1and PA.2 ALARM output), 0.3mA SEGx, -6µA SEGx, COMx, -12µA COMx, 12µA PORT Pull-up resistor (VOH -10µA) RESET RESET1 level trigger option RESET RESET1 edge trigger option
0.85
0.15
1000
SH67L18A
Electrical Characteristics (VDD 1.5V, 25°C, FOSC 32.768KHz, unless otherwise specified) Parameter
Operating Voltage Operating Current Standby Current Standby Current Lighting Input High Voltage Input High Voltage Input Voltage Input Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Pull-up Resistor
Symbol
ISB1 ISB2 ILCD VIH1 VIH2 VIL1 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4
Min.
Typ.
Max.
Unit
Conditions
output pins unload execute instruction, exclude Alarm current output pins unload (HALT mode) exclude current. (Not heavy load mode) output pins unload (STOP mode), off, current panel loaded. pump frequency PORTA, PORTB, PORTC OSCI (Driven external clock) (reference only) RESET TEST (schmitt trigger input) PORTA, PORTB, PORTC OSCI (Driven external clock) (reference only) RESET TEST (schmitt trigger input) PORTA, (IOH 0.3mA) PORTA, (IOL 0.3mA) (set PA.1and PA.2 ALARM output), 0.3mA (set PA.1and PA.2 ALARM output), 0.3mA SEGx, -6µA SEGx, COMx, -12µA COMx, 12µA PORT Pull-up resistor (VOH -10µA)
0.85
0.15
Electrical Characteristics (VDD 1.5V, 25°C, FOSC 200KHz, unless otherwise specified) Parameter
Frequency Variation
Symbol
Min.
Typ.
Max.
Unit
Conditions
Include supply voltage chip chip variations
SH67L18A
Typical Oscillator Resistor Frequency: (Reference only)
1.5V
Frequency (KHz) 1.5V
Resistor (Kohm)
SH67L18A
Code Option:
Addresses: $4000 Body data: 0110 1010 0001 1000 (6A18) Addresses: $4001 Data: CKWR 1000 0000 0000 (System Clock selection)
Code
Connection
OSCI/OSCO
32KHz Crystal 32KHz 32KHz Crystal
OSCXI
200KHz 200KHz 200KHz
Where: (default) 200KHz system clock with 32.768KHz (Crystal) Basetimer 200KHz system clock with 32KHz (RC) Basetimer 32.768KHz Crystal system clock (The Basetimer clock source will fetched from system clock used.) 200KHz system clock (The Basetimer clock source will fetched from system clock used.)
(Watch control) (Reset triggering selection)
Code
Descriotion
enable (default) disable RESET level triggering (low active) (default) RESET edge triggering (falling edge)
SH67L18A
Application Circuits (for reference only)
SH67L18A chip substrate connects system ground.
AP1: 1.5V OSC: 200KHz Base timer: 32KHz LCD: 4.5V, duty, bias PORTB I/O; PORTA.1, Buzzer output.
2200pF 0.1µF CUP1, PORTA.1 PORTA.2 BUZZER
PORTF RESET1 470Khom OSCXI 1.8Mhom OSCO OSCI TEST RESET0 PORTB
SH67L18A
SH67L18A
AP2: 1.5V OSC: 200KHz Base timer: 32KHz Crystal LCD: 4.5V, duty, bias PORTB I/O; PORTA.1, Buzzer output.
2200pF 0.1µF CUP1, PORTA.1 PORTA.2 BUZZER
PORTD PORTE RESET1 RESET0 PORTB OSCXI OSCI 12pFx2 X'tal OSCO TEST PORTF
SH67L18A
SH67L18A
Bonding Diagram:
SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 PORTD0 SEG42 PORTD1 SEG43 PORTD2 SEG44 PORTD3 SEG45 PORTE0 SEG46 PORTE1
SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM1 COM2 COM3 COM4 PORTF0 PORTF1 PORTF2 PORTF3 CUP1
SH67L18A
2646
(0,0)
3220
Substrate connects
Location
unit:
Designation
[47] [48] PORTB3 PORTB2 PORTB1 PORTB0 PORTA3 PORTA2 PORTA1 PORTA0 RESET1
-1410 -1280 -1160 -1040 -920 -805 -690 -575 -460 -345 -230 -115
-1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5 -1157.5 -1252.5 -1252.5 -1252.5 -1252.5 -1252.5
Designation
OSCXI CUP2 CUP1 PORTF3 PORTF2 PORTF1 PORTF0
1040 1160 1280 1410 1540 1540 1540 1540 1540 1540 1540 1540 1540 1540 1540 1540 1540 1540 1540
-1252.5 -1157.5 -1252.5 -1252.5 -1252.5 -1177.5 -1032.5 -892.5 -752.5 -632.5 -517.5 -402.5 -287.5 -172.5 -57.5 57.5 172.5 287.5 402.5 517.5
RESET0 TEST
OSCI OSCO
SH67L18A
Location (continued)
Designation
(GND) (VDD)
1540 1540 1540 1540 1540 1540 1410 1040 1280 1160 1040 -115 -230 -345 -460 -575 -690 -805
632.5 752.5 872.5 992.5 1122.5 1252.5 1252.5 -1252.2 -1252.2 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1252.5
Designation
[28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46]
-920 -1040 -1160 -1280 -1410 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540 -1540
1252.5 1252.5 1252.5 1252.5 1252.5 1252.5 1122.5 992.5 872.5 752.5 632.5 517.5 402.5 287.5 172.5 57.5 -57.5 -172.5 -287.5 -402.5 -517.5 -632.5 -752.5 -872.5 -992.5 -1122.5 -1252.5
[10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
SH67L18A
Ordering Information
Part
SH67L18AH
Package
CHIP FORM
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