4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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SH66P14
4-bit Microcontroller with Driver
SH6610C-based single-chip 4-bit microcontroller ROM: 4096 bits RAM: bits (System Data memory) Operation voltage: 2.5V 6.0V CMOS bi-directional pins 4-Level subroutine nesting (include interrupts) 8-bit auto re-load timer/counter 8-bit Base timer Powerful interrupt sources: External interrupts INT0 Internal interrupt (Timer0) Internal interrupt (Base Timer) Port's falling edge interrupt: PORTB INT1 driver: dots (1/8 duty bias) dots (1/4 duty bias) used scan output Built-in dual tone with noise generator Clock source OSC: (code option) Crystal oscillator 32.768K oscillator: 262K OSCX: (system register select) Ceramic oscillator 455K oscillator 1.8M Instruction cycle time: 122.07µs 32.768 crystal 15.27µs 8.79µs 455KHz ceramic 2.22µs power operation mode: HALT STOP power consumption Warm timer power reset
General Description
SH66P14 single chip microcontroller integrated with SRAM, ROM, Timer Dual-tone PSG, driver port. This chip builds dual-oscillator enhance total chip performance.
Configuration
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 COM6 COM5 COM4 COM3 COM2 COM1 OSCI OSCO OSCXO OSCXI
SH66P14
V1.0
SH66P14
Configuration
COM8 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18
RESET TEST VLCD SEG1 SEG2
SH66P14
Block Diagram
(4096 (512 SH6610C CORE OSCS 8-BIT TIMER0 PORTB
OSCI OSCO OSCXI OSCXO PORTB [0:3] PA.0 (INT0) PA.1 (PSG PA.2 (PSG) PA.3 [1:8]
PORTA EXTERNAL
RESET
COMMON DRIVER SEGMENT
DRIVER SCAN REGISTER
[1:34]
OPERATING VOLTAGE VOLTAGE GENERATOR
SH66P14
Description
Designation SEG1 SEG30 VLCD, TEST RESET Port Port Description Segment signal output display; Share with scan output Connect with external divided resistance Test (Internal pull-low). connect user Reset input internal pull-up) Power supply programmable I/O, Vector interrupt INT1 programmable I/O, PA.0 shared with INT0 PA.1, PA.2shared with output program mode, PA.1 shared with DATA, shared with PINPGMB, shared with PINOE Oscillator input Oscillator output Ground Oscillator output Oscillator input Common signal output display Common/segment signal output display
Port Port
OSCXI OSCXO OSCO OSCI COM1 COM4 COM5 COM8/SEG34 SEG31
Description
Designation Description Segment signal output display; share with scan output Segment signal output display; share with scan output Connect with external divided resistance Test (Internal pull-low). connect user Reset input internal pull-up) Power supply programmable I/O, Vector interrupt INT1 programmable I/O, PA.0 shared with INT0 PA.1, PA.2 shared with output program mode, PA.1 shared with DATA, shared with PINPGMB, shared with PINOE Oscillator input Oscillator output Ground Oscillator output Oscillator input Common signal output display Common/segment signal output display
SEG17 SEG1 SEG30 SEG18 VLCD, TEST RESET Port Port Port Port OSCXI OSCXO OSCO OSCI COM1 COM4 COM5 COM8/SEG34 SEG31
SH66P14
Functional Description
contains following function blocks: Program Counter, Arithmetic Logic Unit (ALU), Carry Flag, Accumulator, Table Branch Register, Data Pointer (INX, DPH, DPM, DPL), Stack. (Program Counter) Program Counter used address program ROM. consists 12-bits: Page Register (PC11), Ripple Carry Counter (PC10, PC9, PC8, PC7, PC6, PC5, PC4, PC3, PC2, PC1, PC0). program counter normally increases (+1) with every execution instruction except following cases: When executing jump instruction (such JMP, BA0, BAC); When executing subroutine call instruction (CALL); When interrupt occurs; When chip INITIAL RESET mode. program counter loaded with data corresponding each instruction. unconditional jump instruction (JMP) 1-bit page register higher than performs arithmetic logic operations. provides following functions: Binary addition/subtraction (ADC, SBC, ADD, SUB, ADI, SBI) Decimal adjustment addition/subtraction (DAA, DAS) Logic operations (AND, EOR, ANDIM, EORIM, ORIM) Decision (BA0, BA1, BA2, BA3, BAZ, Logic Shift (SHR) Carry Flag (CY) holds overflow, which arithmetic operation generates. During interrupt service call instruction, carry flag pushed into stack restored back from stack RTNI instruction. unaffected RTNW instruction. Accumulator Accumulator 4-bit register holding results arithmetic logic unit. conjunction with ALU, data transfers between accumulator system register, RAM, data memory performed. Stack group registers used save contents (10-0) sequentially with each subroutine call interrupt. organized bits levels. saved levels maximum allowed total subroutine calls interrupts. contents Stack returned sequentially with return instructions (RTNI/RTNW). Stack operated first-in, last-out basis. This 4-level nesting includes both subroutine calls interrupts requests. Note that program execution enter abnormal state number calls interrupt requests exceeds bottom stack will shifted out.
address 4096 words bits program area from $000 $FFF. Vector Address Area ($000 $004) program sequentially executed. There area address $000 through $004 that reserved special interrupt service routine such starting vector address. Address $000H $001H $002H $003H $004H Instruction Instruction Instruction Instruction Instruction Instruction Function Jump RESET service routine Jump INT0 service routine Jump Timer0 service routine Jump Base Timer service routine Jump INT1 service routine
Table Data Reference Table Data stored program memory referenced using Table Branch (TJMP) Return Constant (RTNW) instructions. Table Branch Register (TBR) Accumulator (AC) placed offset address program ROM. TJMP instruction branches into address ((PC11 PC8) (TBR, AC)). address determined RTNW return look-up value into (TBR, AC). code bit7-bit4 placed into bit3-bit0 into
SH66P14
Built-in SRAM contains general-purpose data memory, RAM, system registers. They directly accessed instruction cycle. Because static nature, keep data after enters STOP HALT. Data memory, RAM, System register following memory allocation map: $000 $01F: System register $020 $1FF: Data memory (480 4bits, divided into banks). $300 $321, $328 $345, $350 $36D: space bits bits). Data Pointer Data Pointer indirectly address data memory. Pointer address located register (3-bits) (4-bits). addressing range have locations. Pseudo index address (INX) used read write Data memory, then address bit9-bit0 comes from DPH, DPL. Configuration System Register Address Bit3 IRQX TM0.3 BTM.3 T0L.3 T0H.3 PA.3 PB.3 PACR.3 PBCR.3 LPD3 TBR.3 INX.3 DPL3 PPULL Bit2 IET0 IRQT0 TM0.2 BTM.2 T0L.2 T0H.2 PA.2 PB.2 PACR.2 PBCR.2 LPD2 TBR.2 INX.2 DPL2 DPM.2 DPH.2 PAM2 Bit1 IEBT IRQBT TM0.1 BTM.1 T0L.1 T0H.1 PA.1 PB.1 PC.1 PACR.1 PBCR.1 LPD1 TBR.1 INX1 DPL1 DPM.1 DPH.1 PAM1 Bit0 IRQP TM0.0 BTM.0 T0L.0 T0H.0 PA.0 PB.0 PC.0 PACR.0 PBCR.0 LPD0 TBR.0 INX.0 DPL0 DPM.0 DPH.0 Function Interrupt enable flags Interrupt request flags Timer0 mode register Base timer mode register Timer0 load/counter nibble Timer0 load/counter high nibble Reserved PORTA PORTB Bonding option PORTA output port PORTB output port Enable Control (LPD3 0101: Enable (Default); 1010: Disable Table branch register Index register (INX) Data pointer nibble Data pointer middle nibble Data pointer high nibble Bit1, PA.1 PA.2 output PORT Bit0: Heavy load mode Bit3: Port pull-up control Bit0: Turn OSCX oscillator Bit1: clocks select OSCX/0: OSC) Bit3: OSCX type selection Initial Value 0000 0000 0000 0000 0000 0000 0000 0000 (default) 0000 0000 0101 0000 0000 0000 0000 0000 0000
OXON
0000
SH66P14
Initial Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Address
Bit3
Bit2
Bit1
Bit0
Function Bit0: Select DUTY (1/8 1/4) Bit1: Bit2, frequency control Bit2: segment output Bit3: Power degrade channel nibble channel 1high nibble Bit3: channel octave shift control channel nibble alarm output channel nibble channel nibble channel nibble Bit3: channel octave shift control Bit0, Bit1: Channel enable Bit2, Bit3: volume control Bit0, PSG1, PSG2 mode control Bit2, PSG1, PSG2 clock source selection Reserved
LPS1 C1.3 OCT1 C2.3 C2.7 C2.11 OCT2 VOL1 SEL1
LPS0 C1.2 C1.6 C2.2 C2.6 C2.10 C2.14 VOL0 SEL0
LCDOFF C1.1 C1.5 C2.1 C2.5 C2.9 C2.13 CH2EN
DUTY C1.0 C1.4 C2.0 C2.4 C2.8 C2.12 CH1EN
SH66P14
Oscillator circuit Circuit Configuration SH66P14 on-chip oscillation circuits OSCX. frequency crystal (Typ. 32.768KHz) (Typ.262KHz) determined code option. This designed frequency operation. OSCX also types: ceramic (Typ.455KHz) (1.8M 2MHz) determined software option. designed high frequency operation. possible select high speed processing high frequency clock select power operation operation clock. starting reset initialization, starts oscillation OSCX turned off. Immediately after reset initialization, clock automatically selected system clock input source.
OSCI Frequency OSCO Clock Oscillator System clock Source Selector OSCXI OSCXO High Frequency Clock Oscillator Switching control System clock Generator Clock Base Timer
Figure Oscillator Block Diagram
Figure Timing system Clock Switching oscillation generates basic clock pulses that provide peripherals (Timer0, LCD) with operating clock. Crystal oscillator type
STOP OSCI
32768Hz OSCO
5-6p
SH66P14
oscillator type
RBIAS STOP
OSCI
Ring Oscllator
OSCO
OSCX oscillation OSCX clock oscillators. software options select ceramic CPU's clock. OSCX Ceramic oscillator type
CPUSTOP
OSCXI
455KHz Ceramic OSCXO
OSCX oscillator type OSCX used, must masked Ceramic resonator OSCXI must connected GND.
CPUSTOP
RBIAS
OSCI
Ring Oscllator
OSCO
Control oscillator oscillator control register configuration shown blow. Address Bit3 Bit2 Bit1 Bit0 OXON
OXON: OSCX oscillation on/off. 0:Turn OSCX oscillation 1:Turn OSCX oscillation OXM: switching system clock. 0:select system clock 1:select OSCX system clock OXS: OSCX oscillator type selection 0:OSCX ceramic oscillator 1:OSCX oscillator
Programming notes takes least OSCX oscillation circuit until oscillation stabilizes. When switching system clock from OSCX, must wait minimum till OSCX oscillation active. However, start time varies with respect oscillator characteristics operational conditions. Therefore waiting time depends applications. When switching from OSCX OSC, turning OSCX instruction, OSCX turn control would delayed instruction cycle automatically prevent operation error.
SH66P14
System clock system clock varies clock source changes. following table shows instruction execution time according each frequency system clock source. 32.768 Xtal (OSC Cycle time PORT provides 8-bidirectional pins. Each contains pull-up controllable program. When used input, PORT control register (PACR, PBCR) controls ON/OFF output buffer. PORTA These ports contain 8-bidirectional ports. circuit configuration PORTA shown below.
PULLUP
262K (OSC 17.778
455K ceramic Xtal (OSCX) 8.79
1.8M (OSCX) 2.22
(OSCX)
122.07
PULL_UP PMOS
PORT CONTROL REGISTER PORTX PORT DATA REGISTER
DATAINPUT RD_INPUT
ports SH66P14 accessed read/write system register. User output value port time. Bit3 PMOD register controls On/Off pull-ups simultaneously. Pull-up also controlled port data registers (PA, each port also. pull-up turned On/Off. Memory addresses listed follow: Address Port control register: Address Bit3 PACR.3 PBCR.3 Bit2 PACR.2 PBCR.2 Bit1 PACR.1 PBCR.1 Bit0 PACR.0 PBCR.0 Bit3 PORTA.3 PORTB.3 Bit2 PORTA.2 PORTB.2 Bit1 PORTA.1 PORTB.1 Bit0 PORTA.0 PORTB.0
control register: PACR.X, PBCR.X output buffer. input buffer (Power initial). Port mode register (PMOD) Address Bit3 PPULL Bit2 PAM2 Bit1 PAM1 Bit0 Function Bit1, Select PA.1, PA.2 port output Bit0: Hevey load mode Bit3: Port pull-up control Enable Enable pull-up
PAM1, PAM2: HLM: PPULL:
Please sees Enable heavy load mode Disable Port pull-up Disable pull-up
SH66P14
Port Interrupt PORTB interrupt (falling edge) controlled Port register. means that interrupt request (IEx port high goes low) been activated touched conditions other port bits high level time port either output input. External PortA.0 shared external interrupts (active low). Heavy load mode (HLM) heavy load protection circuit when battery load becomes heavy. examples, when external buzzer sound external speaker turned this mode, crystal oscillator circuit been backed high gain. When setup this mode, more power would provided oscillator circuit. Unless necessary, careful this mode with software. Since mode enter would delay instruction, please activate heavy load driving least instruction wait cycle after setting through software. following shows programming setting. HLM: Heavy load protection mode released Heavy load protection mode set.
HEAVYLOAD
Instruction Cycle Time
Programmable sound generator (PSG) channel1 channel2. functional block diagram follows:
CHANNEL1 OSCX CHANNEL2 MIXER
function provides four subfunctions wide applications. Programmable sound Program sound created channels. Each channel programmed follows. Enable/Disable each channel sounds. Select each channel sound frequency. channel sounds mixed into output. output controlled volume levels. Fine noise provide wide-band noise. wide-band noise volume controlled volume levels. Alarm provide many alarm functions through software. alarm carrier frequency programmed individually. alarm volume controlled volume levels. Remote control remote control only expandable application sound. Since remote control frequency 56.13KHz 37.92KHz, software could select sound frequency.
SH66P14
subblock diagram SEL1 SEL0
SEL0 SEL1
source OSC/2 OSCX OSCX/16 32.768K 262K 32.768K 262K OSCX 1.8M OSCX 455K OSCX 1.8M OSCX 455K
32.768K 262K 16.384K 131K 1.8M 455K 112.5K 28.4K
CLK-SLECTOR
OSCX
Figure block diagram Channel
CH1EN SELECTOR DIVIDER OCT1 REGISTER C1.6 C1.0
block selects clock sources that provides channel sources.
OCT1 Channel
Scaling ratio
Channel constructed 7-bit pseudo random counter. Channel enabled/disabled CH1EN. creates either sound frequency alarm carrier frequency remote carrier frequency.
CH2EN OCT2 NOISE GENERATOR C2.14 C2.0 SELECTOR REGISTER C2.14 C2.0 C2.14 C2.8 DIVIDER SELECTOR
C2.3 C2.0 32Hz
ENEVLOP
ENEVLOP
OCT2
Scaling ratio
Channel constructed 15-bit pseudo random counter. Channel enabled/disabled CH2EN 15-bit wide-band noise generator 7-bit sound generator. also create alarm envelope signal.
SH66P14
Mixer Sound generator. Sound generator. Sound generator. Function Sound generator. Noise generator. Alarm mode register.
TIME SLOT
VOL0
VOL1 PA.1
PAM1 SELECTOR1 PA.1
TIME SLOT
CONTROL PA.2 PAM2 SELECTOR2 PA.2
MIXER mixes CH1-OUT CH2-OUT into single tone output PA.1 PA.2, when PAM1 1PAM2 Then tone output controlled volume control into volume levels outputted PSG. PA.1 PA.2 controlled PAM1 PAM2 PAM2 PAM1 PA.1: PORT. PA.2:I/O PORT PA.1: output. PA.2:I/O PORT PA.1: PORT. PA.2: output PA.1: output. PA.2: output Function
SEL1
SEL0
Vol. control
VOL1
VOL0
Vol. Level
Note: Don't enable channels together produce tone, will produce some unpredicted errors. necessary channels together (e.g. play different melodies from channels), don't score always same tone then unpredicted errors will occur will ignore through user hearing.
SH66P14
value divider1 corresponding C1.6 C1.0 C2.14 C2.8 shown following table: LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8) LSFR (C1.6 C1.0) (C2.14 C2.8)
SH66P14
sound generator programmable sound working modes. software designer select clock sources clk. then select frequency divided value that controlled value C1.6 C1.0 C2.14 C2.8.In select volume level controlled VOL0, VOL1. music tone output both also control OCT1, OCT2 that shifts music tone octaves. Example1: CH1EN CH2EN OSCX 1.8M, SEL0 SEL1 112kHz; Switch 28kHz Vol. 112kHz Example2: CH1EN CH2EN OSCX 1.8M, SEL0 SEL1 112kHz; Switch 28kHz; Vol. 112kHz
Example3: CH1EN CH2EN 32k, SEL0 SEL1 32kHz; Switch 32kHz vol. control, level hardware, software should VOL0 VOL1
Note: 32KHz operations, volume control cannot used, because multiplexing frequency high enough switch sound! user wants turn completely, software must disable both channels. User should turn zero wave from output. Both CH1EN CH2EN should power operation mode. Example software designer wants create (channel mixed with (channel sound (the sound frequency, please Music table1 Music table2), level 3.He select suggestion follows. Select CH1EN CH2EN Select OSCX 1.8M SEL0 SEL1 112.5KHz. Select OCT1 value channel LSFR (C1.6 C1.0) 108. Please Music table1.So channel sound frequency 112.5Khz/8/(2 108) 64.10Hz sound frequency. Select OCT1 value channel LSFR (C1.6 C1.0) Please Music table1.So channel sound frequency 112.5Khz/1/(2 694.4Hz sound frequency Lastly, select VOL1 VOL0 level Note: designer provides crossing tables appendix that what designer prefers 32.768K 112.5K. noise generator fine noise created CH2. want create single noise, make music tone output. Otherwise wide-band noise music tone into single output through MIXER. Lastly select volume levels controlled VOL0, VOL1.
SH66P14
alarm generator When alarm mode, provides alarm carrier frequency provides alarm envelope signal. Lastly select volume levels controlled VOL0, VOL1. channel nibble C2.0 C2.3 will alarm control register. Channel output would modulate with ALARM envelope control 32KHz 262KHz. carrier frequency programmed channel 1.In reading this alarm control register, read corresponding output envelope frequency (the 1Hz, 4Hz, 8Hz, 32Hz). Alarm control register (OSC 32KHz 262KHz) C2.3 C2.2 C2.1 C2.0 Alarm output control envelop output output output 32Hz output
Figure Alarm modulation output 32.768KHz 262KHz. remote control remote control only expandable application sound. select tone output will create alarm frequency envelope signal. When channel programmed ALARM mode. Programmer ALARM mode register "0000B". Program adequate frequency output output. Then PAM1 PAM2 control envelope code. this way, remote control function implemented easily. remote frequency 56.73KHz 37.92KHz. software should select OSCX 455KHz, SEL0 that 455KHz. Then select channel alarm mode (C1M OCT1 C2.0 C2.3 00H. VOL1, VOL2 Then select C1.6 C1.0 that output frequency 455KHz/1/(2 37.92KHz. select C1.6 C1.0 that output frequency 455KHz/1/(2 56.87KHz.
SH66P14
Timer SH66P14 8-bit timer. timer consists 8-bit counter 8-bit preload register. timers provide following functions: 8-bit up-counting timer/counter. Automatic re-loads counter. 8-bit prescaler. Interrupt overflow from $00. Configuration Operation Timer-0 consists 8-bit write-only timer load register (TL0L, TL0H), 8-bit read-only timer counter (TC0L, TC0H). counter load register both have order digit high order digit. Writing data into timer load register (TL0L, TL0H) initialize timer counter. Load register programming: low-order digit should written first, then high-order digit. timer counter automatically loaded with contents load register when high order digit written counter counts overflow from $00. Timer Load Register: Since register would control physical READ WRITE operations. Please follow these rules: Write Operation: nibble first High nibble update counter Read Operation: High nibble first; nibble followed.
Load Reg.
Load Reg.
8-bit timer counter Latch Reg.
Figure Timer Load register Configure Timer0 Interrupt timer overflow will generate internal interrupt request, when counter counts overflow from $00. interrupt enable flag enabled, then timer interrupt service routine will start. This also used wake from HALT mode.
Timer0 mode register (TM0) 8-bit counter prescaler overflow output pulses. 4-bit registers used timer control shown Table1. register selects input clock sources timer. Table Timer0 Mode registers ($02) TM0.3 TM0.2 TM0.1 TM0.0 Prescaler /2048 /512 /128 External Auto-Reload function Clock Source System clock System clock System clock System clock System clock System clock System clock INT0
TM0.3 control function: without Auto-Reload function
SH66P14
Base Timer base timer that shared with warm-up timer clock source (Low frequency oscillation: Crystal 32.768KHz 262KHz). After reset, counts every clock-input signal. When counts $FF, right after next clock input, counter counts generates overflow. This causes interrupt base timer interrupt request flag 1.Therefore, base timer function interval timer periodically, generating overflow output every 256th clock signal output. timer accepts 4096Hz 32KHz clock, base timer generates accurate timing interrupt. This base time prescaler reset program accurate timing. This clock-input source sleeted Bregister. Address Bit3 BTM.3 Bit2 BTM.2 Bit1 BTM.1 Bit0 BTM.0 Function Base timer mode register
BTM.3 Disable base timer BTM.2 reset base timer BTM.1 BTM.0
BTM.3 Enable base timer BTM.2 reset base timer Prescaler Ratio Clock source 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz 4096Hz 32KHz
BTM[3]
base timer counter reset
262k 4096/32K
BTM[2]
4Bit Scaler
SH66P14
Driver driver contains controller, voltage generator, common signal pins segment driver pins. There different driving modes programmable: duty bias, other duty bias. driving mode controlled system register power initialization status duty, bias. When duty bias mode used, COM5 used SEG34 SEG1 also used output port, selected system register $16. When SEG1 output port, writes data same addresses (350H-36DH). could used data memory needed. When "STOP" instruction executed, will turned off, data keeps same value before executing "STOP" instruction. Control Register Address. LCDOFF: LPS1 LPS0 LCDOFF DUTY
on/off switch. off. DUTY: duty control duty, bias duty, bias LPS1, LPS0: clock frequency control 0,0: LCDCLK OSC/64 0,1: LCDCLK OSC/512 1,0: LCDCLK System clock/512 1,1: LCDCLK System clock/4096 System clock Instruction cycle time Frame frequency LCDCLK/16 Frame frequency duty; duty same frequency cycle. Frequency 32kHz (#), 32kHz, 32kHz (#), 32kHz, 32kHz(#), 32kHz, 262kHz (#), 262kHz, 262kHz (#), 262kHz 262kHz (#), 262kHz OSCX 455kHz OSCX 455kHz OSCX 1.8MHz OSCX 1.8MHz OSCX 2MHz OSCX 2MHz OSCX 455kHz OSCX 455kHz OSCX 1.8MHz OSCX 1.8MHz OSCX 2MHz OSCX 2MHz LPS1, LPS0 32Hz 32Hz 32Hz 32Hz 32Hz 32Hz 256Hz 256Hz 256Hz 256Hz 256Hz 256Hz 32Hz 32Hz 32Hz 32Hz 32Hz 32Hz 14Hz 55Hz 61Hz 14Hz 55Hz 61Hz 1/8Hz 1.7Hz 1/8Hz 6.9Hz 1/8Hz 7.6Hz 1.7Hz 6.9Hz 7.6Hz
before sleeted system clk. Frame frequency LCDCLK/16 (32Hz) When SCAN OUT, COMx pulled high. easy implement keyboard scan. When STOP mode, COMx SEGx pulled low. easily waken keyboard scan (Port interrupt). When HALT mode, COMx SEGx normal. easily waken base timer timer0 port interrupt.
SH66P14
power
LCDOFF Power Switch Power Supply Control Circuit seg1 segment driver
common driver
com1 com8
LPS0 SYSCLK/512 LPS1 OSC/64
Scaler
LCDCLK
DUTY
scan output
seg34
Figure block diagram reference only Build-in special power control power modulation. Address
O/S: segment/common segment output output ports segment output output ports. When voltage power would degraded about 0.5V, depending level. designed reduce extra contrast control output pins. Then fitted automatically different voltage levels software. Configuration duty, bias (COM1 SEG1 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH 31EH 31FH 320H 321H Address Bit3 COM4 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit2 COM3 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit1 COM2 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 Bit0 COM1 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
SH66P14
duty, bias (COM1 SEG1 Address 300H 301H 302H 303H 304H 305H 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H 313H 314H 315H 316H 317H 318H 319H 31AH 31BH 31CH 31DH Bit3 COM4 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM3 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM2 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM1 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 328H 329H 32AH 32BH 32CH 32DH 32EH 32FH 330H 331H 332H 333H 334H 335H 336H 337H 338H 339H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H Address Bit3 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit2 COM7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit1 COM6 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Bit0 COM5 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
SEG1 used scan output port. Address 350H 351H 352H 353H 354H 355H 356H 357H Bit0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 Address 358H 359H 35AH 35BH 35CH 35DH 35EH 35FH Bit0 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 Address 360H 361H 362H 363H 364H 365H 366H 367H Bit0 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 Address 368H 369H 36AH 36BH 36CH 36DH Bit0 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30
SH66P14
waveform
DUTY BIAS SELECT UNSELECT VLCD SELECT UNSELECT VLCD SELECT UNSELECT VLCD DUTY BIAS SELECT UNSELECT VLCD
Example Duty Bias
VLCD
COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG1 SEG30 FRAME CYCLE
This example SEG1 SEG30 COM1, COM3, COM5, COM7 lighted. SEG1 -SEG30 COM2, COM4, COM6, COM8 lighted.
SH66P14
Interrupt interrupt sources available SH66P14: External interrupt INT0 Timer0 interrupt Base timer interrupt Port's falling edge detection interrupt( INT1 configuration system register Address IRQX IET0 IRQT0 IEBT IRQBT IRQP Function Enable/0: Disable Request/0: request
External Interrupt INT0 External interrupt shared with PA.0, falling edge active. When register (IEX) external interrupt enabled, writing PA.0 will generate external interrupt. Timer interrupt, Base timer interrupt, Port interrupt INT1 then valid interrupt requests will cause interrupt. overflow timer will create interrupt timer 0.The overflow Base timer will create interrupt Base timer. falling edge every port PORTB will create INT1 interrupt (The condition that other port must input/output high level). Enable flags Request flags Both Enable flags Request flags read written software. Request flags will hardware interrupt, Enable flags will reset hardware when interrupt service routine entered. Interrupt Servicing Sequence Diagram: SH6610C interrupt services routine, user enable interrupt enable flag before returning from interrupt. frequently asked question when next interrupt would serviced? Will nesting interrupt happen? From servicing sequence timing diagram, interrupt request ready instruction execution enable, then interrupt start right after next instructions: instruction disable interrupt request enable flag, then interrupt service sequence would terminated.
Inst. cycle
Instruction Execution
Instruction Execution
Instruction Execution
Interrupt Generated
Interrupt Accepted
Vector Generated Stacking
Fetch Vector address Reset IE.X
Start vector address
SH66P14
Options Bonding options System register reserved user opened system developer select these bonding options, selecting subprogram that programmed user. $0A.1 (PC.1)
PC.0 PC.1
$0A.0 (PC.0) goto subroutine goto subroutine (Default) goto subroutine goto subroutine
PC.0 PC.1
PC.0
PC.1
PC.0 PC.1
PC.0
PC.1
PC.0
PC.1
PC.0
PC.1
PC.0
PC.1
SH66P14 Bonding Option Code option Oscillator (OSC) type: 32.768KHz crystal (Default) 262KHz HALT STOP mode After execution HALT instruction, SH66P14 will enter halt mode. halt mode, will stop operating. peripheral circuit (Timer Base timer) will keep operating. After execution STOP instruction, SH66P14 will enter stop mode. stop mode, whole chip (including oscillator) will stop operating. HALT mode, SH66P14 waked interrupt occurs. STOP mode, SH66P14 waked port interrupt occurs. Warm-up counter mode, warm-up counter prescaler divided (128). Crystal mode, warm-up counter prescaler divided (65536).
SH66P14
Instruction
instructions cycle word instruction. characteristic memory-oriented operation. Arithmetic Logical Instruction Accumulator Type Mnemonic ADCM ADDM SBCM SUBM EORM ANDM Immediate Type Mnemonic ADIM SBIM EORIM ORIM ANDIM Instruction Code 01000 iiii xxxx 01001 iiii xxxx 01010 iiii xxxx 01011 iiii xxxx 01100 iiii xxxx 01101 iiii xxxx 01110 iiii xxxx Function Flag Change Instruction Code 00000 0bbb xxxx 00000 1bbb xxxx 00001 0bbb xxxx 00001 1bbb xxxx 00010 0bbb xxxx 00010 1bbb xxxx 00011 0bbb xxxx 00011 1bbb xxxx 00100 0bbb xxxx 00100 1bbb xxxx 00101 0bbb xxxx 00101 1bbb xxxx 00110 0bbb xxxx 00110 1bbb xxxx 11110 0000 0000 Function Flag Change
[3]; shift right
assembler ASM66 V1.0, EORIM mnemonic EORI. However, EORI same operation identical with EORIM. true ORIM with respect ORI, ANDIM with respect ANDI. Decimal Adjust Mnemonic Instruction Code 11001 0110 xxxx 11001 1010 xxxx Function Decimal adjust add. Decimal adjust sub. Flag Change
SH66P14
Transfer Instruction Mnemonic Instruction Code 00111 0bbb xxxx 00111 1bbb xxxx 01111 iiii xxxx Function Flag Change
Control Instruction Mnemonic Instruction Code 10010 xxxx xxxx 10000 xxxx xxxx 10011 xxxx xxxx 10001 xxxx xxxx 10100 xxxx xxxx 10101 xxxx xxxx 10110 xxxx xxxx 10111 xxxx xxxx 11000 xxxx xxxx 11010 000h llll 11010 1000 0000 11011 0000 0000 11011 1000 0000 1110p xxxx xxxx 11110 1111 1111 11111 1111 1111 (Include (PC11-PC8) (TBR) (AC) Operation Function (Not include hhhh; llll Flag Change
CALL RTNW RTNI HALT STOP TJMP Where
Program counter Accumulator Complement accumulator Carry flag Data memory page Stack
Immediate data Logical exclusive Logical Logical bank
Table Branch Register
SH66P14
Absolute Maximum Rating* Supply Voltage -0.3V 7.0V Input Voltage -0.3V 0.3V Operating Ambient Temperature Storage Temperature *Comments Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VDD 3.0V, FOSC 32.768KHz, FOSCX used, unless otherwise specified) Parameter Operating Voltage Operating Current voltage divider resistor Standby Current Standby Current Input High Voltage Input Voltage Drive-high resistance Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage Output high voltage Output voltage lighting Symbol RLCD ISB1 ISB2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 VOH5 VOL5 ILCD Min. 0.85 -0.3 Typ. Max. 0.15 Unit output pins unload (HALT mode) exclude bias current, output pins unload (STOP mode), off, PORTA, PORTB INT0 RESET PORTA, PORTB INT0 RESET PORTA, PORTB (IOH -10µA, PORTA.0, PORTA.3, PORTB (IOH -2mA) PORTA.0, PORTA.3, PORTB (IOL 2mA) PORTA.1, PORTA.2 output, -5mA PORTA.1, PORTA.2 output, SEGx, 50P, rise time 1000ns SEGx SEG1 30to output port, -1mA SEG1 30to output port, COMx, -1mA COMx, exclude core operation current output pins unload execute instruction exclude bias current, Conditions
Operation frequency ISB1 ISB1X (Frequency/32.768KHz) ISB1 0.8, (VDD 3.0V). Operation frequency IOPX (Frequency/32.768KHz) 0.8, (VDD 3.0V). IOP, ISB1 ISB2 IOPX ISB2X ISB2 Circuitry (GND 25°C, FOSC 32.768KHz, unless otherwise specified) Parameter LPD-detected Voltage Symbol VLPD Min. Typ. Max. Unit Condition
SH66P14
Characteristics (VDD 3.0V, FOSC 32.768KHz, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |F|/F Min. Typ. Max. Unit [F(3.0)-F(2.5)]/F(3.0), crystal oscillator Conditions
Characteristics (VDD 3.0V, FOSC 262KHz, FOSCX stop, unless otherwise specified) Parameter Oscillation Start Time Frequency Stability Symbol tSTT |F|/F Min. Typ. Max. Unit [F(3.0)-F(2.5)]/F(3.0), Bias resistance accuracy within Conditions
Characteristics (VDD 4.5V, FOSC 262KHz, FOSCX stop, unless otherwise specified) Parameter Frequency Stability Symbol |F|/F Min. Typ. Max. Unit Conditions [F(4.5)-F(3.6)]/F(4.5), Bias resistance accuracy within
Typical oscillator Resistor Frequency: (for reference only)
(VDD 3.0V)
1000 200.00
250.00
300.00
350.00
400.00
450.00
(KHz)
Figure Resistor FOSC
(VDD 3.0V)
1700.00 1800.00 1900.00 2000.00 2100.00 2200.00 (KHz)
Figure Resistor FOSCX
SH66P14
Application Circuit (for reference only)
AP1: OSC: Crystal oscillator 32.768KHz (code option) OSCX: Ceramic oscillator 455KHz PORTB: PORTA.1, PORTA.2: ALARM output LCD: Internal duty, bias
duty bias RESET OSCXO OSCXI 455KHz
SH66P14
PORTB OSCO
PORTA.1
BUZZER
32768Hz OSCI TEST PORTA.2
AP2: OSC: oscillator 262KHz (mask option) LCD: Internal duty, bias PORTA, PORTB: PORTA.0: External interrupt
duty bias
RESET
OSCXI OSCXO
PORTA PORTB OSCO 930K OSCI
SH66P14
PORTA.0
Ext.int
TEST
SH66P14
AP3: OSC: Crystal oscillator 32.768KHz (mask option) OSCX: oscillator 1.8MHz PORTB: PORTA.1: output PORTA.2: output
RESET
OSCXI OSCXO
120K (VDD
SPEAKETR
SH66P14
PORTB OSCO
PORTA.1
8050
32768Hz OSCI TEST
PORTA.2
AP4: Internal bias.1/8 DUTY bias
COM1 COM8 SEG30
PANNEL
BOARD
SEG1 SEG4 SCAN output port
SH66P14
SEG4 SEG3 SEG2 SEG1 PORTB0 PORTB1 PORTB2 PORTB3
SH66P14
AP5: Large panel: External bias
Bias Bias Normal pannel VLCD Bias Large pannel VLCD Ext.R SH66P14 SH66P14 Ext.R Ext.R Ext.R SH66P14 Ext.R Bias Large pannel VLCD Ext.R
VCC, floating
SH66P14
Music Table1
Following music scale reference table channel 1(or channel under OSCX 1.8MHz. octave possible. Music scale data 1.8M OSCX SEL0 SEL1 Note Ideal freq. 61.73 65.10 69.29 73.42 77.78 82.41 87.31 92.50 98.00 110.00 123.47 130.81 146.83 164.81 174.61 184.99 196.00 220.00 246.94 261.63 293.66 329.63 349.23 369.99 392.00 440.00 493.88 LSFR OCT1 Real (C1.6~C1.0) freq. Error% Note /OCT2 (C2.14~C2.8) 61.68 -0.08 65.10 69.62 73.24 78.13 82.72 86.81 92.52 97.66 103.40 109.86 117.19 123.36 130.21 137.87 146.48 156.25 163.52 175.78 185.03 195.31 206.80 219.73 234.38 251.12 260.42 281.25 292.97 305.71 334.82 351.56 370.07 390.63 413.60 439.45 468.75 502.23 0.01 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.40 -0.13 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.79 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 Ideal freq. 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 1046.48 1108.71 1174.63 1244.48 1318.48 1396.88 1479.95 1567.95 1661.18 1759.96 1864.62 1975.49 2092.96 2217.41 2349.27 2488.96 2636.96 2793.77 2959.89 3135.90 3322.37 3519.93 3729.23 3950.98 LSFR OCT1/ Real Error% (C1.6~C1.0) OCT2 freq. (C2.14~C2.8) 493.42 -0.09 520.83 556.93 585.94 625.00 661.77 694.44 740.13 781.25 827.21 878.91 937.50 986.84 1041.67 1102.94 1171.88 1250.00 1308.14 1406.25 1480.26 1562.50 1654.41 1757.81 1875.00 2008.93 2083.33 2250.00 2343.75 2445.65 2678.57 2812.50 2960.53 3125.00 3308.82 3515.63 3750.00 4017.86 -0.46 0.47 -0.24 0.44 0.38 -0.58 0.02 -0.35 -0.41 -0.12 0.56 -0.09 -0.46 -0.52 -0.24 0.44 -0.78 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69 -0.46 1.47 -0.24 -1.74 1.58 0.67 0.02 -0.35 -0.41 -0.12 0.56 1.69
103.82 116.54
138.59 155.56
207.65 233.08
277.18 311.12
415.30 466.15
SH66P14
Music Table2
Following music scale reference table channel 1(or channel under 32.768KHz. 4-octave possible. Music scale data SEL0 SEL1 Note Ideal freq. 55.00 58.27 61.73 65.41 69.29 73.42 77.78 82.41 87.31 92.50 98.00 103.82 110.00 116.54 123.47 130.81 138.59 146.83 155.56 164.81 174.61 184.99 196.00 207.65 220.00 233.08 246.94 LSFR OCT1 /OCT2 (C1.6~C1.0) (C2.14~C2.8) Real freq. 55.35 58.51 62.06 66.07 68.27 73.14 78.77 81.92 89.04 93.09 97.52 102.40 107.79 113.78 120.47 128.00 136.53 146.29 156.04 165.50 174.30 184.09 195.05 207.39 221.41 234.06 248.24 Error% Note 0.64 0.42 0.54 1.00 -1.48 -0.38 1.27 -0.60 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37 0.31 0.42 -0.18 -0.49 -0.49 -0.12 0.64 0.42 0.53 Ideal freq. 261.63 277.18 293.66 311.12 329.63 349.23 369.99 392.00 415.30 440.00 466.15 493.88 523.25 554.35 587.33 622.24 659.26 698.46 739.97 783.99 830.59 880.00 932.31 987.77 LSFR OCT1 Real Error% /OCT2 (C1.6~C1.0) freq. (C2.14~C2.8) 260.06 -0.60 277.70 292.57 309.13 327.68 348.60 372.36 390.10 420.10 442.81 468.11 496.49 528.52 546.13 585.14 630.15 655.36 712.35 744.73 780.19 819.20 862.32 910.22 963.77 1024.00 1092.27 1170.29 0.19 -0.37 -0.64 -0.59 -0.18 0.64 -0.49 1.16 0.64 0.42 0.53 1.01 -1.48 -0.37 1.27 -0.59 1.99 0.64 -0.49 -1.37 -2.01 -2.37 -2.43 -2.15 -1.48 -0.37
1046.48
1108.71 1174.63
SH66P14
Ordering Informations
Part SH66P14H SH66P14F Packages CHIP FORM
SH66P14
Bonding diagram
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 COM6 COM5 COM4 COM3 COM2 COM1 OSCI OSCO OSCXO OSCXI
SH66P14
(0,0)
2420µm
1930µm
Substrate connect bonding option bonding option Designation SEG2 SEG1 VLCD TEST RESET OSCXI OSCXO OSCO OSCI COM[1] COM[2] COM[3] COM[4] COM[5] COM[6] X(µm) -890.55 -720.55 -595.55 -470.55 -345.55 -220.55 -90.55 39.45 204.45 204.45 364.45 489.45 614.45 739.45 884.45 884.45 884.45 884.45 884.45 884.45 784.45 884.45 884.45 884.45 884.45 884.45 884.45 884.45 884.45 884.45 Y(µm) -1121.05 -1135.00 -1135.00 -1135.00 -1135.00 -1135.00 -1135.00 -1135.00 -1030.00 -1135.00 -1135.00 -1135.00 -1135.00 -1135.00 -1135.00 -1010.00 -885.00 -760.00 -260.00 -135.00 -10.00 -10.00 115.00 240.00 365.00 490.00 615.00 740.00 865.00 990.00 Designation COM[7] COM[8] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18] SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] X(µm) 884.45 759.45 634.45 509.45 384.45 259.45 134.45 9.45 -115.55 -240.55 -365.55 -490.55 -615.55 -740.55 -865.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 -890.55 Y(µm) 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 1135.00 990.00 740.00 615.00 490.00 365.00 240.00 115.00 -10.00 -135.00 -260.00 -385.00 -510.00 -635.00 -760.00 -995.35
SH66P14
Package Informations 100L Outline Dimensions
unit: inches/mm
Detail Seating Plane
Detail
Symbol
Dimensions inches 0.130 Max. 0.004 Min. 0.112 0.005 0.012 +0.004 -0.002
Dimensions 3.30 Max. 0.10 Min. 2.85 0.13 0.31 +0.10 -0.05 0.15 +0.10 -0.05 14.00 0.13 20.00 0.13 0.65 0.15 18.85 NOM. 17.60 NOM. 23.60 NOM. 18.80 0.31 24.79 0.31 1.19 0.20 2.41 0.20 0.15 Max.
0.006 +0.004 -0.002 0.551 0.005 0.787 0.005 0.026 0.006 0.742 NOM. 0.693 NOM. 0.929 NOM. 0.740 0.012 0.976 0.012 0.047 0.008 0.095 0.008 0.006 Max.
Notes: Dimensions include resin fins. Dimensions Board surfaces mount pitch Design reference only.

4-bit Microcontroller with Driver SH6610C-based single-chip 4-bit

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