Xilinx Inc. 2100 Logic Drive Jose, 95124 Phone: 408-559-7778 Fax: 408-

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Binary Counter V3.0
Xilinx Inc. 2100 Logic Drive Jose, 95124 Phone: 408-559-7778 Fax: 408-559-7114 URL: www.xilinx.com/ipcenter Support: support.xilinx.com Drop-in module VirtexTM-, Virtex, Virtex-E Spartan- FPGAs Generates Down Up/Down Counters Supports counts ranging from bits wide Optional load capability Optional user programmable threshold outputs Optional clock enable asynchronous synchronous controls Counter increment value user defined supplied externally. User-programmable Count limit Incorporates Xilinx Smart-IP technology maximum performance used with version 3.1i later Xilinx CORE Generator System
Figure Main Binary Counter Parameterization Screen November 2000
Binary Counter V3.0
Functional Description
binary counter used create counters, down counters up/down counters with outputs bits wide. Support provided threshold signals that programmed become active when counter reaches user defined count. upper limit count user programmable, counter's increment value user defined provided external port. Options provided Clock Enable, Asynchronous Set, Clear, Init, Synchronous Set, Clear Init. optional Load capability also provided which load value Load port directly into output register. module optionally generated Relationally Placed Macro (RPM) unplaced logic. When generated logic placed column. When counter reaches terminal count "count value" next count will zero.
Pinout
Signal names schematic symbol shown Figure described Table
composed from following characters: "_". Output Width: Enter width counter. valid range default value Operation: Select appropriate radio button operation required. default setting Count Style: module incremented constant value, have count value supplied IV[N:0] port. default setting Count Constant. Count Restrictions: Count Value: Enter count increment value. This text only enabled Count Style Count Constant. When Restrict Count check unchecked Count Value MAX) valid range 2Output Width When Restrict Count check checked valid settings Count Value governed equation: (Count Value Count Value Integer default value Restrict Count: When this check checked counter will only count value specified Count Value box. When unchecked counter will count maximum value that represented using specified output width.The default count restriction. Count Value: Enter count limit value keyword (which corresponds each counter output bits). valid range values 2Output Width 1.This text only enabled when Restrict Count check checked. default value MAX.
CORE Generator Parameters
main CORE Generator parameterization screen this module shown Figure parameters follows: Component Name: component name used base name output files generated this module. Names must begin with letter must
Figure Binary Counter Register Options Parameterization Screen
Figure Core Schematic Symbol
November 2000
Xilinx, Inc. Output Options: behavior threshold outputs depends state Threshold Early checkbox. Threshold Early checked, registered threshold output will become active same clock edge that sets output counter Threshold Value. nonregistered threshold output will become active clock cycle before threshold value reached counter outputs. This allows more setup time ripple operations that utilize nonregistered threshold output prior clock edge that sets counter outputs threshold value. Threshold Early unchecked, nonregistered output will become active when threshold value reached counter outputs registered output will become active next clock edge. This allows implementation combinatorial terminal count signal. Threshold When this check checked Threshold output(s) (registered, non-registered, both) will generated. default generate Threshold output. Threshold Value: Enter value which THRESH_0 value will activated value keyword (which corresponds each counter output bits). valid range values Count Value. This text only enabled when Threshold check checked. default value MAX. Note that when Restrict Count check checked Threshold Value setting must less than equal Count Value setting. Threshold When this check checked Threshold output(s) (registered, non-registered, both) will generated. default generate Threshold output. Threshold Value: Enter value which THRESH_1 value will activated value keyword (which corresponds each counter output bits). valid range values Count Value. This text only enabled when Threshold check checked. default value MAX. Note that when Restrict Count check checked Threshold Value setting must less than equal Count Value settings. Output Options: Select appropriate radio button types outputs required Threshold signals. default setting Registered. Register Options: Clicking this button brings Register Options parameterization screen (see figure Load: Activating LOAD allows value L[N:0] input port pass through logic loaded into output register next active clock edge. default LOAD generated. synchronous options selected through Register Options parameterization screen, precedence LOAD port depends whether Restrict Count option checked. details Table Table Precedence LOAD over Synchronous Signals LOAD port and: SCLR SSET SINIT Restrict Count LOAD LOAD SSET LOAD SINIT LOAD
change precedence result internal implementation restricted count functionality. different precedence required user, must implemented external logic. Override Load: This parameter controls whether LOAD input qualified When this checked activation LOAD signal will also enable output register. When this unchecked register needs have active order load port data. default this check checked.
Table Core Signal Pinout Signal L[N:0] LOAD IV[N:0] Signal Direction Description Input Load data port Input Load Control signal Input Count Increment Value Input Controls count direction up/down counter. Counts when High, Down when Input Clock Enable Input Clock rising edge clock signal Input Asynchronous forces registered output High state when driven Input Asynchronous Clear forces outputs state when driven Input Synchronous forces registered output High state next concurrent clock edge
ASET
ACLR
SSET
November 2000
Binary Counter V3.0 Table Core Signal Pinout Signal SCLR Signal Direction Description Input Synchronous Clear forces registered output state next concurrent clock edge Input Asynchronous Initialize forces registered outputs user defined state when driven Input Synchronous Initialize forces registered outputs user defined state next concurrent clock edge Output User programmable threshold signal Output Registered user programmable threshold signal Output User programmable threshold signal Output Registered user programmable threshold signal Output Output Clock Enable: When this checked module generated with clock enable input. default setting unchecked. Overrides: This parameter controls whether SSET, SCLR, SINIT inputs qualified This parameter only enabled when Clock Enable input been requested. When Overrides Sync Controls selected active level synchronous control inputs will only acted upon when also Active. Note that this that dedicated inputs flip-flop primitives work, setting Overrides parameter Overrides Sync Controls will force synchronous control functionality implemented using logic Look Tables (LUTs) preceding output register. This results increased resource utilization. When Sync Controls Override selected active level synchronous control inputs acted upon irrespective state pin. This setting allows dedicated inputs flip-flop primitives used synchronous control functions provided that asynchronous controls requested. both asynchronous synchronous controls requested, synchronous control functionality must implemented using logic LUTs preceding output register. this case, input gated with synchronous control inputs that each synchronous control input input generate signal flip-flops. This results performance degradation module additional gating path. default setting Sync Controls Override that more efficient implementation generated. Asynchronous Settings: asynchronous controls implemented using dedicated inputs flipflop primitives. module generated with following asynchronous control inputs clicking appropriate button: None: asynchronous control inputs. This default setting. Set: ASET control generated. Clear: ACLR control generated. Clear: Both ASET ACLR control pins generated. ACLR priority over ASET when both asserted same time. Init: AINIT control generated which, when asserted, will asynchronously output register value defined Asynchronous Init Value text box. Asynchronous Init Value: This text accepts value whose equivalent width must less than equal Output Width. value entered that fewer bits than Output Width padded with zeros. invalid value highlighted text November 2000
AINIT
SINIT
THRESH0 Q_THRESH0
THRESH1 Q_THRESH1
Q[N:0]
Note:
control inputs Active High. Should Active input required particular control inverter must placed path pin. inverter will absorbed appropriately during mapping.
Load Sense: LOAD only that parameter control active sense. This because selection Active bypass results significant area savings module. default this parameter Active High that conforms with active sense other control signals. Create RPM: When this checked module generated with relative location attributes attached. resulting placement module column with bits slice. default operation create RPM. Note that when module created possible that more module dimensions exceed those device being targeted. this case mapping errors will occur compilation process will fail. this case module should regenerated with Create checkbox unchecked.
Register Options parameterization screen this module shown Figure parameters follows:
Xilinx, Inc. box. default value Synchronous Settings: When asynchronous controls requested (i.e. Asynchronous Setting None) synchronous controls implemented using dedicated inputs flip-flop primitives. There exceptions this which described sections Set/Clear Priority Overrides parameters. When asynchronous controls present synchronous control functionality must implemented using logic Look Tables (LUTs) preceding output register. With modules where non-registered output required there combinations parameters that allow this logic absorbed into same LUTs used implement function. cases where this absorption possible synchronous control logic will require additional output bit. module generated with following synchronous control inputs clicking appropriate button: None: synchronous control inputs. This default setting. Set: SSET control generated. Clear: SCLR control generated. Clear: Both SSET SCLR control pins generated. SCLR/SSET priority defined setting Set/Clear Priority parameter. Init: SINIT control generated which, when asserted, will synchronously output register value defined Synchronous Init Value text box. Set/Clear Priority: selecting appropriate radio button relative priority SCLR SSET controlled. This parameter only enabled when Clear selected Synchronous Settings. setting Clear Overrides corresponds native operation flip-flop primitive. This setting will result more efficient implementation when asynchronous controls requested. setting Overrides Clear only implemented using logic LUTs preceding output register. default setting Clear Overrides that dedicated inputs flip-flops used available. Synchronous Init Value: This text accepts value whose equivalent width must less than equal Output Width. value entered that fewer bits than Output Width padded with zeros. invalid value highlighted text box. This parameter only enabled when Synchronous Settings parameter Init. default value
Power Conditions
FD-based Register datasheet information power values counter. Note that user requests Restrict Count functionality, final register internally used synchronous clear which affect power value.
Parameter Values File
Names file parameters their parameter values identical names values shown GUI, except that underscore characters used instead spaces. text file case insensitive. Table shows file parameters values, summarizes defaults. following example CSET parameters file: CSET component_name abc123 CSET output_width CSET operation CSET count_style count_by_constant CSET count_by_value CSET restrict_count FALSE CSET count_to_value CSET threshold_0 FALSE CSET threshold_0_value CSET threshold_1 FALSE CSET threshold_1_value CSET threshold_options non_registered CSET threshold_early TRUE CSET load FALSE CSET ce_override_for_load FALSE CSET load_sense active_high CSET create_rpm TRUE CSET clock_enable FALSE CSET ce_overrides ce_overrides_sync_controls CSET asynchronous_settings none CSET async_init_value 0000 CSET synchronous_settings none CSET sync_init_value 0000 CSET set_clear_priority clear_overrides_set
Core Resource Utilization
accurate measure usage primitives, slices, CLBs particular point solution, check Display Core Viewer after Generation checkbox, CoreGen.
Ordering Information
This core downloadable free charge from Xilinx Center (www.xilinx.com/ipcenter), with version 3.1i later versions Xilinx Core Generator System. Core Generator System bundled with Alliance Foundation implementation tools.
November 2000
Binary Counter V3.0 order Xilinx software contact your local Xilinx sales representative. information Xilinx sales office nearest you, please refer
Table Default Values File Values Parameter component_name File values ASCII text starting with letter based upon following character set: a.z, Integer range following keywords: down, up_down following keywords: count_by_constant, count_by_variable value range count_to_value that meets following restriction: (count_to_value count_by_value Integer following keywords: true, false keyword (which corresponds setting output_width value range output_width following keywords: true, false keyword "MAX" value range count_to_value following keywords: true, false keyword "MAX" value range count_to_value following keywords: non_registered, registered, both following keywords: true, false following keywords: true, false following keywords: true, false following keywords: active_high, active_low following keywords: true, false following keywords: true, false following keywords: sync_controls_override_ce, ce_overrides_sync_controls following keywords: none, set, clear, set_and_clear, init value whose value does exceed output_width following keywords: none, set, clear, set_and_clear, init value whose value does exceed output_width following keywords: clear_overrides_set, set_overrides_clear Default Setting blank
output_width operation count_style count_by_value
count_by_constant
restrict_count count_to_value
false
threshold_0 threshold_0_value threshold_1 threshold_1_value threshold_options threshold_early load ce_override_for_load load_sense create_rpm clock_enable ce_overrides
false false non_registered true false true active_high true false sync_controls_override_ce
asynchronous_settings async_init_value synchronous_settings sync_init_value set_clear_priority
none none clear_overrides_set
November 2000

Xilinx Inc. 2100 Logic Drive Jose, 95124 Phone: 408-559-7778 Fax: 408-

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